A memory compute array and memory device
By employing three types of resistive magnetic tunnel junction bits and switching devices in the storage computing array, the problems of large memory area and high power consumption are solved, and the number of memory devices and power consumption are reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG HIKSTOR TECHOGY CO LTD
- Filing Date
- 2021-09-03
- Publication Date
- 2026-05-15
AI Technical Summary
Existing memory computing arrays only have two resistive states for memory, resulting in a large number of memory and switching devices, large area, and high power consumption.
A storage node with three resistance states is adopted by using magnetic tunnel junction bits. By combining switching devices and magnetic storage devices, multiple storage states can be achieved by controlling the resistance state of the magnetic tunnel junction bits, thereby reducing the number of switching devices.
By increasing the number of resistive states in the magnetic tunnel junction bits, the area and power consumption of the storage computing array are reduced, thereby increasing the amount of information stored.
Smart Images
Figure CN115762593B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a storage computing array and storage device. Background Technology
[0002] Neural network algorithms are widely used in the field of artificial intelligence, utilizing the current-voltage relationship between analog signals and analog storage arrays to perform large-scale matrix operations. The analog storage array includes a memory; during each matrix operation, the analog value is repeatedly compared with the target current, and the result is written into the memory. Currently, in storage computing arrays, the memory and switching devices are connected in series or parallel. The memory has two states: a high-resistance state and a low-resistance state, controlled by turning the switching devices on or off. Because the memory only has two resistance states, to handle large amounts of data to be written, storage computing arrays require a large number of memories and correspondingly, a large number of switching devices, resulting in large area and high power consumption.
[0003] Therefore, how to solve the above-mentioned technical problems should be a key focus for those skilled in the art. Summary of the Invention
[0004] The purpose of this application is to provide a storage computing array and storage device to reduce the number of switching devices, reduce the area of the storage computing array, and reduce power consumption.
[0005] To address the aforementioned technical problems, this application provides a storage computing array, comprising storage cells arranged in an array. Each storage cell includes multiple storage nodes, each storage node includes switching devices and magnetic storage devices, and each magnetic storage device includes multiple magnetic tunnel junction bits. Each magnetic tunnel junction bit has at least three resistive states, and each magnetic tunnel junction bit includes a first reference layer, a first barrier layer, a free layer, a second barrier layer, and a second reference layer stacked sequentially from bottom to top.
[0006] Optionally, the size of the magnetic tunnel junction bits in each of the magnetic storage devices is different.
[0007] Optionally, the magnetic tunnel junction bits in each of the magnetic storage devices may be connected in series, in parallel, or both series and parallel connections may exist simultaneously.
[0008] Optionally, the materials of the first barrier layer and the second barrier layer are any one or any combination of the following:
[0009] Mg, MgO, AlO, MgAlO.
[0010] Optionally, the materials of the first reference layer, the free layer, and the second reference layer are any one or any combination of the following:
[0011] CoFeB, CoB, Fe, FeB.
[0012] Optionally, the switching device is a single MOSFET.
[0013] Optional, also includes:
[0014] An enable device connected in series with the memory cell is used to control the on or off state of the memory cell.
[0015] Optional, also includes:
[0016] A correction unit used to remove systematic errors from calculation results.
[0017] Optionally, the magnetic tunnel junction bit further includes:
[0018] The first pinning layer is located on the surface of the first reference layer that is away from the first barrier layer;
[0019] The second pinning layer is located on the surface of the second reference layer away from the second barrier layer.
[0020] This application also provides a storage device, which includes any of the storage computing arrays described above.
[0021] The present application provides a storage computing array comprising arrayed storage cells, each storage cell comprising multiple storage nodes, each storage node comprising switching devices and magnetic storage devices, each magnetic storage device comprising multiple magnetic tunnel junction bits, each magnetic tunnel junction bit having at least three resistive states, and each magnetic tunnel junction bit comprising, from bottom to top, a first reference layer, a first barrier layer, a free layer, a second barrier layer, and a second reference layer.
[0022] As can be seen, the storage computing array in this application includes arrayed storage cells, each storage cell including multiple storage nodes, each storage node including switching devices and magnetic storage devices, each magnetic storage device including multiple magnetic tunnel junction bits, each magnetic tunnel junction bit including a first reference layer, a first barrier layer, a free layer, a second barrier layer, and a second reference layer stacked sequentially from bottom to top, so that the magnetic tunnel junction bit has at least three resistance states. The switching devices can make the magnetic tunnel junction bit be in different resistance states. Compared with memory with two resistance states, the magnetic tunnel junction bit has more types of resistance states, and the amount of information that can be stored is increased. Therefore, the number of magnetic tunnel junction bits can be reduced, and thus the number of switching devices is also reduced, thereby reducing the area of the storage computing array and reducing power consumption.
[0023] This application also provides a storage device. Attached Figure Description
[0024] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 A schematic diagram of a storage unit provided in an embodiment of this application;
[0026] Figures 2 to 4 This is a schematic diagram illustrating different connection relationships between magnetic tunnel junctions in this application;
[0027] Figure 5 This is a schematic diagram of the structure of a magnetic tunnel junction provided in an embodiment of this application;
[0028] Figure 6 This is a schematic diagram of another magnetic tunnel junction provided in an embodiment of this application. Detailed Implementation
[0029] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0030] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.
[0031] As described in the background section, in current storage computing arrays, memory and switching devices are connected in series or parallel. The memory has two states: a high-resistance state and a low-resistance state. The resistance state of the memory is controlled by turning the switching devices on or off. Because the memory only has two resistance states, a large number of memories are needed in the storage computing array to handle a large amount of data that needs to be written. Consequently, the number of switching devices is also large, resulting in a large area and high power consumption for the storage computing array.
[0032] In view of this, this application provides a storage computing array, please refer to... Figure 1 , Figure 1This is a schematic diagram of a storage cell provided in an embodiment of the present application, including an array of storage cells 1. The storage cell 1 includes multiple storage nodes 2. Each storage node 2 includes a switching device T and a magnetic storage device. The magnetic storage device includes multiple magnetic tunnel junction bits R. Each magnetic tunnel junction bit R has at least three resistive states. Each magnetic tunnel junction bit R includes a first reference layer, a first barrier layer, a free layer, a second barrier layer, and a second reference layer stacked sequentially from bottom to top.
[0033] Storage cells 1 are generally arranged in rows and columns. Storage cells 1 can be arranged in neatly aligned rows and columns or in staggered rows and columns. For example, the storage cell 1 in the next row is located between two adjacent storage cells 1 in the previous row.
[0034] Storage cell 1 has signal terminals connected to its two ends, one as a signal input and the other as a signal output. The switching device T has on and off states. The write resistance of storage cell 1 is determined by changing the resistance state of the magnetic storage device by controlling the switching state of the switching device T. The write resistance of storage cell 1 is the parallel resistance of storage node 2, determined by changing the resistance state of the magnetic storage device.
[0035] It should be noted that the type of switching device T is not limited in this application and can be set by the user. Optionally, the switching device T is a single MOS (metal oxide semiconductor) transistor or a diode.
[0036] Multiple storage nodes 2 are generally connected in parallel. Each storage node 2 includes a switching device T and a magnetic storage device. Each magnetic storage device includes multiple magnetic tunnel junction bits R. The switching current of the magnetic tunnel junction bits R varies with the size of the magnetic tunnel junction bits R. Optionally, the size of the magnetic tunnel junction bits R in each magnetic storage device is different, thereby realizing the controllable switching of the magnetic tunnel junction bits R to a fixed resistance state.
[0037] The number and resistance state of magnetic tunnel junction bits R in each storage node 2 determine the amount of information that storage cell 1 can store. In this application, the number of magnetic tunnel junction bits R in each storage node 2 is not limited, but depends on the situation. For example, the number of magnetic tunnel junction bits R can be four, six, seven, etc. Figure 1 The number of magnetic tunnel junction bits R is four, namely R1, R2, R3, and R4.
[0038] One end of storage node 2 is connected to BL (Bit Line), that is... Figure 1 In the diagram, B is connected to SL (Source Line), i.e. Figure 1The letter A in the diagram is connected to the word line (WL) at one end. Figure 1 C in the middle.
[0039] It should be noted that this application does not limit the connection relationship of the magnetic tunnel junction bits R in each magnetic storage device; it depends on the situation. For example, the magnetic tunnel junction bits R in each magnetic storage device may be connected in series, in parallel, or both series and parallel connections may exist simultaneously. Please refer to... Figures 2 to 4 , Figure 2 The magnetic tunnel junctions R are connected in series. Figure 3 Parallel connection between the magnetic tunnel junction R and other elements. Figure 4 The magnetic tunnel junctions R are connected in both series and parallel.
[0040] A schematic diagram of the structure of the magnetic tunnel junction R is shown below. Figure 5 As shown, from bottom to top, there are first reference layer 1, first barrier layer 2, free layer 3, second barrier layer 4, and second reference layer 5, which enables the magnetic tunnel junction R to achieve three resistive states, while improving the process reliability of the magnetic tunnel junction R and reducing the miniaturization difficulty.
[0041] In the initial state, the magnetic field forms all the magnetic tunnel junction bits R into parallel or antiparallel states. Subsequently, the write voltage is controlled by the switching device T, thereby realizing different resistance states of the entire magnetic storage cell 1.
[0042] The first reference layer 1 has the largest flip current, followed by the second reference layer 5, and the free layer 3 has the smallest flip current. By initializing the magnetic field, the magnetic moments of the first reference layer 1 and the second reference layer 5 can be magnetized to be the same. Then, a smaller magnetic field is used to magnetize the free layer 3 in the opposite direction to the magnetic moments of the first reference layer 1 and the second reference layer 5, at which point the resistance is the largest. By applying write currents of different directions and magnitudes, the flip current of the free layer 3 can be controlled, at which point the resistance is the smallest, or the flip currents of the first reference layer 1 and the second reference layer 5 can be controlled, at which point the resistance is intermediate.
[0043] This application does not limit the materials of each layer in the magnetic tunnel junction R; the materials can be selected freely. Specifically, the materials of the first barrier layer 2 and the second barrier layer 4 can be any one or any combination of the following:
[0044] Mg, MgO, AlO, MgAlO.
[0045] The materials of the first reference layer 1, the free layer 3, and the second reference layer 5 are any one or any combination of the following:
[0046] CoFeB, CoB, Fe, FeB.
[0047] The storage computing array in this application includes arrayed storage cells 1, each storage cell 1 including multiple storage nodes 2, each storage node 2 including switching devices T and magnetic storage devices, each magnetic storage device including multiple magnetic tunnel junction bits R, each magnetic tunnel junction bit R including a first reference layer 1, a first barrier layer 2, a free layer 3, a second barrier layer 4, and a second reference layer 5 stacked sequentially from bottom to top, such that the magnetic tunnel junction bit R has at least three resistance states. The switching devices T can make the magnetic tunnel junction bit R be in different resistance states. Compared with a memory with two resistance states, the magnetic tunnel junction bit R has more types of resistance states, and the amount of information that can be stored is increased. Therefore, the number of magnetic tunnel junction bits R can be reduced, and thus the number of switching devices T is also reduced, thereby reducing the area of the storage computing array and reducing power consumption.
[0048] Based on the above embodiments, in one embodiment of this application, the storage computing array further includes:
[0049] An enable device connected in series with the storage unit 1 is used to control the on or off state of the storage unit 1.
[0050] The enable device is connected in series with the end of the memory cell 1. When the enable device is under the control of the non-enable signal, the memory cell 1 is always in the off state. The non-enable signal can correspond to the preset write resistance value. When it is less than the preset write resistance value, the memory cell 1 is always in the off state.
[0051] The enabling device can be a transmission gate, which is composed of a PMOS transistor and an NMOS transistor connected in parallel, wherein the gate inputs of the PMOS transistor and the NMOS transistor are complementary signals. The transmission gate has two switching states: on and off. When the transmission gate is on, both the PMOS transistor and the NMOS transistor are in the on state; when the transmission gate is off, both the PMOS transistor and the NMOS transistor are in the off state, thus allowing for a lower on-resistance using a lower gate voltage.
[0052] The storage cells in the column direction of the storage computing array have constant leakage current, which causes systematic errors in the calculation results output by the storage computing array. In order to improve the accuracy of the calculation results, the storage computing array also includes a correction unit for removing systematic errors from the calculation results.
[0053] It should be noted that this application does not limit the method of removing systematic errors, but depends on the type of correction unit.
[0054] Optionally, the correction unit includes a differential operator, which performs a differential operation between the calculation result and the calculation result of the memory cells in another column direction that are all in the highest resistance state, thereby outputting a calculation result after removing system errors. Alternatively, the correction unit includes a digital arithmetic circuit, which subtracts system errors from the calculation result.
[0055] Please refer to Figure 6 , Figure 6 This is a schematic diagram of another magnetic tunnel junction bit provided in an embodiment of this application. Based on any of the above embodiments, in one embodiment of this application, the magnetic tunnel junction bit further includes:
[0056] The first pinning layer 6 is located on the surface of the first reference layer 1 that is away from the first barrier layer 2;
[0057] The second pinning layer 7 is located on the surface of the second reference layer 5 away from the second barrier layer 4.
[0058] The first pinning layer 6 and the second pinning layer 7 can pin the magnetization directions of the first reference layer 1 and the second reference layer 5 respectively, so that the magnetization directions do not reverse during the use of the device.
[0059] This application also provides a storage device, which includes the storage computing array described in any of the above embodiments.
[0060] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0061] The storage computing array and storage device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A storage computing array, comprising storage units arranged in an array, wherein each storage unit includes multiple storage nodes, characterized in that, The storage node includes switching devices and magnetic storage devices. The magnetic storage devices include multiple magnetic tunnel junction bits. Each magnetic tunnel junction bit has at least three resistive states. Each magnetic tunnel junction bit includes a first reference layer, a first barrier layer, a free layer, a second barrier layer, and a second reference layer stacked sequentially from bottom to top. The first reference layer has the largest flip current, followed by the second reference layer, and the free layer has the smallest flip current. The magnetic moments of the first reference layer and the second reference layer are magnetized to be consistent by initializing the magnetic field. Then, the free layer is magnetized to be in the opposite direction to the magnetic moments of the first reference layer and the second reference layer by the magnetic field. At this time, the resistance is the largest. By applying write currents of different directions and magnitudes, the free layer is controlled to flip, and the resistance is the smallest. The first reference layer and the second reference layer are controlled to flip, and this is the intermediate resistance state. The flip current of the magnetic tunnel junction bit varies with the size of the magnetic tunnel junction bit, and the size of the magnetic tunnel junction bit is different in each of the magnetic storage devices; An enabling device connected in series with the memory cell is used to control the on or off state of the memory cell. A correction unit used to remove systematic errors from calculation results.
2. The storage computing array as described in claim 1, characterized in that, The magnetic tunnel junction bits in each of the magnetic storage devices are connected in series, in parallel, or both series and parallel connections exist simultaneously.
3. The storage computing array as described in claim 1, characterized in that, The materials of the first barrier layer and the second barrier layer are any one or any combination of the following: Mg, MgO, AlO, MgAlO.
4. The storage computing array as described in claim 1, characterized in that, The materials of the first reference layer, the free layer, and the second reference layer are any one or any combination of the following: CoFeB, CoB, Fe, FeB.
5. The storage computing array as described in claim 1, characterized in that, The switching device is a single MOS transistor.
6. The storage computing array as described in any one of claims 1 to 5, characterized in that, The magnetic tunnel junction also includes: The first pinning layer is located on the surface of the first reference layer that is away from the first barrier layer; The second pinning layer is located on the surface of the second reference layer away from the second barrier layer.
7. A storage device, characterized in that, The storage device includes a storage computing array as described in any one of claims 1 to 6.