Three-dimensional memory device and ternary content addressable storage unit thereof

Abstract

The present disclosure provides a three-dimensional memory device and a ternary content-addressable memory cell thereof. The ternary content-addressable memory cell includes a first memory cell, a second memory cell, a first search switch, and a second search switch. The first memory cell is disposed in a first AND-type flash memory cell row. The second memory cell is disposed in a second AND-type flash memory cell row. The first search switch is coupled between a first bit line and a match line corresponding to the first AND-type flash memory cell row, and the first search switch is controlled by a first search signal to be turned on or off. The second search switch is coupled between a second bit line and a match line corresponding to the second AND-type flash memory cell row, and the second search switch is controlled by a second search signal to be turned on or off.

Description

Technical Field

[0001] The present invention relates to a three-dimensional memory device and a ternary content addressable memory cell thereof, and more particularly to a three-dimensional memory device and a ternary content addressable memory cell thereof that can save more power during a search operation. Background Art

[0002] In electronic devices, high-density and high-speed ternary content addressable memory cells have become an important architecture to provide high-performance lookup tables.

[0003] Using nonvolatile memory to construct ternary content addressable memory cells is a common choice. However, the electrical characteristics of nonvolatile memory, such as bit error rate, are an important parameter to consider.

[0004] In the prior art, NOR flash memory is commonly used to construct ternary content addressable memory cells. However, due to the circuit architecture of NOR flash memory, it is difficult to use NOR flash memory to construct a sufficiently high-density ternary content addressable memory cell array.

[0005] Public content

[0006] The present invention provides a three-dimensional memory device and a ternary content addressable storage unit thereof, which can reduce the power consumption required during the search action.

[0007] A ternary content-addressable memory cell according to the present invention includes a first memory cell, a second memory cell, a first search switch, and a second search switch. The first memory cell is disposed in a first AND-type flash memory cell row. The second memory cell is disposed in a second AND-type flash memory cell row. The first search switch is coupled between a first bit line and a match line corresponding to the first AND-type flash memory cell row. The first search switch is controlled by a first search signal to be turned on or off. The second search switch is coupled between a second bit line and a match line corresponding to the second AND-type flash memory cell row. The second search switch is controlled by a second search signal to be turned on or off.

[0008] The three-dimensional memory device of the present invention includes an AND-type flash memory bank and at least one ternary content-addressable memory cell. The AND-type flash memory bank includes at least one memory cell array block. The ternary content-addressable memory cell includes a first memory cell, a second memory cell, a first search switch, and a second search switch. The first memory cell is disposed in a first AND-type flash memory cell row. The second memory cell is disposed in a second AND-type flash memory cell row. The first search switch is coupled between a first bit line and a match line corresponding to the first AND-type flash memory cell row and is controlled by a first search signal to be turned on or off. The second search switch is coupled between a second bit line and a match line corresponding to the second AND-type flash memory cell row and is controlled by a second search signal to be turned on or off.

[0009] Based on the above, the present invention combines two memory cells in different AND-type flash memory cell rows in a three-dimensional memory device with corresponding bitline switches to form a ternary content addressable memory cell. The bitline switches function as search switches, reducing the power consumption of the ternary content addressable memory cell during search operations. Furthermore, using the bitline switches as search switches not only saves layout area but also improves reliability, effectively enhancing the overall performance of the ternary content addressable memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 FIG. 1 is a schematic diagram of a ternary content addressable memory cell according to an embodiment of the present invention.

[0011] Figure 2 For the present invention Figure 1 Schematic diagram of an equivalent circuit of a ternary content addressable memory cell 100 according to an embodiment.

[0012] Figures 3A to 5C They are schematic diagrams of implementation methods of a search action of a ternary content addressable storage unit according to an embodiment of the present invention.

[0013] Figure 6A as well as Figure 6B Schematic diagrams of different configurations of a three-dimensional memory device and a search switch of a ternary content addressable memory cell according to embodiments of the present invention.

[0014] Figure 7 Schematic diagrams of different implementations of a three-dimensional memory device and a configuration of a ternary content addressable memory cell according to an embodiment of the present invention.

[0015] Description of Reference Numerals

[0016] 100, 300, 400, 500: Ternary content addressable storage units

[0017] 110, 120: AND type flash memory cell row

[0018] 600, 700: Three-dimensional memory device

[0019] 610, 620, 710, 720: bit line switch area

[0020] BLT1, BLT2: Search switch / bit line switch

[0021] BLT3~BLT8, BLT51~BLT81, BLT52~BLT82: bit line switches

[0022] CT1, CT2: control signals

[0023] GBL: Common Bit Line

[0024] LBL1, LBL2: bit lines

[0025] LSL1, LSL2: source lines

[0026] MC1, MC2: storage units

[0027] ML: Match Line

[0028] SL, SLB: Search signal

[0029] SLT1, SLT2: Source line switches

[0030] TL1, TL2: memory cell array blocks

[0031] VSS: Reference ground voltage

[0032] WL0: word line DETAILED DESCRIPTION

[0033] Please refer to Figure 1, Figure 1 This diagram illustrates a ternary content-addressable memory cell according to one embodiment of the present invention. The ternary content-addressable memory cell 100 is implemented in an AND-type flash memory device. The ternary content-addressable memory cell 100 includes memory cells MC1 and MC2, search switches BLT1 and BLT2, and source line switches SLT1 and SLT2. In this embodiment, the search switches BLT1 and BLT2 and the source line switches SLT1 and SLT2 can all be implemented using transistors, such as N-type transistors. The memory cells MC1 and MC2 can be flash memory cells.

[0034] Memory cells MC1 and MC2 are respectively arranged in different AND-type flash memory cell rows 110 and 120. Search switch BLT1 is coupled between bit line LBL1 corresponding to AND-type flash memory cell row 110 and match line ML. Search switch BLT2 is coupled between bit line LBL2 corresponding to AND-type flash memory cell row 120 and match line ML. In this embodiment, search switches BLT1 and BLT2 serve as bit line switches of the AND-type flash memory device, and match line ML may be a global bit line. Search switch BLT1 is controlled by search signal SL to be turned on or off, while search switch BLT2 is controlled by search signal SLB to be turned on or off. Search signals SL and SLB may have different voltage combinations based on different search conditions. For example, when performing a search operation for a first logic state (e.g., logic 1), the search signals SL and SLB may be logic high and logic low voltages, respectively; when performing a search operation for a second logic state (e.g., logic 0), the search signals SL and SLB may be logic low and logic high voltages, respectively; when performing a search operation for a third logic state (e.g., don't care), the search signals SL and SLB may both be logic low voltages.

[0035] On the other hand, source line switch SLT1 is coupled between source line LSL1 corresponding to flash memory cell row 110 and reference ground voltage VSS. Source line switch SLT2 is coupled between source line LSL2 corresponding to flash memory cell row 120 and reference ground voltage VSS. Source line switches SLT1 and SLT2 are controlled by control signals CT1 and CT2, respectively. When a search operation of ternary content addressable memory cell 100 is performed, source line switches SLT1 and SLT2 are turned on according to control signals CT1 and CT2. Source line switches SLT1 and SLT2 are coupled to a common source line and receive reference ground voltage VSS through the common source line.

[0036] In this embodiment, the memory cells MC1 and MC2 are coupled to the same word line WL0. In other embodiments of the present invention, the memory cells MC1 and MC2 may also be coupled to different word lines, without any particular limitation.

[0037] Please refer to the following Figure 2 , Figure 2 For the present invention Figure 1Schematic diagram of an equivalent circuit of a ternary content-addressable memory cell 100 according to an embodiment. During a search operation, source line switches SLT1 and SLT2 are both turned on, allowing one end of memory cells MC1 and MC2 to receive a reference ground voltage VSS. The other ends of memory cells MC1 and MC2 are coupled to search switches BLT1 and BLT2, respectively. Search switches BLT1 and BLT2 are coupled between memory cells MC1 and MC2 and match line ML. Search switches BLT1 and BLT2 are controlled by search signals SL and SLB, respectively.

[0038] For details on the search action, please refer to Figures 3A to 5C , Figures 3A to 5C Schematic diagrams of the implementation of the search action of the ternary content addressable storage unit according to the embodiment of the present invention. Figures 3A to 3C In the embodiment, ternary content addressable memory cell 300 stores data in a first logic state, wherein memory cell MC1 is in a programmed state and memory cell MC2 is in an erased state. During an initial time interval before a search operation for the first logic state is performed, a match signal on match line ML may be precharged to a reference voltage, where the reference voltage is greater than reference ground voltage VSS.

[0039] exist Figure 3A During the search operation for the first logic state, search signal SL is at a logic high voltage, and search signal SLB is at a logic low voltage. At this point, because memory cell MC1 is turned off and search switch BLT2 is also turned off, there is no conductive path between match line ML and reference ground voltage VSS. Therefore, the match signal on match line ML can be maintained essentially unchanged at the reference voltage. At this point, the search result of the search operation for the first logic state is determined to be a match.

[0040] exist Figure 3B During the search operation for the second logic state, search signal SL is at a logic low voltage, and search signal SLB is at a logic high voltage. At this time, because memory cell MC2 and search switch BLT2 are both in the turned-on state, memory cell MC2 and search switch BLT2 form a conductive path between match line ML and reference ground voltage VSS. Consequently, the match signal on match line ML can drop to equal reference ground voltage VSS. At this point, the search result of the search operation for the second logic state can be determined to be an unmatch.

[0041] exist Figure 3CDuring the third logic state search operation, search signal SL is at a logic low voltage, and search signal SLB is also at a logic low voltage. At this point, because memory cell MC1, search switches BLT2, and BLT1 are all turned off, there is no conductive path between match line ML and reference ground voltage VSS. Therefore, the match signal on match line ML can be maintained essentially unchanged at the reference voltage. At this point, the search result of the third logic state search operation can be determined to be a match.

[0042] exist Figures 4A to 4C In the example, ternary content addressable memory cell 400 stores data in the second logic state, wherein memory cell MC2 is in the programmed state and memory cell MC1 is in the erased state. During an initial time interval before the search operation for the first logic state is performed, the match signal on match line ML can be precharged to a reference voltage. The reference voltage is greater than reference ground voltage VSS.

[0043] exist Figure 4A During the search operation for the first logic state, search signal SL is at a logic high voltage, and search signal SLB is at a logic low voltage. At this point, because memory cell MC1 and search switch BLT1 are both in the turned-on state, a conductive path is formed between memory cell MC1 and search switch BLT1 between match line ML and reference ground voltage VSS. Consequently, the match signal on match line ML can drop to equal reference ground voltage VSS. At this point, the search result of the search operation for the second logic state can be determined to be a mismatch.

[0044] exist Figure 4B During the second logic state search operation, search signal SL is at a logic low voltage, and search signal SLB is at a logic high voltage. At this point, because memory cell MC2 and search switch BLT1 are both turned off, there is no conductive path between match line ML and reference ground voltage VSS. Therefore, the match signal on match line ML remains at the reference voltage and remains unchanged. At this point, the search result of the second logic state search operation is determined to be a match.

[0045] exist Figure 4C During the third logic state search operation, search signal SL is at a logic low voltage, and search signal SLB is also at a logic low voltage. At this point, because memory cell MC2, search switches BLT2, and BLT1 are all turned off, there is no conductive path between match line ML and reference ground voltage VSS. Therefore, the match signal on match line ML can be maintained essentially unchanged at the reference voltage. At this point, the search result of the third logic state search operation can be determined to be a match.

[0046] exist Figures 5A to 5CIn the embodiment, ternary content addressable memory cell 500 stores data in a third logic state, wherein memory cells MC1 and MC2 are both in a programmed state. During an initial time interval before a search operation for the third logic state is performed, a match signal on match line ML may be precharged to a reference voltage, where the reference voltage is greater than reference ground voltage VSS.

[0047] exist Figure 5A During the search operation for the first logic state, search signal SL is at a logic high voltage, and search signal SLB is at a logic low voltage. At this point, because both memory cells MC1 and MC2 are turned off, and search switch BLT2 is also turned off, there is no conductive path between match line ML and reference ground voltage VSS. Therefore, the match signal on match line ML can be maintained essentially unchanged at the reference voltage. At this point, the search result of the search operation for the first logic state can be determined to be a match.

[0048] exist Figure 5B During the second logic state search operation, search signal SL is at a logic low voltage, and search signal SLB is at a logic high voltage. At this point, because memory cells MC1 and MC2 and search switch BLT1 are all in the off state, there is no conductive path between match line ML and reference ground voltage VSS. Therefore, the match signal on match line ML can be maintained essentially unchanged at the reference voltage. At this point, the search result of the third logic state search operation can be determined to be a match.

[0049] exist Figure 5C During the third logic state search operation, search signal SL is at a logic low voltage, and search signal SLB is also at a logic low voltage. At this point, because memory cells MC1 and MC2, and search switches BLT2 and BLT1 are all turned off, there is no conductive path between match line ML and reference ground voltage VSS. Therefore, the match signal on match line ML can be maintained essentially unchanged at the reference voltage. At this point, the search result of the third logic state search operation can be determined to be a match.

[0050] It is worth mentioning that Figures 3A to 5C In an embodiment, the first logic state is complementary to the second logic state, and the third logic state is a don't care. In detail, the first logic state can be a logic 1 (or a logic 0), and the second logic state can be a logic 0 (or a logic 1).

[0051] Furthermore, in other embodiments of the present invention, during the search actions in various states, the voltage values ​​of the search signals SL and SLB may be set differently than described above. Specifically, in other embodiments of the present invention, during the search action in the first logical state, the search signals SL and SLB may be logic low and logic high, respectively; during the search action in the second logical state, the search signals SL and SLB may be logic high and logic low, respectively; and during the search action in the third logical state, the search signals SL and SLB may be logic high. Furthermore, when the ternary content addressable memory cell records data in the third logical state, both memory cells MC1 and MC2 are erased. Under these conditions, during the search action in the logical state, when the match signal on the match line ML remains equal to the reference voltage, the search result indicates a mismatch; and when the match signal on the match line ML drops to the reference ground voltage, the search result indicates a match.

[0052] Please refer to the following Figure 6A as well as Figure 6B , Figure 6A as well as Figure 6B Schematic diagram of different implementations of the configuration of the search switch of the three-dimensional memory device and the ternary content addressable memory cell according to the embodiment of the present invention. Figure 6A In the embodiment, a three-dimensional memory device 600 has a bank comprising a plurality of memory cell array tiles TL1 and TL2. Memory cell array tiles TL1 and TL2 have corresponding bit line switch areas 610 and 620, respectively. Bit line switch area 610 includes bit line switches BLT5-BLT8, while bit line switch area 620 includes bit line switches BLT1-BLT4.

[0053] The three-dimensional memory device 600 may include one or more ternary content addressable memory cells. In this embodiment, corresponding to one of the ternary content addressable memory cells, bit line switches BLT1 and BLT2 may serve as two search switches for the ternary content addressable memory cell. In other words, the two search switches corresponding to the same ternary content addressable memory cell may be provided in the same memory cell array block TL2. Bit line switches BLT1 and BLT2 are controlled by search signals SL and SLB, respectively.

[0054] It is worth mentioning that, in this embodiment, the bit line switches BLT1 ˜ BLT4 and the bit line switches BLT5 ˜ BLT8 may be commonly coupled to a common bit line GBL.

[0055] exist Figure 6BIn the example, the two search switches corresponding to a ternary content addressable memory cell can be bit line switches BLT1 and BLT5. In other words, the two search switches corresponding to the same ternary content addressable memory cell can be respectively disposed in different memory cell array blocks TL1 and TL2. Bit line switches BLT1 and BLT5 are controlled by search signals SL and SLB, respectively.

[0056] Please refer to the following Figure 7 , Figure 7 Schematic diagram of different implementations of the configuration of a three-dimensional memory device and a ternary content addressable memory cell according to an embodiment of the present invention. Figure 7 In the embodiment, a three-dimensional memory device 700 has a bank comprising a plurality of memory cell array tiles TL1 and TL2. Memory cell array tiles TL1 and TL2 have corresponding bit line switch areas 710 and 720, respectively. Bit line switch area 710 includes bit line switches BLT51-BLT81 and BLT52-BLT82, while bit line switch area 720 includes bit line switches BLT11-BLT41 and BLT12-BLT42.

[0057] In this embodiment, a plurality of ternary content addressable memory cells may be provided in the three-dimensional memory device 700. The first ternary content addressable memory cell includes memory cells MC1 and MC2. Memory cells MC1 and MC2 are provided in the same memory cell array block TL2. Furthermore, memory cells MC1 and MC2 are arranged in pairs in two adjacent memory cell rows. Corresponding to memory cells MC1 and MC2, bit line switches BT21 and BT31 may serve as search switches. Bit line switches BT21 and BT31 are commonly coupled to a common bit line GBL. The common bit line GBL may serve as a match line for the ternary content addressable memory cell.

[0058] Furthermore, the second ternary content-addressable memory cell includes memory cells MC3 and MC4. Memory cells MC3 and MC4 are respectively arranged in different memory cell array blocks TL1 and TL2. Corresponding to memory cells MC3 and MC4, bit line switches BT12 and BT52 can function as search switches. Notably, bit line switches BT12 and BT52 are commonly coupled to a common bit line GBL, which serves as a match line for this ternary content-addressable memory cell.

[0059] It is worth noting that in embodiments of the present invention, a three-dimensional memory device may include one or more ternary content-addressable memory cells. The three-dimensional memory device may include multiple memory cell array blocks. The multiple ternary content-addressable memory cells may all be located within a single memory cell array block, or they may be distributed across multiple different memory cell array blocks, without any particular limitation.

[0060] In summary, the ternary content addressable storage cell of the present invention is provided in an AND-type flash memory device. By utilizing a bit line switch as a search switch and utilizing a common bit line as a match line, the voltage of the search signal received by the search switch can be lower than the voltage of the corresponding word line, thereby saving the required power consumption. In addition, a single bit line switch can be constructed using a single transistor. Furthermore, without the need to increase the voltage of the search signal, the setting of a voltage shifter circuit can be eliminated, effectively reducing the circuit area. In addition, during the search operation, the search switch provides at most one current path to pass through the corresponding bit line, effectively improving the reliability of the circuit.

Claims

1. A ternary content addressable storage unit, comprising: a first memory cell disposed in a first AND-type flash memory cell row; a second memory cell disposed in a second AND-type flash memory cell row; a first search switch coupled between a first bit line corresponding to the first AND-type flash memory cell row and a match line, the first search switch being controlled by a first search signal to be turned on or off; and a second search switch coupled between a second bit line corresponding to the second AND-type flash memory cell row and the match line, the second search switch being controlled by a second search signal to be turned on or off; wherein the data stored in the ternary content addressable memory cell is in a first logic state in response to the first memory cell being in a programmed state and the second memory cell being in an erased state; wherein the data stored in the ternary content addressable memory cell is in a second logic state in response to the first memory cell being in an erased state and the second memory cell being in a programmed state; In response to the first memory cell and the second memory cell being in a programmed state, the data stored in the ternary content addressable memory cell is in a third logic state.

2. The ternary content addressable storage unit according to claim 1 , further comprising: a first source line switch coupled between a first source line corresponding to the first AND-type flash memory cell row and a reference ground voltage, the first source line switch being controlled by a control signal to be turned on or off; as well as A second source line switch is coupled between a second source line corresponding to the second AND-type flash memory cell row and the reference ground voltage. The second source line switch is controlled by the control signal to be turned on or off. 3 . The ternary content addressable memory cell according to claim 1 , wherein the first memory cell and the second memory cell are coupled to the same word line, or are respectively coupled to two different word lines.

4. The ternary content addressable storage unit according to claim 1 , wherein the first search switch comprises: a first transistor, wherein a first terminal of the first transistor is coupled to the first bit line, a second terminal of the first transistor is coupled to the match line, and a control terminal of the first transistor receives the first search signal; The second search switch includes: A second transistor has a first terminal coupled to the second bit line, a second terminal coupled to the match line, and a control terminal of the second transistor receiving the second search signal. 5 . The ternary content addressable memory cell according to claim 1 , wherein during an initial time interval of a search operation, a match signal of the match line is precharged to a reference voltage. 6 . The ternary content addressable memory cell according to claim 1 , wherein the match line is a common bit line of an AND-type flash memory bank.

7. A three-dimensional memory device comprising: An AND-type flash memory bank includes at least one memory cell array block; as well as At least one ternary content addressable storage unit comprising: a first memory cell disposed in a first AND-type flash memory cell row; a second memory cell disposed in a second AND-type flash memory cell row; a first search switch coupled between a first bit line corresponding to the first AND-type flash memory cell row and a match line, the first search switch being controlled by a first search signal to be turned on or off; and a second search switch coupled between a second bit line corresponding to the second AND-type flash memory cell row and the match line, the second search switch being controlled by a second search signal to be turned on or off; wherein the data stored in the ternary content addressable memory cell is in a first logic state in response to the first memory cell being in a programmed state and the second memory cell being in an erased state; wherein the data stored in the ternary content addressable memory cell is in a second logic state in response to the first memory cell being in an erased state and the second memory cell being in a programmed state; In response to the first memory cell and the second memory cell being in a programmed state, the data stored in the ternary content addressable memory cell is in a third logic state.

8. The three-dimensional memory device according to claim 7 , wherein the first AND-type flash memory cell row and the second AND-type flash memory cell row are located in the same first memory cell array block, or the first AND-type flash memory cell row and the second AND-type flash memory cell row are located in different first memory cell array blocks and second memory cell array blocks, respectively.

9. The three-dimensional memory device according to claim 7, wherein the first search switch and the second search switch are disposed in the same first memory cell array block, or are disposed in different first memory cell array blocks and the second memory cell array blocks respectively.

10. The three-dimensional memory device according to claim 7, wherein the at least one ternary content addressable memory cell further comprises: a first source line switch coupled between a first source line corresponding to the first AND-type flash memory cell row and a reference ground voltage, the first source line switch being controlled by a control signal to be turned on or off; as well as A second source line switch is coupled between a second source line corresponding to the second AND-type flash memory cell row and the reference ground voltage. The second source line switch is controlled by the control signal to be turned on or off.

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