Semiconductor memory device and erase verification method

Abstract

The present application relates to a semiconductor memory device and a method of verifying erasure. A semiconductor memory device according to an embodiment includes a memory block having first to third control signal lines connected to gates of a first selection gate transistor, a plurality of memory cell transistors, and a second selection gate transistor, respectively; a resistance measuring circuit that measures resistance of at least one of the first to third control signal lines; and a control circuit that performs erasure, programming, and reading of data with respect to the plurality of memory cell transistors included in the memory block; the control circuit determines whether a result of erasure check that verifies the erasure is in a fail state based on a measurement result of the resistance measurement by the resistance measuring circuit.

Description

Semiconductor memory devices and erasure verification methods

[0001] [Cross-reference to related applications]

[0002] This application claims priority based on the priority of a prior Japanese patent application No. 2021-144217 filed on September 3, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor memory device and an erasure verification method. Background Technology

[0004] In recent years, three-dimensional structures have been achieved for semiconductor memory devices such as NAND (Not AND) memory to meet the requirements of miniaturization and large capacity. Furthermore, in these semiconductor memory devices, there are not only SLC (Single Level Cell) configurations where the memory cell transistors are configured to store 1 bit (2-value) data, but also MLC (Multi Level Cell) configurations that can store 2 bits (4-value) data, TLC (Triple Level Cell) configurations that can store 3 bits (8-value) data, or QLC (Quad Level Cell) configurations that can store 4 bits (16-value) data.

[0005] In such semiconductor memory devices, high resistance in word lines and other components can lead to read errors. Summary of the Invention

[0006] One embodiment provides a semiconductor memory device and an erasure verification method capable of suppressing read failures.

[0007] A semiconductor memory device according to an embodiment includes: a memory block configured to include a plurality of memory strings, a first control signal line, a plurality of second control signal lines, a third control signal line, and a plurality of bit lines; the plurality of memory strings include a first select-gate transistor, a plurality of memory cell transistors, and a second select-gate transistor connected in series; the first control signal lines are commonly connected to the gates of the first select-gate transistors of the plurality of memory strings; the plurality of second control signal lines are each commonly connected to the gates of the memory cell transistors in the same row of the plurality of memory strings; the third control signal lines are each commonly connected to the gates of the second select-gate transistors of the plurality of memory strings; and the plurality of bit lines are respectively connected to the plurality of memory strings; a resistance measuring circuit for measuring the resistance of at least one of the first to third control signal lines; and a control circuit for erasing, programming, and reading data from the plurality of memory cell transistors included in the memory block; the control circuit determines, based on the resistance measurement result of the resistance measuring circuit, whether to set the erase verification result of the erase verification to a failed state.

[0008] Based on the aforementioned configuration, a semiconductor memory device and an erasure verification method can be provided that can suppress the occurrence of read errors. Attached Figure Description

[0009] Figure 1 is a block diagram showing an example of the configuration of a memory system according to an implementation method.

[0010] Figure 2 is a block diagram showing an example of the configuration of the non-volatile memory in this embodiment.

[0011] Figure 3 is a diagram showing an example of the block configuration of a three-dimensional NAND memory cell array 23.

[0012] Figure 4 is a cross-sectional view of a portion of a three-dimensional NAND memory cell array.

[0013] Figure 5 is a block diagram illustrating an example of the sensing amplifier 24 in Figure 2.

[0014] Figure 6 is a block diagram illustrating an example of the line decoder 25 in Figure 2.

[0015] Figure 7 is a circuit diagram showing the configuration of a voltage generation circuit 28 that includes a resistance measurement circuit for measuring the resistance value of a control signal line.

[0016] Figure 8 is a circuit diagram showing an example of the specific configuration of the resistance measuring circuit 42 in Figure 7.

[0017] Figure 9 is a diagram illustrating the use of resistance measuring circuit 42 and logic circuit 43 to measure the resistance of the control signal line.

[0018] Figure 10 is a circuit diagram showing the equivalent circuit of the control signal line.

[0019] Figure 11 is a flowchart used to determine the status of the erase verification. Detailed Implementation

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0021] (First Embodiment)

[0022] This implementation determines the erase state based on the resistance of control signal lines such as word lines, thereby suppressing read errors. When new data is to be written to the semiconductor memory device, the data within the block is erased by an erase operation, and the required data is written to the memory cell by a programming operation. During the erase operation, verification is performed to confirm whether the erase was performed correctly (erase verification). Additionally, during the programming operation, verification is performed to confirm whether the programming was performed correctly (programming verification). The verification result is obtained in the form of a pass status indicating success or a fail status indicating failure.

[0023] Furthermore, sometimes poor contact can cause control signal lines, such as word lines, to become highly resistive. For example, source-side select gate lines with contacts formed at the substrate end are prone to poor contact. However, even if such poor contact occurs, the source-side select gate may still be partially turned on due to coupling effects, resulting in a pass during erase and program verification. In this case, when reading data by precisely controlling the voltage applied to the word line, the read data may contain uncorrectable errors.

[0024] Therefore, in this embodiment, the resistance of the control signal line is detected after the erase operation, and the state is determined, thereby suppressing uncorrectable errors during reading.

[0025] (The structure of a memory system)

[0026] Figure 1 is a block diagram showing an example configuration of the memory system according to the embodiment. The memory system of this embodiment includes a memory controller 1 and non-volatile memory 2. The memory system can be connected to a host computer. The host computer is, for example, an electronic device such as a personal computer or a mobile terminal.

[0027] Non-volatile memory 2 is a semiconductor memory device that stores data non-volatilely, such as a NAND flash memory. In this embodiment, non-volatile memory 2 is described as a NAND flash memory having memory cell transistors capable of storing 3 bits per cell, i.e., a 3-bit / cell (TLC) Triple Level Cell NAND flash memory, but it is not limited to this. Non-volatile memory 2 is three-dimensional.

[0028] The memory controller 1 is connected to the non-volatile memory 2 via a NAND bus. The memory controller 1 controls the writing of data to the non-volatile memory 2 based on write requests from the host. Additionally, the memory controller 1 controls the reading of data from the non-volatile memory 2 based on read requests from the host. The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correct) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0029] The host interface 13 outputs requests received from the host, write data, etc., to the internal bus 16. In addition, the host interface 13 sends data read from the non-volatile memory 2, responses from the processor 12, etc., to the host.

[0030] The memory interface 15 controls the processes of writing data to the non-volatile memory 2 based on the instructions of the processor 12, and the processes of reading data from the non-volatile memory 2.

[0031] Processor 12 provides overall control over memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. When processor 12 receives a request from the host via host interface 13, it performs control according to that request. For example, processor 12, upon receiving a request from the host, instructs memory interface 15 to write data and parity information to non-volatile memory 2. Additionally, processor 12, upon receiving a request from the host, instructs memory interface 15 to read data and parity information from non-volatile memory 2.

[0032] Processor 12 determines a storage region (hereinafter referred to as a storage region) on non-volatile memory 2 for the data stored in RAM 11. Data is stored in RAM 11 via internal bus 16. Processor 12 determines the storage region for page data, i.e., page data, which is written as a unit. In this specification, the data stored in one page of non-volatile memory 2 is defined as unit data. Unit data is stored in non-volatile memory 2, for example, in the form of codewords after being encoded.

[0033] Furthermore, encoding is not always necessary. The memory controller 1 can also store unit data in the non-volatile memory 2 without encoding, but Figure 1 shows an example of an encoding configuration. When the memory controller 1 does not encode, the page data is identical to the unit data. Alternatively, a codeword can be generated based on a single unit data, or it can be generated based on the segmented data resulting from dividing the unit data. Furthermore, a codeword can also be generated using multiple units of data.

[0034] Processor 12 determines the storage region of non-volatile memory 2 as the destination for each unit of data. A physical address is allocated to the storage region of non-volatile memory 2. Processor 12 uses physical addresses to manage the storage region as the destination for each unit of data. Processor 12 instructs memory interface 15 to specify the physical address of the determined storage region and write the data to non-volatile memory 2. Processor 12 manages the correspondence between the logical address (the logical address managed by the host) and the physical address of the data. When processor 12 receives a read request containing a logical address from the host, it specifies the physical address corresponding to the logical address, and after specifying the physical address, instructs memory interface 15 to read the data.

[0035] ECC circuit 14 encodes the data stored in RAM 11 to generate codewords. In addition, ECC circuit 14 decodes the codewords read from non-volatile memory 2.

[0036] RAM 11 temporarily stores the data received from the host before storing it in non-volatile memory 2, or temporarily stores the data read from non-volatile memory 2 before sending it to the host. RAM 11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0037] Figure 1 shows an example configuration of the memory controller 1, which includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can be integrated into the non-volatile memory 2.

[0038] Upon receiving a write request from the host, the memory controller 1 operates as follows: The processor 12 temporarily stores the write data in RAM 11. The processor 12 reads the data stored in RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and provides the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the non-volatile memory 2.

[0039] Upon receiving a read request from the host, the memory controller 1 operates as follows: The memory interface 15 provides the codeword read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 sends the data stored in the RAM 11 to the host via the host interface 13.

[0040] (The structure of non-volatile memory)

[0041] Figure 2 is a block diagram showing an example of the configuration of the non-volatile memory according to this embodiment. The non-volatile memory 2 includes a logic control circuit 21, an input / output circuit 22, a memory cell array 23, a sense amplifier 24, a line decoder 25, a register 26, a sequencer 27, a voltage generation circuit 28, an input / output pad group 32, a logic control pad group 34, and a power input terminal group 35.

[0042] The memory cell array 23 comprises multiple blocks (memory blocks). Each block BLK comprises multiple memory cell transistors (memory cells). Multiple bit lines, multiple word lines, and source lines are provided in the memory cell array 23 to control the voltage applied to the memory cell transistors. The specific structure of the block BLK will be described below.

[0043] The input / output pad group 32 has multiple terminals (pads) corresponding to the signals DQ<7:0> and data strobe signals DQS and / DQS, so as to transmit and receive signals containing data with the memory controller 1.

[0044] The logic control pad group 34 has multiple terminals (pads) corresponding to the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protection signal / WP, so as to transmit and receive various signals with the memory controller 1. The " / " appended to the signal name indicates that it is active low.

[0045] The / CE signal enables selection of non-volatile memory 2. The CLE signal latches the instruction sent as the DQ signal into the instruction register. The ALE signal latches the address sent as the DQ signal into the address register. The / WE signal enables writing. The RE signal enables reading. The / WP signal disables writing and erasing. The R / B signal indicates whether non-volatile memory 2 is in a ready state (able to accept commands from external sources) or a busy state (unable to accept commands from external sources). Memory controller 1 can understand the status of non-volatile memory 2 by receiving the R / B signal.

[0046] The power input terminal group 35 has multiple terminals for inputting power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss, so as to supply various operating power supplies to the non-volatile memory 2 from the outside. The power supply voltage Vcc is the circuit power supply voltage that is normally supplied externally as the operating power supply, for example, a voltage of about 3.3V can be input. The power supply voltage VccQ, for example, can input a voltage of 1.2V. The power supply voltage VccQ is used when transmitting and receiving signals between the memory controller 1 and the non-volatile memory 2. The power supply voltage Vpp is a power supply voltage that is higher than the power supply voltage Vcc, for example, a voltage of 12V can be input.

[0047] The logic control circuit 21 and the input / output circuit 22 are connected to the memory controller 1 via a NAND bus. The input / output circuit 22 and the memory controller 1 communicate via the NAND bus to send and receive signals DQ (e.g., DQ0 to DQ7).

[0048] The logic control circuit 21 receives external control signals (such as chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protection signal / WP) from the memory controller 1 via the NAND bus. Additionally, the logic control circuit 21 sends a ready / busy signal R / B to the memory controller 1 via the NAND bus.

[0049] Register 26 includes an instruction register, an address register, and a status register. The instruction register temporarily stores instructions. The address register temporarily stores addresses. The status register temporarily stores data required for the operation of the non-volatile memory 2. Register 26 may contain, for example, SRAM.

[0050] The sequencer 27, acting as a control circuit, receives instructions from the register 26 and controls the non-volatile memory 2 according to the program based on those instructions.

[0051] The voltage generation circuit 28 receives a power supply voltage from the external source of the non-volatile memory 2 and uses this power supply voltage to generate multiple voltages required for write, read, and erase operations. The voltage generation circuit 28 supplies the generated voltages to the memory cell array 23, the sense amplifier 24, and the line decoder 25, etc.

[0052] The row decoder 25 receives the row address from register 26 and decodes it. Based on the decoded row address, the row decoder 25 performs word line selection. Then, the row decoder 25 transmits the multiple voltages required for write, read, and erase operations to the selected block.

[0053] The sense amplifier 24 receives the column address from the register 26 and decodes it. Based on the decoded column address, the sense amplifier 24 selects any bit line. Additionally, during data readout, the sense amplifier 24 detects and amplifies the data read from the memory cell transistor to the bit line. Furthermore, during data writeout, the sense amplifier 24 writes the data to the bit line.

[0054] The sensing amplifier 24 includes a sensing amplifier assembly group 24A and a data register 24B. During data readout, the data register 24B temporarily stores the data detected by the sensing amplifier 24 and transmits the data to the input / output circuit 22. Additionally, during data writeout, the data register 24B temporarily stores data continuously transmitted from the input / output circuit 22 and transmits the data to the sensing amplifier 24. The data register 24B includes SRAM, etc.

[0055] (Block structure of a memory cell array)

[0056] Figure 3 is a diagram showing an example of the block configuration of a three-dimensional NAND memory cell array 23. Figure 3 shows one block BLK among the multiple blocks constituting the memory cell array 23. The other blocks of the memory cell array also have the same configuration as in Figure 3. Furthermore, this embodiment can also be applied to two-dimensional memory cell arrays.

[0057] As shown in the figure, the block BLK, for example, contains four string components (SU0 to SU3). Each string component SU contains multiple NAND strings NS. Here, each NAND string NS, serving as a memory string, contains eight memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. Furthermore, the number of memory cell transistors MT in the NAND string NS is eight, but not limited to eight; for example, it could be 32, 48, 64, or 96. The select gate transistors ST1 and ST2 are represented as one transistor in the electrical circuit, but their construction can be the same as the memory cell transistors. Additionally, for example, to improve cutoff characteristics, multiple select gate transistors can be used as select gate transistors ST1 and ST2. Furthermore, a dummy cell transistor can be placed between the memory cell transistors MT and the select gate transistors ST1 and ST2.

[0058] The memory cell transistor MT is configured in series between the select gate transistors ST1 and ST2. The memory cell transistor MT7 on one side is connected to the select gate transistor ST1, and the memory cell transistor MT0 on the other side is connected to the select gate transistor ST2.

[0059] The gates of the select gate transistors ST1 for each of the string components SU0 to SU3 are respectively connected to select gate lines SGD0 to SGD3. On the other hand, the gates of the select gate transistors ST2 are shared by multiple string components SU within the same block BLK and connected to the same select gate line SGS. Furthermore, the gates of the memory cell transistors MT0 to MT7 within the same block BLK are shared by word lines WL0 to WL7. That is, word lines WL0 to WL7 and select gate line SGS are shared by multiple string components SU0 to SU3 within the same block BLK. In contrast, the select gate line SGD is independent for each of the string components SU0 to SU3, even within the same block BLK.

[0060] The gates of the memory cell transistors MT0 to MT7 that constitute the NAND string NS are connected to word lines WL0 to WL7, respectively. The gates of the memory cell transistors MTi located in the same row within block BLK are connected to the same word line WLi. Furthermore, in the following description, the NAND string NS may sometimes be simply referred to as "string".

[0061] Each NAND string NS is connected to its corresponding bit line. Therefore, each memory cell transistor MT is connected to the bit line via the select gate transistor ST1, ST2, or other memory cell transistor MT contained in the NAND string NS. As described above, the data of the memory cell transistor MT located within the same block BLK is erased once. On the other hand, data reading and writing are performed in units of memory cell groups MG (or in units of pages). In this specification, a group of memory cell transistors MT connected to one word line WLi and belonging to one string assembly SU is defined as a memory cell group MG. In this embodiment, the non-volatile memory 2 is a TLC-type NAND memory capable of storing 3 bits (8 values) of data. Therefore, one memory cell group MG can store 3 pages of data. The 3 bits that each memory cell transistor MT can store correspond to the 3 pages.

[0062] Furthermore, since the state of the select gate transistors ST1 and ST2 is controlled by the select gate lines SGD and SGS, and the state of the memory cell transistors MT0 to MT7 is controlled by the word lines WL0 to WL7, these select gate lines SGD and SGS, and word lines WL0 to WL7 are also called control signal lines.

[0063] Figure 4 is a cross-sectional view of a portion of the three-dimensional NAND memory cell array. As shown in Figure 4, multiple NAND strings NS are formed in the D1 direction on the p-well region. That is, multiple wiring layers 333 functioning as select gate lines (SGS), multiple wiring layers 332 functioning as word lines (WLi), and multiple wiring layers 331 functioning as select gate lines (SGD) are stacked on the p-well region.

[0064] Furthermore, a memory via 334 is formed, penetrating these wiring layers 333, 332, and 331 and reaching the p-type well region. On the side of the memory via 334, a barrier insulating film 335, a charge storage film (charge storage region) 336, and a gate insulating film 337 are sequentially formed, and a conductive pillar 338 is embedded within the memory via 334. The conductive pillar 338, for example, comprises polysilicon and functions as a region forming a channel when the memory cell transistor MT and the select gate transistors ST1 and ST2 contained in the NAND string NS are operated. That is, wiring layer 331, conductive pillar 338, and the films 335-337 between them function as select gate transistor ST1, wiring layer 332, conductive pillar 338, and the films 335-337 between them function as memory cell transistor MT, and wiring layer 333, each conductive pillar 338, and the films 335-337 between them function as select gate transistor ST2.

[0065] Furthermore, in Figure 4, the memory hole 334 and the conductive post 338 are shown as cylindrical shapes of the same diameter, but in reality, they have a wedge shape in which the diameter tapers towards the p-type well region. Additionally, depending on the manufacturing process, the memory hole 334 and the conductive post 338 may also have a multi-segment wedge shape in which the diameter expands midway through the wedge shape and then tapers again towards the p-type well region.

[0066] In each NAND string NS, a select gate transistor ST2, multiple memory cell transistors MT, and a select gate transistor ST1 are sequentially formed in the p-type well region. A wiring layer, functioning as a bit line BL, is formed on the side above the conductor post 338 (in the D3 direction). A contact plug 339, connecting the conductor post 338 to the bit line BL, is formed at the upper end of the conductor post 338.

[0067] Furthermore, an n+ type impurity diffusion layer and a p+ type impurity diffusion layer are formed within the surface of the p-type well region. A contact plug 340 is formed on the n+ type impurity diffusion layer, and a wiring layer that functions as the source line SL is formed on the contact plug 340.

[0068] In the depth direction (D2 direction) of the paper in Figure 4, there are multiple structures as shown in Figure 4 above, and a string component SU is formed by a collection of multiple NAND strings arranged in a row in the depth direction.

[0069] (Sensing amplifier)

[0070] Figure 5 is a block diagram illustrating an example of the sensing amplifier 24 in Figure 2.

[0071] The sensing amplifier 24 includes a sensing amplifier assembly group 24A and a data register 24B. The sensing amplifier assembly group 24A includes sensing amplifier assemblies SAU0 to SAU(m-1) corresponding to bit lines BL0 to BL(m-1). Each sensing amplifier assembly SAU includes a sensing amplifier section SA and data latch circuits SDL, ADL, BDL, and CDL. The sensing amplifier section SA and the data latch circuits SDL, ADL, BDL, and CDL are connected in a manner that enables data transmission between them.

[0072] The data latch circuits SDL, ADL, BDL, and CDL temporarily store data. During a write operation, the sense amplifier section SA controls the voltage of the bit line BL based on the data stored in the data latch circuit SDL. The data latch circuits ADL, BDL, and CDL are used for multi-value operations where the memory cell transistor MT stores more than 2 bits of data. That is, the data latch circuit ADL is used to store the next bit page, the data latch circuit BDL is used to store the middle bit page, and the data latch circuit CDL is used to store the next bit page. The number of data latch circuits in the sense amplifier assembly SAU can be arbitrarily changed depending on the number of bits stored by one memory cell transistor MT.

[0073] During a read operation, the sensing amplifier section SA detects the data read onto the corresponding bit line BL and determines whether the data is "0" or "1". Conversely, during a write operation, the sensing amplifier section SA applies a voltage to the bit line BL based on the data being written.

[0074] Data register 24B includes data latch circuits XDL, the number of which corresponds to the number of sense amplifier components SAU0 to SAU(m-1). The data latch circuits XDL are connected to input / output circuit 21. The data latch circuits XDL are used for data transmission between the sense amplifier 24 and external devices, temporarily storing write data transmitted from input / output circuit 21 and read data transmitted from sense amplifier components SAU. More specifically, data transmission between input / output circuit 21 and sense amplifier components SAU0 to SAU(m-1) is performed via one page of data latch circuit XDL. Write data received by input / output circuit 21 is transmitted via data latch circuit XDL to any one of data latch circuits ADL, BDL, or CDL. Read data read by sense amplifier section SA is transmitted to input / output circuit 21 via data latch circuit XDL.

[0075] (Line decoder)

[0076] Figure 6 is a block diagram illustrating an example of the line decoder 25 in Figure 2.

[0077] The voltage generation circuit 28 includes multiple SG drivers (select gate line drivers) 29A that supply voltage to signal lines SG0 to SG4, and multiple CG drivers (word line drivers) 29B that supply voltage to signal lines CG0 to CG7. Hereinafter, without distinguishing between SG drivers 29A and CD drivers 29B, they will be referred to as drivers 29. These control signal lines SG0 to SG4 and CG0 to CG7 are branched by the line decoder 25 and connected to the wiring of each BLK block. That is, signal lines SG0 to SG3 function as global drain-side select gate lines and are connected via the line decoder 25 to the select gate lines SGD0 to SGD3 in each BLK block as local select gate lines. Signal lines CG0 to CG7 function as global word lines and are connected via the line decoder 25 to the word lines WL0 to WL7 in each BLK block as local word lines. Signal line SG4 functions as a global source-side select gate line and is connected to each BLK block as a local select gate line SGS via line decoder 25.

[0078] That is, signal lines SG0~SG4 and CG0~CG7 become the select gate lines SGD0~SGD3 and word lines WL0~WL7, respectively, used to control the state of select gate transistors ST1 and ST2 and memory cell transistor MT. Therefore, these signal lines SG0~SG4 and CG0~CG7 will also be referred to as global control signal lines below.

[0079] The voltage generation circuit 28, controlled by the sequencer 27, generates various voltages. The SG driver 29A and CG driver 29B supply the generated voltages to the corresponding signal lines SG0-SG4 and CG0-CG7, respectively. For example, each CG driver 29B selects voltages such as VCGRV, VREAD, and VCG_ER according to the action object (row address) in the read operation and supplies them to the corresponding word line WL.

[0080] The line decoder 25 includes: multiple switch circuit groups 25A corresponding to each block, and multiple block decoders 25B respectively configured to correspond to the multiple switch circuit groups 25A. Each switch circuit group 25A includes: multiple transistors TR_SG0 to TR_SG3, connecting signal lines SG0 to SG3 to select gate lines SGD0 to SGD3 respectively; multiple transistors TR_CG0 to TR_CG7, connecting signal lines CG0 to CG7 to word lines WL0 to WL7 respectively; and transistor TR_SG4, connecting signal line SG4 to select gate line SGS. Transistors TR_SG0 to TR_SG4 and transistors TR_CG0 to TR_CG7 are all high-voltage transistors.

[0081] When each block decoder 25B is specified by a row address, it supplies the block selection signal BLKSEL to the gates of transistors TR_SG0 to TR_SG4 and transistors TR_CG0 to TR_CG7. As a result, in the switching circuit group 25A in which the block decoder 25B specified by the row address supplies the block selection signal BLKSEL, transistors TR_SG0 to TR_SG4 and transistors TR_CG0 to TR_CG7 are turned on and conducted. Therefore, the voltage supplied from the power generation circuit 28 to the signal lines SG0 to SG4 and signal lines CG0 to CG7 is supplied to the selection gate lines SGD0 to SGD3, SGS and word lines WL0 to WL7 contained in the block BLK to be operated.

[0082] That is, the voltage generation circuit 28 and the line decoder 25 supply various voltages required for operation to each word line WL. In addition, for example, the voltage VSGD is supplied to the selection gate line SGD (SGDsel) connected to the selection gate transistor ST1 of the string component SU which is the target of operation, the voltage Vss is supplied to the selection gate line SGD (SGDusel) connected to the selection gate transistor ST1 of the string component SU which is not the target of operation, and the voltage VSGS is supplied to the selection gate line SGS of each BLK which is connected to the selection gate transistor ST2.

[0083] (Programming action)

[0084] When writing multi-valued data to the memory cell transistor MT, the threshold voltage of the memory cell transistor MT is made to correspond to the value of the data. When a programming voltage VPGM and a bit line voltage VBL are applied to the memory cell transistor MT, electrons are injected into the charge accumulation film 336, causing the threshold voltage to rise. By increasing the programming voltage VPGM, the amount of electron injection is increased, thereby increasing the threshold voltage of the memory cell transistor MT. However, because memory cell transistors MT differ, even when the same programming voltage VPGM is applied, the amount of electron injection for each memory cell transistor MT is different. The temporarily injected electrons are retained until the erase operation is performed. Therefore, the programming voltage VPGM is gradually increased while performing multiple programming and verification operations (loops) in a manner that does not exceed the threshold voltage range (hereinafter referred to as the target region) that is permissible for the threshold voltage set for each memory cell transistor MT.

[0085] Next, data is read after the programming operation to perform a verification operation to determine whether the threshold voltage of the memory cell transistor has reached the target region. By repeatedly executing the above combination of programming and verification operations, the threshold voltage of the memory cell transistor rises to the target region. Memory cell transistors whose threshold voltage has been determined to have reached the target region (i.e., exceeded the target level, which is the minimum value of the target region) through the verification operation are then prevented from being written to.

[0086] (Read the action aloud)

[0087] Data is read from the multi-valued memory cell transistors as follows: a readout voltage is applied to the word line (hereinafter referred to as the select word line) WL connected to the memory cell transistor MT to be read out using the line decoder 25, and the data read out to the bit line BL is sensed using the sense amplifier 24 to determine whether the readout data is "0" or "1". Furthermore, to turn on the memory cell transistors connected to word lines other than the select word line (hereinafter referred to as the non-select word line) WL, the line decoder 25 supplies a sufficiently high voltage VREAD to the non-select word line WL to turn on each memory cell transistor.

[0088] During the readout operation, the sensing amplifier 24 fixes the bit line BL at a certain voltage (e.g., 0.5V) and charges the sensing node SEN (not shown) inside the sensing amplifier section SA to a predetermined precharge voltage Vpre higher than the voltage of the bit line BL. In this state, the sensing amplifier 24 electrically connects the sensing node SEN to the bit line BL. As a result, current flows from the sensing node SEN into the bit line BL, and the voltage of the sensing node SEN slowly decreases.

[0089] The voltage at the sensing node SEN changes based on the threshold voltage of the memory cell transistor connected to the corresponding bit line BL. Specifically, when the threshold voltage of the memory cell transistor is lower than the read voltage, the transistor is on, a larger cell current flows into it, and the voltage at the sensing node SEN decreases more rapidly. Conversely, when the threshold voltage of the memory cell transistor is higher than the read voltage, it is off, a smaller cell current flows into it, or no current flows at all, and the voltage at the sensing node SEN decreases more slowly.

[0090] By utilizing the rate of voltage decrease at the sensing node SEN, the write state of the memory cell transistor is determined, and the result is stored in the data latch circuit. For example, at the first point in a predetermined period after the start of discharge from the sensing node SEN, it is determined whether the voltage of the sensing node SEN is low (hereinafter "L") or high (hereinafter "H"). For example, if the threshold voltage of the memory cell transistor is lower than the read voltage, the memory cell transistor is fully turned on, and a large cell current flows into the memory cell transistor. Therefore, the voltage of the sensing node SEN decreases rapidly, and the voltage drop is relatively large. At the first point in time, the sensing node SEN becomes "L".

[0091] Furthermore, when the threshold voltage of the memory cell transistor is higher than the read voltage, the memory cell transistor is in the off state, and the cell current flowing into the memory cell transistor is very small, or no cell current flows into the memory cell transistor. Therefore, the voltage of the sensing node SEN decreases very slowly, and the voltage drop is relatively small. At point 1, the sensing node SEN remains at "H".

[0092] In this way, while applying a readout voltage to the select word line using the line decoder 25, the state of the sensing node SEN is monitored by the sensing amplifier 24 to determine whether the threshold voltage of the memory cell transistor is higher or lower than the readout voltage. Therefore, by applying the voltage between each level as the readout voltage to the select word line WL, the level of each memory cell transistor can be determined, and the data assigned to each level can be read.

[0093] (Erase verification)

[0094] During erasure, a specified high-voltage pulse (hereinafter referred to as the erase pulse) is applied to the source line SL. This discharges the charge stored in the charge storage film 336 of each memory cell transistor MT in the NAND string NS, restoring the threshold voltage of all memory cell transistors MT to the Er level (erasure level).

[0095] An erase check is performed to confirm whether the memory cell transistor MT has reached the Er level. The erase check is performed by applying an erase check voltage VCG_ER, higher than the Er level, to the gate of each memory cell transistor MT. A voltage VSGS is applied to the gate of select gate transistor ST2 to turn it on. On the other hand, a voltage VSGD is applied to select gate transistor ST1 to turn on only the gate of select gate transistor ST1 that constitutes the NAND string being checked, and a voltage VSS is applied to turn off the gate of other select gate transistors ST1. That is, the erase check is performed on each NAND string NS.

[0096] The sensing amplifier 24 fixes the bit line BL at a certain voltage (e.g., 0.5V) and charges the sensing node SEN (not shown) inside the sensing amplifier section SA to a predetermined precharge voltage Vpre higher than the voltage of the bit line BL. In this state, the sensing amplifier 24 connects the sensing node SEN to the bit line BL. As a result, current flows from the sensing node SEN into the bit line BL, and the voltage of the sensing node SEN decreases slowly.

[0097] When the threshold voltage of all memory cell transistors MT in the NAND string NS, which is the target of the erase verification, is at the Er level, when the erase verification voltage VCG_ER is applied to the gate of the memory cell transistor MT, all memory cell transistors MT become on, a large cell current flows into the memory cell transistor MT, and the voltage of the sensing node SEN decreases faster.

[0098] On the other hand, if the threshold voltage of any memory cell transistor MT has not recovered to the Er level, the memory cell transistor MT is in an off state, the current flowing into the memory cell transistor MT, that is, the current flowing into the bit line BL, is small or no, and the voltage of the sensing node SEN decreases more slowly.

[0099] Therefore, it can be determined that if the voltage of the sensing node SEN decreases rapidly, the erasure of the NAND string NS of the erasure verification object is successful; if the voltage of the sensing node SEN decreases slowly, there is a memory cell transistor MT in the NAND string NS of the erasure verification object that has not recovered to the Er level, and the erasure fails. In this case, erasure is performed by repeatedly applying erasure pulses and performing erasure verification. When the result is successful erasure, a pass state is obtained. On the other hand, for example, if the erasure fails even after applying erasure pulses and performing erasure verification a specified number of times, the erasure fails, and an erasure failure state is obtained. The pass and failure states are stored in registers by the processor 12 and transmitted to the host as needed.

[0100] For example, if the select gate line SGS, which supplies the voltage VSGS used to turn on the select gate transistor ST2, becomes highly resistive due to poor contact, the erase check should normally fail. However, as mentioned above, the select gate transistor ST2 may sometimes be turned on to some extent due to coupling, thus making the erase check pass.

[0101] Therefore, in this embodiment, when an erase pass state occurs, the resistance value of the control signal line is measured, and the pass state is determined based on the measured resistance value.

[0102] (Resistance Measurement)

[0103] Figure 7 is a circuit diagram showing the configuration of a voltage generation circuit 28, which includes a resistance measuring circuit for measuring the resistance value of a control signal line. Furthermore, the voltage generation circuit 28 includes a voltage generation circuit for generating multiple voltages, and a readout voltage generation circuit 41 is shown in Figure 7. Additionally, the voltage generation circuit 28 has multiple drivers 29, and one driver 29 is shown in Figure 7.

[0104] The voltage generation circuit 28 includes a readout voltage generation circuit 41, a driver 29, a resistance measurement circuit 42, and a logic circuit 43. The readout voltage generation circuit 41 generates a readout voltage VCG. This readout voltage VCG is provided to switch M0 of the driver 29. Additionally, as described below, the resistance measurement circuit 42 generates a measurement voltage RC_OUT and outputs it to switch M1 of the driver 29. During readout operation, the driver 29 turns on switch M0 and turns off switch M1. Furthermore, during resistance measurement of the control signal line, the driver 29 turns on switch M1 and turns off switch M0. Thus, during resistance measurement of the control signal line, the measurement voltage RC_OUT from the resistance measurement circuit 42 is selected by switch M1 and transmitted to the control signal line via the global control signal line.

[0105] Figure 8 is a circuit diagram showing an example of the specific configuration of the resistance measuring circuit 42 in Figure 7.

[0106] The resistance measuring circuit 42 includes a buffer circuit 51, a current amplification circuit 52, and a current detector 53. The buffer circuit 51 includes an amplifier AP1 and a transistor M11. The amplifier AP1 acts as a regulator, generating a voltage corresponding to the voltage VSRC input to the negative input terminal. This voltage is supplied to the gate of the transistor M11. The source of the transistor M11 is connected to the power supply line, applying the output of the amplifier AP1 to its gate, thus forming a current source. The drain of the transistor M11 generates a current Ichg based on the output of the amplifier AP1. The drain voltage RC_OUT of the transistor M11 is fed back to the positive input terminal of the amplifier AP1, boosting it to the same voltage as VSRC. During resistance measurement, the voltage RC_OUT is connected to the control signal line, and Ichg is its charging current.

[0107] The current amplifier circuit 52 includes transistors M12 to M17. The source of transistor M12 is connected to the power supply line, and the output of amplifier AP1 is applied to its gate. The drain of transistor M12 generates a current Ichg based on the output of amplifier AP1. The drain of transistor M12 is connected to a reference potential point via the current path of transistor M13.

[0108] The gate of transistor M13 is connected to the drain of transistor M13, and also to the gates of transistors M14 and M15. The drain of transistor M14 is connected to the negative input terminal of amplifier CP1, which constitutes current detector 53, via the current path of transistor M16, and its source is connected to a reference potential. Similarly, the drain of transistor M15 is connected to the negative input terminal of amplifier CP1, which constitutes current detector 53, via the current path of transistor M17, and its source is connected to a reference potential. Control signals from logic circuit 43 are provided to the gates of transistors M16 and M17.

[0109] A current mirror circuit is formed by transistors M13 to M15. The charging current Ichg flows into the control signal line through the current path of transistor M13, and the same current Ichg flows into the current path of transistor M14. Furthermore, the current Ichg flowing into the current path of transistor M15 is multiplied by e (the base of the natural logarithm (Napier's constant)) to obtain the current (Ichg × e).

[0110] Logic circuit 43 generates control signals for the gates of transistors M16 and M17. Logic circuit 43 supplies drain current to the negative input terminal of amplifier CP1, which constitutes current detector 53, by turning on transistor M16 and turning off transistor M17, and supplies drain current to the negative input terminal of amplifier CP1, which constitutes current detector 53, by turning on transistor M17 and turning off transistor M16.

[0111] A certain comparison current IREF is supplied from the reference current source 54 to the positive input terminal of the amplifier CP1, which constitutes the current detector 53. The amplifier CP1 compares the current from the current amplification circuit 52 with the comparison current IREF from the reference current source 54, detects when the current reaches the comparison current, and outputs the detection result FLG to the logic circuit 43. The logic circuit 43 generates control signals for the control transistors M16 and M17 based on the detection result FLG, and measures the time by counting the reference clock.

[0112] Figure 9 is a diagram illustrating the resistance measurement of the control signal line of the resistance measurement circuit 42 and the logic circuit 43, and Figure 10 is a circuit diagram showing the equivalent circuit of the control signal line.

[0113] As shown in Figure 10, the gate line SGD, SGS, and word line WL, among other control signal lines, can be represented using an equivalent circuit consisting of resistors and capacitors. Figure 10 shows a circuit that applies a voltage VSRC from a voltage source to one end of the control signal line.

[0114] The VSRC in Figure 9 represents the voltage VSRC generated by the voltage source shown in the equivalent circuit of Figure 10. Because the control signal line has resistive and capacitive components, the voltage VEND at the far end (terminus) of the control signal line, as shown in VEND in Figure 9, does not increase sharply but increases slowly due to the resistance and capacitance of the control signal line. On the other hand, the current Ichg that charges the control signal line rises at the point when the voltage VSRC is applied and decreases slowly according to the time constant corresponding to the resistance and capacitance of the control signal line.

[0115] Therefore, regarding the charging current Ichg(t) of the control signal line over time, with the resistance and capacitor values ​​of the control signal line set as R and C respectively, and the constant set as A, it can be expressed by the following equation (1): Ichg(t)=A×e (-t / RC) …(1)

[0116] Equation (2) is obtained from equation (1).

[0117] t=RC×ln(A / Ichg(t))…(2)

[0118] Here, as shown in Figure 9, after a specified time has elapsed since the current Ichg rises, when the current Ichg decays to the point where the comparison current IREF is reached, transistor M16 of the current amplifier circuit 52 is turned off, and transistor M17 is turned on. The negative polarity input of the current detector CP1 is switched to amplify the charging current of the control signal line to a multiple of e (Ichg × e). This amplified current, as shown in Figure 9, decreases slowly according to the time constant corresponding to the resistance and capacitor value of the control signal line.

[0119] The dashed line in Figure 9 represents the change of the charging current Ichg(t)×e in this case. Here, the time when the charging current Ichg(t) based on the current Ichg reaches the comparison current IREF as the constant current is set as t0, the time when the charging current Ichg(t)×e obtained by amplifying the charging current reaches the comparison current IREF is set as t1, and the time from time t0 to time t1 is set as Δt. Δt is expressed by the following equation (3) using the charging currents at times t0 and t1 as Ichg(t0) and Ichg(t1), respectively, using the above equation (2).

[0120] Δt=RC×ln(A / Ichg(t1))-RC×ln(A / Ichg(t0))

[0121] =RC×{ln(A / Ichg(t1))-ln(A / Ichg(t0))}

[0122] =RC×ln(Ichg(t0) / Ichg(t1))…(3)

[0123] Here, since Ichg(t0)=IREF=Ichg(t1)×e, after substituting into equation (3), we obtain the following equation (4).

[0124] Δt=RC…(4)

[0125] Equation (4) indicates that Δt is a value proportional to the resistance of the control signal line. Logic circuit 43 controls transistors M16 and M17 of current amplifier circuit 52 to calculate Δt.

[0126] Logic circuit 43 first turns on transistor M16 and turns off transistor M17. The amplifier CP1 of the current detector 53 detects the time point t0 when Ichg(t) becomes Ichg(t0) = IEF by comparing Ichg(t) with the comparison current IEF. Amplifier CP1 outputs the detection result FLG to logic circuit 43. Logic circuit 43 starts counting at the time point t0 when it receives the detection result FLG from amplifier CP1, and turns on transistor M17 and turns off transistor M16.

[0127] Therefore, the negative input of amplifier CP1 of current detector 53 switches to Ichg(t)×e, and is compared with the comparison current IREF, thus detecting Ichg(t)×e at time t1 when Ichg(t1)×e = IREF. Amplifier CP1 outputs the detection result FLG at time t1 to logic circuit 43. Logic circuit 43 stops counting at the time point when it receives the detection result FLG from amplifier CP1. Logic circuit 43 outputs the count value to the internal register 26, etc.

[0128] The sequencer 27 receives the count value from the logic circuit 43 and compares it with a predetermined threshold value stored in register 26 or similar memory within non-volatile memory. When the count value exceeds the threshold, the resistance of the control signal line is determined to be high. In this case, even if a pass status is obtained during the erase check, it will be changed to a fail status, and the status information will be stored in the register. The status information stored in the register is transmitted to the host at a predetermined time.

[0129] (effect)

[0130] Next, the operation of this embodiment will be described with reference to the flowchart in FIG11. FIG11 is a flowchart showing the process for determining the state of the erase verification.

[0131] In this embodiment, high resistance is detected on the control signal line, and the state of the erase verification is determined. This high resistance detection is performed after the erase verification has been completed, provided the state is "passed".

[0132] During erasure, sequencer 27 controls each part of the non-volatile memory 2 according to the process shown in FIG11. That is, in step S1 of FIG11, sequencer 27 controls voltage generation circuit 28 to generate a high-voltage erase pulse and apply it to the select gate line SGS. As a result, the charge stored in the charge storage film 336 of each memory cell transistor MT of the NAND string NS in the target block BLK is discharged.

[0133] Next, in order to confirm whether the threshold voltage of the memory cell transistor MT has reached the Er level, the sequencer 27 performs an erase check in step S2. The sequencer 27 controls the voltage generation circuit 28 to generate the voltage required for the erase check and supplies it to the memory cell array 23, the sense amplifier 24, and the line decoder 25.

[0134] First, the sequencer 27 supplies voltage VSGS to select gate transistor ST2 via row decoder 25 to turn it on, and supplies voltage VSGD to select gate transistor ST1 of the target NAND string NS to turn it on, and applies erase verification voltage VCG_ER to the gate of each memory cell transistor MT. Additionally, the sequencer 27 uses sense amplifier 24 to fix bit line BL at a certain voltage (e.g., 0.5V), and charges the voltage of sense node SEN to a predetermined precharge voltage Vpre.

[0135] When the threshold voltages of all memory cell transistors MT in the NAND string NS become Er level, all memory cell transistors MT become ON, and a large cell current flows into the memory cell transistors MT. Consequently, the voltage of the sensing node SEN connected to the specified bit line BL decreases relatively rapidly. Therefore, in this case, the sensing node SEN becomes a voltage below the specified threshold at a relatively early specified time point.

[0136] On the other hand, if the threshold voltage of any memory cell transistor MT in the target NAND string NS has not recovered to the Er level, the memory cell transistor MT is in an off state, and the rate at which the voltage of the sensing node SEN connected to the specified bit line BL decreases is slower. Therefore, in this case, the sensing node SEN still maintains a high voltage above the specified threshold at a relatively early specified time point.

[0137] When the sensing node SEN is below a predetermined threshold at a specified time point, the sensing amplifier 24 obtains a determination result indicating that the erasure of the memory cell transistor MT of the NAND string NS connected to the bit line BL of the sensing node SEN was successful (erasure verification passed). When the sensing node SEN is above the predetermined threshold, the sensing amplifier 24 obtains a determination result indicating that the erasure of the memory cell transistor MT of the NAND string NS was unsuccessful (erasure verification failed). The sensing amplifier 24 outputs the success or failure determination result to the sequencer 27.

[0138] Sequencer 27 determines that all the verification results obtained from all NAND strings NS indicate successful erasure (erasure verification passed) (S3). If all are successful, sequencer 27 considers the erasure successful; if not all are successful, the process returns to step S1, repeatedly performing erasure and erasure verification. Furthermore, in this case, erasure and erasure verification are only performed on the NAND strings NS that failed the erasure verification.

[0139] If the sequencer 27 fails to complete the erase check even after processing for more than the prescribed number of times in steps S1 and S2, it sets the erase check to a failed state in step S7. On the other hand, if the sequencer 27 obtains a passed state for the erase check in step S3, it performs a resistance measurement of the control signal line in the next step S4.

[0140] The sequencer 27 can also select, for example, the select gate line SGS as the control signal line to be measured. Due to the manufacturing process, the select gate line SGS, the lowest layer of the three-dimensional structure in the control signal line, is prone to defects that are the main cause of high resistance. For this reason, the sequencer 27 selects the select gate line SGS as the object of high resistance detection. In addition, the sequencer 27 can also select the select gate line SGD, the highest layer of the three-dimensional structure in the control signal line, as the object of high resistance detection, and any word line WL can also be selected as the object of high resistance detection. Furthermore, the sequencer 27 can select multiple control signal lines as the objects of high resistance detection.

[0141] The resistance measurement circuit 42, controlled by the sequencer 27, supplies the measurement voltage RC_OUT to the control signal line, and a charging current flows into the control signal line. Ideally, the voltage of the storage unit array, such as the line decoder and sensing amplifier, should be the same as during the readout operation. When the charging current Ichg(t) becomes the comparison current IREF, the current detector 53 in the resistance measurement circuit 42 outputs the detection result FLG to the logic circuit 43. The logic circuit 43 controls the current amplification circuit 52, causing the negative input current of the amplifier CP1 of the current detector 53 to change to xe times the charging current of the control signal line. When the charging current Ichg(t)xe reaches the comparison current IREF again, the current detector 53 outputs the detection result FLG to the logic circuit 43. The logic circuit 43 counts the period between the two detection results FLG and outputs the count result, i.e., the value equivalent to the resistance value of the control signal line of the measured object, to the sequencer 27.

[0142] The sequencer 27 receives the count value from the logic circuit 43 and compares it with a predetermined threshold value pre-stored in the register 26 or similar memory within the non-volatile memory. If the count value is greater than the threshold, the resistance of the control signal line is determined to be high (step S5). In this case, even if the erasure check passes, it will be changed to a failed state, and the status information will be stored in the register (step S7). If the count value is determined to be within the predetermined threshold, that is, if the resistance of the control signal line being measured is determined to be within the normal range, a pass status indicating successful erasure check will be recorded in the register (S6). The status information stored in the register is transmitted to the host at a predetermined time.

[0143] In this embodiment, the resistance of control signal lines such as word lines is measured, and the erase state is determined based on the measurement results. Therefore, even if the erase check passes but the control signal lines still exhibit high resistance, the erase check can be changed to a failed state, thus suppressing read errors caused by high resistance in the control signal lines.

[0144] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. In fact, these novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as set forth in the claims and their equivalents.

Claims

1. A semiconductor memory device comprising: a memory block having a plurality of memory strings, a first control signal line, a plurality of second control signal lines, a third control signal line, and a plurality of bit lines, wherein the plurality of memory strings includes a first select-gate transistor, a plurality of memory cell transistors, and a second select-gate transistor connected in series, the first control signal line being commonly connected to the gate of the first select-gate transistor of the plurality of memory strings, the plurality of second control signal lines being commonly connected to the gates of the memory cell transistors in the same row of the plurality of memory strings, the third control signal lines being commonly connected to the gates of the second select-gate transistors of the plurality of memory strings, and the plurality of bit lines being respectively connected to the plurality of memory strings; A resistance measuring circuit is used to measure the resistance of at least one of the first to third control signal lines. And control circuitry, for erasing, programming and reading data from the plurality of memory cell transistors contained in the memory block; The control circuit determines whether to set the erase verification result as failed based on the resistance measurement result of the resistance measurement circuit.

2. The semiconductor memory device according to claim 1, wherein the memory block has a three-dimensional structure, and the control circuit uses the lowest or highest control signal line of the memory block among the first to third control signal lines as the object of the resistance measurement.

3. The semiconductor memory device according to claim 1, wherein the memory block has a three-dimensional structure, and the control circuit uses the second control signal line as the object of the resistance measurement.

4. The semiconductor memory device according to claim 1, wherein the control circuit uses a plurality of control signal lines among the first to third control signal lines as the object of the resistance measurement.

5. The semiconductor memory device of claim 1, wherein the control circuit performs the resistance measurement after the erase and before the programming.

6. The semiconductor memory device according to claim 1, wherein when the control circuit obtains a pass status in an erase verification that verifies the erase, it determines whether to change the result of the erase verification based on the measurement result of the resistance measurement by the resistance measurement circuit.

7. The semiconductor memory device of claim 1, wherein the control circuit determines whether to change the result of the erase verification by comparing the result of the resistance measurement with a threshold.

8. The semiconductor memory device of claim 7, wherein the memory block records the threshold in a specific area.

9. The semiconductor memory device of claim 1, wherein the control circuit transmits the result of the erase verification to the host.

10. The semiconductor memory device according to claim 1, wherein the control circuit is capable of setting whether to perform a failure determination process based on the resistance measurement and the measurement result.

11. The semiconductor memory device according to claim 1, wherein the resistance measuring circuit comprises: a voltage generating circuit that applies a voltage to the control signal line to be measured; an amplification circuit that supplies a second charging current to the control signal line, the first charging current being used to charge the control signal line; and a logic circuit that calculates the resistance of the control signal line to be measured by calculating the time from the point when the first charging current becomes a first current value to the time when the second charging current becomes the first current value.

12. An erasure verification method for verifying the erasure of a memory block, the memory block being configured to have: a plurality of memory strings, including a first select gate transistor, a plurality of memory cell transistors and a second select gate transistor connected in series; and a first control signal line, which is commonly connected to the gate of the first select gate transistor of the plurality of memory strings. Multiple second control signal lines are respectively connected to the gates of the memory cell transistors in the same row of the multiple memory strings; The third control signal line is commonly connected to the gate of the second select gate transistor of the plurality of memory strings; And multiple bit lines, respectively connected to the multiple memory strings; after the erase and before the programming, the resistance measuring circuit measures the resistance of at least one of the first to third control signal lines; based on the resistance measurement result of the resistance measuring circuit, the control circuit determines whether to set the erase verification result of the erase verification to a failed state.

13. The erasure verification method according to claim 12, wherein when the control circuit obtains a pass status in the erasure verification that verifies the erasure, it determines whether to change the result of the erasure verification based on the resistance measurement result of the resistance measurement circuit.

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