A serial memory test vector generation method and full address test method

Abstract

The application provides a serial memory test vector generation method and a full address test method, which comprises the following steps: S1, obtaining the structure and capacity of the serial memory; S2, obtaining the address range of the serial memory; S3, obtaining the write timing, read timing and erase timing of the serial memory; S4, sequentially performing page write verification, write enable operation and erase command, and inputting the address of the data to be erased; S5, dividing the structure of the write timing; S6, realizing the fixed sentence part, the loop sentence part and the transformation sentence part of the write timing, and obtaining all serial memory test vectors; S7, generating a full address write test vector; and S8, reading and comparing the test data, and completing the test. The application can quickly generate a test vector file of a large-capacity serial memory, perform full address test, simplify the test as much as possible and improve the test efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of serial memory testing, and in particular to a serial memory test vector generation method and a full-address testing method. Background Art

[0002] During serial memory write and read testing, due to its design, address selection, data input, and data output are each controlled by a single pin, with all data input and output occurring serially. Furthermore, serial memory operations must rely on predetermined serial timing instructions; otherwise, all operations will be ineffective. Therefore, testing large-capacity serial memories requires a very large number of test vectors to test the full address range of serial memory reads and writes, and these test vectors must be arranged according to a predetermined timing sequence to be effective.

[0003] Typically, a 256Mbit serial memory has 7 million lines of test vectors required for full-address writes. Writing all test vectors in a short period of time and in a predetermined sequence is crucial for addressing the complexity and inefficiency of test vectors for large-capacity serial memories. To this end, the present invention provides a serial memory test vector generation method and a full-address test method to rapidly generate test vector files for large-capacity serial memories and perform full-address testing. Summary of the Invention

[0004] The present invention provides a serial memory test vector generation method and a full-address test method, so as to quickly generate a test vector file of a large-capacity serial memory, perform a full-address test, simplify the test as much as possible and improve the test efficiency.

[0005] An aspect of an embodiment of this specification discloses a method for generating a serial memory test vector, comprising:

[0006] S1. Get the structure and capacity of the serial memory;

[0007] S2 obtains the address range of the serial memory;

[0008] S3 obtains the serial memory write timing, read timing and erase timing;

[0009] S4. First perform a page write verification, then perform a write enable operation, and then perform an erase command and enter the address of the data to be erased;

[0010] S5. Divide the write timing structure: Divide the page write timing test vector structure into a fixed statement part, a loop statement part, and a transformation statement part;

[0011] S6. Implementing the fixed statement part, the loop statement part and the transform statement part of the write timing by using a high-level language, specifically: based on the loop statement part, the fixed statement part and the transform statement part are started from address 0, after writing once, the loop is executed once, and the address is increased by 1, until all addresses are looped, and all serial memory test vectors are obtained.

[0012] In one embodiment disclosed in the specification, in S2, according to the capacity of the serial memory, the address range that needs to be programmed is explicitly required.

[0013] In one embodiment disclosed in the specification, in S3, according to the technical data and supported protocol standards of the serial memory, the write timing of the serial memory is determined.

[0014] In one embodiment disclosed in the specification, in S4, after generating the test vector of the page write timing of the serial memory, the test vector of the read timing is loaded after the page write is completed, the read operation is performed, the data written by the page write is compared with the read timing byte by byte, and if the written data and the read data are consistent, it is confirmed that the timing is correct.

[0015] In one embodiment disclosed in the specification, in S5, the fixed statement part includes the chip select, the write enable part, the write command part, the read command and the erase command of the serial memory;

[0016] The loop statement part includes the address of the serial memory, a piece of data is written per page, and after the address is increased by 1, the fixed statement part and the transform statement part are looped once;

[0017] The transform statement part includes the data of the serial memory that needs to be written.

[0018] In one embodiment disclosed in the specification, in S5, based on the python language, the test vector is written according to the write timing part, the read timing part and the erase timing part.

[0019] Another aspect of the embodiment of the specification discloses a serial memory full address test method, comprising:

[0020] S1-S6 in the serial memory test vector generation method described in any of the above;

[0021] S7. Based on all serial memory test vectors obtained in S6, a full address write test vector is generated;

[0022] S8. Based on the test vector of the read timing, read the full address data of the serial memory and compare it with the full address write test vector. If they are consistent, it is confirmed that the full address of the serial memory is correct; if they are inconsistent, an error is reported and S1 to S8 are modified or re-executed until they are consistent; the test is completed.

[0023] In one embodiment disclosed in this specification, after the full-address read and write test of the serial memory is completed, the DC parameter test and the AC parameter test are performed.

[0024] The embodiments of this specification can achieve at least the following beneficial effects:

[0025] 1. The serial memory test vector generation method of the present invention first performs page writing, then loads the test vector of the read timing to perform a read operation, compares the page write data with the read timing byte by byte, and after the two are consistent, divides the test vector structure of the page write timing, distinguishes the fixed statement part, the loop statement part and the transformation statement part, and finally uses a high-level language to implement the fixed statement part, the loop statement part and the transformation statement part of the write timing. After all address cycles are completed, all serial memory test vectors can be obtained; this method can quickly generate a test vector file for a large-capacity serial memory.

[0026] 2. The serial memory full-address test method of the present invention is based on the serial memory test vector generation method, that is, after quickly generating a test vector file for a large-capacity serial memory, a full-address write test vector is generated based on all the obtained serial memory test vectors, and the full-address data of the serial memory is read out based on the test vector of the read timing, and compared with the full-address write test vector. If they are consistent, it is confirmed that the full address of the serial memory is correct; if they are inconsistent, an error is reported and S1 to S8 are modified or re-executed until they are consistent; the test is completed; this method can simplify testing and improve test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 Schematic diagram of the steps of a method for generating a serial memory test vector involved in some embodiments of the present invention.

[0029] Figure 2 Schematic diagram of the steps of a serial memory full-address testing method involved in some embodiments of the present invention.

[0030] Figure 3 This is a partial schematic diagram of a portion of the write timing involved in some embodiments of the present invention remaining unchanged during each cycle.

[0031] Figure 4 This is a partial schematic diagram of adding 1 to each cycle address involved in some embodiments of the present invention.

[0032] Figure 5 This is a partial schematic diagram of writing data 0 during each address cycle involved in some embodiments of the present invention.

[0033] Figure 6 This is a partial schematic diagram of reading data at all addresses involved in some embodiments of the present invention.

[0034] Figure 7 It is a partial schematic diagram of the erase timing portion involved in some embodiments of the present invention.

[0035] Figures 8 to 10 It is a partial schematic diagram of a test program project that can be recognized by an integrated circuit test machine including test vectors involved in some embodiments of the present invention. DETAILED DESCRIPTION

[0036] Hereinafter, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present invention. Therefore, the drawings and description are to be considered as illustrative in nature and not restrictive.

[0037] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the products of the present invention are conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present invention.

[0038] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0039] Furthermore, the terms "mounted," "connected," "connect," and "fixed" should be interpreted broadly. For example, they may refer to fixed connection, detachable connection, or integration; they may refer to direct connection or indirect connection through an intermediate medium; they may refer to internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0040] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] like Figure 1 As shown, one aspect of an embodiment of this specification discloses a method for generating a serial memory test vector, comprising:

[0042] S1. Get the structure and capacity of the serial memory;

[0043] S2 obtains the address range of the serial memory;

[0044] S3 obtains the serial memory write timing, read timing and erase timing;

[0045] S4. First perform a page write verification, then perform a write enable operation, and then perform an erase command and enter the address of the data to be erased;

[0046] S5. Divide the write timing structure: Divide the page write timing test vector structure into a fixed statement part, a loop statement part, and a transformation statement part;

[0047] S6. Use high-level language to implement the fixed statement part, loop statement part and transformation statement part of the write timing. Specifically: based on the loop statement part, start the fixed statement part and the transformation statement part from address 0, loop once after each write, and increase the address by 1 until all addresses are cycled through, and obtain all serial memory test vectors.

[0048] In some embodiments, in S2, the address range that needs to be programmed is determined based on the capacity of the serial memory.

[0049] In some embodiments, in S3 , the write timing of the serial memory is determined according to the technical data and supported protocol standards of the serial memory.

[0050] In some embodiments, in S4, the page write timing of the serial memory is generated and then loaded with a test vector. After the page is written, the test vector of the read timing is loaded, and a read operation is performed. The data written to the page is compared byte by byte with the read timing. If the written data is consistent with the read data, the timing is confirmed to be correct.

[0051] In some embodiments, in S5, the fixed statement portion includes a chip select portion, a write enable portion, a write command portion, a read command, and an erase command of the serial memory;

[0052] The loop statement part includes the address of the serial memory, writes a piece of data to each page, and after the address is increased by 1, the fixed statement part and the transformation statement part are looped once;

[0053] The transformation statement portion includes data to be written into the serial memory.

[0054] In some embodiments, in S5, based on Python language, test vector writing is performed according to the write timing part, the read timing part and the erase timing part.

[0055] like Figure 2 As shown, another aspect of the embodiment of this specification discloses a serial memory full address test method, including:

[0056] S1 to S6 in any one of the above serial memory test vector generation methods;

[0057] S7. Generate a full-address write test vector based on all serial memory test vectors obtained in S6;

[0058] S8. Based on the test vector of the read timing, read the full address data of the serial memory and compare it with the full address write test vector. If they are consistent, it is confirmed that the full address of the serial memory is correct; if they are inconsistent, an error is reported and S1 to S8 are modified or re-executed until they are consistent; the test is completed.

[0059] In some embodiments, after the full-address read and write test of the serial memory is completed, the DC parameter test and the AC parameter test are performed.

[0060] In order to better describe the technical solution of the present invention, the concept of the present invention is as follows:

[0061] S1. Clarify the structure and capacity of serial memory.

[0062] Large-capacity serial memory provides page programming, and erasing provides 4k erase, 32k erase, 64k erase and other methods.

[0063] Take the 256M bit serial NOR FLASH memory model EFM25Q256 as an example. This serial memory is an erasable memory that supports the standard SPI interface protocol and has a capacity of 256M bits.

[0064] S2. Define the address range of the serial memory.

[0065] According to the capacity of the serial memory, the address range that needs to be programmed is clearly defined.

[0066] Based on the capacity of the EFM25Q256 serial memory, the chip's programming address should be: 0 to 2^26. When operating using the standard SPI interface protocol, the chip's read and write addresses are divided into the upper eight bits, the middle eight bits, and the lower eight bits. This method uses page programming to write to all addresses. The lower eight bits remain unchanged at 0, while the middle and upper eight bits are continuously incremented by 1 to write to the entire address page.

[0067] S3. Determine the write timing, read timing, and erase timing of the serial memory.

[0068] Determine the write timing of the serial memory based on the serial memory's technical data and supported protocol standards.

[0069] The EFM25Q256 serial memory write sequence first requires chip selection of the memory under test, then write enable operation, followed by write command, input of the address of the data to be written, and finally input of the write data.

[0070] The read sequence first selects the chip of the memory under test, then issues the read command, and finally the chip outputs the data.

[0071] The erase sequence first selects the chip of the memory under test.

[0072] S4. Perform a page write verification, then perform a write enable operation, and then execute an erase command and input the address of the data to be erased.

[0073] Use the test machine to generate a test vector for the page write timing of the serial memory and then load it. After the page is written, load the test vector for the read timing and perform a read operation. The data written to the page is compared byte by byte with the read timing. If there is no error during the test process of the test machine and the written data is consistent with the read data, the timing is confirmed to be correct.

[0074] S5. Structure for dividing write sequence.

[0075] The test vector structure of the page write timing is divided into the fixed statement part, the loop statement part and the transformation statement part.

[0076] The statements in these three parts mainly comply with the standard SPI protocol. If the serial writing is incorrect, any operation on the memory under test will be invalid.

[0077] The fixed statement part mainly includes the chip selection of the memory under test, the write enable part, the write command part, the read command, the erase command, etc.

[0078] The loop statement part mainly contains the address of the memory under test. After writing a piece of data to each page, the address is increased by 1, and the fixed statement part and the change statement part are looped once.

[0079] The transformation statement mainly contains the data to be written to and read from the memory under test. Memory testing can use various data combinations, such as writing and reading all 0s, writing and reading all 1s, writing and reading all 5s, and writing and reading all As. This section needs to be adjusted based on the test data combination.

[0080] S6. Generate write timing using high-level language.

[0081] A high-level language is used to implement the fixed, looping, and transformation sections of the write sequence. The fixed sections, such as those for serial memory chip select and clock control, remain constant or maintain a certain pattern throughout the test. The serial memory's storage addresses increment sequentially from 0 to FF, so the fixed and transformation sections start at address 0 and loop once after each write, incrementing the address by 1 until all memory addresses are cycled through. The transformation section writes a "0" or "1" to each address in the serial memory.

[0082] Based on Python language, test vectors are written according to the write timing part, read timing part and erase timing part.

[0083] Write timing part: write the memory chip select, write enable, and write command timings, and these three timings remain unchanged. Figure 3 As shown, this part remains unchanged in each cycle.

[0084] Then the address cycle is performed, the high eight-bit address and the middle eight-bit address start from 0, and the address increases by 1 in each cycle. Figure 4 shown.

[0085] Then write the data. Figure 5 As shown, Figure 5 For example, data 0 is written each time the address is cycled.

[0086] Readout timing part: read out data, read out 8 bits each time, cycle all addresses 2^26 / 8 times, and read out data of all addresses of the memory under test. Figure 6 As shown.

[0087] Erase timing part: write the write enable and erase command, then write the address to be erased, and then the erase of the specified address can be performed. As shown. Figure 7

[0088] The above is to generate the test vector of the measured memory by the python language. The whole test vector is a TXT document, and the resources in the integrated circuit test platform are needed to perform the fan-in and fan-out of the signal.

[0089] S7. Generate a full address write test vector.

[0090] Load the whole serial memory test vector produced by the high-level language of S6 step into the integrated circuit test platform. Run the test vector through the test platform, and only start once, which can write specific content to all addresses of the serial memory. As shown, Figures 8 to 10 Figures 8 to 10 It is a test program project that the integrated circuit test platform containing the test vector can recognize.

[0091] S8. Test data read comparison.

[0092] Load the read timing test vector into the test platform, read the full address data of the serial memory using the test platform, and the test platform can automatically compare. The storage unit with inconsistency will report an error.

[0093] S9. Other parameter test.

[0094] After the full address read and write test of the serial memory is completed, DC parameter test and AC parameter test are performed to ensure that the internal elements of the memory are in good condition and can complete the action within the specified time. Finally, the test vector for erasing is executed by the test platform to ensure that the memory returns to the factory state. The whole serial memory full address test is completed, the data is saved, and the program is exited.

[0095] In summary, under normal circumstances, a timing of the serial memory can only perform one bit operation, and 8 timings are needed to execute a byte. Usually, when testing the serial memory, a single timing needs to be manually input, and through this method, the test program of the serial memory with different capacities and addresses can be automatically generated, which can avoid the error caused by manual input, and the test program cannot be run. It also greatly increases the time consumed by manual input; that is, this method simplifies the test and improves the test efficiency.

[0096] ​​In summary, multiple specific embodiments of the present invention are disclosed. Under the condition that there is no self-contradiction, the various embodiments can be freely combined to form new embodiments. That is, the embodiments belonging to the replacement schemes can be freely replaced but cannot be combined with each other; the embodiments that do not belong to the replacement schemes can be combined with each other, and these new embodiments also belong to the essential content of the present invention.

[0097] The above embodiments describe multiple specific implementations of the present invention, but those skilled in the art should understand that various changes or modifications can be made to these implementations without departing from the principles and essence of the present invention, but these changes and modifications are all within the scope of protection of the present invention.

Claims

1. A method for generating a serial memory test vector, characterized in that: include: S1. Get the structure and capacity of the serial memory; S2 obtains the address range of the serial memory; S3 obtains the serial memory write timing, read timing and erase timing; S4. First perform a page write verification, then perform a write enable operation, and then perform an erase command and enter the address of the data to be erased; S5. Divide the write timing structure: Divide the page write timing test vector structure into a fixed statement part, a loop statement part, and a transformation statement part; S6. Use high-level language to implement the fixed statement part, loop statement part and transformation statement part of the write timing. Specifically: based on the loop statement part, start the fixed statement part and the transformation statement part from address 0, loop once after each write, and increase the address by 1 until all addresses are cycled through, and obtain all serial memory test vectors.

2. The method for generating serial memory test vectors according to claim 1, wherein: In S2, the address range to be programmed is determined based on the capacity of the serial memory.

3. The method for generating serial memory test vectors according to claim 1, wherein: In S3 , the write timing of the serial memory is determined according to the technical data of the serial memory and the supported protocol standard.

4. The method for generating serial memory test vectors according to claim 1, wherein: In S4, the page write timing of the serial memory is generated and loaded with a test vector. After the page is written, the test vector of the read timing is loaded, and a read operation is performed. The data written to the page is compared byte by byte with the read timing. If the written data is consistent with the read data, the timing is confirmed to be correct.

5. The method for generating serial memory test vectors according to claim 1, wherein: In S5, the fixed statement part includes a chip select, a write enable part, a write command part, a read command and an erase command of the serial memory; The loop statement part includes the address of the serial memory, writes a piece of data to each page, and after the address is increased by 1, the fixed statement part and the transformation statement part are looped once; The transformation statement portion includes data to be written into the serial memory.

6. The method for generating serial memory test vectors according to claim 1, wherein: In S5, based on Python language, test vectors are written according to the write timing part, read timing part and erase timing part.

7. A serial memory full address test method, characterized in that: include: S1 to S6 in the serial memory test vector generation method according to any one of claims 1 to 6; S7. Generate a full-address write test vector based on all serial memory test vectors obtained in S6; S8. Based on the test vector of the read timing, read the full address data of the serial memory and compare it with the full address write test vector. If they are consistent, it is confirmed that the full address of the serial memory is correct; if they are inconsistent, an error is reported and S1 to S8 are modified or re-executed until they are consistent; the test is completed.

8. The serial memory full address test method according to claim 7, wherein: After the full-address read and write test of the serial memory is completed, the DC parameter test and AC parameter test are performed.

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