A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

The embodiment of the present disclosure provides a preparation method of a semiconductor structure and the semiconductor structure, wherein the preparation method comprises the following steps: a substrate comprises at least a mark area and a blank area between the mark areas; a target layer and a mask layer are formed in sequence, the target layer and the mask layer conformally cover the substrate; a core pattern is formed; the mask layer is etched with the core pattern as a mask to obtain a plurality of first patterns in the mark area and a plurality of first dummy patterns in the blank area; a first dielectric layer is formed, the first dielectric layer at least covers the sidewalls of the first patterns and the first dummy patterns; a filling layer is formed, the filling layer at least covers the sidewalls of the first dielectric layer, and the filling layer fills the gaps between adjacent first patterns, between the first dummy patterns and between the first patterns and the first dummy patterns; a barrier layer is formed, the first dielectric layer is etched along the sidewalls of the first patterns with the barrier layer as a mask to form second patterns in the mark area; and the target layer is etched to transfer the second patterns to the target layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] With the further reduction of the size of semiconductor structures, in order to increase the integration density of the semiconductor structure, self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP) and other processes are introduced into the manufacturing process of the semiconductor structure.

[0003] However, in the process of performing the above-mentioned patterning process, there can be a large difference in the pattern density in different regions, which is easy to cause a load effect, resulting in defects such as voids in the semiconductor structure, and thus there are still many problems in the method for manufacturing the semiconductor structure that need to be improved. SUMMARY

[0004] Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, comprising:

[0005] providing a substrate, the substrate comprising at least a mark region and a blank region between the mark regions; sequentially forming a target layer and a mask layer on the substrate, the target layer and the mask layer conformally covering the substrate; forming a core pattern on the mask layer;

[0006] etching the mask layer with the core pattern as a mask to obtain a plurality of first patterns in the mark region and a plurality of first dummy patterns in the blank region;

[0007] forming a first dielectric layer, the first dielectric layer covering at least the sidewalls of the first patterns and the first dummy patterns;

[0008] forming a filling layer, the filling layer covering at least the sidewalls of the first dielectric layer and filling the gaps between adjacent first patterns, between first dummy patterns, and between a first pattern and a first dummy pattern;

[0009] forming a barrier layer in the blank region, and etching the first dielectric layer along the sidewalls of the first patterns with the barrier layer as a mask to form second patterns in the mark region;

[0010] etching the target layer to transfer the second patterns to the target layer.

[0011] In some embodiments, forming a core pattern on the mask layer comprises:

[0012] forming a core layer, the core layer covering the mask layer;

[0013] forming an anti-reflection layer, the anti-reflection layer covering the core layer;

[0014] etching the anti-reflection layer and the core layer to form an initial pattern;

[0015] forming a second dielectric layer, the second dielectric layer covering the sidewall and top of the initial pattern and the surface of the mask layer between the initial pattern;

[0016] removing the second dielectric layer on the top of the initial pattern and the portion of the second dielectric layer on the surface of the mask layer between the initial pattern, while removing the initial pattern, leaving the second dielectric layer on the sidewall of the initial pattern to form the core pattern.

[0017] In some embodiments, sequentially forming a target layer and a mask layer on the substrate comprises:

[0018] forming a target layer, the target layer covering the substrate;

[0019] forming a first mask layer, the first mask layer covering the target layer;

[0020] forming a second mask layer, the second mask layer covering the first mask layer;

[0021] etching the mask layer with the core pattern as a mask comprises:

[0022] etching the second mask layer and the first mask layer with the core pattern as a mask to form a plurality of initial first patterns in the mark area and a plurality of initial first dummy patterns in the blank area;

[0023] removing the second mask layer, leaving the first mask layer in the mark area to form the first pattern and leaving the first mask layer in the blank area to form the first dummy pattern.

[0024] In some embodiments, forming a first dielectric layer comprises:

[0025] forming a first dielectric layer, the first dielectric layer covering the sidewall and top of the first pattern and the first dummy pattern and covering the surface of the target layer between the first pattern, between the first dummy pattern and between the first pattern and the first dummy pattern.

[0026] In some embodiments, forming a fill layer comprises:

[0027] forming a filling material layer on the first dielectric layer, the filling material layer filling gaps between adjacent first patterns, between first dummy patterns, and between first patterns and first dummy patterns, and covering a surface of the substrate;

[0028] performing a thinning process on the filling material layer to form the filling layer, the filling layer exposing a portion of the first dielectric layer on top of the first patterns and the first dummy patterns.

[0029] In some embodiments, forming a barrier layer on the blank area comprises:

[0030] forming a barrier material layer covering the filling layer and the portion of the first dielectric layer exposed by the filling layer;

[0031] performing a patterning process to form an initial barrier layer on the blank area;

[0032] performing a thinning process on the initial barrier layer to form the barrier layer.

[0033] In some embodiments, etching the first dielectric layer along sidewalls of the first patterns with the barrier layer as a mask comprises:

[0034] etching the first dielectric layer along sidewalls of the first patterns with the barrier layer as a mask, the first patterns and the filling layer in the mark area constituting the second patterns.

[0035] In some embodiments, the first dummy pattern located at the outermost side of the plurality of first dummy patterns comprises a first boundary, and a boundary of the barrier layer located at the same side of the first boundary is defined as a second boundary.

[0036] The blank area has a first width W1, the barrier layer has a second width W2, a variation value of a barrier layer critical dimension is defined as A, and an offset value between a normal projection of the first boundary and the second boundary on the substrate is defined as B; the first width W1 and the second width W2 satisfy the following relationship:

[0037] W1-W2≥A+B (1).

[0038] In some embodiments, the first dummy pattern located at the outermost side of the plurality of first dummy patterns comprises a first boundary, and a boundary of the barrier layer located at the same side of the first boundary is defined as a second boundary.

[0039] The blank area has a first width W1, the barrier layer has a second width W2, a variation value of the barrier layer critical dimension is defined as A, an offset value between the normal projection of the first boundary and the second boundary on the substrate is defined as B, and a width of a single first dummy pattern is defined as W3; the following relationship is satisfied between the first width W1 and the second width W2:

[0040] A+B≤W1-W2<2W3 (2).

[0041] In some embodiments, etching the target layer comprises:

[0042] Etching the target layer with the second pattern and the first dummy pattern, the filling layer and the first medium layer located in the blank area as masks to transfer the second pattern to the part of the target layer located in the mark area; wherein the part of the target layer located in the blank area is in an unetched state.

[0043] In some embodiments, after etching the target layer to transfer the second pattern to the target layer, the preparation method further comprises:

[0044] Removing the second pattern, the first dummy pattern, the filling layer and the first medium layer located on the target layer.

[0045] In some embodiments, sequentially forming a target layer and a mask layer on the substrate comprises:

[0046] Forming a target layer, the target layer covering the substrate;

[0047] Forming a first mask layer, the first mask layer covering the target layer;

[0048] Forming a second mask layer, the second mask layer covering the first mask layer;

[0049] Forming a third mask layer, the third mask layer covering the second mask layer;

[0050] Forming a fourth mask layer, the fourth mask layer covering the third mask layer.

[0051] In some embodiments, etching the mask layer with the core pattern as a mask comprises:

[0052] Etching the fourth mask layer and the third mask layer with the core pattern as a mask to form an initial third pattern located in the mark area and an initial second dummy pattern located in the blank area;

[0053] Removing the fourth mask layer, the third mask layer remaining in the mark area constitutes a third pattern, and the third mask layer remaining in the blank area constitutes a second dummy pattern;

[0054] forming a third dielectric layer covering at least the third pattern and the sidewall of the second dummy pattern;

[0055] performing an etching process to remove the third pattern and the second dummy pattern, and defining the third dielectric layer remained in the mark area as a fourth pattern and the third dielectric layer remained in the blank area as a third dummy pattern.

[0056] The embodiments of the present disclosure further provide a semiconductor structure manufactured by the method described in any of the above embodiments.

[0057] The preparation method of the semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure, wherein the preparation method comprises the following steps: providing a substrate, the substrate at least comprising a mark area and a blank area between the mark areas; sequentially forming a target layer and a mask layer on the substrate, the target layer and the mask layer conformally covering the substrate; forming a core pattern on the mask layer; etching the mask layer with the core pattern as a mask to obtain a plurality of first patterns located in the mark areas and a plurality of first dummy patterns located in the blank areas; forming a first dielectric layer, the first dielectric layer at least covering the sidewalls of the first patterns and the first dummy patterns; forming a filling layer, the filling layer at least covering the sidewalls of the first dielectric layer and filling the gaps between adjacent first patterns, between the first dummy patterns and between the first patterns and the first dummy patterns; forming a barrier layer located in the blank areas, and etching the first dielectric layer along the sidewalls of the first patterns with the barrier layer as a mask to form second patterns located in the mark areas; etching the target layer to transfer the second patterns to the target layer. In the process step before etching the target layer, pattern structures are formed on both the mark areas and the blank areas between the mark areas, so that the pattern densities in the two areas are kept as consistent as possible, preventing the occurrence of recessed areas in the position with low pattern density in the subsequent step of forming the filling layer to cause the generation of the loading effect, greatly reducing the possibility of damage to the material layer under the pattern structure in the subsequent operation. Then, in the step of etching the first dielectric layer, by setting the barrier layer on the blank areas, after the step of etching the first dielectric layer ends, only the second patterns located in the mark areas are generated, which can be used for subsequent pattern transfer, while in the blank areas, the first dummy patterns, the filling layer between the first dummy patterns and the first dielectric layer on the sidewalls of the first dummy patterns are still in a continuous state and no pattern structure separated from each other is generated. Therefore, when the step of etching the target layer ends, only the patterns transferred down can be obtained in the position where the target layer is located in the mark areas, while no pattern transfer occurs in the position where the target layer is located in the blank areas. In summary, the preparation method of the semiconductor structure provided by the embodiments of the present disclosure can not only prevent the generation of the loading effect, but also obtain the complete pattern expected on the target layer, which can significantly improve the yield of the semiconductor structure in the preparation process.

[0058] Details of one or more embodiments of the present disclosure are presented in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0059] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described below only show some of the embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0060] Figure 1 A flow chart of a preparation method of a semiconductor structure provided by some embodiments of the present disclosure is shown in FIG. 1.

[0061] Figures 2 to 13 A process flow chart of a semiconductor structure in a preparation process provided by some embodiments of the present disclosure is shown in FIG. 2.

[0062] Figures 14 to 19 A process flow chart of a semiconductor structure in a preparation process provided by some embodiments of the present disclosure is shown in FIG. 2. DETAILED DESCRIPTION

[0063] The exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms, and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0064] The terms used herein are only for the purpose of describing specific embodiments and not as limitations of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprise" and / or "comprising", when used in this specification, determine the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0065] In order to increase the integration density of the semiconductor structure, in the process of performing self-aligned double patterning and self-aligned quadruple patterning, it is usually necessary to form a plurality of core layers on the target material layer to be etched, and then a plurality of core patterns can be formed on the core layers by etching the core layers, which can be used as a mask in the subsequent pattern transfer process.

[0066] However, the distribution of the core patterns is usually uneven, and in the area where the core pattern distribution is sparse, the material surface filled between the core patterns usually appears concave, which is extremely easy to cause the generation of load effect, and seriously reduces the reliability and yield of the finally obtained semiconductor structure.

[0067] Based on this, the following technical scheme of the embodiments of the present disclosure is proposed:

[0068] The embodiments of the present disclosure provide a preparation method of a semiconductor structure, as shown in the following formula: Figure 1 The method comprises the following steps:

[0069] Step S101: providing a substrate, the substrate at least comprising a mark area and a blank area between the mark areas; sequentially forming a target layer and a mask layer on the substrate, the target layer and the mask layer conformally covering the substrate; and forming a core pattern on the mask layer;

[0070] Step S102: etching the mask layer with the core pattern as a mask to obtain a plurality of first patterns located in the mark areas and a plurality of first dummy patterns located in the blank areas;

[0071] Step S103: forming a first dielectric layer, the first dielectric layer at least covering the sidewalls of the first patterns and the first dummy patterns;

[0072] Step S104: forming a filling layer, the filling layer at least covering the sidewalls of the first dielectric layer, and filling the gaps between adjacent first patterns, between the first dummy patterns, and between the first patterns and the first dummy patterns;

[0073] Step S105: forming a barrier layer located in the blank areas, and etching the first dielectric layer along the sidewalls of the first patterns with the barrier layer as a mask to form second patterns located in the mark areas;

[0074] Step S106: etching the target layer to transfer the second patterns to the target layer.

[0075] In the process steps prior to etching the target layer, patterned structures are formed in both the marked area and the blank area between the marked areas. This ensures that the pattern density in both areas remains as consistent as possible, preventing the formation of depressions in areas with low pattern density during the subsequent filling layer formation step, which could lead to a loading effect. This significantly reduces the possibility of damage to the material layer beneath the patterned structure in subsequent operations. Next, during the etching of the first dielectric layer, a barrier layer is provided in the blank area. This ensures that after the final etching of the first dielectric layer, a second pattern suitable for subsequent pattern transfer is generated only at the marked area. In the blank area, the first dummy pattern, the filling layer between the first dummy patterns, and the first dielectric layer on the sidewalls of the first dummy pattern remain continuous, without separated pattern structures. Therefore, at the end of the target layer etching step, the transferred pattern is only obtained at the marked area of ​​the target layer, while no pattern transfer occurs at the blank area. In summary, the semiconductor structure fabrication method provided by this disclosure not only prevents loading effects but also obtains the desired complete pattern on the target layer, significantly improving the yield of the semiconductor structure during fabrication.

[0076] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0077] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figures 2 to 13 This is a process flow diagram of the semiconductor structure fabrication process provided in some embodiments of this disclosure.

[0078] The method for preparing the semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0079] First, execute step S101, as follows: Figures 2 to 5 As shown, a substrate 10 is provided, which includes at least a marking region 21 and a blank region 22 located between the marking regions 21; a target layer 11 and a mask layer 12 are sequentially formed on the substrate 10, and the target layer 11 and the mask layer 12 conformally cover the substrate 10; a core pattern 152a is formed on the mask layer 12.

[0080] Here, the substrate can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate.

[0081] In some embodiments, the marker area and blank area may be located in the outer area, but are not limited thereto. The marker area and blank area may also be located in other areas, such as cutting paths or any other area where graphic transfer is required.

[0082] Continue to refer to Figure 2 In some embodiments, a target layer 11 and a mask layer 12 are sequentially formed on the substrate 10, including:

[0083] A target layer 11 is formed, and the target layer 11 covers the substrate 10;

[0084] A first mask layer 121 is formed, which covers the target layer 11;

[0085] A second mask layer 122 is formed, which covers the first mask layer 121.

[0086] In practice, the target layer material includes, but is not limited to, dielectric layers, semiconductor layers, and conductive layers (e.g., metal layers). In some embodiments, the target layer material can be an oxide layer, such as silicon oxide. It is understood that the mask layer can include two parts: a first mask layer and a second mask layer. The material of the first mask layer includes, but is not limited to, advanced patterning film (APF) materials, and the material of the second mask layer includes, but is not limited to, oxynitride, such as silicon oxynitride, but is not limited thereto. In some embodiments, the material of the second mask layer can also be other suitable materials.

[0087] Optionally, the target layer, the first mask layer, and the second mask layer can be formed using one or more thin film deposition processes; specifically, the thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0088] Continue to refer to Figures 2 to 5 In some embodiments, a core pattern 152a is formed on the mask layer 12, including:

[0089] A core layer 13 is formed, which covers the mask layer 12.

[0090] An anti-reflection layer 14 is formed, covering the core layer 13;

[0091] The anti-reflection layer 14 and the core layer 13 are etched to form an initial pattern 13b;

[0092] A second dielectric layer 152 is formed, covering the sidewalls of the initial pattern 13b, the top of the initial pattern 13b and the surface of the mask layer 12 between the initial pattern 13b;

[0093] The second dielectric layer 152 on the top of the initial pattern 13b and the portion of the second dielectric layer 152 on the surface of the mask layer 12 between the initial pattern 13b are removed, while the initial pattern 13b is removed, and the second dielectric layer 152 on the sidewalls of the initial pattern 13b is reserved to form a core pattern 152a.

[0094] Here, the core pattern 152a is formed on both the mark area 21 and the blank area 22 in such a way that there is no difference (or only a small difference) in the pattern density in the mark area 21 and the blank area 22. In this case, there is no difference (or only a small difference) in the pattern density in the mark area 21 and the blank area 22, which can effectively prevent the occurrence of the loading effect in the subsequent pattern transfer process, thereby effectively avoiding or reducing the occurrence of local damage to the pattern structure or the occurrence of a hole defect in the material layer in the finally formed semiconductor structure, which is conducive to the improvement of the stability and yield of the semiconductor structure. It can be understood that the more times the subsequent pattern transfer is performed with the above-mentioned core pattern 152a as a mask, the more obvious the improvement of the stability and yield of the semiconductor structure provided by the method of the present embodiment will be.

[0095] In some embodiments, the pattern density in the mark area 21 can be consistent with the pattern density in the blank area 22, and in this case, the finally obtained semiconductor structure can have better stability and yield.

[0096] However, it is not limited thereto, and in actual operation, considering the size limitation in the mark area and the blank area or the size limitation of a single pattern or the pattern pitch, etc., the pattern density set in the mark area and the blank area can also be slightly different. However, compared with the way of not setting a pattern structure in the blank area and then performing pattern transfer in the conventional technology, the way of setting a pattern structure in the blank area can greatly prevent the occurrence of the loading effect and the occurrence of defects in the finally formed semiconductor structure, which is conducive to the improvement of the stability and yield of the semiconductor structure.

[0097] Optionally, in some embodiments, the material of the core layer includes, but is not limited to, a spin-on hard mask layer, which can include an amorphous carbon layer or an amorphous silicon layer, etc. The material of the anti-reflective layer includes, but is not limited to, an oxynitride, such as silicon oxynitride, etc.

[0098] It can be understood that the forming process of the core layer and the anti-reflective layer can be the same as or different from the forming process of the target layer and the mask layer, which is not specifically limited herein.

[0099] It can be understood that, in actual operation, before etching the anti-reflective layer 14 and the core layer 13 to form the initial pattern 13b, the method further includes:

[0100] forming a first mask pattern M1 on the core layer 13.

[0101] Here, the material of the first mask pattern includes, but is not limited to, photoresist, etc.

[0102] It can be understood that, when the material of the first mask pattern includes photoresist, a photolithography process is usually required to complete the definition of the first mask pattern. Generally, because the materials (such as metal layers and dielectric layers) located below the photoresist have a relatively high reflection coefficient, the exposure light source is easily reflected on the surface of these material layers, causing the first mask pattern to be deformed or have a size deviation, so that the mask pattern cannot be correctly transferred. In the preparation method of the embodiments of the present disclosure, the anti-reflective layer is formed below the first mask pattern before the first mask pattern is formed, which can effectively avoid the phenomenon that the first mask pattern is deformed or has a size deviation due to the reflection of the material surface during the photolithography process, so that the pattern on the mask can be correctly transferred to obtain the first mask pattern, thereby providing favorable conditions for obtaining a better pattern structure in the subsequent process.

[0103] Next, step S102 is performed, as shown in Figure 6 and Figure 7 , to etch the mask layer 12 with the core pattern 152a as a mask, so as to obtain a plurality of first patterns 12a located in the mark area 21 and a plurality of first dummy patterns 12d located in the blank area 22.

[0104] In some embodiments, etching the mask layer 12 with the core pattern 152a as a mask includes:

[0105] As shown in Figure 6 , etching the second mask layer 122 and the first mask layer 121 with the core pattern 152a as a mask to form a plurality of initial first patterns 12b located in the mark area 21 and a plurality of initial first dummy patterns 12c located in the blank area 22;

[0106] As shown in Figure 7As shown, the second mask layer 122 is removed, and the first mask layer 121 retained in the mark area 21 forms the first pattern 12a, and the first mask layer 121 retained in the blank area 22 forms the first dummy pattern 12d.

[0107] Optionally, the etching process used to form the first pattern 12a and the first dummy pattern 12d can be a dry etching process, but is not limited thereto. In some embodiments, a wet etching process can also be used to obtain the first pattern 12a and the first dummy pattern 12d. In actual operation, the specific etching method can be flexibly selected according to actual conditions, and is not specifically limited herein.

[0108] Next, step S103 is performed, as shown in Figure 7 The first dielectric layer 151 is formed, which at least covers the sidewalls of the first pattern 12a and the first dummy pattern 12d.

[0109] In some embodiments, forming the first dielectric layer 151 includes:

[0110] The first dielectric layer 151 is formed, which covers the sidewalls and top of the first pattern 12a and the first dummy pattern 12d, and covers the surface of the target layer 11 located between the first pattern 12a, between the first dummy pattern 12d, and between the first pattern 12a and the first dummy pattern 12d.

[0111] Here, the material of the first dielectric layer includes but is not limited to an oxide material, such as silicon oxide, etc.

[0112] Then, step S104 is performed, as shown in Figure 8 and Figure 9 The filling layer 17 is formed, which at least covers the sidewalls of the first dielectric layer 151, and fills the gaps located between adjacent first patterns 12a, between the first dummy patterns 12d, and between the first pattern 12a and the first dummy pattern 12d.

[0113] In some embodiments, forming the filling layer 17 includes:

[0114] The filling material layer 17a is formed on the first dielectric layer 151, which fills the gaps located between adjacent first patterns 12a, between the first dummy patterns 12d, and between the first pattern 12a and the first dummy pattern 12d, and covers the surface of the substrate 10;

[0115] A thinning process is performed on the filling material layer 17a to form the filling layer 17, which exposes the portion of the first dielectric layer 151 located on the top of the first pattern 12a and the first dummy pattern 12d.

[0116] In actual operation, the material of the filling material layer includes, but is not limited to, a spin-on hard mask layer, which can include an amorphous carbon layer or an amorphous silicon layer, etc.

[0117] Next, step S105 is performed, as shown in Figure 9 、 Figure 10 and Figure 11 , the barrier layer 18 located in the blank area 22 is formed, and the first dielectric layer 151 is etched along the sidewall of the first pattern 12a to form the second pattern 12e located in the mark area 21, taking the barrier layer 18 as a mask.

[0118] In some embodiments, the barrier layer 18 located in the blank area 22 is formed, including:

[0119] A barrier material layer (not shown in the figure) is formed, which covers the filling layer 17 and the part of the first dielectric layer 151 exposed by the filling layer 17;

[0120] As shown in Figure 9 , a patterning process is performed to form an initial barrier layer 18a located in the blank area 22;

[0121] As shown in Figure 10 , a thinning process is performed on the initial barrier layer 18a to form the barrier layer 18.

[0122] In some embodiments, as shown in Figure 11 , etching the first dielectric layer 151 along the sidewall of the first pattern 12a, taking the barrier layer 18 as a mask, includes:

[0123] Etching the first dielectric layer 151 along the sidewall of the first pattern 12a, taking the barrier layer 18 as a mask, retains the first pattern 12a and the filling layer 17 in the mark area 21 to form the second pattern 12e.

[0124] It can be understood that by setting the barrier layer on the blank area, after the step of etching the first dielectric layer, only the second pattern in the mark area is generated, which can be used for subsequent pattern transfer, while in the blank area, due to the presence of the barrier layer, the first dummy pattern, the filling layer between the first dummy pattern, and the first dielectric layer on the sidewall of the first dummy pattern are still in a continuous state, that is, there is no pattern structure separated from each other on the blank area, that is, the pattern structure with pattern transfer function is not obtained in the blank area, so that in the subsequent step of etching the target layer for pattern transfer (step S106), no pattern transfer phenomenon occurs in the blank area of the target layer.

[0125] In actual process, as shown in Figure 11As shown, after the process step of etching the first dielectric layer 151 ends, the remaining blocking layer 18 with a certain thickness is still present at the location of the blank area 22. At this time, the remaining blocking layer 18 does not need to be removed, and it can further prevent the phenomenon of the first dummy pattern 12d and the filling layer 17 between the first dummy pattern 12d from being transferred downward at the location of the blank area 22 in the subsequent process of etching the target layer 11 for pattern transfer (step S106).

[0126] In summary, in the embodiments of the present disclosure, the generation of the pattern structure with the transfer function in the blank area can be blocked by setting the blocking layer before etching the first dielectric layer, and the generation of the pattern structure with the transfer function in the blank area due to the first dielectric layer being etched through can be further prevented by retaining the blocking layer with a certain thickness after etching the first dielectric layer. Therefore, in the embodiments of the present disclosure, the setting of the blocking layer on the blank area is conducive to obtaining the desired complete pattern on the target layer after the subsequent etching step ends.

[0127] In actual processes, the material of the blocking layer includes but is not limited to photoresist, and the thickness of the blocking layer can be flexibly selected according to the required etching time, the type and thickness of the material layer thereunder, and the like, which is not specifically limited here.

[0128] It can be understood that in some embodiments, the position of the blocking layer on the blank area and the width relationship between the blocking layer and the blank area can meet certain conditions to help obtain the desired complete pattern on the target layer.

[0129] In some embodiments, when the blocking layer is set, the width information of the blocking layer can refer to the width value between the two outermost boundaries in the orthographic projection of the plurality of first dummy patterns on the substrate in the blank area, but in actual operations, due to various factors such as equipment or process, the actual width value of the blocking layer will have a certain deviation value compared to the set width value, for example, the width value can be larger or smaller.

[0130] It should be noted that in some other embodiments, in addition to referring to the first dummy pattern, the determination of the width information of the blocking layer can also refer to other structures, for example, the filling layer in the blank area, that is, the width information of the blocking layer can be determined by obtaining the width value between the two outermost boundaries in the orthographic projection of the filling layer on the substrate, which can be selected according to actual conditions, which is not specifically limited here.

[0131] Next, the position of the blocking layer on the blank area and the width relationship between the blocking layer and the blank area will be further described in detail in full consideration of the above factors and other possible influencing factors.

[0132] In some embodiments, as shown in FIG. 1, the first dummy pattern 12d located at the outermost side of the plurality of first dummy patterns 12d comprises a first boundary S1, and a boundary of the barrier layer 18 located at the same side of the first boundary S1 is defined as a second boundary S2. Figure 10

[0133] The blank area 22 has a first width W1, the barrier layer 18 has a second width W2, a variation value of the critical dimension of the barrier layer 18 is defined as A, and an offset value between the orthographic projection of the first boundary S1 and the second boundary S2 on the substrate 10 is defined as B. The following relationship is satisfied between the first width W1 and the second width W2:

[0134] W1-W2≥A+B (1).

[0135] It can be understood that, by setting the width difference between the blank area and the barrier layer to be greater than the sum of the variation value of the critical dimension of the barrier layer and the offset value between the two boundaries, the two end portions of the barrier layer can be offset in the direction of the blank area along the mark area within the blank area, so that the barrier layer only plays a blocking role within the blank area, and it can be ensured that the barrier layer will not adversely affect the normal transfer of the pattern in the mark area.

[0136] It can be understood that, in some other embodiments, the width difference between the blank area and the barrier layer can be further limited to help obtain the expected pattern transfer effect. For example:

[0137] In some other embodiments, as shown in FIG. 2, the first dummy pattern 12d located at the outermost side of the plurality of first dummy patterns 12d comprises a first boundary S1, and a boundary of the barrier layer 18 located at the same side of the first boundary S1 is defined as a second boundary S2. Figure 10 The blank area 22 has a first width W1, the barrier layer 18 has a second width W2, a variation value of the critical dimension of the barrier layer 18 is defined as A, an offset value between the orthographic projection of the first boundary S1 and the second boundary S2 on the substrate 10 is defined as B, and the width of a single first dummy pattern 12d is defined as W3. The following relationship is satisfied between the first width W1 and the second width W2:

[0138] A+B≤W1-W2<2W3 (2).

[0139]

[0140] ​​It can be understood that when the end of the blocking layer is too much offset to the inside of the blank area, the first medium layer in the blank area located at the first dummy pattern sidewall will be exposed, at this time, in the process of etching the first medium layer, the pattern structure with pattern transfer function will appear in the blank area. In this case, when the subsequent step of etching the target layer (step S106) is performed, the target layer located in the blank area will appear the unexpected pattern transfer, which should be avoided.

[0141] In the embodiment of the present disclosure, in addition to setting a lower limit value to ensure that the blocking layer plays a blocking function in the blank area without affecting the process of the mark area, an upper limit value is also set, that is, the width difference between the blank area and the blocking layer is less than twice the single first dummy pattern width value, so as to prevent the first medium layer in the blank area from being etched through and the structure with pattern transfer function from appearing. Therefore, the limitation of the width difference range between the blank area and the blocking layer in this embodiment can not only ensure that the blocking layer only plays a blocking role in the blank area, but also further has the beneficial effect of preventing the appearance of pattern structures with pattern transfer function in the blank area, so that the semiconductor structure is greatly conducive to obtaining the expected complete pattern.

[0142] Finally, step S106 is performed, as shown in Figure 12 , the target layer 11 is etched to transfer the second pattern 12e to the target layer 11.

[0143] In some embodiments, etching the target layer 11 includes:

[0144] The target layer 11 is etched with the second pattern 12e and the first dummy pattern 12d, the filling layer 17 and the first medium layer 151 in the blank area 22 as masks to transfer the second pattern 12e to the part of the target layer 11 located in the mark area 21; wherein the part of the target layer 11 located in the blank area 22 is in an unetched state.

[0145] In the embodiment of the present disclosure, since the first dummy pattern 12d located in the blank area 22, the filling layer 17 and the first medium layer 151 located between the first dummy pattern 12d are still in a continuous state when the second pattern 12e is formed, and the blocking layer 18 of a certain thickness is still reserved on the blank area 22, the first medium layer 151 above the blank area 22 of the target layer 11 will not be etched through after the process step of etching the target layer 11. At this time, the first dummy pattern 12d and the filling layer 17 located in the blank area 22 do not have the ability of pattern transfer, so that after the etching process is completed, no pattern transfer phenomenon will occur on the target layer 11 located in the blank area 22, and only the fifth pattern 11a transferred down can be obtained on the target layer 11 located in the mark area 21.

[0146] In some embodiments, as shown in FIG. 1A, after the etching of the target layer 11 to transfer the second pattern 12e onto the target layer 11, the preparation method further comprises: Figure 13

[0147] removing the second pattern 12e, the first dummy pattern 12d, the filling layer 17 and the first dielectric layer 151 on the target layer 11.

[0148] It can be understood that the preparation method provided by the embodiments of the present disclosure can be applied to the fabrication of various semiconductor structures. For example, when the above method is applied in a dynamic random access memory, the structure obtained by the above preparation method in the target layer includes, but is not limited to, an active region, a bit line, a capacitor structure, etc.

[0149] It should be noted that although only the case where the substrate includes the mark area and the blank area is shown in the drawings, the substrate can also include other areas, such as an array area and a peripheral area, in actual processes.

[0150] Optionally, in actual operations, the pattern spacing in the mark area can follow the design size of the spacing between the pattern structures in the array area, and the extension direction of the pattern in the mark area can be parallel to the array line of the array area.

[0151] In addition, optionally, the pattern spacing of the dummy pattern in the blank area can follow the design rule of the dummy pattern in the peripheral area.

[0152] The above embodiments all mention the case of performing pattern transfer on one mask layer after obtaining the core pattern. It can be understood that in actual operations, the number of mask layers located below the core pattern can also be multiple layers, such as 2 layers, 3 layers, 4 layers, 5 layers, 6 layers, dozens of layers, hundreds of layers or even more layers. The multiple mask layers are beneficial to further increase the pattern density or can take into account the effect of improving the pattern transfer precision.

[0153] In the following, taking the structure with 2 mask layers as an example, the method provided by the embodiments of the present disclosure is used to obtain the desired complete pattern on the target layer when the number of mask layers is increased.

[0154] Figures 14 to 19 The process flow chart of the semiconductor structure provided by the embodiments of the present disclosure in the preparation process.

[0155] First, in some embodiments, as shown in FIG. 1A, the target layer 11 and the mask layer 12 are sequentially formed on the substrate 10, including: Figure 14

[0156] ​​A target layer 11 is formed, and the target layer 11 covers the substrate 10;

[0157] A first mask layer 121 is formed, which covers the target layer 11;

[0158] A second mask layer 122 is formed, which covers the first mask layer 121;

[0159] A third mask layer 191 is formed, which covers the second mask layer 122;

[0160] A fourth mask layer 192 is formed, which covers the third mask layer 191.

[0161] In practice, the materials of the third mask layer and the first mask layer can be the same or different; no specific restrictions are imposed here. Similarly, the materials of the second mask layer and the fourth mask layer can be the same or different; no specific restrictions are imposed here.

[0162] Next, as Figures 14 to 16 As shown, in some embodiments, after forming the mask layer 12, the method further includes forming a core pattern 152a. In this embodiment, the method for forming the core pattern 152a is the same as that in the previous embodiment. Figures 2 to 5 The method for forming the core pattern 152a is basically the same, and will not be described in detail here. The difference lies in this embodiment. Figure 16 The pattern density of the core pattern 152a in the previous embodiment is lower than that in the previous embodiment. Figure 5 The density of the core pattern 152a in the image.

[0163] Next, as Figures 17 to 19 As shown, in some embodiments, etching the mask layer 12 using the core pattern 152a as a mask includes:

[0164] Using the core pattern 152a as a mask, the fourth mask layer 192 and the third mask layer 191 are etched to form the initial third pattern 19b located in the marking area 21 and the initial second dummy pattern 19c located in the blank area 22.

[0165] The fourth mask layer 192 is removed, and the third mask layer 191 retained in the marking area 21 forms the third pattern 19a. The third mask layer 191 retained in the blank area 22 forms the second dummy pattern 19d.

[0166] A third dielectric layer 153 is formed, which at least covers the sidewalls of the third pattern 19a and the second dummy pattern 19d;

[0167] An etching process is performed to remove the third pattern 19a and the second dummy pattern 19d, and the third dielectric layer 153 retained in the marked area 21 is defined as the fourth pattern 153a, and the third dielectric layer 153 retained in the blank area 22 is defined as the third dummy pattern 153d.

[0168] Then, in some embodiments, after forming the fourth pattern 153a and the third dummy pattern 153d, the method further includes:

[0169] Execute similar Figure 6 and Figure 7 The steps shown involve first etching the second mask layer 122 and the first mask layer 121 using the fourth pattern 153a and the third dummy pattern 153d as masks, and then removing the second mask layer 122 located above the first mask layer 121 to obtain the desired result. Figure 7 Consistent first pattern 12a and first dummy pattern 12d.

[0170] After that, Figure 7 Based on the structure shown, by executing and Figures 7 to 13 The same or similar steps can be used to obtain the following on target layer 11: Figure 13 The fifth pattern 11a is shown.

[0171] As can be seen, in this embodiment, even if the core pattern has a low pattern density, a pattern structure of the same density can be obtained on the target layer through two pattern transfer processes. Here, the final increase in pattern density occurs on the bottommost mask layer. Therefore, after forming the fill layer and before etching the first dielectric layer, it is only necessary to introduce a barrier layer on the blank area of ​​the bottommost mask layer to prevent the formation of a structure with pattern transfer function in the blank area of ​​this layer.

[0172] Understandably, as the number of mask layers continues to increase (3, 4, 5, 6, a dozen, dozens, or even more layers), the pattern transfer process in the upper mask layers can proceed normally. Only during the final pattern density increase operation, introducing a barrier layer structure in the blank area can prevent pattern transfer at the target layer's location in the blank area in the final semiconductor structure. Therefore, this embodiment is applicable to pattern transfer using multi-layer masks. Furthermore, during the pattern transfer process, introducing a barrier layer only during the final pattern density increase operation is sufficient to obtain the desired complete pattern, with almost no increase in process complexity, and significantly improves the stability and yield of the semiconductor structure.

[0173] This disclosure also provides a semiconductor structure, such as... Figure 11 As shown, the semiconductor structure includes:

[0174] a substrate 10, the substrate 10 at least comprising mark areas 21 and blank areas 22 between the mark areas 21;

[0175] a target layer 11 on the substrate 10;

[0176] a plurality of second patterns 12e on the target layer 11 and a plurality of first dummy patterns 12d on the blank areas 22, a filling layer 17 between the first dummy patterns 12d and a first dielectric layer 151 on sidewalls of the first dummy patterns 12d; wherein the first dummy patterns 12d on the blank areas 22, the filling layer 17 between the first dummy patterns 12d and the first dielectric layer 151 on sidewalls of the first dummy patterns 12d are in a continuous state;

[0177] a barrier layer 18 on the first dummy patterns 12d of the blank areas 22.

[0178] The embodiments of the present disclosure further provide another semiconductor structure, as shown in the accompanying drawings: Figure 13 The semiconductor structure comprises:

[0179] a substrate 10, the substrate 10 at least comprising mark areas 21 and blank areas 22 between the mark areas 21;

[0180] a target layer 11 on the substrate 10, the target layer 11 being provided with a fifth pattern 11a only at positions of the mark areas 21.

[0181] It can be understood that the semiconductor structure can be manufactured by the method provided in any of the above embodiments.

[0182] It should be noted that the method for manufacturing the semiconductor device provided by the embodiments of the present disclosure can be applied to a DRAM structure or other semiconductor devices, and is not limited herein. The embodiments of the method for manufacturing the semiconductor device provided by the present disclosure belong to the same concept as the embodiments of the semiconductor device; the technical features in the technical solutions described in each embodiment can be combined arbitrarily without conflict.

[0183] The above merely describes the preferred embodiments of the present disclosure, but not for limiting the protection scope of the present disclosure, and any modification, equivalent replacement and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Preparation methods include: A substrate is provided, the substrate including at least a marking area and a blank area located between the marking areas; a target layer and a mask layer are sequentially formed on the substrate, the target layer and the mask layer conformally covering the substrate; a core pattern is formed on the mask layer; The mask layer is etched using the core pattern as a mask to obtain a plurality of first patterns located in the marked area and a plurality of first dummy patterns located in the blank area; A first dielectric layer is formed, the first dielectric layer at least covering the sidewalls of the first pattern and the first dummy pattern; A filling layer is formed, which at least covers the sidewalls of the first dielectric layer and fills the gaps between adjacent first patterns, between first dummy patterns, and between first patterns and first dummy patterns; A barrier layer is formed in the blank area. Using the barrier layer as a mask, the first dielectric layer is etched along the sidewall of the first pattern to form a second pattern in the marking area. The target layer is etched to transfer the second pattern onto the target layer.

2. The preparation method according to claim 1, characterized in that, Forming a core pattern on the mask layer includes: A core layer is formed, which covers the mask layer; An anti-reflective layer is formed, which covers the core layer; The anti-reflective layer and the core layer are etched to form an initial pattern; A second dielectric layer is formed, which covers the sidewalls, top, and surface of the mask layer located between the initial patterns; Remove the second dielectric layer located on top of the initial pattern and a portion of the second dielectric layer located between the initial patterns and on the surface of the mask layer, while simultaneously removing the initial pattern, leaving the second dielectric layer located on the sidewall of the initial pattern to form the core pattern.

3. The preparation method according to claim 1, characterized in that, A target layer and a mask layer are sequentially formed on the substrate, including: A target layer is formed, the target layer covering the substrate; A first mask layer is formed, which covers the target layer; A second mask layer is formed, which covers the first mask layer; Etching the mask layer using the core pattern as a mask includes: The second mask layer and the first mask layer are etched using the core pattern as a mask to form a plurality of initial first patterns located in the marked area and a plurality of initial first dummy patterns located in the blank area; The second mask layer is removed, and the first mask layer remaining in the marked area constitutes the first pattern, while the first mask layer remaining in the blank area constitutes the first dummy pattern.

4. The preparation method according to claim 1 or 3, characterized in that, Forming a first dielectric layer includes: A first dielectric layer is formed, which covers the sidewalls and top of the first pattern and the first dummy pattern, and covers the surface of the target layer located between the first patterns, between the first dummy patterns, and between the first patterns and the first dummy patterns.

5. The preparation method according to claim 4, characterized in that, Forming a filler layer, including: A filling material layer is formed on the first dielectric layer, the filling material layer filling the gaps between adjacent first patterns, between first dummy patterns and between first patterns and first dummy patterns, and covering the surface of the substrate; A thinning process is performed on the filler material layer to form the filler layer, which exposes the portion of the first dielectric layer located on top of the first pattern and the first dummy pattern.

6. The preparation method according to claim 5, characterized in that, Forming a barrier layer located in the blank area includes: A barrier material layer is formed, which covers the portion of the filler layer and the first dielectric layer exposed by the filler layer; A patterning process is performed to form an initial barrier layer located in the blank area; A thinning process is performed on the initial barrier layer to form the barrier layer.

7. The preparation method according to claim 6, characterized in that, Using the barrier layer as a mask, etching the first dielectric layer along the sidewall of the first pattern includes: Using the barrier layer as a mask, the first dielectric layer is etched along the sidewall of the first pattern, and the first pattern retained in the marking area and the filling layer constitute the second pattern.

8. The preparation method according to claim 1, characterized in that, The outermost first dummy pattern among the plurality of first dummy patterns includes a first boundary, and the boundary of the barrier layer located on the same side as the first boundary is defined as a second boundary; The blank area has a first width W1, the barrier layer has a second width W2, the variation value of the critical dimension of the barrier layer is defined as A, and the offset value between the orthographic projections of the first boundary and the second boundary on the substrate is defined as B; the first width W1 and the second width W2 satisfy the following relationship: W1-W2≥A+B (1).

9. The preparation method according to claim 1, characterized in that, The outermost first dummy pattern among the plurality of first dummy patterns includes a first boundary, and the boundary of the barrier layer located on the same side as the first boundary is defined as a second boundary; The blank area has a first width W1, the barrier layer has a second width W2, the variation value of the critical dimension of the barrier layer is defined as A, the offset value between the orthographic projections of the first boundary and the second boundary on the substrate is defined as B, and the width of a single first dummy pattern is defined as W3; the first width W1 and the second width W2 satisfy the following relationship: A+B≤W1-W2<2W3 (2).

10. The preparation method according to claim 1, characterized in that, Etching the target layer includes: The target layer is etched using the second pattern, the first dummy pattern located in the blank area, the filling layer, and the first dielectric layer as a mask to transfer the second pattern to the portion of the target layer located in the marked area; wherein the portion of the target layer located in the blank area is in an unetched state.

11. The preparation method according to claim 10, characterized in that, After etching the target layer to transfer the second pattern onto the target layer, the fabrication method further includes: Remove the second pattern, the first dummy pattern, the fill layer, and the first dielectric layer located on the target layer.

12. The preparation method according to claim 1, characterized in that, A target layer and a mask layer are sequentially formed on the substrate, including: A target layer is formed, the target layer covering the substrate; A first mask layer is formed, which covers the target layer; A second mask layer is formed, which covers the first mask layer; A third mask layer is formed, which covers the second mask layer; A fourth mask layer is formed, which covers the third mask layer.

13. The preparation method according to claim 12, characterized in that, Etching the mask layer using the core pattern as a mask includes: The fourth mask layer and the third mask layer are etched using the core pattern as a mask to form an initial third pattern in the marked area and an initial second dummy pattern in the blank area; The fourth mask layer is removed, and the third mask layer remaining in the marked area forms a third pattern, while the third mask layer remaining in the blank area forms a second dummy pattern. A third dielectric layer is formed, which at least covers the sidewalls of the third pattern and the second dummy pattern; An etching process is performed to remove the third pattern and the second dummy pattern, and the third dielectric layer retained in the marked area is defined as the fourth pattern, and the third dielectric layer retained in the blank area is defined as the third dummy pattern.

14. A semiconductor structure, characterized in that, The semiconductor structure is manufactured using the method described in any one of claims 1-13.

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