Tungsten filling method, semiconductor manufacturing method, and semiconductor device

Abstract

The present application relates to a tungsten filling method, a semiconductor manufacturing method and a semiconductor device. The tungsten filling method comprises the following steps: growing a silicon layer on the inner wall of a hole; introducing WF6 gas into the hole to cause a displacement reaction with the silicon layer, thereby replacing the silicon layer with a tungsten layer; growing a silicon layer on the surface of the generated tungsten layer and introducing WF6 gas to displace the next layer of tungsten layer; repeating the above steps until the generated tungsten fills the hole. The tungsten filling method can fill metal tungsten in the hole without gaps.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a tungsten filling method, a semiconductor manufacturing method and a semiconductor device. BACKGROUND

[0002] Three-dimensional (3D) wafer-to-wafer, die-to-wafer, or die-to-die vertical stacking technology seeks to achieve the long-sought goal of vertically stacking multiple layers of active IC devices (such as processors, programmable devices, and memory devices) to shorten average wire length, thereby reducing interconnect RC delay and improving system performance.

[0003] In the process of chip packaging, vertical conduction between chips and between wafers is made through contact via to realize the interconnection between chips. The contact via is filled with conductive material, and tungsten is usually deposited by chemical vapor deposition for filling. For example, a layer of adhesion layer (Ti / TiN) is first grown in the contact via, and then tungsten is filled.

[0004] However, although the deposition of tungsten has good coverage, the contact via has a high aspect ratio, and a seam is usually generated during the filling process, which can cause a series of problems in the manufacture of electronic devices. Moreover, as the size of the element decreases, the generation of the seam becomes one of the main problems affecting the electrical properties of the contact via. SUMMARY

[0005] In view of at least one deficiency in the related art, the present application provides a tungsten filling method, a semiconductor manufacturing method, and a semiconductor device.

[0006] A first aspect of an embodiment of the present application provides a tungsten filling method for filling tungsten in a hole, comprising the following steps:

[0007] Growing a silicon layer on the inner wall of the hole;

[0008] Introducing WF6 gas into the hole to cause a displacement reaction between the WF6 gas and the silicon layer, and replace the silicon layer with a tungsten layer;

[0009] Growing a silicon layer on the surface of the generated tungsten layer and introducing WF6 gas to displace the next layer of tungsten;

[0010] Repeating the above steps until the generated tungsten is filled in the hole.

[0011] In some embodiments of the present application, after each round of displacement reaction is completed, the surface of the generated tungsten layer is subjected to plasma treatment.

[0012] In some embodiments of the present application, no adhesion layer is provided on the inner wall of the hole before the growth of the silicon layer.

[0013] In some embodiments of the present application, after the hole is filled with tungsten, a planarization process is further performed on the surface of the hole.

[0014] A second aspect of the embodiments of the present application provides a manufacturing method of a semiconductor device, comprising the following steps:

[0015] forming one or more than one semiconductor chip assembly on the semiconductor substrate;

[0016] forming an interlayer dielectric on the semiconductor substrate and the semiconductor chip assembly;

[0017] forming a contact window extending into the semiconductor substrate in the interlayer dielectric;

[0018] filling the contact window according to the tungsten filling method of any one of the above;

[0019] performing a backside thinning process on the semiconductor substrate to expose the contact window on the backside of the semiconductor substrate.

[0020] In some embodiments of the present application, in the step of forming the contact window, a patterned hard mask is provided on the interlayer dielectric, and the contact window is formed by a wet etching or dry etching process.

[0021] In some embodiments of the present application, after the filling of the contact window is completed, the following steps are further included: forming a metal interlayer dielectric on the contact window and the interlayer dielectric, and forming a first conductive element in the metal interlayer dielectric, the first conductive element being electrically connected with the semiconductor chip assembly and the contact window.

[0022] In some embodiments of the present application, after the backside thinning process is performed, the following steps are further included: forming a backside dielectric layer on the backside of the semiconductor substrate, and forming a second conductive element in the backside dielectric layer, the second conductive element being electrically connected with the contact window.

[0023] A third aspect of the embodiments of the present application provides a semiconductor device manufactured according to the manufacturing method of the semiconductor of any one of the above.

[0024] In some embodiments of the present application, the contact window is filled with tungsten, and there is no gap inside the tungsten and no adhesion layer between the tungsten and the inner wall of the contact window.

[0025] Compared with the prior art, the present application has the following advantages and positive effects:

[0026] (1) The tungsten filling method provided by at least one embodiment of the present application uses a silicon layer as the basis, and grows tungsten layers in turn through multiple displacement reactions, so that metal tungsten can be filled in the hole without gaps.

[0027] (2) The tungsten filling method provided by at least one of the embodiments of the present application can effectively remove surface impurities and improve the purity of the tungsten layer film after each round of tungsten layer replacement is completed, thereby avoiding the situation that the contact window is sealed and the formed tungsten layer is more dense.

[0028] (3) The semiconductor device provided by at least one of the embodiments of the present application has no gap in the filled metal tungsten of the contact window, and the electrical performance of the semiconductor device can be improved; in addition, the contact window is filled by means of the silicon layer replacement stack, and the adhesion layer (Ti / TiN) in the prior art can be cancelled. BRIEF DESCRIPTION OF DRAWINGS

[0029] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and serve to explain the present application. In the drawings:

[0030] Figure 1 A flowchart of a semiconductor manufacturing method provided by an embodiment of the present application;

[0031] Figure 2 A flowchart of a tungsten filling method provided by an embodiment of the present application;

[0032] Figures 3a-3f A schematic diagram of each stage in the filling process of a contact window in an embodiment of the present application;

[0033] Figure 4 A cross-sectional schematic diagram of a semiconductor device after step S2 of the semiconductor manufacturing method provided by an embodiment of the present application is completed;

[0034] Figure 5 A cross-sectional schematic diagram of a semiconductor device after step S3 of the semiconductor manufacturing method provided by an embodiment of the present application is completed;

[0035] Figure 6 A cross-sectional schematic diagram of a semiconductor device after step S4 of the semiconductor manufacturing method provided by an embodiment of the present application is completed;

[0036] Figure 7 A cross-sectional schematic diagram of a semiconductor device after step S7 of the semiconductor manufacturing method provided by an embodiment of the present application is completed.

[0037] In the drawings:

[0038] 100, semiconductor substrate; 101, interlayer dielectric; 102, contact window; 103, metal interlayer dielectric; 104, conductive pad; 105, back dielectric layer; 200, semiconductor chip assembly. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0040] Obviously, the drawings in the following description are only some examples or embodiments of the present application, and for those of ordinary skill in the art, the present application can be applied to other similar scenarios without creative effort on the basis of the drawings. In addition, it can be understood that although the efforts made in this development process can be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacture or production changes on the basis of the technical content disclosed in the present application are only routine technical means, and should not be understood as insufficient disclosure of the content disclosed in the present application.

[0041] In the present application, "embodiments" means that the specific features, structures or characteristics described in combination with the embodiments can be contained in at least one embodiment of the present application. The phrase appears at various places in the specification does not necessarily refer to the same embodiments, nor is it mutually exclusive or alternative embodiments to other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in the present application can be combined with other embodiments without conflict.

[0042] It is worth understanding that although the drawings can show a specific order of method steps, the order of steps can be different from the depicted order. In addition, two or more steps can be performed simultaneously or partially simultaneously. Such variations will depend on the chosen software and hardware and the designer's choice. All such variations are within the scope of the present disclosure.

[0043] Unless otherwise defined, technical terms and scientific terms used in the present application shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terms "a", "an", "one", "this", and similar referents in the context of describing the application are to be construed to be inclusive, not exclusive. The terms "comprising", "containing", "having", and "including" and their variations are to be construed as open-ended, not limiting. For example, a process, method, system, product, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but can include other steps or elements not expressly listed or inherent to such process, method, system, product, or apparatus. The terms "coupled", "connected", "coupling", and "connecting" refer to either a direct connection or an indirect connection through one or more intermediate connections or elements. The term "multiple" means two or more. The term "and / or" describes associated objects in that there can be one, two, or all three of the associated objects. The term " / " is generally used to indicate "or". The terms "first", "second", and the like are used to distinguish similar objects, not to denote a particular order.

[0044] The "aspect ratio" as described in the present application refers to the ratio of the height to the width of a contact. The term "contact" refers to an opening in a semiconductor device for filling with a conductive material, the opening passing through at least a portion of a semiconductor substrate. In the present application, elements not specifically shown or described can take a variety of forms known to those skilled in the art. Also, when a layer is said to be on or over another layer or a substrate, it can be directly on or over the other layer or the substrate, or intervening layers can also be present.

[0045] The embodiments of the present application provide a semiconductor manufacturing method, in which a tungsten filling method provided by the embodiments of the present application is included. The semiconductor manufacturing method provided by the present application will be described in detail below in combination with embodiments, in which the tungsten filling method will be described in detail in corresponding method steps taking a semiconductor contact as an example.

[0046] As shown in FIG. 1, the semiconductor manufacturing method provided by the embodiments of the present application includes the following steps: Figure 1

[0047] S1: forming one or more than one semiconductor chip assembly on a semiconductor substrate;

[0048] S2: forming an interlayer dielectric on the semiconductor substrate and the semiconductor chip assembly;

[0049] ​S3: forming a contact hole in the interlayer dielectric extending into the semiconductor substrate;

[0050] S4: filling the contact hole with tungsten;

[0051] S5: forming a metal interlayer dielectric on the contact hole and the interlayer dielectric, and forming a first conductive element in the metal interlayer dielectric electrically connected with the chip component and the contact hole;

[0052] S6: performing a backside thinning process on the semiconductor substrate to expose the contact hole on a backside of the semiconductor substrate;

[0053] S7: forming a backside dielectric layer on the backside of the semiconductor substrate, and forming a second conductive element in the backside dielectric layer electrically connected with the contact hole.

[0054] The steps in the manufacturing method will be described in detail below in conjunction with the accompanying drawings.

[0055] In the embodiments of the present application, the semiconductor structure is formed by means of a wafer. Specifically, step S1, a semiconductor substrate 100 is formed in a wafer, and one or more than one semiconductor chip component 200 is formed in and / or on the semiconductor substrate 100.

[0056] In some embodiments, the semiconductor substrate 100 is a bulk substrate, alternatively, it can also be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate has a front surface and a back surface, and the chip component 200 is formed on the front surface side of the semiconductor substrate 100.

[0057] In some embodiments, the semiconductor chip component 200 can include a plurality of individual circuit elements, such as transistors (e.g. MOS), diodes, resistors, capacitors, and / or other active or passive semiconductor devices formed by various integrated circuit manufacturing processes. As for the specific formation method of the semiconductor chip component 200, no detailed description will be given in the present application, and any prior art method capable of forming the semiconductor chip component 200 can be referred to.

[0058] Step S2, an interlayer dielectric 101 is formed on the semiconductor substrate 100 and the semiconductor chip component 200. For example, the interlayer dielectric 101 is formed by deposition. The cross-sectional view of the semiconductor device formed after step S2 is shown in FIG. 1B. Figure 4In some embodiments, the interlayer dielectric (ILD) 101 can employ an oxygen-containing dielectric material, for example, tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped PSG (BPSG), etc. In some embodiments, the interlayer dielectric 101 can be formed by, for example, FCVD, spin coating, CVD, or another deposition method.

[0059] Next, at step S3, a contact window 102 extending into the semiconductor substrate 100 is formed in the interlayer dielectric 101. A cross-sectional view of the semiconductor device formed after step S3 is shown in FIG. 1C. Figure 5 The contact window 102 has a high aspect ratio, for example, an aspect ratio of 5-10. In some embodiments, a patterned hard mask is disposed on the interlayer dielectric 101, and a contact window extending from the interlayer dielectric 101 into the semiconductor substrate 100 is formed by a wet etching or dry etching process. Dry etching uses plasma gas to bombard the surface of the material to achieve etching effect. Because of its high etching rate, good directionality, ability to manufacture large aspect ratio holes, and strong controllability of etching rate, dry etching is the most commonly used method. The contact window 102 extends from the surface of the interlayer dielectric 101 to at least a portion of the semiconductor substrate 100. In some embodiments, the etching process includes a deep reactive ion etching process to etch a portion of the semiconductor substrate 100.

[0060] At step S4, the contact window 102 is filled with a conductive material, typically a metal material, and thus this step is also referred to as metallization of the contact window 102. In the embodiments provided in the present application, the contact window 102 is mainly filled with tungsten, and the tungsten filling method provided in the present application is used to fill the contact window 102. In the following description, the contact window 102 will be used as a specific form of a hole in the tungsten filling method, and the tungsten filling method will be described in detail with the aid of the contact window 102. The tungsten filling method provided in the embodiments of the present application (in this embodiment, the contact window filling method) is shown in FIG. 1D, and includes the following steps: Figure 2

[0061] S401: growing a silicon layer on the inner wall of the contact window 102;

[0062] S402: introducing WF6 gas into the contact window 102, so that the silicon layer on the inner wall of the contact window 102 reacts with the WF6 gas to replace the silicon layer with a tungsten layer;

[0063] S403: growing a silicon layer on the surface of the generated tungsten layer and introducing WF6 gas to replace the next layer of tungsten;

[0064] S404: repeating the above step S403 until the generated tungsten is filled in the contact window 102.​

[0065] The following will refer to Figures 3a-3f The tungsten filling method provided in the above embodiments will be described in detail. A schematic diagram of the initial stage of the filling process is shown below. Figure 3a As shown.

[0066] In step S401, any suitable method can be used to grow the silicon layer. For example, in some embodiments, ultra-high vacuum chemical vapor deposition (UHV-CVD) or MEB (Medium-Expansion) methods are used as the growth method. For example, silane (SiH4) or tetraethoxysilane (TEOS) can be used to generate the silicon layer. Figure 3b As shown, after step S401, a silicon layer is grown on the inner wall of the contact window 102.

[0067] In step S402, WF6 gas is introduced into the contact window 102. The WF6 gas enters the contact window 102 and undergoes a displacement reaction with the silicon layer grown on the inner wall of the contact window 102. The chemical formula for the displacement reaction is 2WF6 + 3Si → 2W + 3SiF4. After the displacement reaction, the tungsten layer replaces the original silicon layer, and the colorless SiF4 gas generated escapes from the opening at the top of the contact window 102. Thus, a thin film of metallic tungsten is filled into the contact window 102. Figure 3c As shown.

[0068] In step S403, a silicon layer is grown on the surface of the generated tungsten layer and WF6 gas is introduced to replace the next tungsten layer; after this round of replacement is completed, a second tungsten layer is grown on the surface of the first tungsten layer.

[0069] In step S404, step S403 is repeated until the tungsten generated by the displacement fills the contact window 102, as shown. Figure 3e As shown.

[0070] In some embodiments, after steps S402 and S403, i.e., as Figure 3d As shown, after each round of displacement reaction, step S405 is included, which involves plasma treatment of the surface of the tungsten layer generated by the displacement. During plasma treatment, the tungsten layer generated after displacement is bombarded by a high-energy ion stream, which effectively removes surface impurities, improves the purity of the tungsten layer, and prevents the contact window 102 from sealing during metallization. Furthermore, the tungsten layer after plasma treatment is denser and more compact. In some embodiments, the plasma gas used in the plasma treatment process is H2 or N2, etc.

[0071] The above embodiment, after the first displacement reaction is completed, plasma treatment (optional), and then the first layer of tungsten layer on the growth of silicon layer, followed by the introduction of WF6gas and silicon layer displacement reaction, the second layer of tungsten layer, plasma treatment (optional) is carried out on the second layer of tungsten layer, and then according to the above steps cycle for the third layer, the fourth layer... Growth of tungsten layer until the tungsten fills the contact window 102.

[0072] The filling method of the contact window 102 provided by the above embodiment uses displacement reaction to sequentially grow tungsten layer film, and uses plasma treatment to post-treat the newly grown film after film growth, which can sequentially and seamlessly grow tungsten layer, avoids the pore problem generated by the traditional process, and the grown tungsten layer has high purity and good density.

[0073] In addition, compared with the traditional process, the filling method of the contact window 102 fills the contact window 102 by growing the silicon layer, which does not generate gaps, and the tungsten layer does not have adhesion problems through subsequent process flow, so that in the filling method provided in the present application, the adhesion layer (Ti / TiN) can not be set.

[0074] It can be understood that the filling method provided in the above application can be applied to any scene that needs to fill metal tungsten, and is not limited to the contact window.

[0075] In some embodiments, after the tungsten fills the contact window, the process of planarizing the surface of the contact window 102 is further included in step S406, so that the silicon layer accumulated at the opening of the contact window 102 is removed, so that the metallized contact window 102 has a surface flat with the surrounding opening. The contact window after the planarization process is shown in Figure 3f In some embodiments, the planarization process can use existing methods such as etching, chemical mechanical polishing (CMP), etc.

[0076] After the above steps, the metallization of the contact window 102 in the semiconductor device is completed. Next, the semiconductor device is subjected to back-end-of-line (BEOL) interconnection.

[0077] Step S5, forming a metal interlayer dielectric 103 on the metallized contact window 102 and the interlayer dielectric 101 (see Figure 7), a first conductive element is formed in the metal interlayer dielectric 103, and the first conductive element is electrically connected to the semiconductor chip assembly 200 and the contact window 102. There can be two or more first conductive elements. In some embodiments, the metal interlayer dielectric 103 can be a dielectric layer including multiple layers of dielectric material, one or more of which is made of a low dielectric constant material, such as SiO2, etc. In some embodiments, the conductive element includes a wire (not shown) and a conductive pad 104 in the metal interlayer dielectric 103, the conductive pad 104 being connected to the semiconductor chip assembly 200 and the contact window 102 by the wire. The conductive pad 104 can be made of, for example, copper or a copper alloy.

[0078] At step S6, a backside thinning process is performed on the semiconductor substrate 100 to expose the metal tungsten in the contact window 102 on the backside of the semiconductor substrate 100. During the thinning process, the wafer is bonded to a carrier due to its relatively thin thickness, and the backside of the wafer is thinned, and the metal tungsten in the contact window 102 is exposed on the backside of the wafer after the thinning. The thinning process can be performed using existing techniques, such as polishing, etc.

[0079] At step S7, after the thinning process is performed, a backside dielectric layer 105 (see FIG. 1C) is formed on the backside of the semiconductor substrate 100, and a second conductive element is formed in the backside dielectric layer 105. The second conductive element can include a wire and a conductive pad 104 in the backside dielectric layer 105, the conductive pad 104 being electrically connected to the contact window 102 by the wire (not shown). Figure 7

[0080] Two or more semiconductor devices formed by the above method are bonded together at the location of the conductive pad to form a three-dimensional chip structure. The bonding method can include oxide-oxide bonding, oxide-silicon bonding, copper-copper bonding, copper-solder bonding, adhesive bonding, or a combination thereof.

[0081] Another aspect of the embodiments of the present application provides a semiconductor device formed by the above semiconductor manufacturing method. In the structure of the semiconductor device, the contact window 102 is filled with metal tungsten, and there is no adhesion layer between the tungsten and the inner wall of the contact window 102, which is usually a Ti or TiN layer in the prior art. That is, in some embodiments, there is no Ti layer or TiN layer between the tungsten and the inner wall of the contact window 102.

[0082] Finally, it should be noted that the various embodiments described in the specification are progressive, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0083] ​The above examples are only used to illustrate the technical solutions of the present application but not to limit the present application; although the present application has been described in detail with reference to the preferred embodiments, it is understood by the person of ordinary skill in the art that the specific embodiments of the present application can be modified or some technical features can be replaced by equivalent ones without departing from the spirit of the technical solutions of the present application, and all of them should be covered in the technical solution range of the present application claimed.

Claims

1. A filling method of tungsten for filling tungsten in a hole, characterized by, The method comprises the following steps: forming a silicon layer on the inner wall of the hole; no adhesion layer is formed on the inner wall of the hole before the formation of the silicon layer; introducing WF6 gas into the hole to cause a displacement reaction between the WF6 gas and the silicon layer, thereby replacing the silicon layer with a tungsten layer; forming a silicon layer on the surface of the generated tungsten layer and introducing WF6 gas to displace the next tungsten layer; repeating the above steps until the hole is filled with the generated tungsten.

2. The tungsten filling method according to claim 1, wherein After each round of displacement reaction is completed, the surface of the generated tungsten layer is subjected to plasma treatment.

3. The tungsten filling method according to claim 1, wherein After the hole is filled with tungsten, a process of planarizing the surface of the hole is further included.

4. A method of manufacturing a semiconductor device, characterized by The method comprises the following steps: forming one or more than one semiconductor chip assembly on a semiconductor substrate; forming an interlayer dielectric on the semiconductor substrate and the semiconductor chip assembly; forming a contact window extending into the semiconductor substrate in the interlayer dielectric; filling the contact window according to the tungsten filling method of any one of claims 1-3; performing a back-thinning process on the semiconductor substrate to expose the contact window on the back surface of the semiconductor substrate.

5. The method of manufacturing a semiconductor device according to claim 4, wherein In the step of forming the contact window, a patterned hard mask is formed on the interlayer dielectric, and the contact window is formed by a wet etching or dry etching process.

6. The method of manufacturing a semiconductor device according to claim 4, wherein After the filling of the contact window is completed, a metal interlayer dielectric is further formed on the contact window and the interlayer dielectric, and a first conductive element is formed in the metal interlayer dielectric, wherein the first conductive element is electrically connected to the semiconductor chip assembly and the contact window.

7. The method of manufacturing a semiconductor device according to claim 4, wherein After the back-thinning process is performed, a back dielectric layer is further formed on the back surface of the semiconductor substrate, and a second conductive element is formed in the back dielectric layer, wherein the second conductive element is electrically connected to the contact window.

8. A semiconductor device manufactured according to the manufacturing method of the semiconductor device of any one of claims 4-7.

9. The semiconductor device of claim 8, wherein, The contact window is filled with tungsten, and there is no gap inside the tungsten and no adhesion layer between the tungsten and the inner wall of the contact window.

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