Digital power amplifier and power decoupling method, system thereof

Abstract

The application discloses a digital power amplifier and a power decoupling method and system thereof, wherein a power decoupling circuit is used as an energy buffering link to balance the unbalanced energy on the input side and the output side, the current of a direct-current side energy storage capacitor is tracked, and the direct-current bus current component is shunted, so that the current of the direct-current side energy storage capacitor is reduced. The direct-current bus voltage and current ripple are effectively suppressed, power decoupling is realized, and the application can be applied to the special requirements of wideband and multi-frequency mixed output, and is widely applicable.

Description

TECHNICAL FIELD

[0001] The present application relates to the power supply technical field in electrical engineering, and particularly to a digital power amplifier and a power decoupling method and system thereof. BACKGROUND

[0002] The digital power amplifier, as one of the commonly used DC / AC converters, is essentially a single-phase inverter. In the single-phase inverter, no matter what kind of topology structure is adopted, the instantaneous power imbalance between the DC side and the AC side of the single-phase inverter will cause the double-frequency pulsating power and the reactive power on the AC side to be mapped to the DC side, and form the double-frequency ripple of the DC side voltage and current, which increases the loss of the power devices and the passive magnetic devices in the device, causes the temperature of the device to rise, and affects the reliable operation of the device; at the same time, it affects the closed-loop control of the front-stage DC power supply and the modulation calculation of the rear-stage power amplifier, and poses a threat to the stability of the device.

[0003] In view of the above problems, a large number of electrolytic capacitors are usually placed on the DC side of the single-phase inverter in engineering to balance the instantaneous power and reduce the amplitude of the capacitor voltage fluctuation, but this method will also cause the power density and reliability of the device to decrease, and will also cause the volume and cost of the digital power amplifier to increase substantially.

[0004] The invention patent application “Power decoupling circuit coupled on AC side” (publication number: CN106787873A, publication date: May 31, 2017) can realize the decoupling of the DC power and the AC power on the AC side by being connected in parallel on the output side of the inverter, but the decoupling circuit thereof is composed of seven switching tubes, one capacitor and one inductor, has a complex structure, the control method is extremely complex, and since it is designed for the control of the parameters of the photovoltaic power generation grid-connected system, it cannot effectively decouple the power in the case of multi-frequency mixed output. The invention patent application “Single-phase inverter capable of suppressing secondary ripple and improving power density and control method” (publication number: CN113037120A, publication date: June 25, 2021) can realize the decoupling of the DC power and the AC power by adding a power decoupling circuit on the DC side, but it needs to additionally add four switching tubes, one power decoupling filter capacitor and one inductor, and since the control method designed for the power decoupling circuit is obtained by calculating the control signal when the inverter outputs a single frequency, the power cannot be effectively decoupled in the case of multi-frequency mixed output of the inverter. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a digital power amplifier and a power decoupling method and system thereof for solving the problems in the prior art, which can well realize the DC power decoupling in the special cases of wideband output and multi-frequency mixed output.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: a power decoupling method for a digital power amplifier, wherein the digital power amplifier includes a single-phase full-bridge inverter circuit; the single-phase full-bridge inverter circuit is connected to a power decoupling circuit; the power decoupling circuit is connected to a DC-side energy storage capacitor; the power decoupling circuit includes two series-connected switching transistors, one end of a decoupling inductor is connected between the two switching transistors, and the other end is connected to a decoupling capacitor; the method includes:

[0007] S1. Calculate the current tracking reference i using the following formula. axref :i axref =ai c -i cs ; where i cs To decouple capacitor C ax voltage reference value u axref Compared with the actual value u ax The difference is subtracted, and the fluctuation of the decoupling capacitor current is obtained through proportional-integral control, i c DC-side energy storage capacitor C dc The current, where a is a set constant;

[0008] Decoupling inductor L ax current i L (t) The corresponding control current i is obtained through proportional control. ax ;

[0009] S2, Transfer the current tracking reference i axref With control current i ax The difference is calculated, and the difference is used to obtain the control duty cycle d of the power decoupling circuit through proportional control. s ;

[0010] S3, adjust the duty cycle d s The switching control signal PWM is obtained by comparing it with a triangular carrier wave with a threshold of 0-1;

[0011] S4. Based on the PWM signal and the mode signal, obtain the switching timing signal G of the two switching transistors in the power decoupling circuit. S5 and G S6 : Where, when i c When (t)>0, mode=1; when i c When (t) < 0, mode = 0; i c (t) represents the instantaneous current of the DC-side capacitor.

[0012] The present application only needs to measure the DC side capacitor voltage of the digital power amplifier, thereby observing the DC side current double-frequency ripple, and controlling the power decoupling circuit through the power decoupling control method, and tracking the current of the DC side capacitor by a times, since the decoupling control method only needs to observe the current of the DC side capacitor in the digital power amplifier to control the realization of the pulsating power and the DC power decoupling, and the output frequency of the digital power amplifier is not required, so the power decoupling can be realized in the special case of the wideband and multi-frequency mixed output of the digital power amplifier.

[0013] In order to realize the maximum decoupling capacity of the decoupling circuit and prevent the divergence of the decoupling capacitor voltage, in the present application, U dc is the DC side power supply voltage value.

[0014] In the present application, the design of the parameter a is equivalent to introducing a proportional control link, so the value of a should not be too large, and therefore a is set to be less than 10.

[0015] i ax = K1i L In the present application, in order to ensure the control speed and prevent the excessive overshoot, K1 is less than 10.

[0016] In step S2, the duty ratio d s is calculated according to the formula: d s = K2(i axref -i ax ). In the present application, in order to facilitate the comparison with the 0-1 triangular carrier, the coefficient K2 is set to be K2 = max(i axref -i ax ).

[0017] In step S4, the calculation formula of i c (t) is: i L (t) = l L C ax ; wherein, u L (t0) represents the voltage sampling value at t0, u L (t1) and u L (t2) respectively represent the voltage sampling value at t1 and the voltage sampling value at t2, u * L (t3) represents the voltage calculation value at t3, t s represents the sampling period, t r represents the filter delay, l L represents the current voltage change rate calculation value, and C ax represents the capacitance value of the decoupling capacitor.

[0018] The rate of change of capacitor voltage is obtained by sampling and calculating the voltage. However, the sampled voltage signal contains a large number of switching subharmonics, requiring filtering of the sampling stage before it can be used. The low-pass filter of this invention has a cutoff frequency approximately equal to the switching frequency, introducing a delay. Simultaneously, the rate of change of voltage obtained by subtracting consecutive samples differs from the actual rate of change of voltage by one sampling period, equivalent to a delay stage with one sampling period itself. To eliminate the delay effects of these two stages, the above formula is used for fitting and extrapolation, which can predict the rate of change of voltage at the current moment, thus solving the delay problem.

[0019] The output voltage u of the digital power amplifier o and output current i o Satisfy the following formula: In the formula, the output voltage amplitude of the digital power amplifier is U. S The output current amplitude of the digital power amplifier is I S The output angular frequency of the digital power amplifier is ω, and the impedance angle of the load is... Calculate the instantaneous output power P of the digital power amplifier o for: It can be seen that the output power P of the digital power amplifier o The expression consists of two parts: constant power P. con and pulsating power P pul The output power of the pre-amplifier DC power supply is P. in The DC-side energy storage capacitor of the digital power amplifier provides part of the pulsating power, P. c In this embodiment of the invention, the power decoupling circuit provides a portion of the pulsating power, P. ax With the addition of a power decoupling stage, based on the principle that instantaneous input power equals output power, the mathematical relationships between each stage are as follows: Therefore, we can know that the second harmonic power P of the power amplifier output is... pul for: The decoupling capacitor C can be calculated using the energy formula for a capacitor. ax The maximum energy that can be withstood is as follows: In the formula U ax Indicates the decoupling capacitor C ax The voltage, combined with the law of conservation of energy, the capacitance C ax The maximum energy is equal to the maximum value of the pulsating power, which gives us the following formula: Further calculations show that the capacitance value of the decoupling capacitor should satisfy the following formula: Due to the decoupling inductor L ax With decoupling capacitor C axMainly plays a low-pass filter, low-pass filter as filter circuit commonly used circuit, its cutoff frequency is at least set to 10 times the output frequency.According to the LC filter cutoff frequency formula has: (10ω out ) 2 LC=1, according to which the decoupling inductance calculation can be represented as: In the formula, ω out Indicates the working angular frequency of the power decoupling circuit switch tube S5-S6, and ω out Further substitution can obtain the inductance L ax Satisfies the following formula: Where, C ax Is the capacitance value of the decoupling capacitor, and f ax Indicates the working frequency of the two switch tubes of the power decoupling circuit.

[0020] As an inventive concept, the application also provides a digital power amplifier, comprising a single-phase full-bridge inverter circuit; the single-phase full-bridge inverter circuit is connected with a power decoupling circuit; the power decoupling circuit is connected with a direct-current side energy storage capacitor; the power decoupling circuit comprises two serially connected switch tubes, one end of a decoupling inductor is connected between the two switch tubes, and the other end is connected with a decoupling capacitor; and the switching time signals of the two switch tubes are calculated by the power decoupling method of the application.

[0021] As an inventive concept, the application also provides a digital power amplifier power decoupling system, comprising a processor and a memory; the memory stores a computer program; and the processor is used to execute the computer program to realize the steps of the power decoupling method of the application.

[0022] Compared with the prior art, the application has the beneficial effects that: since the input side and the output side are not equal in instantaneous power when the digital power amplifier works, the double-frequency voltage fluctuation and current fluctuation of the output voltage appear on the direct-current bus. The power decoupling circuit is used as an energy buffer link in the application to balance the unbalanced energy of the input side and the output side, the current of the direct-current side energy storage capacitor is tracked, and the direct-current bus current component is shunted, so that the purpose of reducing the current i c of the direct-current side energy storage capacitor is achieved; the direct-current bus voltage and current ripple are effectively suppressed, the power decoupling is realized, and the application can be applied in the case of special requirements of wide frequency band and mixed output of multiple frequencies, and the application range is wide. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 It is the topology diagram of the digital power amplifier used in the embodiment of the application;

[0024] Figure 2 It is the control block diagram of the wide frequency power decoupling control method of the digital power amplifier of the embodiment of the application.

[0025] Figure 3 The control system design drawing of the wide frequency power decoupling control method of the digital power amplifier embodiment of the present application;

[0026] Figures 4a to 4d The comparison chart of DC side capacitor voltage, DC side capacitor current, power decoupling circuit capacitor voltage and power decoupling circuit inductor current before and after power decoupling at a single output frequency (200Hz) in the simulation example using the method of the embodiment of the present application; Figure 4a DC side capacitor voltage waveform comparison chart, Figure 4b power decoupling circuit capacitor voltage waveform comparison chart, Figure 4c power decoupling circuit inductor current waveform comparison chart, Figure 4d switching power amplifier output waveform comparison chart;

[0027] Figures 5a to 5d The comparison chart of DC side capacitor voltage, DC side capacitor current, power decoupling circuit capacitor voltage and power decoupling circuit inductor current before and after power decoupling at a single output frequency (200Hz) in the simulation example using the method of the embodiment of the present application; Figure 5a DC side capacitor voltage waveform comparison chart, Figure 5b power decoupling circuit capacitor voltage waveform comparison chart, Figure 5c power decoupling circuit inductor current waveform comparison chart, Figure 5d switching power amplifier output waveform comparison chart. DETAILED DESCRIPTION

[0028] As Figure 1 shown, in the embodiment of the present application, the digital power amplifier with power decoupling capability comprises:

[0029] a DC side energy storage capacitor C dc , four switching devices S1, S2, S3 and S4, a filter inductor L f and a filter capacitor C f , which constitute a single-phase full-bridge inverter circuit;

[0030] a power decoupling circuit composed of two power devices S5 and S6, a decoupling inductor L ax and a decoupling capacitor C ax .

[0031] The power decoupling circuit is connected in parallel across the DC side energy storage capacitor.

[0032] In the embodiment of the present application, the switching devices S1-S6 are all wide bandgap devices.

[0033] By controlling the switching devices S1-S6, the DC side capacitor C dcThe voltage of the digital power amplifier is measured, the double-frequency ripple of the DC side current is observed, and the DC side current is compensated by using the power decoupling circuit controlled by the wideband power decoupling control method, so that the pulsating power and the DC power are decoupled.

[0034] The digital power amplifier can control the single-phase full-bridge inverter circuit to make the switching power amplifier generate a sine voltage with variable amplitude and frequency, and the equivalent impedance of the power decoupling circuit is always 1 / a times (a is a constant) of the DC side capacitor by using the wideband power decoupling control method, so that the AC component of the DC bus current is shunted by the different impedance characteristics, and the DC side energy storage capacitor C dc is reduced. c The purpose is to suppress the DC side voltage fluctuation, reduce the DC side capacitor current, and realize the pulsating power and the DC power decoupling for the wideband output and the multi-frequency mixed output.

[0035] In the embodiment of the application, the control method of the wideband power decoupling control method of the digital power amplifier comprises:

[0036] Suppose that the output voltage u o and the output current i o of the digital power amplifier satisfy the following formula (1):

[0037]

[0038] In formula (1), the output voltage amplitude of the digital power amplifier is U S , the output current amplitude is I S , the output angular frequency is ω, and the impedance angle of the load is The instantaneous output power P o of the digital power amplifier is calculated as the following formula (2):

[0039]

[0040] As can be seen from formula (2), the expression of the output power P o of the digital power amplifier is composed of two parts, that is, the constant power P con and the pulsating power P pul . The output power of the front-stage DC power supply is P in , the part of the pulsating power provided by the DC side energy storage capacitor of the digital power amplifier is P c , and the part of the pulsating power provided by the power decoupling circuit is P ax . In the case of adding the power decoupling link, according to the principle that the instantaneous input power is equal to the output power, the mathematical relationship of each link is as follows formula (3):

[0041]

[0042] Under the condition of no loss, according to the law of conservation of energy, the following formula (4) can be obtained:

[0043]

[0044] In formula (4), u cav and Δu c respectively represent the average value and the peak-to-peak value of the DC side capacitor voltage when there is no power decoupling circuit; u cav and Δu c respectively represent the average value and the peak-to-peak value of the DC side capacitor voltage when there is a power decoupling circuit; u axav and Δu ax respectively represent the average value and the peak-to-peak value of the energy storage capacitor voltage of the decoupling circuit.

[0045] According to formula (3) and formula (4), it can be seen that, in order to reduce the part of the pulsating power P c provided by the DC side energy storage capacitor in formula (3), it is necessary to increase the part of the pulsating power P ax provided by the power decoupling circuit in formula (3). Considering that the output power and the DC side voltage cannot be changed, in order to reduce the part of the pulsating power P c provided by the DC side energy storage capacitor, it is essentially necessary to reduce the DC side energy storage capacitor current i c . In order to reduce the capacitor current i c , the equivalent impedance of the power decoupling circuit is always 1 / a times of the DC side capacitor. Due to the design of the parameter a, a proportional control link is introduced, and therefore the value of a should not be too large (a < 10), and in the embodiment of the present application, a = 5. By means of different impedance characteristics, the AC component of the DC bus current is shunted, so as to achieve the purpose of reducing i c . According to the KCL node current law, the following formula (5) can be obtained:

[0046]

[0047] In formula (5), U dc is the DC component of the DC side current, i dc is the DC component of the DC side current, i ac is the DC component of the DC side current, and i ax is the current of the power decoupling circuit. According to the mathematical relationship between i c and i ax in formula (5), i ax is a times of i cThe tracking is performed, so that the impedance value of the power decoupling circuit is kept as 1 / a times of the impedance value of the DC side capacitor. In an ideal case, when the power decoupling circuit is operated, the current of the DC side capacitor at this time can be reduced to 1 / (a+1) times of the current when the power decoupling circuit is not added, and with the great reduction of the capacitor current, the DC side voltage fluctuation is also obviously inhibited. Considering the large number of DC side capacitors and the difficulty in measuring the current of the DC side capacitors, in order to facilitate engineering application, the capacitor current observation method without current sensor is adopted in the embodiment of the application, and the capacitor current is observed by sampling the DC side capacitor voltage. The discrete expression of the capacitor current i

[0048]

[0049] According to the calculation of formula (6), the capacitor instantaneous current i c (t) can be obtained, but when the capacitor instantaneous voltage u c (t) is sampled and obtained in the actual system, filtering is performed, and delay is introduced. In order to avoid the delay, the Lagrange interpolation method is used to fit the capacitor voltage, according to the definition of the Lagrange interpolation method: generally, if the function values y0, y1,..., y n of y=f(x) at n+1 different points x0, x1,..., x n are known (that is, the function passes through the n+1 points (x0, y0), (x1, y1),..., (x n , y n )), a polynomial passing through the n+1 points and having a degree not more than n can be constructed, so as to satisfy the following formula (7):

[0050] P n (x k )=y k , k=0, 1,..., n (7)

[0051] To estimate any point ξ, ξ≠x i ,i=0,1,2,...,n, the value of P n (ξ) can be used as the approximate value of the accurate value f(ξ), which is called "interpolation method". Taking n points (x0, y0), (x1, y1),..., (x n-1 , y n-1 ) on the plane, a function f(x) is made to pass through the n points. Let D n be a set of indices about points (x, y), D n ={0, 1,..., n-1}, and n polynomials p j (x), j∈D n are made. For any k∈D n , there are p k(x), B k = {il≠k, i∈D n} such that the following equation (8) is satisfied, where p k (x) is an n-1 degree polynomial, the Lagrange interpolation polynomial L n (x) is the following equation (9):

[0052]

[0053]

[0054] When n = 3, the above equation can be simplified to the following equation (10):

[0055]

[0056] The predicted voltage rate of change at the current time can be predicted by equation (10) to satisfy the following equation (11):

[0057]

[0058] where u c (t0) represents the voltage sampling value at t0, u c (t1) and u c (t2) represent the voltage sampling values at t1 and t2, respectively; u * c (t3) represents the voltage calculation value at t3; t s represents the sampling period, t r represents the filtering delay, and l represents the current voltage rate of change calculation value.

[0059] According to equation (12), the current of the capacitor C ax in the power decoupling circuit, i.e., the current i ax (t) of the decoupling inductor L L , can be obtained.

[0060]

[0061] where u L (t0) represents the voltage sampling value at t0, u L (t1) and u L (t2) represent the voltage sampling values at t1 and t2, respectively; u * L (t3) represents the voltage calculation value at t3; t s represents the sampling period, t r represents the filtering delay, and l L represents the current voltage rate of change calculation value, and C ax represents the capacitance value of the decoupling capacitor.

[0062] In the actual device, in order to achieve the decoupling ability of the decoupling circuit to reach the maximum and make the decoupling capacitor voltage not diverge, the control decoupling capacitor C ax The voltage reference value u axref is 1 / 2 of the DC side power supply voltage value, that is, the voltage reference value u axref The size satisfies the following formula:

[0063]

[0064] The voltage sampling of the decoupling capacitor C ax of the power decoupling circuit obtains u ax The difference between u axref and u ax is obtained by PI control loop to obtain i cs The current tracking reference i axref is obtained by the following formula:

[0065] i axref = ai c - i cs (14)

[0066] The current i ax (t) of the decoupling inductance L L in the decoupling circuit obtained according to formula (12) is obtained by proportional control to obtain the corresponding control current i ax , wherein K1 represents the proportional coefficient. K1 is the proportional parameter of the proportional control link, in order to ensure the control speed and prevent the overshoot from being too high, the value of K1 is not too large (K1<10), and in the embodiment of the application, K1=5. The specific mathematical expression is as follows:

[0067] i ax = K1i L (15)

[0068] The difference between i axref obtained by formula (14) and i ax obtained according to formula (15) is obtained by proportional control, and the control duty cycle d s of the corresponding decoupling circuit is obtained, wherein K2 represents the proportional coefficient. The specific mathematical expression is as follows:

[0069]

[0070] The duty cycles in formula (16) are compared with the triangular carrier with threshold value of 0-1 respectively to obtain the switching control signal PWM.

[0071] The capacitor instantaneous current i c (t) obtained by formula (11) is compared with 0 to obtain the output signal mode. When i cWhen (t) > 0, mode = 1; when (t) < 0, mode = 0. c When (t) < 0, mode = 0.

[0072] Finally, according to the PWM signal and the mode signal, the switching time expression of the switches S5 and S6 in the power decoupling circuit is as follows:

[0073]

[0074] According to the switching time expression of the switches S5 and S6 in the formula (17), the conduction and turn-off of the switches can be controlled.

[0075] The circuit elements of the wideband power decoupling control method of the digital power amplifier provided by the application include a capacitance value calculation method of a power decoupling circuit capacitor and an inductance value calculation method of an inductor.

[0076] According to the formulas (2) and (3), the double-frequency power P pul is as follows:

[0077]

[0078] According to the energy calculation formula of the capacitor, the maximum energy that can be borne by the decoupling capacitor C ax is as follows:

[0079]

[0080] In the formula, U ax represents the voltage of the decoupling capacitor C ax , and according to the formula (8), the following formula can be obtained:

[0081]

[0082] According to the law of conservation of energy, the maximum energy of the capacitor C ax is equal to the maximum value of the pulsating power, and the following formula can be obtained:

[0083]

[0084] Further calculation of the above formula (21) can obtain that the capacitance value of the decoupling capacitor should satisfy the following formula:

[0085]

[0086] The decoupling inductor L ax and the decoupling capacitor C ax mainly play a low-pass filtering role. The low-pass filter is a commonly used circuit in the filter circuit, and the cutoff frequency is at least set to 10 times the output frequency. According to the LC filter cutoff frequency calculation formula, the following formula is obtained:

[0087] (10ωout 2 LC = 1 (23)

[0088] According to the above formula (23), the calculation of the decoupling inductance can be represented as

[0089]

[0090] In the formula, ω out represents the working angular frequency of the power decoupling circuit switch tube S5-S6, and ω out Further substitution can be made to obtain the following formula:

[0091]

[0092] As shown in Figure 4a , based on the digital power amplifier structure of the embodiment of the present application, when t = 0.10s, the power decoupling circuit controlled by the wideband power decoupling control method of the embodiment of the present application is added to the main body power amplifier to start working, and it can be seen that, due to the effect of the power decoupling circuit controlled by the wideband power decoupling control method of the embodiment of the present application, the fluctuation of the input voltage double frequency of the digital power amplifier is obviously reduced. The traditional switching power amplifier generates a double frequency voltage ripple with a peak-to-peak value of 75.6V; after being added, the peak-to-peak value of the voltage ripple is reduced to 21.1V, which is reduced by 72.1%, and the voltage ripple suppression effect is obvious; as shown in Figure 4b , with the addition of the power decoupling circuit controlled by the wideband power decoupling control method, the current of the DC side capacitor is also reduced to achieve the expected effect; as shown in Figure 4c and 4d , after the addition of the power decoupling circuit controlled by the wideband power decoupling control method at t = 0.10s, the power decoupling circuit quickly and stably enters the working state. As shown in Figures 5a to 5d , similarly to Figures 4a to 4d , for the case of multiple frequency output, the decoupling effect of the power decoupling circuit controlled by the wideband power decoupling control method of the embodiment of the present application is still significant, and the fluctuation of the input voltage double frequency is obviously reduced. According to the output waveform graph of Figure 5d , it can be seen that the output waveform quality is good, and the quality of the output waveform is not reduced due to the introduction of the decoupling circuit to reduce the ripple of the input voltage.​

Claims

1. A power decoupling method for a digital power amplifier, wherein the digital power amplifier includes a single-phase full-bridge inverter circuit; the single-phase full-bridge inverter circuit is connected to a power decoupling circuit; the power decoupling circuit is connected to a DC-side energy storage capacitor; the power decoupling circuit includes two series-connected switching transistors, one end of a decoupling inductor is connected between the two switching transistors, and the other end is connected to the decoupling capacitor; characterized in that, The method includes: S1. Calculate the current tracking reference i using the following formula. axref :i axref =ai c -i cs ; where i cs To decouple capacitor C ax voltage reference value u axref Compared with the actual value u ax The difference is subtracted, and the fluctuation of the decoupling capacitor current is obtained through proportional-integral control, i c DC-side energy storage capacitor C dc The current, where a is a set constant; Decoupling inductor L ax Current i at time t L (t) The corresponding control current i is obtained through proportional control. ax ; S2, Transfer the current tracking reference i axref With control current i ax The difference is calculated, and the difference is proportionally controlled to obtain the duty cycle d of the power decoupling circuit. s ; S3, adjust the duty cycle d s The switching control signal PWM is obtained by comparing it with a triangular carrier wave with a threshold of 0-1; S4. Based on the PWM signal and the mode signal, obtain the switching timing signal G of the two switching transistors in the power decoupling circuit. S5 and G S6 : Where, when i c When (t)>0, mode=1; when i c When (t) < 0, mode = 0; i c (t) represents the instantaneous current of the DC-side capacitor; i c The formula for calculating (t) is: i L (t)=l L C ax ;in, u L (t0) represents the voltage sample value at time t0, u L (t1) and u L (t2) represent the voltage sampled values ​​at time t1 and t2, respectively, u * L (t3) represents the calculated voltage value at time t3. s Indicates the sampling period, t r Indicates the filter delay, l L C represents the calculated value of the current voltage change rate. ax This indicates the capacitance value of the decoupling capacitor.

2. The digital power amplifier power decoupling method according to claim 1, characterized in that, U dc This is the DC-side power supply voltage value.

3. The digital power amplifier power decoupling method according to claim 1, characterized in that, a＜10。 4. The digital power amplifier power decoupling method according to claim 1, characterized in that, i ax =K1i L ;K1<10。 5. The digital power amplifier power decoupling method according to claim 1, characterized in that, In step S2, the duty cycle d s The calculation formula is:

6. The digital power amplifier power decoupling method according to claim 1, characterized in that, The capacitance value C of the decoupling capacitor ax The following conditions must be met: Among them, U S For the output voltage amplitude of the digital power amplifier, I S ω is the output current amplitude of the digital power amplifier, and ω is the output angular frequency of the digital power amplifier.

7. The digital power amplifier power decoupling method according to claim 1, characterized in that, The inductance value L of the decoupling inductor ax The following conditions must be met: Among them, C ax f is the capacitance value of the decoupling capacitor. ax This indicates the operating frequency of the two switching transistors in the power decoupling circuit.

8. A digital power amplifier, characterized in that, It includes a single-phase full-bridge inverter circuit; the single-phase full-bridge inverter circuit is connected to a power decoupling circuit; the power decoupling circuit is connected to a DC-side energy storage capacitor; the power decoupling circuit includes two series-connected switching transistors. One end of the decoupling inductor is connected between the two switching transistors, and the other end is connected to the decoupling capacitor; The switching timing signals of the two switching transistors are calculated by the method described in any one of claims 1 to 7.

9. A power decoupling system for a digital power amplifier, characterized in that, It includes a processor and a memory; the memory stores a computer program; the processor is used to execute the computer program to implement the steps of the method according to any one of claims 1 to 7.

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