6-18ghz power amplifier with active matching combined with passive matching and method of implementation

Abstract

The application discloses a 6-18GHz power amplifier with active matching combined with passive matching, which comprises a passive input matching network, an active input matching network, a passive inter-stage matching network, an active inter-stage matching network, a passive output matching network, an active output matching network, a first transistor and a second transistor; the impedance position of the first transistor and the second transistor is accurately controlled in a manner that active matching is combined with passive matching. The implementation method of the application firstly preliminarily matches the transistor impedance position through a passive matching circuit, reduces the matching difficulty, and then corrects the fundamental wave impedance position and the harmonic impedance position through active matching on the basis, so that the impedance position is accurately controlled. The application solves the problem that the transistor impedance in the traditional ultra-wideband power amplifier cannot be ideally matched at all frequency points, and finally improves the overall efficiency of the 6-18GHz power amplifier.

Description

Technical Field

[0001] This invention relates to microwave power amplifiers, and more particularly to a 6-18 GHz power amplifier with active matching combined with passive matching and its implementation method. Background Technology

[0002] Power amplifiers are the main power-consuming components in transceiver links, and improving their efficiency can effectively reduce power consumption. Due to the demands of integration and miniaturization, power amplifiers are generally required to operate over a wide frequency range rather than a specific frequency. How to achieve greater output power and higher gain over a wide, especially ultra-wide, range, while ensuring the highest possible efficiency, has always been a hot research topic in academia and industry.

[0003] Traditional ultra-wideband power amplifiers, whether using distributed circuit topologies or reactance-matched circuit topologies, employ fixed passive matching circuit structures. According to Foster's reactance theorem, in the Smith chart, the matching position of a conventional passive matching circuit rotates clockwise with frequency. However, load-pull testing results show that the optimal impedance point of the transistor rotates counter-clockwise with frequency. Therefore, the transistor impedance in existing ultra-wideband power amplifiers cannot be ideally matched at all frequency points, thus limiting the efficiency of the ultra-wideband power amplifier. Summary of the Invention

[0004] Purpose of the invention: This invention discloses a 6-18GHz power amplifier and its implementation method that combines active matching and passive matching to achieve ideal impedance matching of transistors at all frequency points, thereby improving the efficiency of the power amplifier.

[0005] Technical solution: The power amplifier of the present invention includes a passive input matching network, an active input matching network, a passive interstage matching network, an active interstage matching network, a passive output matching network, an active output matching network, a first transistor, and a second transistor;

[0006] The input terminal of the passive input matching network is connected to the radio frequency input terminal, and the input terminal of the active input matching network is connected to the output terminal of the passive input matching network; the gate of the first transistor is connected to the output terminal of the active input matching network; the source of the first transistor is grounded.

[0007] The input terminal of the passive interstage matching network is connected to the drain of the first transistor; the input terminal of the active interstage matching network is connected to the output terminal of the passive interstage matching network; the gate of the second transistor is connected to the output terminal of the active interstage matching network; and the source of the second transistor is grounded.

[0008] The input terminal of the passive output matching network is connected to the drain of the second transistor; the input terminal of the active output matching network is connected to the output terminal of the passive output matching network; the radio frequency output terminal is connected to the output terminal of the active output matching network.

[0009] The control signal for the active input matching network is the first control signal; the control signal for the active inter-stage matching network is the second control signal; and the control signal for the active output matching network is the third control signal.

[0010] The input signal at the radio frequency input terminal is an input signal source; the first control signal, the second control signal, and the third control signal are all combinations of the output signals of the first signal source, the second signal source, ..., the nth signal source; where n is a positive integer and n≥3;

[0011] The frequency of the output signal of the input signal source is f0; the frequency of the output signal of the first signal source is f0; the frequency of the output signal of the second signal source is 2f0; ...; the frequency of the output signal of the nth signal source is nf0.

[0012] Furthermore, the passive input matching network includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first microstrip line, a second microstrip line, a third microstrip line, a fourth microstrip line, a first capacitor, a second capacitor, and a third capacitor; one end of the first resistor is connected to the RF input terminal; the other end of the first resistor is connected to one end of the second resistor and one end of the third resistor respectively; the other end of the third resistor is connected to one end of the first microstrip line; the other end of the first microstrip line is grounded; the other end of the second resistor is connected to one end of the first capacitor; the other end of the first capacitor is connected to one end of the second capacitor and one end of the second microstrip line respectively; the other end of the second capacitor is grounded; the other end of the second microstrip line is connected to one end of the third microstrip line and one end of the fourth resistor respectively; the other end of the third microstrip line is connected to one end of the fifth microstrip line in the active input matching network; the other end of the fourth resistor is connected to one end of the fourth microstrip line; the other end of the fourth microstrip line is connected to the gate bias voltage and one end of the third capacitor respectively; the other end of the third capacitor is grounded.

[0013] The active input matching network includes a fifth microstrip line, a sixth microstrip line, and a seventh microstrip line. One end of the fifth microstrip line is connected to one end of the third microstrip line in the passive input matching network. The other end of the fifth microstrip line is connected to one end of the sixth microstrip line and one end of the seventh microstrip line, respectively. The other end of the sixth microstrip line is connected to the gate of the first transistor. The other end of the seventh microstrip line is connected to the first control signal.

[0014] Furthermore, the passive interstage matching network includes an eighth microstrip line, a ninth microstrip line, a tenth microstrip line, an eleventh microstrip line, a twelfth microstrip line, a thirteenth microstrip line, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a fifth resistor, and a sixth resistor; one end of the eighth microstrip line is connected to the drain of the first transistor; the other end of the eighth microstrip line is connected to one end of the ninth microstrip line and one end of the tenth microstrip line, respectively; the other end of the ninth microstrip line is connected to the drain bias voltage and one end of the fourth capacitor, respectively; the other end of the fourth capacitor is grounded; the other end of the tenth microstrip line is connected to one end of the fifth capacitor; the other end of the fifth capacitor... One end of the capacitor is connected to one end of the sixth capacitor, the seventh capacitor, and the fifth resistor, respectively; the other end of the sixth capacitor is grounded; the other end of the seventh capacitor and the other end of the fifth resistor are connected and then connected to one end of the eighth capacitor and the eleventh microstrip line, respectively; the other end of the eighth capacitor is grounded; the other end of the eleventh microstrip line is connected to one end of the twelfth microstrip line and the sixth resistor, respectively; the other end of the twelfth microstrip line is connected to one end of the fourteenth microstrip line in the active stage matching network; the other end of the sixth resistor is connected to one end of the thirteenth microstrip line; the other end of the thirteenth microstrip line is connected to the gate bias voltage and one end of the ninth capacitor, respectively; the other end of the ninth capacitor is grounded.

[0015] The active interstage matching network includes a fourteenth microstrip line, a fifteenth microstrip line, and a sixteenth microstrip line. One end of the fourteenth microstrip line is connected to one end of the twelfth microstrip line in the passive input matching network. The other end of the fourteenth microstrip line is connected to one end of the fifteenth microstrip line and one end of the sixteenth microstrip line, respectively. The other end of the fifteenth microstrip line is connected to the gate of the second transistor. The other end of the sixteenth microstrip line is connected to the second control signal.

[0016] Furthermore, the passive output matching network includes a seventeenth microstrip line, an eighteenth microstrip line, a nineteenth microstrip line, a twentieth microstrip line, a twenty-first microstrip line, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, and a fourteenth capacitor; one end of the seventeenth microstrip line is connected to the drain of the second transistor; the other end of the seventeenth microstrip line is connected to one end of the eighteenth and nineteenth microstrip lines respectively; the other end of the eighteenth microstrip line is connected to the drain bias voltage and one end of the tenth capacitor respectively; the other end of the tenth capacitor is grounded; the other end of the nineteenth microstrip line is connected to one end of the eleventh and twelfth capacitors respectively; the other end of the eleventh capacitor is grounded; the other end of the twelfth capacitor is connected to one end of the twentieth and twenty-first microstrip lines respectively; the other end of the twentieth microstrip line is grounded; the other end of the twenty-first microstrip line is connected to one end of the thirteenth and fourteenth capacitors respectively; the other end of the thirteenth capacitor is grounded; the other end of the fourteenth capacitor is connected to one end of the twenty-second microstrip line in the active output matching network.

[0017] The active output matching network includes a 22nd microstrip line, a 23rd microstrip line, and a 24th microstrip line. One end of the 22nd microstrip line is connected to one end of the 14th capacitor in the passive output matching network. The other end of the 22nd microstrip line is connected to one end of the 23rd microstrip line and one end of the 24th microstrip line. The other end of the 23rd microstrip line is connected to the RF output terminal. The other end of the 24th microstrip line is connected to the third control signal.

[0018] A method for implementing a 6-18GHz power amplifier using active matching combined with passive matching is disclosed. This method employs a combination of active and passive matching to precisely control the impedance positions of the first and second transistors: First, a passive matching circuit is used to initially match the impedance positions of the two transistors, reducing the matching difficulty; then, active matching is used to further correct the impedance positions, including correction of the fundamental impedance position and harmonic impedance position. The method includes the following steps:

[0019] A1: Select the process approach based on the required operating frequency range; select the total gate width of the final stage of the power amplifier based on the required output power and the power density of the selected process approach; determine the number of stages of the power amplifier based on the required gain; determine the interstage drive ratio based on the gain compression characteristics of the devices in the selected process approach.

[0020] A2: Through Load Pull and Source Pull tests or simulations, determine the first fundamental load impedance, first second harmonic load impedance, first third harmonic load impedance, first fundamental source impedance, first second harmonic source impedance, and first third harmonic source impedance of the first transistor (pHEMT1), and determine the second fundamental load impedance, second second harmonic load impedance, second third harmonic load impedance, second fundamental source impedance, second second harmonic source impedance, and second third harmonic source impedance of the second transistor;

[0021] A3: Under the premise of ensuring that the insertion loss of the passive output matching network is small, the fundamental load impedance of the second transistor (pHEMT2) is matched to the circular region near the output load impedance;

[0022] A4: Under the premise of ensuring that the insertion loss of the passive interstage matching network is small, the first fundamental load impedance of the first transistor is matched to the circular region near the second fundamental source impedance of the second transistor.

[0023] A5: Under the premise of ensuring that the insertion loss of the passive input matching network is small, the first fundamental source impedance Z1_S1 of the first transistor is matched to the circular region near the input load impedance.

[0024] A6: Based on step A3, the third control signal is injected into the active output matching network to strictly match the second fundamental load impedance of the second transistor from the circular region near the output load impedance to the output load impedance point.

[0025] A7: Based on step A4, the first fundamental load impedance of the first transistor is strictly matched from the circular region near the second fundamental source impedance of the second transistor to the second fundamental source impedance of the second transistor by injecting the second control signal into the active interstage matching network.

[0026] A8: Based on step A5, the first control signal is injected into the active input matching network to strictly match the first fundamental source impedance of the first transistor from the circular region near the input load impedance to the input load impedance point.

[0027] A9: Based on the matching network designed in steps A3-A8, complete the integration and optimization of the schematic and layout.

[0028] Furthermore, in step A6, the active output matching network is injected with a third control signal to make the second second harmonic load impedance and the second third harmonic load impedance of the second transistor either short-circuit or open-circuit.

[0029] Furthermore, in step A7, the second control signal is injected into the active interstage matching network so that the first second harmonic load impedance, the first third harmonic load impedance of the first transistor, and the second second harmonic source impedance and the second third harmonic source impedance of the second transistor are respectively at the short circuit point or the open circuit point.

[0030] Furthermore, in step A8, the first control signal is injected into the active input matching network to make the first second harmonic source impedance and the first third harmonic source impedance of the first transistor at the short circuit point or the open circuit point, respectively.

[0031] Compared with the prior art, the significant advantages of this invention are as follows:

[0032] 1. This invention employs a combination of active and passive matching to precisely control the impedance positions of the first and second transistors. Firstly, passive matching is used for initial impedance matching, reducing the matching difficulty. Then, active matching further corrects the impedance positions, including fundamental and harmonic impedance correction, achieving precise impedance control and ultimately improving the overall efficiency of the power amplifier. This invention breaks the constraints of Foster's reactance theorem on circuit design, solving the problem that transistor impedances in traditional ultra-wideband power amplifiers cannot be ideally matched at all frequency points. It avoids the trade-offs between bandwidth, output power, and efficiency in power amplifiers, thus improving the efficiency of the power amplifier.

[0033] 2. This invention has multiple active matching networks, including an active input matching network, an active inter-stage matching network, and an active output matching network. Each active matching network has an independent first control signal, a second control signal, and a third control signal. The control signals can be flexibly adjusted according to the initial impedance matching of the first transistor pHEMT1 and the second transistor pHEMT2 by the passive input matching network, the passive inter-stage matching network, and the passive output matching network, thus enriching the design flexibility.

[0034] 3. The first control signal, the second control signal, and the third control signal of the present invention are all combinations of the output signals of the first signal source, the second signal source, ..., the third signal source. They can not only achieve fundamental load impedance and fundamental source impedance matching for the first transistor and the second transistor, but also harmonic load impedance and harmonic source impedance matching, so that the second harmonic load impedance, the third harmonic load impedance, the second harmonic source impedance, and the third harmonic source impedance are at the open circuit point or the short circuit point. Attached Figure Description

[0035] Figure 1 This is a block diagram of the overall structure of the present invention;

[0036] Figure 2 This is a schematic diagram of the input matching network in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of the inter-level matching network in an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of the output matching network in an embodiment of the present invention;

[0039] Figure 5 This is a flowchart of the implementation method of the present invention;

[0040] Figure 6 These are diagrams illustrating the passive and active matching effects of this invention.

[0041] Figure 7 This is a comparison of the efficiency of a passive matching network during initial impedance matching and the efficiency of an active matching network after further impedance correction. Detailed Implementation

[0042] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0043] The overall structure of the invention is as follows Figure 1 As shown, it includes a passive input matching network, an active input matching network, a passive inter-stage matching network, an active inter-stage matching network, a passive output matching network, an active output matching network, a first transistor pHEMT1, and a second transistor pHEMT2.

[0044] The input terminal of the passive input matching network is connected to the RF input. in Connections: The input terminal of the active input matching network is connected to the output terminal of the passive input matching network; the gate of the first transistor pHEMT1 is connected to the output terminal of the active input matching network; the source of the first transistor pHEMT1 is grounded; used to provide good input standing wave ratio and power gain flatness.

[0045] The input terminal of the passive interstage matching network is connected to the drain of the first transistor pHEMT1; the input terminal of the active interstage matching network is connected to the output terminal of the passive interstage matching network; the gate of the second transistor pHEMT2 is connected to the output terminal of the active interstage matching network; the source of the second transistor pHEMT2 is grounded; the first transistor pHEMT1 and the second transistor pHEMT2 are connected to the RF input terminal. in Multi-stage amplification is used to provide sufficient power gain.

[0046] The input of the passive output matching network is connected to the drain of the second transistor pHEMT2; the input of the active output matching network is connected to the output of the passive output matching network; the RF output terminal... out Connect to the output of an active output matching network to provide good output power and efficiency.

[0047] The control signal for the active input matching network is the first control signal CS. in1 The control signal for the active inter-stage matching network is the second control signal CS. in2 The control signal for the active output matching network is the third control signal CS. in3 .

[0048] RF input terminal in The input signal is the input signal source S0; the first control signal CS in1 Second control signal CS in2 Third control signal CS in3 All are first signal source S1, second signal source S2, ..., nth signal source S n A combination of output signals; where n is a positive integer and n≥3.

[0049] The input signal source S0 outputs a signal with frequency f0; the first signal source S1 outputs a signal with frequency f0; the second signal source S2 outputs a signal with frequency 2f0; ...; the nth signal source S n The output signal frequency is nf0.

[0050] The matching networks at each level of this invention specifically involve the following:

[0051] In this embodiment, the schematic diagram of the input matching network is as follows: Figure 2As shown. The passive input matching network includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first microstrip line TL1, a second microstrip line TL2, a third microstrip line TL3, a fourth microstrip line TL4, a first capacitor C1, a second capacitor C2, and a third capacitor C3. One end of the first resistor R1 is connected to the RF input RF. in Connections: The other end of the first resistor R1 is connected to one end of the second resistor R2 and the third resistor R3 respectively; the other end of the third resistor R3 is connected to one end of the first microstrip line TL1; the other end of the first microstrip line TL1 is grounded; the other end of the second resistor R2 is connected to one end of the first capacitor C1; the other end of the first capacitor C1 is connected to one end of the second capacitor C2 and the second microstrip line TL2 respectively; the other end of the second capacitor C2 is grounded; the other end of the second microstrip line TL2 is connected to one end of the third microstrip line TL3 and the fourth resistor R4 respectively; the other end of the third microstrip line TL3 is connected to one end of the fifth microstrip line TL5 in the active input matching network; the other end of the fourth resistor R4 is connected to one end of the fourth microstrip line TL4; the other end of the fourth microstrip line TL4 is connected to the gate bias voltage V G1 One end of the third capacitor C3 is connected to the third microstrip line C3; the other end of the third capacitor C3 is grounded. The active input matching network includes a fifth microstrip line TL5, a sixth microstrip line TL6, and a seventh microstrip line TL7. One end of the fifth microstrip line TL5 is connected to one end of the third microstrip line TL3 in the passive input matching network; the other end of the fifth microstrip line TL5 is connected to one end of the sixth microstrip line TL6 and the seventh microstrip line TL7, respectively; the other end of the sixth microstrip line TL6 is connected to the gate of the first transistor pHEMT1; the other end of the seventh microstrip line TL7 is connected to the first control signal CS. in1 connect.

[0052] The schematic diagram of the inter-level matching network in this embodiment of the invention is as follows: Figure 3 As shown. The passive interstage matching network includes the eighth microstrip line TL8, the ninth microstrip line TL9, and the tenth microstrip line TL1. 10 11th microstrip line TL 11 12th microstrip line TL 12 The thirteenth microstrip line TL 13 The capacitors are: C4 (fourth), C5 (fifth), C6 (sixth), C7 (seventh), C8 (eighth), C9 (ninth), R5 (fifth), and R6 (sixth). One end of the eighth microstrip line TL8 is connected to the drain of the first transistor pHEMT1; the other end of the eighth microstrip line TL8 is connected to the ninth microstrip line TL9 and the tenth microstrip line TL1, respectively. 10 One end is connected; the other end of the ninth microstrip line TL9 is connected to the drain bias voltage V. D1 Connect one end of the fourth capacitor C4; the other end of the fourth capacitor C4 is grounded; the tenth microstrip line TL 10The other end is connected to one end of the fifth capacitor C5; the other end of the fifth capacitor C5 is connected to one end of the sixth capacitor C6, the seventh capacitor C7, and the fifth resistor R5 respectively; the other end of the sixth capacitor C6 is grounded; the other end of the seventh capacitor C7 and the other end of the fifth resistor R5 are connected and respectively connected to the eighth capacitor C8 and the eleventh microstrip line TL 11 One end is connected; the other end of the eighth capacitor C8 is grounded; the eleventh microstrip line TL 11 The other end is connected to the twelfth microstrip line TL. 12 Connect one end of the sixth resistor R6; the twelfth microstrip line TL 12 The other end connects to the fourteenth microstrip line TL in the active stage matching network. 14 One end is connected; the other end of the sixth resistor R6 is connected to the thirteenth microstrip line TL. 13 One end is connected; the thirteenth microstrip line TL 13 The other end is connected to the gate bias voltage V. G2 One end of the ninth capacitor C9 is connected; the other end of the ninth capacitor C9 is grounded. The active stage interstage matching network includes the fourteenth microstrip line TL. 14 The fifteenth microstrip line TL 15 The sixteenth microstrip line TL 16 The fourteenth microstrip line TL 14 One end is connected to the twelfth microstrip line TL in the passive input matching network. 12 One end is connected; the fourteenth microstrip line TL 14 The other end is connected to the fifteenth microstrip line TL. 15 and the sixteenth microstrip line TL 16 One end is connected; the fifteenth microstrip line TL 15 The other end is connected to the gate of the second transistor pHEMT2; the sixteenth microstrip line TL 16 The other end is connected to the second control signal CS in2 connect.

[0053] The schematic diagram of the output matching network in this embodiment of the invention is as follows: Figure 4 As shown. The passive output matching network includes the seventeenth microstrip line TL. 17 The 18th microstrip line TL 18 The nineteenth microstrip line TL 19 20th microstrip line TL 20 TL, the twenty-first microstrip line 21 The tenth capacitor C 10 Eleventh capacitor C 11 The twelfth capacitor C 12 The thirteenth capacitor C 13 Fourteenth capacitor C 14 The seventeenth microstrip line TL 17One end is connected to the drain of the second transistor pHEMT2; the seventeenth microstrip line TL 17 The other end is connected to the eighteenth microstrip line TL. 18 and the nineteenth microstrip line TL 19 One end is connected; the eighteenth microstrip line TL 18 The other end is respectively connected to the drain bias voltage V D2 and the tenth capacitor C 10 One end is connected; the tenth capacitor C 10 The other end is grounded; the nineteenth microstrip line TL 19 The other end is connected to the eleventh capacitor C. 11 and the twelfth capacitor C 12 One end is connected; the eleventh capacitor C 11 The other end is grounded; the twelfth capacitor C 12 The other end is connected to the twentieth microstrip line TL. 20 21st microstrip line TL 21 One end is connected; the twentieth microstrip line TL 20 The other end is grounded; the twenty-first microstrip line TL 21 The other end is connected to the thirteenth capacitor C. 13 and the fourteenth capacitor C 14 One end is connected; the thirteenth capacitor C 13 The other end is grounded; the fourteenth capacitor C 14 The other end connects to the 22nd microstrip line TL in the active output matching network. 22 One end is connected. The active output matching network includes the twenty-second microstrip line TL. 22 23rd microstrip line TL 23 24th microstrip line TL 24 The 22nd microstrip line TL 22 One end is connected to the fourteenth capacitor C in the passive output matching network. 14 One end is connected; the twenty-second microstrip line TL 22 The other end is connected to the 23rd microstrip line TL. 23 24th microstrip line TL 24 One end is connected; the twenty-third microstrip line TL 23 The other end is connected to the radio frequency output RF out Connection; Twenty-fourth microstrip line TL 24 The other end is connected to the third control signal CS in3 connect.

[0054] The flowchart of the implementation method of the present invention is as follows: Figure 5 As shown, it includes the following steps:

[0055] Step A1: Select the process approach based on the required operating frequency range; select the total gate width of the final stage of the power amplifier based on the required output power and the power density of the selected process approach; determine the number of stages of the power amplifier based on the required gain; and determine the interstage drive ratio based on the gain compression characteristics of the devices in the selected process approach.

[0056] Step A2, to more easily describe the subsequent steps, uses a two-stage amplification configuration with a first transistor pHEMT1 and a second transistor pHEMT2 as an example. It should be noted that the described implementation method is still applicable to multi-stage amplification configurations. The first fundamental load impedance, first and second harmonic load impedance, first and third harmonic load impedance, first fundamental source impedance, first and second harmonic source impedance, and first and third harmonic source impedance of the first transistor pHEMT1 are determined through load pull and source pull tests or simulations. The second fundamental load impedance, second and second harmonic load impedance, second and third harmonic load impedance, second fundamental source impedance, second and second harmonic source impedance, and second and third harmonic source impedance of the second transistor pHEMT2 are also determined.

[0057] Step A3: Under the premise of ensuring that the insertion loss of the passive output matching network is small, the second fundamental load impedance of the second transistor pHEMT2 is matched to the circular region near the output load impedance (generally 50Ω), that is, the second fundamental load impedance of the second pair of transistors pHEMT2 is initially matched.

[0058] Step A4: Under the premise of ensuring that the insertion loss of the passive interstage matching network is small, the first fundamental load impedance of the first transistor pHEMT1 is matched to the circular region near the second fundamental source impedance of the second transistor pHEMT2, that is, preliminary impedance matching is performed on the first fundamental load impedance of the first transistor pHEMT1 and the second fundamental source impedance of the second transistor pHEMT2.

[0059] Step A5: Under the premise of ensuring that the insertion loss of the passive input matching network is small, the first fundamental source impedance of the transistor pHEMT1 is matched to the circular region near the input load impedance (generally 50Ω), that is, the first fundamental source impedance of the transistor pHEMT1 is initially matched.

[0060] Step A6, based on step A3, uses the third control signal CS in3 An active output matching network is injected to precisely match the second fundamental load impedance of the second transistor pHEMT2 from the circular region near the output load impedance to the output load impedance point, thus further correcting the second fundamental load impedance of the second transistor pHEMT2 and achieving precise control. On the other hand, the third control signal CS... in3An active output matching network is injected to make the second and third harmonic load impedances of the second transistor pHEMT2 either short-circuited or open-circuited.

[0061] Step A7, based on step A4, uses the second control signal CS in2 An active-stage matching network is injected to precisely match the first fundamental load impedance of the first transistor pHEMT1 from the circular region near the fundamental source impedance of the second transistor pHEMT2 to the second fundamental source impedance of the second transistor pHEMT2. This further corrects the first fundamental load impedance of the first transistor pHEMT1 and the second fundamental source impedance of the second transistor pHEMT2, achieving precise control. On the other hand, the second control signal CS... in2 An active stage matching network is injected so that the first second harmonic load impedance and the first third harmonic load impedance of the first transistor pHEMT1, and the second second harmonic source impedance and the second third harmonic source impedance of the second transistor pHEMT2 are at short-circuit points or open-circuit points.

[0062] Step A8, based on step A5, uses the first control signal CS in1 An active input matching network is injected to precisely match the first fundamental source impedance of the first transistor pHEMT1 from the circular region near the input load impedance to the input load impedance point, thus further correcting the first fundamental load impedance of the first transistor pHEMT1 and achieving precise control. On the other hand, the first control signal CS... in1 An active input matching network is injected so that the second harmonic source impedance and the second harmonic source impedance of the second transistor pHEMT1 are either short-circuited or open-circuited.

[0063] Step A9: Based on the matching network designed in steps A3-A8, complete the integration and optimization of the schematic and layout.

[0064] The passive and active matching effect diagrams of this invention are shown below. Figure 6As shown. For easier description, we will take the fundamental load impedance of the second transistor pHEMT2 matched to the output load impedance (typically 50Ω) as an example. It should be noted that the described matching effect also applies to the first fundamental load impedance of the first transistor pHEMT1, the second fundamental source impedance of the second transistor pHEMT2, and the first fundamental source impedance of the first transistor pHEMT1. In the following description, the initial impedance point refers to the second fundamental load impedance of the second transistor pHEMT2, and the optimal impedance point refers to the output load impedance (typically 50Ω). The initial impedance point is close to the edge of the Smith chart and far from the optimal impedance point. In the case of ultra-wideband, it is not possible to directly match the initial impedance point to the optimal impedance point. Therefore, we first perform preliminary impedance matching on the initial impedance point through a passive output matching network, that is, match it to the circular area near the optimal impedance point. Then, we further correct the impedance position through an active output matching network, that is, strictly match it from the circular area near the optimal impedance point to the optimal impedance point.

[0065] like Figure 7 The figure shows a comparison between the efficiency of the passive matching network during initial impedance matching and the efficiency of the active matching network after further impedance correction in an embodiment of the present invention. The typical power-added efficiency (PAE) of the passive matching network during initial impedance matching is 26%, while the typical PAE of the active matching network after further impedance correction is 32%. According to the efficiency comparison figure, the 6-18GHz power amplifier of the present invention can solve the transistor impedance matching problem in ultra-wideband power amplifiers, thereby improving the efficiency of ultra-wideband power amplifiers.

[0066] Finally, it should be noted that the above embodiments are only for illustrating the technical concept of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in the present invention shall fall within the scope of protection of the present invention.

Claims

1. A 6-18GHz power amplifier combining active matching and passive matching, characterized in that: It includes a passive input matching network, an active input matching network, a passive interstage matching network, an active interstage matching network, a passive output matching network, an active output matching network, a first transistor (pHEMT1), and a second transistor (pHEMT2). The input terminal of the passive input matching network and the radio frequency input terminal (RF) in The active input matching network is connected to the output of the passive input matching network; the gate of the first transistor (pHEMT1) is connected to the output of the active input matching network; and the source of the first transistor (pHEMT1) is grounded. The input terminal of the passive interstage matching network is connected to the drain of the first transistor (pHEMT1); the input terminal of the active interstage matching network is connected to the output terminal of the passive interstage matching network; the gate of the second transistor (pHEMT2) is connected to the output terminal of the active interstage matching network; and the source of the second transistor (pHEMT2) is grounded. The input terminal of the passive output matching network is connected to the drain of the second transistor (pHEMT2); the input terminal of the active output matching network is connected to the output terminal of the passive output matching network; the radio frequency output terminal (RF) out Connect to the output of the active output matching network; The control signal for the active input matching network is the first control signal (CS). in1 The control signal for the active inter-stage matching network is the second control signal (CS). in2 The control signal for the active output matching network is the third control signal (CS). in3 ); Radio frequency input (RF) in The input signal is the input signal source (S0); the first control signal (CS) in1 ), second control signal (CS) in2 ), third control signal (CS) in3 All of them are the first signal source (S1), the second signal source (S2), ..., the nth signal source (Sn). n The combination of output signals; where n is a positive integer and n≥3; The frequency of the output signal from the input signal source (S0) is f0; the frequency of the output signal from the first signal source (S1) is f0; the frequency of the output signal from the second signal source (S2) is 2f0; ...; the frequency of the nth signal source (S... n The output signal frequency is nf0; The passive input matching network includes a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a first microstrip line (TL1), a second microstrip line (TL2), a third microstrip line (TL3), a fourth microstrip line (TL4), a first capacitor (C1), a second capacitor (C2), and a third capacitor (C3); one end of the first resistor (R1) is connected to the radio frequency input terminal (RF). in The first resistor (R1) is connected to one end of the second resistor (R2) and the third resistor (R3); the other end of the third resistor (R3) is connected to one end of the first microstrip line (TL1); the other end of the first microstrip line (TL1) is grounded; the other end of the second resistor (R2) is connected to one end of the first capacitor (C1); the other end of the first capacitor (C1) is connected to one end of the second capacitor (C2) and the second microstrip line (TL2); the other end of the second capacitor (C2) is grounded; the other end of the second microstrip line (TL2) is connected to one end of the third microstrip line (TL3) and the fourth resistor (R4); the other end of the third microstrip line (TL3) is connected to one end of the fifth microstrip line (TL5) in the active input matching network; the other end of the fourth resistor (R4) is connected to one end of the fourth microstrip line (TL4); the other end of the fourth microstrip line (TL4) is connected to the gate bias voltage (V) G1 One end of the capacitor is connected to the third capacitor (C3); the other end of the third capacitor (C3) is grounded. The active input matching network includes a fifth microstrip line (TL5), a sixth microstrip line (TL6), and a seventh microstrip line (TL7). One end of the fifth microstrip line (TL5) is connected to one end of the third microstrip line (TL3) in the passive input matching network; the other end of the fifth microstrip line (TL5) is connected to one end of the sixth microstrip line (TL6) and the seventh microstrip line (TL7), respectively; the other end of the sixth microstrip line (TL6) is connected to the gate of the first transistor (pHEMT1); and the other end of the seventh microstrip line (TL7) is connected to the first control signal (CS). in1 )connect.

2. The 6-18GHz power amplifier with active matching combined with passive matching according to claim 1, characterized in that: The passive interstage matching network includes the eighth microstrip line (TL8), the ninth microstrip line (TL9), and the tenth microstrip line (TL1). 10 ), eleventh microstrip line (TL) 11 ), the twelfth microstrip line (TL) 12 ), the thirteenth microstrip line (TL) 13 The capacitors are: fourth capacitor (C4), fifth capacitor (C5), sixth capacitor (C6), seventh capacitor (C7), eighth capacitor (C8), ninth capacitor (C9), fifth resistor (R5), and sixth resistor (R6); one end of the eighth microstrip line (TL8) is connected to the drain of the first transistor (pHEMT1); the other end of the eighth microstrip line (TL8) is connected to the ninth microstrip line (TL9) and the tenth microstrip line (TL1), respectively. 10 One end of the ninth microstrip line (TL9) is connected to the drain bias voltage (V). D1 The fourth capacitor (C4) is connected to one end; the other end of the fourth capacitor (C4) is grounded; the tenth microstrip line (TL) 10 The other end of capacitor C5 is connected to one end of capacitor C6; the other end of capacitor C5 is connected to one end of capacitor C6, capacitor C7, and resistor R5 respectively; the other end of capacitor C6 is grounded; the other end of capacitor C7 and resistor R5 are connected and connected to capacitor C8 and resistor R5 respectively. 11 One end of the capacitor is connected; the other end of the eighth capacitor (C8) is grounded; the eleventh microstrip line (TL) 11 The other end of the line is connected to the twelfth microstrip line (TL). 12 The first end of the 12th microstrip line (TL) is connected to one end of the sixth resistor (R6); the second end of the 12th microstrip line (TL) is connected to the first end of the 13th microstrip line (TL) and the third end of the 14th microstrip line (TL) is connected to the first end of the 15th microstrip line (R6). 12 The other end of the line is connected to the fourteenth microstrip line (TL) in the active interstage matching network. 14 One end of the sixth resistor (R6) is connected to the thirteenth microstrip line (TL). 13 One end is connected; the thirteenth microstrip line (TL) 13 The other end of the circuit is connected to the gate bias voltage (V) respectively. G2 One end of the capacitor is connected to the ninth capacitor (C9); the other end of the ninth capacitor (C9) is grounded. The active interstage matching network includes a fourteenth microstrip line (TL). 14 ), the fifteenth microstrip line (TL) 15 ) and the sixteenth microstrip line (TL 16 ), the fourteenth microstrip line (TL 14 One end of the line is connected to the twelfth microstrip line (TL) in the passive input matched network. 12 One end is connected; the fourteenth microstrip line (TL) 14 The other end of the line is connected to the fifteenth microstrip line (TL). 15 ) and the sixteenth microstrip line (TL 16 One end is connected; the fifteenth microstrip line (TL) 15 The other end of the line is connected to the gate of the second transistor (pHEMT2); the sixteenth microstrip line (TL) 16 The other end of the signal is connected to the second control signal (CS). in2 )connect.

3. The 6-18GHz power amplifier with active matching combined with passive matching according to claim 1, characterized in that: The passive output matching network includes a seventeenth microstrip line (TL). 17 ), the eighteenth microstrip line (TL 18 ), the nineteenth microstrip line (TL 19 ), 20th microstrip line (TL) 20 ), the twenty-first microstrip line (TL) 21 ), tenth capacitor (C) 10 ), Eleventh capacitor (C) 11 ), the twelfth capacitor (C) 12 ), the thirteenth capacitor (C) 13 ) and the fourteenth capacitor (C 14 ); the seventeenth microstrip line (TL 17 One end of the 17th microstrip line (TL) is connected to the drain of the second transistor (pHEMT2); 17 The other end of the line is connected to the eighteenth microstrip line (TL). 18 ) and the nineteenth microstrip line (TL 19 One end is connected; the eighteenth microstrip line (TL) 18 The other end of the circuit is connected to the drain bias voltage (V) respectively. D2 ) and the tenth capacitor (C 10 Connect one end of the capacitor; the tenth capacitor (C) 10 The other end of the line is grounded; the nineteenth microstrip line (TL) 19 The other end of the capacitor is connected to the eleventh capacitor (C). 11 ) and the twelfth capacitor (C 12 Connect one end of the capacitor; the eleventh capacitor (C) 11 The other end of the capacitor is grounded; the twelfth capacitor (C) 12 The other end of the line is connected to the twentieth microstrip line (TL). 20 ) and the twenty-first microstrip line (TL 21 One end is connected; the twentieth microstrip line (TL) 20 The other end of the line is grounded; the twenty-first microstrip line (TL) 21 The other end of the capacitor is connected to the thirteenth capacitor (C). 13 ) and the fourteenth capacitor (C 14 Connect one end of the capacitor; the thirteenth capacitor (C) 13 The other end of the capacitor is grounded; the fourteenth capacitor (C) 14 The other end of the line is connected to the 22nd microstrip line (TL) in the active output matching network. 22 Connect one end of the device; The active output matching network includes a twenty-second microstrip line (TL). 22 ), the 23rd microstrip line (TL) 23 ) and the twenty-fourth microstrip line (TL 24 ), the twenty-second microstrip line (TL 22 One end of the capacitor is connected to the fourteenth capacitor (C) in the passive output matching network. 14 One end is connected; the twenty-second microstrip line (TL) 22 The other end of the line is connected to the twenty-third microstrip line (TL). 23 ) and the twenty-fourth microstrip line (TL 24 One end is connected; the twenty-third microstrip line (TL) 23 The other end of the terminal is connected to the radio frequency output terminal (RF). out ) connection; Twenty-fourth microstrip line (TL 24 The other end of the signal is connected to the third control signal (CS). in3 )connect.

4. A method for implementing a 6-18GHz power amplifier combining active matching and passive matching, characterized in that: For the 6-18GHz power amplifier as described in any one of claims 1-3, the impedance positions of the first transistor (pHEMT1) and the second transistor (pHEMT2) are precisely controlled by a combination of active matching and passive matching: firstly, the impedance positions of the two transistors are initially matched by a passive matching circuit to reduce the matching difficulty; then, the impedance positions are further corrected by active matching, including correction of the fundamental impedance position and correction of the harmonic impedance position. Includes the following steps: A1: Select the process approach based on the required operating frequency range; select the total gate width of the final stage of the power amplifier based on the required output power and the power density of the selected process approach; determine the number of stages of the power amplifier based on the required gain; determine the interstage drive ratio based on the gain compression characteristics of the devices in the selected process approach. A2: Through Load Pull and Source Pull tests or simulations, determine the first fundamental load impedance, first second harmonic load impedance, first third harmonic load impedance, first fundamental source impedance, first second harmonic source impedance, and first third harmonic source impedance of the first transistor (pHEMT1), and determine the second fundamental load impedance, second second harmonic load impedance, second third harmonic load impedance, second fundamental source impedance, second second harmonic source impedance, and second third harmonic source impedance of the second transistor (pHEMT2). A3: Under the premise of ensuring that the insertion loss of the passive output matching network is small, the fundamental load impedance of the second transistor (pHEMT2) is matched to the circular region near the output load impedance; A4: Under the premise of ensuring that the insertion loss of the passive interstage matching network is small, the first fundamental load impedance of the first transistor (pHEMT1) is matched to the circular region near the second fundamental source impedance of the second transistor (pHEMT2). A5: Under the premise of ensuring that the insertion loss of the passive input matching network is small, the first fundamental source impedance of the first transistor (pHEMT1) is matched to the circular region near the input load impedance; A6: Based on step A3, through the third control signal (CS) in3 Injecting into the active output matching network, the second fundamental load impedance of the second transistor (pHEMT2) is strictly matched from the circular region near the output load impedance to the output load impedance point; A7: Based on step A4, through the second control signal (CS) in2 An active interstage matching network is injected to strictly match the first fundamental load impedance of the first transistor (pHEMT1) from the circular region near the second fundamental source impedance of the second transistor (pHEMT2) to the second fundamental source impedance of the second transistor (pHEMT2). A8: Based on step A5, through the first control signal (CS) in1 An active input matching network is injected to strictly match the first fundamental source impedance of the first transistor (pHEMT1) from the circular region near the input load impedance to the input load impedance point; A9: Based on the matching network designed in steps A3-A8, complete the integration and optimization of the schematic and layout.

5. The method for implementing a 6-18GHz power amplifier with active matching combined with passive matching according to claim 4, characterized in that, In step A6, the third control signal (CS) is used. in3 Injecting an active output matching network causes the second harmonic load impedance and the second and third harmonic load impedance of the second transistor (pHEMT2) to be at the short circuit point or the open circuit point, respectively.

6. The method for implementing a 6-18GHz power amplifier with active matching combined with passive matching according to claim 4, characterized in that, In step A7, the second control signal (CS) is used. in2 Injecting an active interstage matching network, so that the first second harmonic load impedance and the first third harmonic load impedance of the first transistor (pHEMT1) and the second second harmonic source impedance and the second third harmonic source impedance of the second transistor (pHEMT2) are at short-circuit points or open-circuit points, respectively.

7. The method for implementing a 6-18GHz power amplifier with active matching combined with passive matching according to claim 4, characterized in that, In step A8, the first control signal (CS) is used. in1 Injecting an active input matching network causes the first and second harmonic source impedances and the first and third harmonic source impedances of the first transistor (pHEMT1) to be at short-circuit points or open-circuit points, respectively.

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