Current-mode parallel-serial conversion circuit based on positive feedback

Abstract

The application belongs to the field of integrated circuit design, and proposes and serial conversion circuit, which is used for solving the problem of readout signal attenuation in the transmission process and the problem of readout signal error code caused by excessive parasitic capacitance, so as to improve the performance of the image sensor. The application comprises a current type SA circuit, a three-state gate module and a shift register, wherein the current type SA circuit is divided into two parts, namely a column parallel local circuit and a global circuit, which are respectively recorded as local module and global module; the working process is divided into two steps: the first step is completed by the current type SA circuit, and S column parallel data is converted into S / M group parallel data; the second step is completed by the three-state gate module and the shift register, and S / M group parallel data is converted into S / M group serial data. The application is mainly applied to the occasion of integrated circuit design and manufacturing.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more specifically to a parallel-to-serial conversion circuit suitable for ultra-large array image sensors. Background Technology

[0002] The main structure of a Complementary Metal Oxide Semiconductor (CMOS) image sensor includes a pixel array, readout circuitry, row drive circuitry, and peripheral circuitry such as timing control. For CMOS image sensors, resolution is a crucial parameter; higher resolution allows for clearer resolution of image details. Generally, resolution depends on the number of pixels in the image sensor; a larger pixel array results in higher resolution. However, as the pixel array increases, the readout circuitry also grows, leading to more pronounced non-ideal effects such as parasitic resistance and capacitance, thus increasing the difficulty and complexity of image sensor design.

[0003] Generally, after analog signals are processed by the readout circuit, they still need to pass through a parallel-to-serial conversion circuit to convert parallel data into serial data. Most parallel-to-serial conversion circuits are based on voltage transmission. However, for ultra-large array image sensors, the large readout array introduces large parasitic resistance and capacitance, and these parasitic effects cause a certain degree of attenuation in the voltage-type readout signal during transmission. Therefore, a current-type parallel-to-serial conversion circuit has been proposed. The operation of this circuit is divided into two steps: the readout signal passes through a current-type parallel-to-serial conversion circuit... Figure 2 , Figure 3 and Figure 4 The current-mode sensing amplifier (SA), composed of these components, completes the first step of parallel-to-serial conversion, and then... Figure 6 The tri-state gate module shown and as Figure 7 The shift register shown completes the second step of parallel-to-serial conversion. The first step, parallel-to-serial conversion, converts the input signal into a logic level, thereby effectively suppressing the attenuation of the read signal during transmission. However, this process involves the charging and discharging of capacitors, such as... Figure 2 The capacitors C1 and C2 shown are as follows: Figure 4 The capacitors C3 and C4 shown are the main parasitic capacitors in the current-mode SA circuit. The large array of readout circuits makes these capacitors quite large, which affects the charging and discharging speed and causes bit errors in the readout signal during rapid readout. Therefore, a current-mode parallel-to-serial conversion circuit based on positive feedback is proposed to solve the bit error problem. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, this invention aims to propose a design method for a current-mode parallel-to-serial converter circuit based on positive feedback. This circuit is suitable for ultra-large array image sensors and is used to solve the problems of readout signal attenuation during transmission and readout signal errors caused by excessive parasitic capacitance, thereby improving the performance of the image sensor. To this end, the technical solution adopted by this invention is a current-mode parallel-to-serial converter circuit based on positive feedback, including a current-mode SA circuit, a tri-state gate module, and a shift register. The current-mode SA circuit is divided into two parts: a column-parallel local circuit and a global circuit, denoted as the local module and the global module, respectively. The image sensor has a total of S columns of pixels in its entire array, and each column has an analog-to-digital converter (ADC). The converter has a precision of N bits, with one local module corresponding to one bit of output data. Therefore, each column of the circuit contains N parallel local modules. The entire array is divided into several groups, denoted as several blocks. Each block contains M columns of readout circuits, resulting in a total of S / M blocks. Each block contains N parallel global modules. Thus, the parallel-to-serial conversion circuit consists of S*N local modules, S*N / M global modules, one tri-state gate module, and one shift register. Its operation is divided into two steps: the first step is completed by the current-mode SA circuit, which converts S columns of parallel data into S / M groups of parallel data; the second step is completed by the tri-state gate module and the shift register, which converts the S / M groups of parallel data into S / M groups of serial data.

[0005] Each group of local modules includes inverters INV1, INV2, and INV3, NMOS transistors M6, M6b, M7, and M7b, and output parasitic capacitors C1 and C2; each column of ADC outputs N bits of data Q. <0> Q <1> Q <2> Q <3> Q <n-2> 、Q <n-1>Each of the N local modules receives the data, and each block contains M*N local modules.

[0006] The local module receives data Q. <0> At that time, Q <0> There are two flow paths available: one is through inverter INV1 connected to the gate of M7, and the other is through inverters INV2 and INV3 connected to the gate of M7b. The sources of NMOS transistors M7 and M7b are grounded, and the drains of M7 and M7b are connected to the sources of NMOS transistors M6 and M6b, respectively. <1> The signal is connected to the gates of M6 and M6b, and the drains of M6 and M6b serve as output terminals. The output signals are GLOBAL_IN- and GLOBAL_IN- respectively. <0> and GLOBAL_IN+ <0> .

[0007] Each global module includes a reset circuit and a positive feedback output circuit. The reset circuit includes PMOS transistors M1 and M1b, NMOS transistors M2, M2b, and M3; the positive feedback output circuit includes PMOS transistors M4, M4b, M8, M8b, M9, and M9b, NMOS transistors M5, M5b, M10, and M10b, transmission gate TG, inverters INV4 and INV5, NAND gates NAND1 and NAND2, and parasitic capacitors C3 and C4.

[0008] The local module receives data Q. <0> At that time, its output signal GLOBAL_IN+ <0> With GLOBAL_IN- <0> The drains of M5 and M5b are respectively connected to the sources of the NMOS transistors M5 and M5b. The drains of M5 and M5b are respectively connected to the drains of the PMOS transistors M4 and M4b. The sources of M4 and M4b are connected to the power supply voltage VDD. The gates of M4 and M5 are connected and then connected to the drain of M4b. This drain voltage is denoted as GLOBAL_BUS+. <0> The gates of M4b and M5b are connected, and the drain of M4 is also connected. The drain voltage is denoted as GLOBAL_BUS-. <0> The gates of M4 and M4b are connected through the transmission gate TG. The two control signals of TG are RST and RSTb, respectively. The RSTb signal is generated by the RST signal through the inverter INV4. When RST is set to a high level, TG is turned on and the reset circuit starts to work. The PMOS transistor M9 is connected to the gate of the NMOS transistor M10 and to the drain of M4. The source of M10 is grounded, and the drain of M10 is connected to the drain of M9 and then to the drain of M6. The source of M9 is connected to the drain of the PMOS transistor M8. The gate of M8 is connected to the enable signal EN, and the source of M8 is connected to VDD. The PMOS transistor M9b is connected to the gate of the NMOS transistor M10b and to the drain of M4b. The source of M10b is grounded, and the drain of M10b is connected to the drain of M9b and then to the drain of M6b. The source of M9b is connected to the drain of the PMOS transistor M8b. The gate of M8b is connected to the EN signal, and the source of M8b is connected to VDD. M8, M9, and M10, as well as M8b, M9b, and M10b, form a positive feedback structure. The EN signal controls whether the positive feedback structure operates. When TG is disconnected, the EN signal is set to low, and the positive feedback structure starts operating. GLOBAL_BUS+ <0> The control signal SC is used as the input of the NAND gate NAND1. The output of NAND1 is connected to the input of the inverter INV4. The output signal of INV4 is GLOBAL_OUT+. <0> GLOBAL_BUS- <0> The control signal SC is used as the input of the NAND gate NAND2. The output of NAND2 is connected to the input of the inverter INV5. The output signal of INV5 is GLOBAL_OUT. <0> Simultaneously, the drain of M6b and the drain of M6 are connected to the source and drain of NMOS transistor M3, respectively. The source and drain of M3 are connected to the source of NMOS transistor M2 and the source of NMOS transistor M2b, respectively. The RST signal is connected to the gates of M2, M2b, and M3. The drain of M2 is connected to the drain of PMOS transistor M1, and the drain of M2b is connected to the drain of PMOS transistor M1b. The sources of M1 and M1b are connected to VDD, and the gates of M1 and M1b are connected to the reference signal VREF. The VREF signal is used to control the magnitude of the reset voltage. Similarly, when the local module receives Q... <1> Q <2> Q <n-2> 、Q <n-1>At the same time, the analysis method is the same, and the N-bit data is converted synchronously. Under the control of the strobe signal SEL, the data in each column is converted in sequence, completing the first step of parallel-to-serial conversion.

[0009] The tri-state gate module circuit structure consists of N tri-state gates, 1 resistor, and 1 buffer. The inputs of the N tri-state gates are, in sequence, GLOBAL_OUT+... <0> GLOBAL_OUT+ <1> GLOBAL_OUT+ <2> GLOBAL_OUT+ <3> , , GLOBAL_OUT+ <n-2>、GLOBAL_OUT+ <n-1>The enable signals are sequentially: Enable <0> Enable <1> Enable <2> Enable <3> Enable <n-2>、Enable <n-1>The shift register circuit consists of N D flip-flops with reset connected end to end. The clock CLK is active on the rising edge, generating N active enable bits in sequence, so that the N bits of data are serially output through the buffer from the least significant bit to the most significant bit, completing the second step of parallel-to-serial conversion.

[0010] The features and beneficial effects of this invention are:

[0011] This invention proposes a positive feedback-based current-mode parallel-to-serial conversion circuit to address readout signal errors and improve image sensor performance. A two-step current-mode parallel-to-serial conversion circuit is employed. The first step, using a current-mode switch (SA), converts the entire array of parallel data into several parallel columns. This suppresses readout signal attenuation during transmission and, through a positive feedback structure, increases the charging and discharging speed, ensuring readout signal accuracy. The final parallel-to-serial conversion is then achieved by using a shift register and tri-state gates to convert the parallel columns into serial data. Attached image description:

[0012] Figure 1 The system showcased is an architecture for an ultra-large array image sensor.

[0013] Figure 2 This demonstrates the local module circuit structure of a current-mode SA circuit.

[0014] Figure 3 This demonstrates the reset circuit structure in the global module of a current-type SA circuit.

[0015] Figure 4 This demonstrates the positive feedback output circuit structure in the global module of a current-type SA circuit.

[0016] Figure 5 The diagram shown is the timing diagram of a current-mode SA circuit.

[0017] Figure 6 This demonstrates the circuit structure of a tri-state gate module.

[0018] Figure 7 This demonstrates the circuit structure of a shift register. Detailed Implementation

[0019] A current-mode parallel-to-serial converter circuit based on positive feedback includes a current-mode analog-switched (SA) circuit, a tri-state gate module, and a shift register. The current-mode SA circuit is divided into two parts: a column-parallel local module and a global module. Assuming the image sensor's entire array has S columns of pixels, each column's ADC has an accuracy of N bits, and one local module corresponds to one bit of output data, then each column circuit contains N parallel local modules. The entire array is further divided into several groups, denoted as blocks, each block containing M columns of readout circuits, resulting in a total of S / M blocks. Each block contains N parallel global modules. Therefore, the parallel-to-serial converter circuit consists of S*N local modules, S*N / M global modules, one tri-state gate module, and one shift register. Its operation involves two steps: the first step, performed by the current-mode SA circuit, converts the S columns of parallel data into S / M groups of parallel data; the second step, performed by the tri-state gate module and the shift register, converts the S / M groups of parallel data into S / M groups of serial data.

[0020] Figure 2 The local module circuit structure of the current-mode SA circuit is shown. Each local module includes inverters INV1, INV2, and INV3, NMOS transistors M6, M6b, M7, and M7b, and parasitic capacitors C1 and C2 at the output. Each column of the ADC outputs N bits of data Q. <0> Q <1> Q <2> Q <3> Q <n-2> 、Q <n-1>Each of the N local modules receives the data, so a block contains M*N local modules.

[0021] Receive data Q using the local module <0> For example, Q <0> There are two flow paths available: one is through inverter INV1 connected to the gate of M7, and the other is through inverters INV2 and INV3 connected to the gate of M7b. The sources of NMOS transistors M7 and M7b are grounded, and the drains of M7 and M7b are connected to the sources of NMOS transistors M6 and M6b, respectively. <1> The signal is connected to the gates of M6 and M6b, and the drains of M6 and M6b serve as output terminals, respectively GLOBAL_IN- <0> and GLOBAL_IN+ <0> .

[0022] Figure 3 The reset circuit structure in the global module of the current-mode SA circuit is shown. Figure 4 The positive feedback output circuit structure in the global module of a current-mode SA circuit is shown. Each column of the ADC has an accuracy of N bits. The M-column readout circuit of a block contains M*N local modules and N global modules. This design ensures output data consistency while reducing layout area and improving circuit utilization. The global module consists of a reset circuit and a positive feedback output circuit. The reset circuit includes PMOS transistors M1 and M1b, and NMOS transistors M2, M2b, and M3. The output circuit includes PMOS transistors M4, M4b, M8, M8b, M9, and M9b, NMOS transistors M5, M5b, M10, and M10b, a transmission gate TG, inverters INV4 and INV5, NAND gates NAND1 and NAND2, and parasitic capacitors C3 and C4.

[0023] Receive data Q using the local module <0> For example, its output signal GLOBAL_IN+ <0> With GLOBAL_IN- <0> The drains of M5 and M5b are respectively connected to the sources of the NMOS transistors M5 and M5b. The drains of M5 and M5b are respectively connected to the drains of the PMOS transistors M4 and M4b. The sources of M4 and M4b are connected to the power supply voltage VDD. The gates of M4 and M5 are connected and then connected to the drain of M4b. This drain voltage is denoted as GLOBAL_BUS+. <0> The gates of M4b and M5b are connected, and the drain of M4 is also connected. The drain voltage is denoted as GLOBAL_BUS-. <0> The gates of M4 and M4b are connected through the transmission gate TG. The two control signals of TG are RST and RSTb, respectively. The RSTb signal is generated by the RST signal through the inverter INV4. When RST is set to a high level, TG is turned on and the reset circuit starts to work. The PMOS transistor M9 is connected to the gate of the NMOS transistor M10 and to the drain of M4. The source of M10 is grounded, and the drain of M10 is connected to the drain of M9 and then to the drain of M6. The source of M9 is connected to the drain of the PMOS transistor M8. The gate of M8 is connected to the enable signal EN, and the source of M8 is connected to VDD. The PMOS transistor M9b is connected to the gate of the NMOS transistor M10b and to the drain of M4b. The source of M10b is grounded, and the drain of M10b is connected to the drain of M9b and then to the drain of M6b. The source of M9b is connected to the drain of the PMOS transistor M8b. The gate of M8b is connected to the EN signal, and the source of M8b is connected to VDD. M8, M9, and M10, as well as M8b, M9b, and M10b, form a positive feedback structure. The EN signal controls whether the positive feedback structure operates. When TG is disconnected, the EN signal is set to low, and the positive feedback structure starts operating. GLOBAL_BUS+ <0> The SC signal is used as the input of the NAND gate NAND1. The output of NAND1 is connected to the input of the inverter INV4. The output signal of INV4 is GLOBAL_OUT+. <0> GLOBAL_BUS- <0> The SC signal is used as the input of the NAND gate NAND2. The output of NAND2 is connected to the input of the inverter INV5. The output signal of INV5 is GLOBAL_OUT. <0> Simultaneously, the drain of M6b and the drain of M6 are connected to the source and drain of NMOS transistor M3, respectively. The source and drain of M3 are connected to the source of NMOS transistor M2 and the source of NMOS transistor M2b, respectively. The RST signal is connected to the gates of M2, M2b, and M3. The drain of M2 is connected to the drain of PMOS transistor M1, and the drain of M2b is connected to the drain of PMOS transistor M1b. The sources of M1 and M1b are connected to VDD, and the gates of M1 and M1b are connected to the reference signal VREF. The VREF signal is used to control the magnitude of the reset voltage. Similarly, when the local module receives Q... <1> Q <2> Q <n-2> 、Q <n-1>At the same time, the analysis method is the same, and the N-bit data is converted synchronously. Under the control of the strobe signal SEL, the data in each column is converted in sequence, completing the first step of parallel-to-serial conversion.

[0024] Figure 6 The circuit structure of a tri-state gate module is shown, which consists of N tri-state gates, 1 resistor, and 1 buffer. The input terminals of the N tri-state gates are GLOBAL_OUT+... <0> GLOBAL_OUT+ <1> GLOBAL_OUT+ <2> GLOBAL_OUT+ <3> , , GLOBAL_OUT+ <n-2>、GLOBAL_OUT+ <n-1>The enable signals are sequentially: Enable <0> Enable <1> Enable <2> Enable <3> Enable <n-2>、Enable <n-1>. Figure 7 The circuit structure of the shift register is shown. It consists of N D flip-flops with reset connected end to end. The clock CLK is active on the rising edge, and N bits of enable are generated in sequence. This enables the N bits of data to be serially output from the least significant bit to the most significant bit after passing through the buffer, thus completing the second step of parallel-to-serial conversion.

[0025] This invention is a current-mode parallel-to-serial conversion circuit, and the working process is described in detail below.

[0026] Figure 5 The timing diagram of the current-mode SA circuit is shown. The SEL signal is sequentially set to high, and different columns start operating in sequence. Data Q is received by the local module. <0> For example, SEL <1> When the signal is set to high, M6 and M6b are turned on. Assume Q... <0> If the signal is low, then M7 is turned on and M7b is turned off, thus forming a conductive path to ground between M6 and M7.

[0027] During time intervals t0 to t1, the reset circuit in the global module starts working, the RST signal is set to high level, and M2, M2b, and M3 are turned on, affecting node GLOBAL_IN+. <0> With GLOBAL_IN- <0> Perform a reset operation. The VREF signal is a fixed voltage value, controlling the GLOBAL_IN+ node. <0> With GLOBAL_IN- <0> The magnitude of the initial reset voltage. Simultaneously, the transmission gate TG in the output circuit is turned on, and the gates of M4, M4b, M5, and M5b are connected and at the same voltage, with the voltage magnitude being the same as that of node GLOBAL_IN+. <0> and GLOBAL_IN- <0> The magnitude of the initial reset voltage is relevant.

[0028] At times t1 to t2, the RST signal is set low, the EN signal is set low, and the transmission gate TG is opened. M4, M4b, M5, and M5b form a cross-coupled structure, and the positive feedback structure composed of M8, M9, M10, M8b, M9b, and M10b begins to operate. At the instant the transmission gate TG is opened, node GLOBAL_BUS+... <0> With GLOBAL_BUS- <0> The voltage will rise slightly under the influence of the TG current and the charging currents of M6 and M6b. At this time, the node GLOBAL_BUS+ <0> With GLOBAL_BUS- <0> Both are in a high-level state, causing M10 and M10b to conduct, forming a path to ground. Also, because Q... <0> When the signal is low, M6 and M7 in the local module form a conductive path to ground. Therefore, for node GLOBAL_BUS+... <0> In other words, its discharge speed will be faster than that of node GLOBAL_BUS- <0> When node GLOBAL_BUS+ <0> When the voltage is below half of VDD, M10b is cut off, and M8b and M9b will turn on node GLOBAL_IN+. <0> If the pull-up is high, then the node GLOBAL_BUS- <0> The charging speed will be accelerated, and under the action of the cross-coupling structure, it will always be in a high-level state. Therefore, the node GLOBAL_IN- <0> It is constantly pulled low, which has a negative effect on the GLOBAL_BUS+ node. <0> The discharge process forms a positive feedback loop, which continues until the node GLOBAL_BUS+ <0> Discharged to 0, while node GLOBAL_BUS- <0> Charge to VDD.

[0029] Between times t2 and t3, the EN signal is set to high, and the positive feedback structure stops working. At this time, the SC signal, as the output control signal, is set to high. Under the logic relationship of the NAND gate and inverter, the final output GLOBAL_OUT+ is achieved. <0> GLOBAL_OUT is 0. <0> For VDD.

[0030] The global module circuit structure is completely symmetrical, if Q <0> If it's a high level, the analysis method still applies. Similarly, when the local module receives Q... <1> Q <2> Q <n-2> 、Q <n-1>At the same time, the analysis method is the same, and N-bit data are converted synchronously. Under the control of the SEL, RST, EN, and SC signals, the data in each column is converted in sequence, completing the first step of parallel-to-serial conversion.

[0031] Next, GLOBAL_OUT+ <0> GLOBAL_OUT+ <1> GLOBAL_OUT+ <2> GLOBAL_OUT+ <3> , , GLOBAL_OUT+ <n-2>、GLOBAL_OUT+ <n-1>N bits of data are sent to the input of the tri-state gate module. The tri-state gate is controlled by the enable signal Enable, which is active high. This signal is generated by a shift register and enabled through a shift operation. <0> Enable <1> Enable <2> Enable <3> Enable <n-2>、Enable <n-1>In sequence, N-bit data is outputted from the buffer in series from the lowest bit to the highest bit, and the second step and serial conversion are completed.

[0032] The above description is only the preferred embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0033] The above description is only the preferred embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application. < / n-2> < / n-2> < / n-2> < / n-2> < / n-2>

Claims

1. A current-mode parallel-to-serial conversion circuit based on positive feedback, characterized in that, The system includes a current-mode SA circuit, a tri-state gate module, and a shift register. The current-mode SA circuit is divided into two parts: a column-parallel local circuit and a global circuit, denoted as a local module and a global module, respectively. The image sensor's entire array of pixels has S columns. Each column's analog-to-digital converter (ADC) has an accuracy of N bits. One local module corresponds to one bit of output data, so each column circuit contains N parallel local modules. The entire array is further divided into several groups, denoted as several blocks. Each block contains M columns of readout circuits, resulting in a total of S / M blocks. Each block contains N parallel global modules. Therefore, the parallel-to-serial conversion circuit consists of S*N local modules, S*N / M global modules, one tri-state gate module, and one shift register. Its operation is divided into two steps: the first step, completed by the current-mode SA circuit, converts the S columns of parallel data into S / M groups of parallel data; the second step, completed by the tri-state gate module and the shift register, converts the S / M groups of parallel data into S / M groups of serial data. Each global module includes a reset circuit and a positive feedback output circuit. The reset circuit includes PMOS transistors M1 and M1b, NMOS transistors M2, M2b and M3; the positive feedback output circuit includes PMOS transistors M4, M4b, M8, M8b, M9 and M9b, NMOS transistors M5, M5b, M10 and M10b, transmission gate TG, inverters INV4 and INV5, NAND gates NAND1 and NAND2, and parasitic capacitors C3 and C4. The local module receives data Q. <0> At that time, its output signal GLOBAL_IN+ <0> With GLOBAL_IN- <0> The drains of M5 and M5b are respectively connected to the sources of the NMOS transistors M5 and M5b. The drains of M5 and M5b are respectively connected to the drains of the PMOS transistors M4 and M4b. The sources of M4 and M4b are connected to the power supply voltage VDD. The gates of M4 and M5 are connected and then connected to the drain of M4b. This drain voltage is denoted as GLOBAL_BUS+. <0> The gates of M4b and M5b are connected, and the drain of M4 is also connected. The drain voltage is denoted as GLOBAL_BUS-. <0> The gates of M4 and M4b are connected through the transmission gate TG. TG has two control signals, RST and RSTb. The RSTb signal is generated by the RST signal through the inverter INV4. When RST is high, TG is turned on, and the reset circuit starts working. The gates of PMOS transistor M9 and NMOS transistor M10 are connected and connected to the drain of M4. The source of M10 is grounded, and the drain of M10 is connected to the drain of M9 and then to the drain of M6. The source of M9 is connected to the drain of PMOS transistor M8. The gate of M8 is connected to the enable signal EN, and the source of M8 is connected to VDD. The PMOS transistor M9b is connected to the gate of the NMOS transistor M10b and to the drain of M4b. The source of M10b is grounded, and the drain of M10b is connected to the drain of M9b and to the drain of M6b. The source of M9b is connected to the drain of the PMOS transistor M8b. The gate of M8b is connected to the EN signal, and the source of M8b is connected to VDD. A positive feedback structure is formed by M8, M9, M10, M8b, M9b, and M10b. The EN signal controls whether the positive feedback structure works. When TG is disconnected, the EN signal is set to low, and the positive feedback structure starts working. GLOBAL_BUS+ <0> The control signal SC is used as the input of the NAND gate NAND1. The output of NAND1 is connected to the input of the inverter INV4. The output signal of INV4 is GLOBAL_OUT+. <0> GLOBAL_BUS- <0> The control signal SC is used as the input of the NAND gate NAND2. The output of NAND2 is connected to the input of the inverter INV5. The output signal of INV5 is GLOBAL_OUT. <0> Simultaneously, the drain of M6b and the drain of M6 are connected to the source and drain of the NMOS transistor M3, respectively. The source and drain of M3 are connected to the source of the NMOS transistor M2 and the source of the NMOS transistor M2b, respectively. The RST signal is connected to the gates of M2, M2b, and M3. The drain of M2 is connected to the drain of the PMOS transistor M1, and the drain of M2b is connected to the drain of the PMOS transistor M1b. The sources of M1 and M1b are connected to VDD, and the gates of M1 and M1b are connected to the reference signal VREF. The VREF signal is used to control the magnitude of the reset voltage. And so on, when the local module receives Q... <1> Q <2> Q <n-2> 、Q <n-1> At the same time, the analysis method is the same, and the N-bit data is converted synchronously; under the control of the strobe signal SEL, the data in each column is converted in sequence to complete the first step of parallel-to-serial conversion.< / n-1> < / n-2> 2. The current-mode parallel-to-serial conversion circuit based on positive feedback as described in claim 1, characterized in that, Each group of local modules includes inverters INV1, INV2, and INV3, NMOS transistors M6, M6b, M7, and M7b, and output parasitic capacitors C1 and C2; each column of ADC outputs N bits of data Q. <0> Q <1> Q <2> Q <3> Q <n-2> 、Q <n-1> Each of the N local modules receives the data, and each block contains M*N local modules.< / n-1> < / n-2> The local module receives data Q. <0> At that time, Q <0> There are two flow paths available: one is through inverter INV1 connected to the gate of M7, and the other is through inverters INV2 and INV3 connected to the gate of M7b. The sources of NMOS transistors M7 and M7b are grounded, and the drains of M7 and M7b are connected to the sources of NMOS transistors M6 and M6b, respectively. <1> The signal is connected to the gates of M6 and M6b, and the drains of M6 and M6b serve as output terminals. The output signals are GLOBAL_IN- and GLOBAL_IN- respectively. <0> and GLOBAL_IN+ <0> .

3. The current-mode parallel-to-serial conversion circuit based on positive feedback as described in claim 1, characterized in that, The tri-state gate module circuit structure consists of N tri-state gates, 1 resistor, and 1 buffer; the input terminals of the N tri-state gates are GLOBAL_OUT+... <0> GLOBAL_OUT+ <1> GLOBAL_OUT+ <2> GLOBAL_OUT+ <3> ..., GLOBAL_OUT+<N-2>, GLOBAL_OUT+<N-1>, the enable signals are Enable in sequence. <0> Enable <1> Enable <2> Enable <3> Enable <n-2> Enable<N-1>; The shift register circuit consists of N D flip-flops with reset connected end to end. The clock CLK is active on the rising edge, and N bits of active enable are generated in sequence, so that the N bits of data are serially output through the buffer from the least significant bit to the most significant bit, completing the second step of parallel-to-serial conversion.< / n-2>

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