An infrared focal plane readout circuit and an infrared detector device

Abstract

The present application discloses an infrared focal plane readout circuit and infrared detector device, comprising: an infrared focal plane having an array of pixel units; a timing control circuit for controlling the decoding timing of a row decoding circuit and a column decoding circuit; a row decoding circuit for selecting pixel units in a specified row of the infrared focal plane; a column decoding circuit connected to a column-level processing circuit for specifying the selection of the column-level processing circuit; a column-level processing circuit connected to a corresponding column decoding circuit for outputting a signal based on the pixel units in the corresponding column after selection; and an output buffer amplifier circuit disposed at the output end of the column-level processing circuit for serving as an output buffer for column signals of a specified number of column pixel units. The present application can multiply the spacing of pixel array column signal processing circuits, improve the compatibility of column-level processing circuit layout design, reduce the noise level of large-scale, small-pitch readout circuits, and reduce the background fixed pattern noise of the readout circuit.

Description

Technical Field

[0001] The present application relates to the field of infrared detector technology, and in particular to an infrared focal plane readout circuit and an infrared detector device. Background Art

[0002] Infrared detectors are widely used in industrial monitoring, early warning detection, target detection, and other fields. They primarily consist of an infrared focal plane (IFP) sensor array and a traditional IFP readout circuit. The IFP readout circuit's primary function is to integrate, amplify, and sequentially read out the IFP sensing signal. Currently, IFP readout circuit specifications have evolved from 320×256 and 640×512 to larger sizes such as 1280×1024 and 2048×2048, with center-to-center spacing decreasing from 30μm to 10μm, 7.5μm, and even 5μm. The reduction in center-to-center spacing reduces the integrating capacitance, while the increase in readout circuit specifications increases the column line parasitic capacitance. Traditional charge transfer uses a switched capacitor circuit for column-level circuits. The parasitic capacitance of the long column lines generates noise amplification gain with the capacitance of the switched capacitor circuit. When the switched capacitor circuit gain is relatively small, the noise gain generated by the parasitic capacitance increases. Therefore, the traditional charge transfer architecture is increasingly detrimental to readout circuit noise suppression. Summary of the Invention

[0003] The embodiments of the present application provide an infrared focal plane readout circuit and an infrared detector device, which are used to reduce the noise level of a large-scale, small-pitch readout circuit and reduce the background fixed pattern noise of the readout circuit.

[0004] An embodiment of the present application provides an infrared focal plane readout circuit, comprising:

[0005] Infrared focal plane, having pixel units in an array;

[0006] A timing control circuit for controlling the decoding timing of the row decoding circuit and the column decoding circuit;

[0007] A row decoding circuit, used for selecting pixel units of a specified row of the infrared focal plane;

[0008] At least two column decoding circuits are connected to the column-level processing circuits respectively and are symmetrically distributed based on the infrared focal plane, and are used to specify the gating of the column-level processing circuits respectively;

[0009] Column-level processing circuits, the total number of which is equal to the number of columns of the infrared focal plane, are divided into at least two groups, the number of which matches the number of column decoding circuits, and are respectively connected to corresponding column decoding circuits to output signals based on pixel units in corresponding columns after being selected;

[0010] The output buffer amplifier circuit has multiple channels and is divided into at least two groups. The number of groups matches the number of column decoding circuits. The circuit is respectively arranged at the output end of the column-level processing circuit to serve as an output buffer for column signals of a specified number of column pixel units.

[0011] Optionally, the circuit structure of the pixel unit includes: an injection tube MP1, an injection tube MN1, a control switch SW1, a control switch SW2, a control switch SW3, a control switch SW4, an integration capacitor C1, an integration capacitor C2, a sampling capacitor C3, an input tube MN2, and a row selection switch tube MN3;

[0012] The drain and source of the injection tube MP1 and the injection tube MN1 are connected in parallel and connected to the input node IN of the detector signal and the integration node VINT respectively. The gate of the injection tube MP1 is connected to the control signal CKINT_P, and the gate of the injection tube MN1 is connected to the control signal CKINT_N.

[0013] The integration node VINT is connected to the VR reference level through the control switch SW2, and the control switch SW2 is controlled by the control signal RST_INT;

[0014] The control switch SW1 and the integration capacitor C1 are connected in series between the integration node VINT and the node VSSA, and the control switch SW1 is controlled by the GAIN signal;

[0015] The integration capacitor C2 is connected between the integration node VINT and the node VSSA;

[0016] The integration node VINT is connected to the sampling node VSH through the control switch SW3, and the control switch SW3 is controlled by the SH signal;

[0017] The sampling node VSH is connected to the reference voltage VR via the control switch SW4, and the control switch SW4 is controlled by the RST_SH signal;

[0018] The sampling capacitor C3 is connected between the sampling node VSH and the node VSSA;

[0019] The sampling node VSH is connected to the gate of the input transistor MN2. The source of the input transistor MN2 and the drain of the row select transistor MN3 are connected in series. The drain of the input transistor MN2 is connected to the node IBO. The source of the row select transistor MN3 is connected to the node ISO.

[0020] Optionally, the column-level processing circuit includes an OPA amplifier, and the OPA amplifier includes an input tube MN4 and a row selection switch matching tube MN5;

[0021] The drain of the input transistor MN4 is connected to the drain of the current mirror MP3, the source of the input transistor MN4 is connected to the drain of the row selection switch matching transistor MN5, and the gate of the input transistor MN4 is connected to the output end of the OPA amplifier. The input transistor MN4 and the input transistor MN2 of the pixel unit form an input pair of the OPA amplifier.

[0022] The source of the row selection switch matching transistor MN5 is connected to the drain of the current source MN9 , and the gate thereof is connected to the power signal VDDA, which is used to match the row selection switch MN3 of the pixel unit.

[0023] Optionally, the column-level processing circuit specifically includes an OPA amplifier and a multi-channel sampling circuit structure, wherein any sampling circuit structure includes a sampling switch SW5, a sampling capacitor CSHO, and an AMP input structure, wherein the AMP input structure includes an input tube MN6, an input tube MN7, a column decoding switch SW7, a column decoding switch SW8, and a current source I1;

[0024] The output end of the OPA amplifier is connected to the gate of the input tube MN6 through the sampling switch SW5;

[0025] The sources of the input transistors MN6 and MN7 are connected in parallel to the current source I1. The drains of the input transistors MN6 and MN7 are connected to the first signal lead-out terminal and the second signal lead-out terminal via the column decoding switches SW7 and SW8, respectively. The gate of the input transistor MN7 is connected to the output stage feedback signal.

[0026] The column decoding switch SW7 and the column decoding switch SW8 are respectively controlled by corresponding column decoding control signals.

[0027] Optionally, the number of output buffer amplifier circuits corresponds to a pre-configured maximum number of output channels, and the number of output buffer amplifier circuits in each group is the same.

[0028] Optionally, a channel selection switching circuit is further included, which is connected to the output end of each group of the output buffer amplifier circuits and is used to perform signal output based on the corresponding channel based on the channel selection instruction.

[0029] Optionally, a serial port control circuit is also included to configure the functions of the readout circuit.

[0030] Optionally, two column decoding circuits are included, and the column-level processing circuits are divided into two groups.

[0031] An embodiment of the present application further provides an infrared detector device, comprising the aforementioned infrared focal plane readout circuit.

[0032] The embodiments of the present application divide the column-level processing circuits of multiple columns into at least two groups by designing at least two column decoding circuits. This can exponentially increase the spacing of the pixel array column signal processing circuits, improve the compatibility of the column-level processing circuit layout design, reduce the noise level of large-scale, small-pitch readout circuits, and reduce the background fixed pattern noise of the readout circuit.

[0033] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0035] Figure 1 This is an example of the overall structure of the infrared focal plane readout circuit according to an embodiment of the present application;

[0036] Figure 2 This is an example of the pixel unit structure of an embodiment of the present application;

[0037] Figure 3 An example of the control timing of integration and readout according to an embodiment of the present application;

[0038] Figure 4 This is an example of the control timing of integrating and reading out in an embodiment of the present application;

[0039] Figure 5 This is an example of a column-level processing circuit structure of a readout circuit according to an embodiment of the present application;

[0040] Figure 6 This is an example of the OPA principle structure of the column-level processing circuit of an embodiment of the present application;

[0041] Figure 7 This is an example of the connection principle of the 160 column-level processing circuits in an embodiment of the present application;

[0042] Figure 8 This is an example of the principle structure of the output stage unit of an embodiment of the present application. DETAILED DESCRIPTION

[0043] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0044] The embodiment of the present application provides an infrared focal plane readout circuit, such as Figure 1 Shown, including:

[0045] The infrared focal plane has pixel units in an array. The array referred to in this example refers to the array specifications. For example, the infrared focal plane includes large specifications such as 1280 (columns) × 1024 (rows) and 2048 × 2048, and there are also specifications such as 320 × 256 and 640 × 512.

[0046] The timing control circuit is used to control the decoding timing of the row decoding circuit and the column decoding circuit, that is, the infrared focal plane corresponds to one timing control circuit.

[0047] The row decoding circuit is used to select the pixel units of the specified row of the infrared focal plane. The infrared focal plane corresponds to one row decoding circuit. The output of the infrared focal plane is to select the specified row and then the specified column to complete the output. The row selection method can be, for example, row-by-row selection.

[0048] The column decoding circuits include at least two paths, which are respectively connected to the column-level processing circuits and are symmetrically distributed based on the infrared focal plane, and are respectively used to specify the selection of the column-level processing circuits.

[0049] The total number of column-level processing circuits is equal to the number of columns of the infrared focal plane, and is divided into at least two groups. The number of groups matches the number of column decoding circuits, and is respectively connected to the corresponding column decoding circuit to output signals based on the pixel units of the corresponding column after being selected.

[0050] The output buffer amplifier circuit has multiple channels and is divided into at least two groups. The number of groups matches the number of column decoding circuits. The output buffer amplifier circuit is respectively arranged at the output end of the column-level processing circuit to serve as an output buffer for the column signals of a specified number of column pixel units. The output buffer amplifier circuit can complete the signal output.

[0051] The embodiments of the present application divide the column-level processing circuits of multiple columns into at least two groups by designing at least two column decoding circuits. This can exponentially increase the spacing of the pixel array column signal processing circuits, improve the compatibility of the column-level processing circuit layout design, reduce the noise level of large-scale, small-pitch readout circuits, and reduce the background fixed pattern noise of the readout circuit.

[0052] In some embodiments, two column decoding circuits are included, and the column-level processing circuits are divided into two groups. In this example, the design of the PCB board is as follows: Figure 1 As shown, the two column decoding circuits are respectively arranged on the upper and lower sides of the infrared focal plane, thereby increasing the spacing between the pixel array column lines to twice the existing one and facilitating PCB design.

[0053] like Figure 1 As shown in the figure, the ultra-large-scale infrared focal plane readout circuit in this example mainly consists of a 1280 (column) × 1024 (row) pixel array, 1280 column-level processing circuits, timing control circuits, column decoding circuits, row decoding circuits, bias circuits, output buffer amplifier circuits, etc. This example will continue to use the ultra-large scale 1280 × 1024 as an example. The readout circuit designs of other scales are similar and are not detailed in this specification.

[0054] In this example, the 1280 column-level processing circuits are symmetrically distributed up and down, that is, Figure 1 In the figure, there are 640 column-level processing circuits on the top and 640 column-level processing circuits on the bottom, and the spacing between the column-level processing circuits is twice the center spacing of the pixel array.

[0055] Two column decoding circuits, column decoding circuit group A and column decoding circuit group B are located at the bottom and top of the array respectively. Column decoding circuit group A is responsible for selecting the odd column signals (1st, 3rd, 5th...1279th), and column decoding circuit group B is responsible for selecting the even column signals (2nd, 4th, 6th...1280th). The specific selection method can be designed according to actual needs and will not be elaborated on here.

[0056] The row decoding circuit is responsible for selecting the 1024 row signals row by row.

[0057] Bias circuit group A is responsible for providing stable current and voltage bias for the column-level processing circuits below the array; bias circuit group B is responsible for providing stable current and voltage bias for the column-level processing circuits above the array.

[0058] There are a total of 8 groups of output buffer amplifier circuits. The B1, B3, B5, and B7 output buffer operational amplifiers are at the bottom of the array. The B1 output buffer operational amplifier is responsible for the output buffering of the COLS<1:8:1280> column signal, the B3 output buffer operational amplifier is responsible for the output buffering of the COLS<3:8:1280> column signal, the B5 output buffer operational amplifier is responsible for the output buffering of the COLS<5:8:1280> column signal, and the B7 output buffer operational amplifier is responsible for the output buffering of the COLS<5:8:1280> column signal.

[0059] Output buffer op amps B2, B4, B6, and B8 are located at the top of the array. The B2 output buffer op amp is responsible for buffering the COLS<2:8:1280> column signal outputs, the B4 output buffer op amp is responsible for buffering the COLS<4:8:1280> column signal outputs, the B6 output buffer op amp is responsible for buffering the COLS<6:8:1280> column signal outputs, and the B8 output buffer op amp is responsible for buffering the COLS<8:8:1280> column signal outputs. The specific number of output buffer amplifier circuits can be set based on actual needs and is not detailed here.

[0060] In some embodiments, as Figure 2 As shown, the circuit structure of the pixel unit includes: injection tube MP1, injection tube MN1, control switch SW1, control switch SW2, control switch SW3, control switch SW4, integration capacitor C1, integration capacitor C2, sampling capacitor C3, input tube MN2 and row selection switch tube MN3;

[0061] The drain and source of the injection tube MP1 and the injection tube MN1 are connected in parallel and connected to the input node IN of the detector signal and the integration node VINT respectively. The gate of the injection tube MP1 is connected to the control signal CKINT_P, and the gate of the injection tube MN1 is connected to the control signal CKINT_N.

[0062] The integration node VINT is connected to the VR reference level through the control switch SW2, and the control switch SW2 is controlled by the control signal RST_INT;

[0063] The control switch SW1 and the integration capacitor C1 are connected in series between the integration node VINT and the node VSSA, and the control switch SW1 is controlled by the GAIN signal;

[0064] The integration capacitor C2 is connected between the integration node VINT and the node VSSA;

[0065] The integration node VINT is connected to the sampling node VSH through the control switch SW3, and the control switch SW3 is controlled by the SH signal;

[0066] The sampling node VSH is connected to the reference voltage VR via the control switch SW4, and the control switch SW4 is controlled by the RST_SH signal;

[0067] The sampling capacitor C3 is connected between the sampling node VSH and the node VSSA;

[0068] The sampling node VSH is connected to the gate of the input transistor MN2. The source of the input transistor MN2 and the drain of the row select transistor MN3 are connected in series. The drain of the input transistor MN2 is connected to the node IBO. The source of the row select transistor MN3 is connected to the node ISO.

[0069] In this example, all control switches utilize a transmission gate structure. The pixel unit circuit can accommodate both p-on-n and n-on-p infrared detectors. When adapting to a p-on-n infrared detector, injection transistor MN1 is shut down by a timing control signal, placing the MN1 injection transistor in the cutoff state. At this point, reference voltage VR is biased to a relatively low potential, such as 0.75V. When adapting to an n-on-p infrared detector, injection transistor MP1 is shut down by a timing control signal, placing the MP1 injection transistor in the cutoff state. At this point, VR is biased to a relatively high potential, such as 3.0V. Regardless of whether the detector is p-on-n or n-on-p, only one of the injection transistors, MN1 and MP1, operates in a subthreshold state, providing a stable operating bias for the infrared detector.

[0070] The integration capacitors C1, C2 and the sampling capacitor C3 are respectively NMOS capacitors and MIM capacitors in parallel to provide a relatively large charge processing capability. The pixel unit circuit can operate in ITR mode (integrate and then read out) and IWR mode (integrate while reading out). When the readout circuit operates in ITR mode, the control switch SW3 is always closed and the control switch SW4 is always open. At the beginning of the integration signal, the RST_INT signal completes the initial reset of the integration capacitor. During the integration of the readout circuit signal, the integration current completes integration on C1+C2+C3. The ITR working sequence is as follows: Figure 3 As shown; when the readout circuit works in IWR mode, the working timing of the pixel unit circuit is as follows Figure 4 As shown, the pixel unit completes the sampling and readout of the previous frame's integrated signal while integrating the current frame. When the sampling of the previous frame's integrated signal is completed, the sampling capacitor C3 is first reset by the RST_SH signal, and then the switch SW3 is closed by the SH signal to complete the sampling of the previous frame's signal. Next, the switch SW2 is closed to complete the reset of the integration capacitors C1 and C2, and the signal integration of the current frame begins. Switch SW1 can be controlled by the GAIN signal to complete the selection of the integration capacitor. When the GAIN signal is high, the SW1 switch is closed, and the actual integration capacitor is C1+C2. When the GAIN signal is low, the SW1 switch is open, and the actual integration capacitor is C2.

[0071] In this example, the column-level processing circuits of the readout circuit are distributed in an upper and lower arrangement. The column-level processing circuits on the upper side of the infrared focal plane array are responsible for the follow-up buffering and row ping-pong sampling of the even-numbered column pixel signals, while the column-level processing circuits on the lower side of the infrared focal plane array are responsible for the follow-up buffering and row ping-pong sampling of the odd-numbered column pixel signals. In some embodiments, the circuit structure of a single column signal processing circuit is as follows: Figure 5 As shown, the column-level processing circuit includes an OPA amplifier, and the circuit structure of the OPA amplifier is as shown Figure 6As shown, the OPA amplifier includes an input tube MN4 and a row selection switch matching tube MN5.

[0072] The drain of the input tube MN4 is connected to the drain of the current mirror MP3 tube, its source is connected to the drain of the row selection switch matching tube MN5, and its gate is connected to the output end of the OPA amplifier. It and the input tube MN2 of the pixel unit form an input pair tube of the OPA amplifier.

[0073] The source of the row selection switch matching transistor MN5 is connected to the drain of the current source MN9 , and the gate thereof is connected to the power signal VDDA, which is used to match the row selection switch MN3 of the pixel unit.

[0074] In this embodiment, the input transistor MN2 of the pixel unit and the input transistor MN4 of the column-level processing circuit form the input pair of the OPA amplifier. The MN5 transistor is used to match the row select switch MN3 of each pixel to ensure the matching of the input pair of the OPA amplifier, reduce the offset voltage of the OPA, and thus reduce the fixed pattern noise of the readout circuit.

[0075] In some embodiments, the column-level processing circuit specifically includes an OPA amplifier and a multi-channel sampling circuit structure, wherein any sampling circuit structure includes a sampling switch SW5, a sampling capacitor CSHO and an AMP input structure, wherein the AMP input structure includes an input tube MN6, an input tube MN7, a column decoding switch SW7, a column decoding switch SW8 and a current source I1.

[0076] The output end of the OPA amplifier is connected to the gate of the input tube MN6 through the sampling switch SW5;

[0077] The sources of the input transistors MN6 and MN7 are connected in parallel to the current source I1. The drains of the input transistors MN6 and MN7 are connected to the first signal lead-out terminal and the second signal lead-out terminal via the column decoding switches SW7 and SW8, respectively. The gate of the input transistor MN7 is connected to the output stage feedback signal.

[0078] The column decoding switch SW7 and the column decoding switch SW8 are respectively controlled by corresponding column decoding control signals.

[0079] In this example, a 1280 (column) × 1024 (row) pixel array, 8-way output buffer amplifier circuit, each output buffer amplifier circuit corresponds to 160 columns of pixel units, and two-way column decoding circuits correspond to odd and even rows. Other circuit designs are similar and will not be described in detail here. One implementation of the column-level processing circuit in this embodiment is as follows: Figure 7 As shown, it is mainly composed of an OPA amplifier (the specific structure is as follows Figure 6As shown), odd-row sampling switch SW5, even-row sampling switch SW6, odd-row sampling capacitor CSHO, even-row sampling capacitor CSHE, odd-row AMP input structure, even-row AMP input structure, wherein the odd-row AMP input structure includes input pair transistors M6 and M7, column decoding switches SW7 and SW8, and current source I1, and the even-row AMP input structure includes input pair transistors M8 and M9, column decoding switches SW9 and SW10, and current source I2.

[0080] Column decoding control signal LINE_DEC_O <j>(1≤j≤160)、LINE_DEC_E <j>(1≤j≤160), output stage feedback signal VFB (1≤i≤1280), IBOA (1≤i≤1280)、IBOB (1≤i≤1280). The output terminals IBO and ISO of the 1024 rows of pixel units are connected to the IBO and ISO ports of a single column-level signal processing circuit OPA amplifier, respectively. The output terminal VSFO of the OPA is connected to the sampling nodes VSHO and VSHE via sampling switches SW5 and SW6, respectively. The sampling switches SW5 and SW6 are controlled by sampling signals SHO and SHE, respectively.

[0081] The sampling nodes VSHO, VSHE and VSSA ground are connected to the sampling capacitors CSHO and CSHE respectively; the sampling node VSHO is connected to the gate of the odd-row AMP input structure input transistor MN6, the sources of the odd-row AMP input structure input transistors MN6 and MN7 are connected to the current source I1, and the drains are connected to IBOA through the column decoding switches SW7 and SW8 respectively. <j>and IBOB <j>The control signal of the column decoding switch SW7 and the column decoding switch SW8 is LINE_DEC_0. <j>, one end of the current source I1 is connected to the VSSO ground; the sampling node VSHE is connected to the gate end of the input tube MN8 of the even-numbered row AMP input structure; the source ends of the input tubes MN8 and MN9 of the even-numbered row AMP input structure are connected to the current source I2, and the drain ends are connected to IBSA through the control switches SW9 and SW10 respectively. <j>and IBOS <j>Lead-out terminal, control switch SW9 and SW10 control signal is LINE_DEC_E <j>, one end of the current source I2 is connected to the VSSO ground.

[0082] In some embodiments, the number of output buffer amplifier circuits corresponds to the pre-configured maximum number of output channels, and each group of output buffer amplifier circuits has the same number of output buffer amplifier circuits. For example, if the pre-configured maximum number of output channels is 8, two groups of 8-channel output buffer amplifier circuits may be provided.

[0083] The array size of the readout circuit is 1280×1024, 1280 Figure 5 The column signal processing circuit shown in FIG. <j>(1≤j≤160) and LINE_DEC_E <j>(1≤j≤160) control, and orderly output each column processing circuit signal VSHO and VSHE through 8 groups of output buffer operational amplifiers. Figure 7 The connection relationship of 160 column processing circuits through an output buffer operational amplifier is shown in the following figure. Figure 8 As shown, this embodiment adopts a two-stage folded cascode structure, in which the second stage adopts the CLASSA method. Among the 1280 column processing circuits, the IBOA<1:1280:8>, IBOB<1:1280:8>, and VFB<1:1280:8> signals of 160 column processing circuits are respectively connected to the IBOA, IBO, and VFB terminals of the unity gain output buffer amplifier BUFFER1. Figure 7 The connection relationship is similar. In the 1280 column processing circuits, the 160 IBOA<2:1280:8>, IBOB<2:1280:8>, and VFB<2:1280:8> signals are respectively connected to the IBOA, IBO, and VFB terminals of the unity-gain output buffer amplifier BUFFER2, and so on. In the 1280 column processing circuits, the 160 IBOA<8:1280:8>, IBOB<8:1280:8>, and VFB<8:1280:8> signals are respectively connected to the IBOA, IBO, and VFB terminals of the unity-gain output buffer amplifier BUFFER2, and finally to the OU1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, and OUT8 outputs.

[0084] In some embodiments, a channel selection switching circuit is further included, which is connected to the output end of each group of the output buffer amplifier circuits to perform signal output based on the corresponding channel based on the channel selection instruction. For example, the aforementioned OU1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, and OUT8, a total of 8 channels, can be selected and controlled by the channel switching selection circuit (such as Figure 1 As shown), select output from AOUT1, AOUT2, AOUT3, AOUT4, AOUT5, AOUT6, AOUT7, and AOUT8 respectively.

[0085] In some embodiments, a serial port control circuit is included to configure the readout circuit's functionality. Specific configurable functions include, for example, the specifications of the infrared focal plane array (IFPA). For example, if the maximum IFPA array size is 1280×1024, other sizes smaller than or equal to that maximum can be configured based on this size. The aforementioned output channels can also be configured.

[0086] The infrared focal plane readout circuit of this application utilizes an architectural design, pixel-level design, column-level processing circuit design, and output-stage design to address the difficulty of suppressing readout circuit noise, which arises from a reduction in the center-to-center spacing of the readout circuit leading to a reduction in integral capacitance and an increase in the parasitic capacitance of the pixel array column lines due to an increase in readout circuit specifications. This application also proposes a readout circuit design method based on a combination of a direct input stage structure and a voltage transmission structure. While compatible with both n-on-p and p-on-n infrared detectors, this method is particularly suitable for suppressing readout circuit noise in small-pitch infrared detectors, thereby reducing the background fixed pattern noise of the readout circuit.

[0087] An embodiment of the present application further provides an infrared detector device, comprising the aforementioned infrared focal plane readout circuit.

[0088] It should be noted that, in this document, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a..." does not preclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0089] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0090] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are protected by this application.< / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. An infrared focal plane readout circuit, characterized in that: include: Infrared focal plane, having pixel units in an array; A timing control circuit for controlling the decoding timing of the row decoding circuit and the column decoding circuit; A row decoding circuit, used for selecting pixel units of a specified row of the infrared focal plane; At least two column decoding circuits are connected to the column-level processing circuits respectively and are symmetrically distributed based on the infrared focal plane, and are used to specify the gating of the column-level processing circuits respectively; Column-level processing circuits, the total number of which is equal to the number of columns of the infrared focal plane, are divided into at least two groups, the number of which matches the number of column decoding circuits, and are respectively connected to corresponding column decoding circuits to output signals based on pixel units in corresponding columns after being selected; The output buffer amplifier circuit has multiple channels and is divided into at least two groups. The number of groups matches the number of column decoding circuits. The circuit is respectively arranged at the output end of the column-level processing circuit to serve as an output buffer for column signals of a specified number of column pixel units.

2. The infrared focal plane readout circuit according to claim 1, wherein: The circuit structure of the pixel unit includes: injection tube MP1, injection tube MN1, control switch SW1, control switch SW2, control switch SW3, control switch SW4, integration capacitor C1, integration capacitor C2, sampling capacitor C3, input tube MN2 and row selection switch tube MN3; The drain and source of the injection tube MP1 and the injection tube MN1 are connected in parallel and connected to the input node IN of the detector signal and the integration node VINT respectively. The gate of the injection tube MP1 is connected to the control signal CKINT_P, and the gate of the injection tube MN1 is connected to the control signal CKINT_N. The integration node VINT is connected to the VR reference level through the control switch SW2, and the control switch SW2 is controlled by the control signal RST_INT; The control switch SW1 and the integration capacitor C1 are connected in series between the integration node VINT and the node VSSA, and the control switch SW1 is controlled by the GAIN signal; The integration capacitor C2 is connected between the integration node VINT and the node VSSA; The integration node VINT is connected to the sampling node VSH through the control switch SW3, and the control switch SW3 is controlled by the SH signal; The sampling node VSH is connected to the reference voltage VR via the control switch SW4, and the control switch SW4 is controlled by the RST_SH signal; The sampling capacitor C3 is connected between the sampling node VSH and the node VSSA; The sampling node VSH is connected to the gate of the input transistor MN2. The source of the input transistor MN2 and the drain of the row select transistor MN3 are connected in series. The drain of the input transistor MN2 is connected to the node IBO. The source of the row select transistor MN3 is connected to the node ISO.

3. The infrared focal plane readout circuit according to claim 2, wherein: The column-level processing circuit includes an OPA amplifier, and the OPA amplifier includes an input tube MN4 and a row selection switch matching tube MN5; The drain of the input transistor MN4 is connected to the drain of the current mirror MP3, the source of the input transistor MN4 is connected to the drain of the row selection switch matching transistor MN5, and the gate of the input transistor MN4 is connected to the output end of the OPA amplifier. The input transistor MN4 and the input transistor MN2 of the pixel unit form an input pair of the OPA amplifier. The source of the row selection switch matching transistor MN5 is connected to the drain of the current source MN9 , and the gate thereof is connected to the power signal VDDA, which is used to match the row selection switch MN3 of the pixel unit.

4. The infrared focal plane readout circuit according to claim 3, wherein: The column-level processing circuit specifically includes an OPA amplifier and a multi-channel sampling circuit structure, wherein any sampling circuit structure includes a sampling switch SW5, a sampling capacitor CSHO and an AMP input structure, wherein the AMP input structure includes an input transistor MN6, an input transistor MN7, a column decoding switch SW7, a column decoding switch SW8 and a current source I1; The output end of the OPA amplifier is connected to the gate of the input tube MN6 through the sampling switch SW5; The sources of the input transistors MN6 and MN7 are connected in parallel to the current source I1. The drains of the input transistors MN6 and MN7 are connected to the first signal lead-out terminal and the second signal lead-out terminal via the column decoding switches SW7 and SW8, respectively. The gate of the input transistor MN7 is connected to the output stage feedback signal. The column decoding switch SW7 and the column decoding switch SW8 are respectively controlled by corresponding column decoding control signals.

5. The infrared focal plane readout circuit according to claim 1, wherein: The number of output buffer amplifier circuits corresponds to the pre-configured maximum number of output channels, and the number of output buffer amplifier circuits in each group is the same.

6. The infrared focal plane readout circuit according to claim 5, wherein: It also includes a channel selection switching circuit connected to the output end of each group of the output buffer amplifier circuits, and is used to perform signal output based on the corresponding channel based on the channel selection instruction.

7. The infrared focal plane readout circuit according to claim 5, wherein: It also includes a serial port control circuit for configuring the functions of the readout circuit.

8. The infrared focal plane readout circuit according to claim 1, wherein: The column decoding circuits are two-way, and the column-level processing circuits are divided into two groups.

9. An infrared detector device, characterized in that: The method comprises the infrared focal plane readout circuit according to any one of claims 1 to 8.

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