A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductor devices, so that the appearance of a hole formed in a first etching stop layer is consistent with the appearance of a preset scheme, the appearance of a part of a lower electrode formed in the hole meets the requirements of the preset scheme, and the yield of the semiconductor device is improved. The semiconductor device comprises a substrate, a first etching stop layer and a capacitor. The first etching stop layer is located on the substrate. The first etching stop layer is doped with carbon. The doping concentration of carbon in the first etching stop layer from top to bottom is in a semi-Gaussian distribution, and the doping concentration of carbon at the bottom of the first etching stop layer is greater than the doping concentration of carbon at the top of the first etching stop layer. The capacitor is located on the first etching stop layer. The capacitor comprises a lower electrode, an upper electrode and a dielectric layer located between the lower electrode and the upper electrode. The lower electrode penetrates the first etching stop layer. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] In actual manufacturing processes, before forming a capacitor on the substrate, an etch stop layer is typically formed to cover the substrate. The presence of this etch stop layer protects the substrate from subsequent etching, cleaning, and other operations, improving the yield of the resulting semiconductor device. Furthermore, the bottom of the lower electrode included in the capacitor penetrates the etch stop layer and contacts the corresponding area of ​​the substrate.

[0003] However, the morphology of the holes opened in the existing etch stop layer is not consistent with the morphology of the preset scheme, which causes the morphology of the part of the lower electrode formed in the hole to fail to meet the requirements of the preset scheme, resulting in a decrease in the yield of semiconductor devices. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, so that the morphology of the hole formed in the first etch stop layer is consistent with the morphology of a preset scheme, ensuring that the morphology of the portion of the lower electrode formed in the hole meets the requirements of the preset scheme, thereby improving the yield of the semiconductor device.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising:

[0006] Base,

[0007] A first etch stop layer is located on the substrate; the first etch stop layer is doped with carbon; the carbon doping concentration in the first etch stop layer is half-Gaussian from top to bottom, and the carbon doping concentration at the bottom of the first etch stop layer is greater than the carbon doping concentration at the top of the first etch stop layer.

[0008] A capacitor located on a first etch stop layer, the capacitor including a lower electrode, an upper electrode, and a dielectric layer located between the lower electrode and the upper electrode; the lower electrode penetrates the first etch stop layer.

[0009] Compared with the prior art, the semiconductor device provided by the application has a first etching stop layer formed on the substrate, and the first etching stop layer is doped with carbon. The doping concentration of carbon in the first etching stop layer is semi-Gaussian from top to bottom. Meanwhile, the doping concentration of carbon at the bottom of the first etching stop layer is greater than that at the top of the first etching stop layer. Based on this, the first etching stop layer doped with carbon is easier to be etched than the etching stop layer without carbon, and the etching rate of the etchant on the first etching stop layer is greater as the doping concentration of carbon is higher. On this basis, when the film layer above the first etching stop layer is etched, the etching rate of the etchant on the top of the first etching stop layer is very low because the doping concentration of carbon at the top of the first etching stop layer is low, so that the film layer above the first etching stop layer can be etched through and stopped at the top of the first etching stop layer. Based on this, when the etchant is used to etch the first etching stop layer from top to bottom to form a hole pattern, the etching time and etching degree of the etchant on different regions of the first etching stop layer are basically the same because the thickness of the first etching stop layer in different regions is the same, so that the etching morphology between the holes in different regions of the first etching stop layer can be kept consistent, and the morphology of the part of the lower electrode formed in the holes in different regions is consistent.

[0010] Meanwhile, when the hole pattern is formed in the first etching stop layer, the etching rate of the etchant on the first etching stop layer increases and the increasing speed gradually slows down because the doping concentration of carbon in the first etching stop layer increases and the increasing speed gradually slows down with the increase of the depth. At this time, the etching time of the etchant on the top of the first etching stop layer is longer and the etching time of the etchant on the bottom of the first etching stop layer is shorter. However, the etching rate of the etchant on the top of the first etching stop layer is lower and the etching rate of the etchant on the bottom of the first etching stop layer is higher. Therefore, the amount of material etched away from the bottom of the first etching stop layer does not decrease because of the shortening of the etching time, thereby solving the technical problem that the radial size of the hole formed in the etching stop layer gradually decreases and the decreasing speed gradually slows down with the increase of the depth, so that the hole formed in the first etching stop layer has the morphology of "equal width from top to bottom", thereby increasing the bottom surface area of the lower electrode formed in the hole. Because the resistance is inversely proportional to the surface area, the increase of the surface area of the lower electrode can reduce the resistance of the lower electrode, thereby shortening the charging and discharging time of the capacitor and improving the running speed of the semiconductor device. Moreover, the morphology of the bottom of the lower electrode meets the requirements of the preset scheme, which can not only increase the storage capacity of the capacitor but also improve the leakage phenomenon between the lower electrode and the upper electrode and improve the working performance of the semiconductor device. In addition, the etching rate of the etchant on the bottom of the first etching stop layer is greater, so that the hole pattern penetrating through the first etching stop layer is easily formed, thereby enabling the bottom of the lower electrode formed in the hole pattern to be electrically connected with the corresponding structure formed on the substrate, and improving the yield of the semiconductor device.

[0011] The application further provides a semiconductor device manufacturing method, which comprises the following steps:

[0012] providing a substrate;

[0013] forming a first etching stop layer on the substrate; the first etching stop layer is doped with carbon; the carbon doping concentration in the first etching stop layer presents a semi-Gaussian distribution from top to bottom, and the carbon doping concentration at the bottom of the first etching stop layer is greater than that at the top of the first etching stop layer;

[0014] forming a capacitor on the first etching stop layer, the capacitor comprising a lower electrode, an upper electrode and a dielectric layer between the lower electrode and the upper electrode; the lower electrode penetrates the first etching stop layer.

[0015] Compared with the prior art, the semiconductor device manufacturing method provided by the application has the beneficial effects of the semiconductor device provided by the above technical solution, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are included to provide a further understanding of the application and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0017] Figure 1 It is a structural schematic diagram of the structure after forming a pattern hole structure penetrating through two layer stacks and a silicon nitride etching stop layer in the prior art;

[0018] Figure 2 It is a structural schematic diagram of the structure after forming a first etching stop layer on a substrate in an embodiment of the application;

[0019] Figure 3 It is a structural schematic diagram of the structure after forming a second etching stop layer on a substrate in an embodiment of the application;

[0020] Figure 4 It is a structural schematic diagram of the structure after sequentially forming at least one layer stack and a mask pattern on a first etching stop layer in an embodiment of the application;

[0021] Figure 5 It is a structural schematic diagram of the structure after forming a pattern hole structure in an embodiment of the application;

[0022] Figure 6 It is a structural schematic diagram of the structure after forming a lower electrode in an embodiment of the application;

[0023] Figure 7 It is a structural schematic diagram of the structure after removing a molding layer in an embodiment of the application;

[0024] Figure 8A structure schematic diagram after forming a capacitor in an embodiment of the present application.

[0025] The reference numerals are as follows: 1 is a substrate, 2 is a first etching stop layer, 3 is a second etching stop layer, 4 is a stack, 41 is a molding layer, 42 is a support layer, 5 is a pattern hole structure, 6 is a capacitor, 61 is a lower electrode, 62 is a dielectric layer, and 63 is an upper electrode. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary of the present disclosure, but not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known functions and constructions are omitted to avoid obscuring the concept of the present disclosure in unnecessary detail.

[0027] In the drawings, various structure schematic diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, where certain details are shown in a highly exaggerated manner for the purpose of making the drawings more illustrative and easier to understand, and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships between them shown in the drawings are merely exemplary, and in actuality, they can deviate due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0028] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects more clear, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application, and not to limit the present application.

[0029] In addition, the terms "first", "second", etc. are used only for the purpose of description, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited. The meaning of "several" is one or more, unless otherwise explicitly and specifically limited.

[0030] In the description of the present application, it is necessary to point out that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, it can be internal communication of two elements or interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0031] In the process of manufacturing semiconductor devices, after the transistors in the semiconductor devices, the landing plugs electrically connected with the active regions of the corresponding transistors, and the isolation portions for isolating two adjacent landing plugs are manufactured, it is necessary to form an etching stop layer covering the landing plugs and the isolation portions, and a stack layer on the etching stop layer. Then, the stack layer and the etching stop layer are etched from top to bottom to form holes in the stack layer and the etching stop layer. After that, a lower electrode in contact with the corresponding landing plug is formed in each hole, which lays the foundation for the subsequent formation of the overall structure of the capacitor. During the above process, the existence of the etching stop layer can protect the landing plugs and the isolation portions below from being affected by etching, cleaning and other operations.

[0032] In actual application, the material of the etching stop layer is generally silicon nitride or boron nitride silicon. Among them, the silicon nitride etching stop layer has strong etching resistance, so it can be stopped on the silicon nitride etching stop layer after etching the molding layer included in the lowermost stack layer. On this basis, because the thickness of different regions of the silicon nitride etching stop layer is the same after etching the above molding layer, when the holes in the silicon nitride etching stop layer are formed, the etching time of the holes in different regions of the silicon nitride etching stop layer is relatively consistent, so that the etching degree of the etchant to different regions of the silicon nitride etching stop layer is roughly the same, thereby the etching morphology between the holes in different regions of the silicon nitride etching stop layer can be kept relatively consistent. However, because the silicon nitride etching stop layer has strong etching resistance, it cannot be guaranteed that the silicon nitride etching stop layer is etched through when the etchant is used to etch the silicon nitride etching stop layer. At this time, because silicon nitride is an insulating material, the remaining part of the silicon nitride etching stop layer which is not etched at the bottom of the formed hole will cause the bottom of the lower electrode to be unable to be electrically connected with the corresponding landing plug, thereby causing the short circuit of the semiconductor device. In addition, if the thickness of the silicon nitride etching stop layer is too small, the etching stop layer cannot be etched through, and the etching stop layer will be left at the bottom of the hole, which will also cause the short circuit of the semiconductor device. Figure 1As shown, when etching the silicon nitride etching stop layer from top to bottom to open a hole in the silicon nitride etching stop layer, the etching time of the hole opening part is longer than that of the hole bottom part as the etching depth increases, resulting in over-etching of the hole opening part, so that the radial cross-sectional area of the hole gradually decreases with the increase of the depth, and further, the radial dimension of the part of the lower electrode 61 formed in the hole also gradually decreases, resulting in the decrease of the storage capacity of the capacitor 6. Moreover, the morphology of the bottom of the lower electrode 61 is inconsistent with the preset morphology, and a bending phenomenon occurs, thereby easily leading to the leakage phenomenon between the lower electrode 61 and the upper electrode 63 included in the capacitor 6, and finally resulting in poor working performance of the semiconductor device.

[0033] For the boron nitride silicon etching stop layer, compared with the silicon nitride etching stop layer, the boron nitride silicon etching stop layer is more easily etched, so that it can ensure that the hole opened in the boron nitride silicon etching stop layer can penetrate through the etching stop layer, and further ensure that the part of the lower electrode located in the hole can be in contact with the landing plug. In addition, when opening a hole in the boron nitride silicon etching stop layer which is more easily etched, the etchant not only has longitudinal etching ability for the boron nitride silicon etching stop layer, but also has certain lateral etching ability, so as to improve the problem that the sidewall of the hole opened in the boron nitride silicon etching stop layer is inclined, resulting in the gradual decrease of the radial cross-sectional area of the hole with the increase of the depth. However, it is because that the boron nitride silicon etching stop layer is more easily etched, so that it cannot be stopped on the boron nitride silicon etching stop layer after etching the molding layer included in the lowermost layer. On this basis, because the thickness of different regions of the boron nitride silicon etching stop layer is different after etching the above-mentioned molding layer, when a hole is opened in the boron nitride silicon etching stop layer, the etching time of the holes located in different regions of the boron nitride silicon etching stop layer is different due to the non-uniformity of etching and the loading effect. The hole formed in the region with smaller thickness of the boron nitride silicon etching stop layer is formed first, and the hole formed in the region with larger thickness is formed later, so that the hole formed first will be over-etched, resulting in the inconsistent morphology of the holes in different regions of the boron nitride silicon etching stop layer, and further resulting in the inconsistent morphology of the lower electrode formed in the hole with inconsistent morphology, and finally resulting in poor performance of the semiconductor device.

[0034] From the above, it can be seen that whether the silicon nitride etching stop layer or the boron nitride silicon etching stop layer is used, both of them cannot ensure that the etching stop layer has strong etching stop ability while preventing the morphology of the hole opened in the etching stop layer from gradually narrowing with the increase of the depth, thereby reducing the yield of the semiconductor device.

[0035] To solve the above technical problems, the embodiment of the present application provides a semiconductor device and a manufacturing method thereof. In the semiconductor device provided by the embodiment of the present application, a first etching stop layer is formed on a substrate, and the first etching stop layer is doped with carbon. Meanwhile, the doping concentration of carbon in the first etching stop layer is in a semi-Gaussian distribution from top to bottom, and the doping concentration of carbon at the bottom of the first etching stop layer is greater than the doping concentration of carbon at the top of the first etching stop layer, so that the appearance of a hole formed in the first etching stop layer is consistent with the appearance of a preset scheme, thereby ensuring that the appearance of the part of the lower electrode formed in the hole meets the requirements of the preset scheme, and improving the yield of the semiconductor device.

[0036] As shown in Figure 8 , the embodiment of the present application provides a semiconductor device. The semiconductor device can be a DRAM (Dynamic Random Access Memory), a FLASH (Flash Memory) or the like.

[0037] Referring to Figure 8 , the semiconductor device comprises a substrate 1, a first etching stop layer 2 and a capacitor 6.

[0038] Referring to Figure 8 , the first etching stop layer 2 is located on the substrate 1, and the first etching stop layer 2 is doped with carbon. The doping concentration of carbon in the first etching stop layer 2 is in a semi-Gaussian distribution from top to bottom, and the doping concentration of carbon at the bottom of the first etching stop layer 2 is greater than the doping concentration of carbon at the top of the first etching stop layer 2.

[0039] Referring to Figure 8 , the capacitor 6 is located on the first etching stop layer 2, and the capacitor 6 comprises a lower electrode 61, an upper electrode 63 and a dielectric layer 62 located between the lower electrode 61 and the upper electrode 63. The lower electrode 61 penetrates the first etching stop layer 2.

[0040] Specifically, the substrate can be a structure comprising a single semiconductor material, such as a single crystal silicon substrate, a polycrystalline silicon substrate or the like. Of course, the substrate can also be a laminated structure which has been formed with a part of semiconductor structure.

[0041] For example, when the semiconductor device provided by the embodiment of the present application is DRAM (Dynamic Random Access Memory), the substrate can at least include a semiconductor substrate, a transistor, a bit line structure, a storage contact, an insulating portion, a landing plug and an isolation portion. The transistor is formed on the semiconductor substrate. The bit line structure is formed above the transistor. The storage contact and the insulating portion are formed between adjacent bit line structures. The storage contact is in contact with a source region (or a drain region) of the transistor. The insulating portion is used to isolate two adjacent storage contacts. Meanwhile, each landing plug is formed on the corresponding storage contact. The landing plug is electrically connected to the source region (or the drain region) of the transistor through the storage contact. The isolation portion is formed on the bit line structure and the insulating portion. The isolation portion is used to isolate two adjacent landing plugs.

[0042] The transistor can be a buried-gate transistor or any other required transistor. The bit line structure can include a bit line body, a cap layer on the bit line body, and a sidewall on both sides of the bit line body and the cap layer. The bit line body can be electrically connected to the drain region (or the source region) of the transistor through a bit line contact. The materials contained in the above-mentioned parts can be set according to the actual application scenario, which is not limited here.

[0043] As for the capacitor, the number of capacitors can be one or multiple. When the number of capacitors is multiple, the arrangement between the multiple capacitors can be set according to the actual application scenario, as long as it can be applied to the semiconductor device provided by the embodiment of the present application. In addition, referring to Figure 8 When the semiconductor device provided by the embodiment of the present application is DRAM, a plurality of landing plugs and an isolation portion for isolating two adjacent landing plugs can be formed on the substrate 1. Each landing plug is in contact with a corresponding lower electrode 61. It should be understood that if a landing plug has a lower electrode 61 formed thereon, the landing plug corresponds to the lower electrode 61.

[0044] The materials contained in the lower electrode and the upper electrode of the capacitor can be doped polysilicon, metal or metal nitride, etc. The materials contained in the lower electrode and the upper electrode can be the same or different. The material contained in the dielectric layer can be silicon oxide or high-K (dielectric constant) material, etc. The thickness of the dielectric layer can be set according to the actual application scenario, which is not limited here. Specifically, the thickness of the dielectric layer determines the distance between the lower electrode and the upper electrode. The distance between the lower electrode and the upper electrode is inversely proportional to the capacitance, i.e. when the distance between the lower electrode and the upper electrode decreases, the capacitance increases. When the distance between the lower electrode and the upper electrode increases, the capacitance decreases.

[0045] In the actual application process, when manufacturing the semiconductor device provided by the embodiment of the present application, referring to Figure 2The first etching stop layer 2 can be formed on the substrate 1. The material of the first etching stop layer 2 can be set according to the material of the film layer formed on the first etching stop layer 2. In addition, the doping concentration range of carbon in the first etching stop layer 2 and the variation degree of the doping concentration at different heights in the case of the semi-Gaussian distribution of carbon in the first etching stop layer 2 can be set according to the actual application scenario, which is not specifically limited here. For example, before manufacturing the semiconductor device provided in the embodiments of the present application, a conventional etching stop layer can be formed in advance, and a hole pattern can be formed in the etching stop layer after etching the stack on the etching stop layer. After repeating the above operation for several times, the inclination degree of the sidewall of the hole included in the hole pattern is counted. The variation degree of the doping concentration of carbon at different heights in the first etching stop layer 2 is consistent with the inclination degree of the hole sidewall. Based on this, referring to Figure 5 , after subsequently etching the stack 4 on the first etching stop layer 2, when the hole pattern is formed in the first etching stop layer 2, the etching rate of the etchant on different depth parts of the first etching stop layer 2 will also change accordingly, so as to make up for the deficiency of the hole included in the hole pattern in the hole morphology.

[0046] As can be seen from the above, the first etching stop layer doped with carbon is easier to be etched than the etching stop layer without carbon doping, and the etching rate of the etchant to the first etching stop layer is greater as the carbon doping concentration is higher. On this basis, when the hole pattern is opened in the first etching stop layer, since the carbon doping concentration in the first etching stop layer increases with the increase of the depth and the increasing speed gradually slows down, the etching rate of the etchant to the first etching stop layer increases and the increasing speed gradually slows down from top to bottom. At this time, although the etching time of the etchant to the top of the first etching stop layer is longer and the etching time of the etchant to the bottom of the first etching stop layer is shorter. However, because the etching rate of the etchant to the top of the first etching stop layer is lower and the etching rate of the etchant to the bottom of the first etching stop layer is higher. Therefore, the amount of material etched away at the bottom of the first etching stop layer will not decrease due to the shortening of the etching time, thereby solving the technical problem that the radial size of the hole opened in the etching stop layer gradually decreases with the increase of the depth and the decreasing speed gradually slows down, so that the hole opened in the first etching stop layer has a "equal width from top to bottom" appearance, thereby increasing the bottom surface area of the lower electrode formed in the hole. Because the resistance is inversely proportional to the surface area, the increase of the surface area of the lower electrode can reduce the resistance of the lower electrode, thereby shortening the charging and discharging time of the capacitor and improving the operating speed of the semiconductor device. Moreover, the appearance of the bottom of the lower electrode meets the requirements of the preset scheme, which not only increases the storage capacity of the capacitor, but also improves the leakage phenomenon between the lower electrode and the upper electrode and improves the working performance of the semiconductor device. In addition, the etching rate of the etchant to the bottom of the first etching stop layer is large, which is easy to form a hole pattern penetrating through the first etching stop layer, so that the bottom of the lower electrode formed in the hole pattern can be electrically connected with the corresponding structure formed on the substrate, thereby improving the yield of the semiconductor device.

[0047] At the same time, when etching the film layer located above the first etching stop layer, because the doping concentration of carbon at the top of the first etching stop layer is low, the etching rate of the etchant to the top of the first etching stop layer is also very low, so that the film layer above the first etching stop layer can be etched through and stopped at the top of the first etching stop layer. Based on this, when the etchant etches the first etching stop layer from top to bottom to form a hole pattern, because the thickness of different regions of the first etching stop layer is the same, the etching time and etching degree of the etchant to different regions of the first etching stop layer are substantially the same, thereby keeping the etching appearance between the holes located in different regions of the first etching stop layer consistent, and further making the appearance of the bottom of the lower electrode formed in the holes in different regions consistent.

[0048] In an example, the first etching stop layer includes a plurality of sub-layers of silicon carbon nitride stacked on the substrate. The doping concentration of carbon in the plurality of sub-layers of silicon carbon nitride presents a semi-Gaussian distribution from top to bottom.

[0049] Specifically, the number of layers of the silicon carbon nitride sub-layers included in the first etching stop layer and the thickness of each layer of the silicon carbon nitride sub-layers can be set according to actual needs, which are not limited here. It can be understood that the more the number of layers of the silicon carbon nitride sub-layers included in the first etching stop layer and the smaller the thickness of each layer of the silicon carbon nitride sub-layers, the more gentle the change in the doping concentration of carbon in adjacent silicon carbon nitride sub-layers, and the more gentle the change in the etching rate of the etchant when etching adjacent silicon carbon nitride sub-layers from top to bottom, so that the side wall of the hole obtained after etching the multi-layer silicon carbon nitride sub-layers is relatively smooth, and the outer surface of the portion of the lower electrode formed in the hole is also relatively smooth, which can improve the working performance of the semiconductor device.

[0050] It is worth noting that carbon is a relatively stable element in terms of chemical activity, and the first etching stop layer formed after doping carbon has stronger etching resistance than the boron nitride etching stop layer formed after doping boron. And the doping concentration of carbon at the top of the first etching stop layer is low, and the etching rate of the etchant on the top of the first etching stop layer is small, so that the etching of the film layer on the first etching stop layer can be stopped on the first etching stop layer, which can ensure that the morphology of the holes opened in different areas of the first etching stop layer has high consistency. In addition, carbon in the first etching stop layer is in a semi-Gaussian distribution from top to bottom, and the doping concentration of carbon at the top of the first etching stop layer is high, and the etching rate of the etchant on the bottom of the first etching stop layer is large, so that when etching the first etching stop layer, the first etching stop layer can be more easily etched through, and the problem of the radial cross-sectional area of the hole gradually decreasing with the increase of the depth of the silicon nitride etching stop layer can be solved.

[0051] In an example, referring to Figure 8 The semiconductor device described above further includes a second etching stop layer 3 formed on the first etching stop layer 2, and the etching resistance of the second etching stop layer 3 is greater than that of the top of the first etching stop layer 2. The lower electrode 61 penetrates the first etching stop layer 2 and the second etching stop layer 3.

[0052] Specifically, the doping concentration of carbon in the first etching stop layer affects the etching rate of the etchant on the first etching stop layer, i.e., the etching resistance of the first etching stop layer. The etching resistance of the second etching stop layer is greater than that of the top of the first etching stop layer, so the material of the second etching stop layer can be set according to the doping concentration of carbon in the top of the first etching stop layer and the material of the film layer above the second etching stop layer. For example, the second etching stop layer can be a silicon nitride layer. Alternatively, the second etching stop layer can also be a silicon carbon nitride layer, and the doping concentration of carbon in the second etching stop layer is less than the doping concentration of carbon in the topmost silicon carbon nitride sub-layer. In addition, the thickness of the second etching stop layer can be set according to actual needs, as long as it can be applied to the semiconductor device provided in the embodiments of the present application.

[0053] In actual application, as described above, the first etching stop layer doped with carbon is more easily etched, and the higher the doping concentration of carbon, the greater the etching rate of the etchant on the first etching stop layer. The etching resistance of the first etching stop layer is opposite to the change trend of the etching rate of the etchant on the first etching stop layer. When the doping concentration of carbon in the top of the first etching stop layer is not low enough to make the etching resistance of the top of the first etching stop layer not high enough, a second etching stop layer can be formed on the first etching stop layer to prevent the film layer above the first etching stop layer from being etched and then stopping on the first etching stop layer, ensuring that the shapes of the holes opened in different regions of the second etching stop layer and the first etching stop layer have high consistency. It should be understood that when the doping concentration of carbon in the top of the first etching stop layer is low enough, the second etching stop layer described above can also not be formed.

[0054] The embodiments of the present application also provide a manufacturing method of a semiconductor device. Hereinafter, the manufacturing process will be described according to the cross-sectional view of the operation shown in the drawings. Specifically, the manufacturing method of the semiconductor device comprises the following steps. Figures 2 to 8

[0055] First, a substrate is provided. Specifically, the specific structure of the substrate can refer to the foregoing, which will not be described here.

[0056] Referring to Figure 2 A first etching stop layer 2 doped with carbon is formed on the substrate 1. The doping concentration of carbon in the first etching stop layer 2 is in a semi-Gaussian distribution from top to bottom, and the doping concentration of carbon at the bottom of the first etching stop layer 2 is greater than that at the top of the first etching stop layer 2.

[0057] ​Specifically, the material, thickness, carbon doping concentration range in the first etching stop layer, and the variation of carbon doping concentration at different heights of the first etching stop layer can refer to the foregoing. For example, the first etching stop layer can include a plurality of silicon carbon nitride sub-layers stacked on the substrate. The carbon doping concentration in the plurality of silicon carbon nitride sub-layers from top to bottom is a semi-Gaussian distribution.

[0058] For example, when the first etching stop layer includes a plurality of silicon carbon nitride sub-layers stacked on the substrate, an atomic layer deposition process can be used to form the first etching stop layer on the substrate. Specifically, dichlorosilane, ammonia, and a carbon source gas can be used as a gas source to form the first etching stop layer on the substrate by using the atomic layer deposition process. The carbon source gas can be propane, ethane, or other hydrocarbons. In order to form silicon carbon nitride sub-layers with different carbon doping concentrations at different heights, the flow rate of the carbon source gas can be adjusted accordingly as the height increases.

[0059] Alternatively, a silicon nitride layer can be first formed on the substrate by a process such as chemical vapor deposition, and the thickness of the silicon nitride layer is equal to the total thickness of the plurality of silicon carbon nitride sub-layers. Then, carbon is implanted into the silicon nitride layer by ion implantation process. The first etching stop layer with different carbon doping concentrations at different heights can be obtained by adjusting the dose and energy of ion implantation.

[0060] In an example, referring to Figure 3 When the carbon doping concentration at the top of the first etching stop layer 2 is not low enough, a second etching stop layer 3 can be formed on the first etching stop layer 2 after the first etching stop layer 2 is formed on the substrate 1, and the etching resistance of the second etching stop layer 3 is greater than that of the top of the first etching stop layer 2.

[0061] For example, the second etching stop layer can be formed on the first etching stop layer by a process such as chemical vapor deposition. Specifically, the material and thickness of the second etching stop layer can refer to the foregoing.

[0062] It should be noted that when the carbon doping concentration at the top of the first etching stop layer is low enough, and the etching resistance of the top of the first etching stop layer is high enough, the second etching stop layer described above can not be formed.

[0063] Referring to Figures 4 to 8 When the second etching stop layer 3 is formed, a capacitor 6 can be formed on the second etching stop layer 3, and the capacitor 6 includes a lower electrode 61, an upper electrode 63, and a dielectric layer 62 between the lower electrode 61 and the upper electrode 63. The lower electrode 61 penetrates the first etching stop layer 2 and the second etching stop layer 3.

[0064] For example, referring to Figure 4At least one layer of stack 4 can be formed on the second etching stop layer 3 by physical vapor deposition or chemical vapor deposition process, and the stack 4 includes a molding layer 41 and a support layer 42 on the molding layer 41. Specifically, the lower electrode 61 will be formed in the hole opened in the stack 4 later, and the etched part of the support layer 42 surrounds the outer periphery of the lower electrode 61, which can provide support for the lower electrode 61 to prevent the lower electrode 61 from collapsing, so the thickness and number of layers of the stack 4 can be set according to the height of the lower electrode 61 and the position of the lower electrode 61 that needs to be supported. For example, two layers of stack 4 can be formed on the second etching stop layer 3. In this case, the etched parts of the two layers of support layer 42 can surround the outer periphery of the top and middle of the lower electrode 61, respectively, to provide support for the top and middle of the lower electrode 61.

[0065] In addition, the materials of the molding layer and the support layer can be set according to the actual application scenario. The materials contained in the molding layer have a certain etching selectivity ratio with the materials contained in the support layer, the second etching stop layer and the first etching stop layer. For example, the molding layer can be a silicon dioxide layer. The second etching stop layer and the support layer are silicon nitride layers. The first etching stop layer is a silicon carbon nitride layer.

[0066] Referring to Figure 4 and Figure 5 , a pattern hole structure 5 is formed which penetrates the at least one layer of stack 4, the second etching stop layer 3 and the first etching stop layer 2 in sequence.

[0067] For example, referring to Figure 4 , two layers of stack 4 are formed on the second etching stop layer 3, and a mask pattern can be formed on the uppermost layer of stack 4. The area covered by the mask pattern is the area where the pattern hole structure 5 will not be formed later. Referring to Figure 5 , under the mask effect of the mask pattern, the two layers of stack 4, the second etching stop layer 3 and the first etching stop layer 2 are etched from top to bottom by wet etching or dry etching process to form the pattern hole structure 5. Specifically, the number of holes, the size of the holes and the arrangement of the holes when the number of holes is multiple in the pattern hole structure 5 can be set according to the number of capacitors 6 formed on the substrate 1, the size of the lower electrode 61 included in the capacitor 6, and the arrangement of the capacitors 6.

[0068] Referring to Figure 6 , the lower electrode 61 is formed which covers the inner wall of the pattern hole structure 5.

[0069] For example, a layer of conductive material can be formed on the stack and the inner wall of the patterned hole structure by physical vapor deposition or chemical vapor deposition. Then, the portion of the layer of conductive material on the stack is removed by chemical mechanical polishing to obtain the lower electrode. The material of the lower electrode can be the same as described above.

[0070] Referring to Figure 7 The molding layer 41 is removed. For example, the molding layer 41 can be removed by a wet etching process to release the lower electrode 61 from the molding layer 41.

[0071] Referring to Figure 8 A dielectric layer 62 is formed on the lower electrode 61, and an upper electrode 63 is formed on the dielectric layer 62.

[0072] For example, a dielectric layer can be formed on the lower electrode by physical vapor deposition or chemical vapor deposition, and an upper electrode can be formed on the dielectric layer. The material of the dielectric layer and the upper electrode and the thickness of the dielectric layer can be the same as described above.

[0073] It should be noted that when the second etching stop layer is not formed on the first etching stop layer, a capacitor is formed on the first etching stop layer, and the lower electrode of the capacitor only penetrates the first etching stop layer. Specifically, at least one stack is formed on the first etching stop layer. Then, a patterned hole structure is formed which only penetrates the at least one stack and the first etching stop layer.

[0074] Compared with the prior art, the semiconductor device manufacturing method provided by the embodiments of the present application has the same advantages as the semiconductor device provided by the above embodiments, which will not be repeated here.

[0075] In the above description, the patterning, etching and other technical details of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions and the like with the desired shape. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0076] The above describes embodiments of the present disclosure. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, include: Base, A first etch stop layer is located on the substrate; the first etch stop layer is doped with carbon; the doping concentration of carbon in the first etch stop layer from top to bottom follows a half-Gaussian distribution, and the carbon doping concentration at the bottom of the first etch stop layer is greater than the carbon doping concentration at the top of the first etch stop layer. A capacitor located on the first etch stop layer, the capacitor including a lower electrode, an upper electrode, and a dielectric layer located between the lower electrode and the upper electrode; the lower electrode penetrates the first etch stop layer; The first etch stop layer includes multiple silicon carbonitride sublayers stacked on the substrate; the carbon doping concentration in the multiple silicon carbonitride sublayers from top to bottom follows a half-Gaussian distribution.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a second etch stop layer formed on the first etch stop layer, the second etch stop layer having greater etch resistance than the top of the first etch stop layer; the lower electrode penetrates through the first etch stop layer and the second etch stop layer.

3. The semiconductor device according to claim 2, characterized in that, The second etch stop layer is a silicon nitride layer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The number of capacitors is multiple; A plurality of landing plugs and an isolation portion for isolating two adjacent landing plugs are formed on the substrate; each landing plug is in contact with the corresponding lower electrode.

5. A method for manufacturing a semiconductor device, characterized in that, include: Provide a base; A first etch stop layer is formed on the substrate; The first etch stop layer is doped with carbon; the carbon doping concentration in the first etch stop layer from top to bottom follows a half-Gaussian distribution, and the carbon doping concentration at the bottom of the first etch stop layer is greater than the carbon doping concentration at the top of the first etch stop layer; the first etch stop layer includes multiple silicon carbonitride sublayers stacked on the substrate; the carbon doping concentration in the multiple silicon carbonitride sublayers from top to bottom follows a half-Gaussian distribution. A capacitor is formed on the first etch stop layer, the capacitor including a lower electrode, an upper electrode, and a dielectric layer located between the lower electrode and the upper electrode; the lower electrode penetrates the first etch stop layer.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The first etch stop layer is formed using atomic layer deposition or ion implantation.

7. The method for manufacturing a semiconductor device according to claim 5, characterized in that, After forming a first etch stop layer on the substrate and before forming a capacitor on the first etch stop layer, the method for manufacturing the semiconductor device further includes: A second etch stop layer is formed on the first etch stop layer, and the etch resistance of the second etch stop layer is greater than that of the top of the first etch stop layer.

8. The method for manufacturing a semiconductor device according to any one of claims 5 to 7, characterized in that, The process of forming a capacitor on the first etch stop layer includes: At least one stack is formed on the first etch stop layer; the stack includes a molding layer and a support layer located on the molding layer; A patterned hole structure is formed that extends through the at least one stacked layer and the first etch stop layer; The lower electrode is formed to cover the inner wall of the patterned hole structure; Remove the molding layer; The dielectric layer is formed on the lower electrode, and the upper electrode is formed on the dielectric layer.

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