A display panel and a display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes: a photosensing unit, which includes a first to a third transistor and a photosensing element; the first transistor is connected between a first signal input terminal and a first node, and its gate is connected to a first control terminal; the second transistor is connected between the first signal input terminal and a second node, and its gate is connected to the first node; the third transistor is connected between the second node and a signal output terminal, and its gate is connected to a second control terminal; the photosensing element is connected between a second signal input terminal and the first node; the first transistor and / or the third transistor is a dual-gate transistor, and the dual-gate transistor includes a first sub-transistor and a second sub-transistor. The first ends of the first sub-transistor and the second sub-transistor are connected and commonly connected to a dual-gate signal input terminal. In the present invention, a fixed potential is connected to the middle part of the channel of the dual-gate transistor to make its potential stable, which can improve the photosensing detection accuracy and the photosensing quality.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the progress and development of technology and the improvement of people's living standards, the use of display panels has penetrated into various electronic products. With the rapid development of display panels, more auxiliary functions have been integrated into the display panels, enriching the functions of electronic products. For example, the fingerprint recognition function is applied in a large number of display panels.

[0003] Currently, the fingerprint recognition function is integrated in the display panel, and fingerprint imaging is performed through light sensing detection. However, the light sensing detection accuracy of the current display panel is not high, and the fingerprint imaging quality needs to be improved. Summary of the Invention

[0004] The present invention provides a display panel and a display device to improve the light sensing detection accuracy.

[0005] According to one aspect of the present invention, a display panel is provided, including: a light sensing area, the light sensing area includes light sensing units, and each light sensing unit includes a first transistor, a second transistor, a third transistor, and a light sensing element;

[0006] The first transistor is connected between a first signal input terminal and a first node, and the gate of the first transistor is connected to a first control terminal;

[0007] The second transistor is connected between the first signal input terminal and a second node, and the gate of the second transistor is connected to the first node;

[0008] The third transistor is connected between the second node and a signal output terminal, and the gate of the third transistor is connected to a second control terminal;

[0009] The light sensing element is connected between a second signal input terminal and the first node;

[0010] The first transistor and / or the third transistor is a double-gate transistor, the double-gate transistor includes a first sub-transistor and a second sub-transistor, and the first ends of the first sub-transistor and the second sub-transistor are connected and commonly connected to a double-gate signal input terminal;

[0011] The working process of the light sensing unit includes a first stage;

[0012] In the first stage, the first signal input terminal provides a first voltage signal, the double-gate signal input terminal provides a fixed voltage signal, and the double-gate transistor is turned on during part of the time period of this stage.

[0013] According to another aspect of the present invention, there is provided a display device including the display panel as described above.

[0014] In the present invention, at least one of the first transistor and the third transistor is a double-gate transistor. The double-gate transistor includes a first sub-transistor and a second sub-transistor. The first ends of the first sub-transistor and the second sub-transistor are connected and commonly connected to the double-gate signal input terminal. In the first stage, the first signal input terminal provides a first voltage signal, the double-gate signal input terminal provides a fixed voltage signal, and the double-gate transistor is turned on during a partial time period of this stage. By connecting a fixed potential to the middle part of the channel of the double-gate transistor, the potential of the middle part of the channel of the double-gate transistor is stabilized, so that the double-gate transistor does not leak electricity to the output terminal in the cut-off state, solving the problem of potential jitter at the output terminal of the double-gate transistor, improving the signal-to-noise ratio, thereby improving the light-sensing detection accuracy, and finally achieving the effect of improving the light-sensing quality.

[0015] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0018] Figure 2 is a circuit diagram of a light-sensing unit provided by an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of a double-gate transistor provided by an embodiment of the present invention;

[0020] Figure 4 is Figure 3 a cross-sectional view taken along A - A';

[0021] Figure 5 is Figure 2 a timing diagram of the illustrated light-sensing unit;

[0022] Figure 6 is a circuit diagram of another light-sensing unit provided by an embodiment of the present invention;

[0023] Figure 7 is Figure 6The timing diagram of the illustrated photosensing unit;

[0024] Figure 8 is the circuit diagram of another photosensing unit provided by an embodiment of the present invention;

[0025] Figure 9 is Figure 8 The timing diagram of the illustrated photosensing unit;

[0026] Figure 10 is the film stack diagram of the transistor in the photosensing unit;

[0027] Figure 11 is Figure 10 The cross-sectional view along B - B';

[0028] Figure 12 is Figure 10 Another cross-sectional view along B - B';

[0029] Figure 13 is another film stack diagram of the transistor in the photosensing unit;

[0030] Figure 14 is Figure 10 Another cross-sectional view along B - B';

[0031] Figure 15 is Figure 10 Another cross-sectional view along B - B';

[0032] Figure 16 is the schematic diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0033] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the description, claims and the above drawings of the present invention are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0035] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention. Figure 2 is a circuit diagram of a light sensing unit provided by an embodiment of the present invention. As Figures 1 to 2 shown, the display panel includes: a light sensing area 10, the light sensing area 10 includes a light sensing unit 11, the light sensing unit 11 includes a first transistor M1, a second transistor M2, a third transistor M3 and a light sensing element 12; the first transistor M1 is connected between a first signal input terminal V1 and a first node N1, and the gate of the first transistor M1 is connected to a first control terminal C1; the second transistor M2 is connected between the first signal input terminal V1 and a second node N2, and the gate of the second transistor M2 is connected to the first node N1; the third transistor M3 is connected between the second node N2 and a signal output terminal OUT, and the gate of the third transistor M3 is connected to a second control terminal C2; the light sensing element 12 is connected between a second signal input terminal V2 and the first node N1; the first transistor M1 and / or the third transistor M3 is a double-gate transistor, the double-gate transistor includes a first sub-transistor and a second sub-transistor, and the first ends of the first sub-transistor and the second sub-transistor are connected and commonly connected to a double-gate signal input terminal; the working process of the light sensing unit 12 includes a first stage; in the first stage, the first signal input terminal V1 provides a first voltage signal, the double-gate signal input terminal provides a fixed voltage signal, and the double-gate transistor is turned on during a part of the time period of this stage.

[0036] Optionally Figure 2 in the first transistor M1 is a double-gate transistor. In this embodiment, Figure 2 is taken as an example to detail the working process, structure, etc. of the light sensing unit 11, but it can be understood that Figure 2The fact that the first transistor M1 shown is a double-gate transistor is only one example of the light-sensing unit of the present invention. In other embodiments of the present invention, the third transistor of the light-sensing unit may be a double-gate transistor, or both the first transistor and the third transistor of the light-sensing unit may be double-gate transistors; the working process and other contents of the light-sensing unit will be briefly described based on different structures of the light-sensing unit in the subsequent corresponding embodiments. The same parts in different embodiments will not be specifically described again, and the same reference numerals can be used for the same structures in different embodiments.

[0037] In this embodiment, the display panel includes a light-sensing area 10, and the light-sensing area 10 includes a plurality of light-sensing units 11. The light-sensing units 11 sense light signals and generate corresponding electrical signals according to the light signals. Exemplarily, the light-sensing area 10 can be selected as a fingerprint recognition area, and the display panel is provided with a fingerprint recognition module. The fingerprint recognition module performs a fingerprint recognition function in the light-sensing area 10. The fingerprint recognition module includes a plurality of light-sensing units 11 and other auxiliary structures, and the fingerprint recognition module performs fingerprint recognition imaging according to the electrical signals output by the light-sensing units 11. A partial area of the display area of the display panel can be reused as the light-sensing area 10. The display area can include one or more light-sensing areas 10. Based on this, the display panel realizes a partial fingerprint recognition function; or, alternatively, the light-sensing area can cover the display area of the display panel. Based on this, the display panel realizes a full-screen fingerprint recognition function.

[0038] In other embodiments, the light-sensing area 10 can also be used to perform other light-sensing functions. Then, a corresponding light-sensing module for performing other light-sensing functions is provided in the display panel. For example, if the light-sensing area is an infrared light-sensing area, an infrared light-sensing module is provided in the display panel to perform an infrared light-sensing function; but it is not limited thereto. In the present invention, the function of the light-sensing area in the display panel is not specifically limited. According to the different functions of the light-sensing area, the structure of the light-sensing module provided in the display panel is also different, and no specific examples and descriptions are given.

[0039] The light sensing unit 11 includes a first transistor M1. The first transistor M1 is connected between a first signal input terminal V1 and a first node N1, and the gate of the first transistor M1 is connected to a first control terminal C1. The voltage signal provided by the first control terminal C1 controls the conduction or cutoff of the first transistor M1. When the first transistor M1 is conducting, the voltage signal provided by the first signal input terminal V1 is transmitted to the first node N1. Optionally, the first transistor M1 is an N-type transistor. Then, when the voltage signal provided by the first control terminal C1 is at a high level, it controls the first transistor M1 to conduct, and when it is at a low level, it controls the first transistor M1 to cutoff. In other embodiments, optionally, the first transistor is a P-type transistor. When the voltage signal provided by the first control terminal is at a low level, it controls the first transistor to conduct, and when it is at a high level, it controls the first transistor to cutoff. During the light sensing phase, the light sensing module in the display panel operates. The light sensing module provides a corresponding fixed voltage signal Vdd to the first signal input terminal V1, and also provides a voltage signal with alternating high and low levels to the first control terminal C1 to make the first transistor M1 conduct or cutoff, thereby adjusting the potential of the first node N1.

[0040] The light sensing unit 11 includes a light sensing element 12. The light sensing element 12 is connected between a second signal input terminal V2 and the first node N1. Optionally, the light sensing element 12 is a photosensitive diode. The first pole of the photosensitive diode 12 is connected to the second signal input terminal V2 and the second pole is connected to the first node N1. Exemplarily, the first pole of the photosensitive diode 12 is the anode and the second pole is the cathode, but it is not limited thereto. During the light sensing phase, the light sensing module in the display panel operates. The light sensing module provides a corresponding fixed voltage signal Vcom to the second signal input terminal V2. The light sensing element 12 senses the light signal and converts the light signal into an electrical signal, so that the potential of the first node N1 can be adjusted according to the light intensity. Obviously, the potential of the first node N1 changes under the influence of the first transistor M1 and the light sensing element 12.

[0041] The light sensing unit 11 includes a second transistor M2. The second transistor M2 is connected between the first signal input terminal V1 and a second node N2, and the gate of the second transistor M2 is connected to the first node N1. The potential of the first node N1 controls the conduction or cutoff of the second transistor M2. When the second transistor M2 is conducting, the voltage signal provided by the first signal input terminal V1 is transmitted to the potential of the second node N2. Optionally, the second transistor M2 is an N-type transistor. Then, when the potential of the first node N1 is at a high level, it controls the second transistor M2 to conduct, and when it is at a low level, it controls the second transistor M2 to cutoff. In other embodiments, optionally, the second transistor is a P-type transistor. When the potential of the first node is at a low level, it controls the second transistor to conduct, and when it is at a high level, it controls the second transistor to cutoff. During the light sensing phase, the light sensing module in the display panel operates. The light sensing module provides a corresponding fixed voltage signal Vdd to the first signal input terminal V1. The second transistor M2 conducts or cutoff under the control of the first node N1, thereby adjusting the potential of the second node N2.

[0042] The light sensing unit 11 includes a third transistor M3. The third transistor M3 is connected between the second node N2 and the signal output terminal OUT. The gate of the third transistor M3 is connected to the second control terminal C2. The voltage signal provided by the second control terminal C2 controls the conduction or cutoff of the third transistor M3. When the third transistor M3 is conducting, the potential of the second node N2 is transmitted to the signal output terminal OUT. Optionally, the third transistor M3 is an N-type transistor. Then, when the voltage signal provided by the second control terminal C2 is at a high level, it controls the third transistor M3 to conduct, and when it is at a low level, it controls the third transistor M3 to cutoff. In other embodiments, optionally, the third transistor is a P-type transistor. When the voltage signal provided by the second control terminal is at a low level, it controls the third transistor to conduct, and when it is at a high level, it controls the third transistor to cutoff. During the light sensing phase, the light sensing module in the display panel operates. The light sensing module provides an alternating high and low voltage signal to the second control terminal C2 to turn the third transistor M3 on or off, thereby controlling the potential of the signal output terminal OUT.

[0043] During the light sensing phase of the display panel, the light sensing unit 11 operates. The operation process of the light sensing unit 11 at least includes a reset phase and a first reading phase. In the reset phase, the first control terminal C1 controls the first transistor M1 to turn on. The fixed voltage signal Vdd provided by the first signal input terminal V1 is transmitted to the first node N1 through the first transistor M1, resetting the potential of the first node N1. During the first reading period, the first control terminal C1 controls the first transistor M1 to cutoff, and the second control terminal C2 controls the third transistor M3 to turn on. The photosensitive element 12 generates a leakage current when illuminated, causing the potential of the first node N1 to gradually decrease. Under the control of the first node N1, the second transistor M2 operates in the linear region and its leakage current magnitude is proportional to the potential of the first node N1. Then, the fixed voltage signal Vdd provided by the first signal input terminal V1 flows through the second transistor M2 and the third transistor M3 to the signal output terminal OUT. The light sensing module reads the potential of the signal output terminal OUT of each light sensing unit 11 during the light sensing phase for fingerprint recognition imaging. The potential of the first node N1 determines the on / off state of the second transistor M2, and the conduction degree of the second transistor M2 determines the potential of the signal output terminal OUT.

[0044] The first transistor M1 and / or the third transistor M3 is a double-gate transistor. The double-gate transistor has a small leakage current, which can reduce the interference to the output signal of the light sensing unit 11 and improve the light sensing detection accuracy. In this embodiment, it is optional that all the transistors in the light sensing unit 11 are NMOS.

[0045] Ideally, there is no leakage current in a dual-gate transistor when it is in the cut-off state. However, the gate of the dual-gate transistor in the photosensing unit 11 is connected to a stable potential in the cut-off state to ensure that the dual-gate transistor is in the cut-off state. This will result in a large parasitic capacitance between the gate and the middle part of the channel in the dual-gate transistor. Moreover, the potential of the middle part of the channel in the dual-gate transistor is unstable, leading to additional leakage current, causing the potential at the output end of the dual-gate transistor to jitter, generating noise, and further reducing the signal-to-noise ratio, thus affecting the photosensing detection accuracy. As Figure 2 shown, taking the first transistor M1 as a dual-gate transistor as an example, the first control terminal C1 provides a stable potential to ensure that the dual-gate transistor M1 is cut off. Then, there is a large parasitic capacitance between the gate of the dual-gate transistor M1 and the point P in the middle part of the channel. If the potential of the point P in the middle part of the channel is unstable, it will cause slow leakage current from the point P in the middle part of the channel to the output end of the dual-gate transistor, i.e., the first node N1, making the potential of the first node N1 jitter.

[0046] Figure 3 FIG. is a schematic diagram of a dual-gate transistor provided by an embodiment of the present invention. Figure 4 is Figure 3 a cross-sectional view taken along A-A'. As Figure 3 and Figure 4 shown, the dual-gate transistor 21 includes an active layer 22 located on a substrate 20. The active layer 22 includes two ends and a middle part located between the two ends. The two ends of the active layer 22 are used to form source-drain regions and are respectively connected to a source electrode 23 and a drain electrode 24. The middle part of the active layer 22 is used to form a channel region. The dual-gate transistor 21 further includes a first gate 25 and a second gate 26. Optionally, in the direction Z perpendicular to the surface of the active layer 22, the first gate 25 and the second gate 26 do not overlap, and the first gate 25 and the second gate 26 are located on the same side of the middle part of the active layer 22. In the direction Z perpendicular to the surface of the active layer 22, the projection of the first gate 25 on the middle part of the active layer 22 can be defined as the first channel region, and the projection of the second gate 26 on the middle part of the active layer 22 can be defined as the second channel region. Then, in the middle part of the active layer 22, the active layer region located between the first channel region and the second channel region can be defined as the middle part 27 of the channel of the dual-gate transistor 21. Based on this, Figure 2 the point P in the middle part of the channel of the dual-gate transistor M1 in fact corresponds to Figure 3 or Figure 4 the middle part 27 of the channel of the dual-gate transistor 21 in

[0047] In this embodiment, taking the first transistor M1 as a dual-gate transistor as an example, in combination with Figure 2As shown, the double-gate transistor M1 includes a first sub-transistor M11 and a second sub-transistor M12. The first ends of the first sub-transistor M11 and the second sub-transistor M12 are connected and commonly connected to the double-gate signal input terminal VA. The working process of the photosensing unit 12 includes a first stage. In the first stage, the first signal input terminal V1 provides a first voltage signal, the double-gate signal input terminal VA provides a fixed voltage signal, and the double-gate transistor M1 is turned on during a partial time period of the first stage. Optionally, the fixed voltage signal is less than the first voltage signal. Then the fixed voltage signal is connected to the middle part P of the channel of the double-gate transistor M1. When the double-gate transistor M1 is turned on, the double-gate signal input terminal VA providing the fixed voltage signal to the point P does not affect the normal operation of the double-gate transistor M1. When the double-gate transistor M1 is turned off, the double-gate signal input terminal VA providing the fixed voltage signal to the point P prevents the point P from leaking current to the output terminal, i.e., the first node N1.

[0048] During the first stage, when the double-gate transistor M1 is turned on, the first signal input terminal V1 provides a first voltage signal Vdd, and the double-gate signal input terminal VA provides a fixed voltage signal. At this time, the potential of the output terminal of the double-gate transistor M1, i.e., the first node N1, is affected by Vdd. The fixed voltage signal provided by the double-gate signal input terminal VA does not affect the potential of the output terminal of the double-gate transistor M1, i.e., the first node N1, and does not affect the on / off state of the double-gate transistor M1.

[0049] During the first stage, when the double-gate transistor M1 is turned off, the gate of the double-gate transistor M1 is at a stable potential. The fixed voltage signal provided by the double-gate signal input terminal VA is connected to the middle part P of the channel of the double-gate transistor M1 to stabilize the potential of the middle part P of the channel of the double-gate transistor M1. Then the parasitic capacitance between the gate of the double-gate transistor M1 and the middle part P of the channel does not affect the potential of the middle part P of the channel. Based on this, the double-gate transistor M1 does not leak current to the output terminal, i.e., the first node N1, in the off state, solving the problem of potential jitter at the output terminal of the double-gate transistor M1, i.e., the first node N1. In this embodiment, the first transistor M1 is taken as an example of a double-gate transistor. In subsequent embodiments, the working process of the photosensing unit with the third transistor being a double-gate transistor will also be described, which will not be elaborated here specifically.

[0050] In the present invention, at least one of the first transistor and the third transistor is a double-gate transistor. The double-gate transistor includes a first sub-transistor and a second sub-transistor. The first ends of the first sub-transistor and the second sub-transistor are connected and commonly connected to the double-gate signal input terminal. In the first stage, the first signal input terminal provides a first voltage signal, the double-gate signal input terminal provides a fixed voltage signal, and the double-gate transistor is turned on during a partial time period of this stage. By connecting a fixed potential to the middle part of the channel of the double-gate transistor, the potential of the middle part of the channel of the double-gate transistor is stabilized, so that the double-gate transistor will not leak electricity to the output terminal in the cut-off state, solving the problem of potential jitter at the output terminal of the double-gate transistor, improving the signal-to-noise ratio, thereby improving the light-sensing detection accuracy, and finally achieving the effect of improving the light-sensing quality.

[0051] Optionally, the first transistor is a double-gate transistor. Among them, the second end of the first sub-transistor is connected to the first signal input terminal, and the first end of the first sub-transistor is connected to the first double-gate signal input terminal. In the first stage, the first double-gate signal input terminal provides a first fixed voltage signal.

[0052] As Figure 2 shown, the first transistor M1 is a double-gate transistor, so the double-gate transistor in this embodiment can be marked as M1; the first double-gate signal input terminal is VA, and the first double-gate signal input terminal VA provides a first fixed voltage signal. In this embodiment, the double-gate transistor M1 includes a first sub-transistor M11 and a second sub-transistor M12. The first ends of the first sub-transistor M11 and the second sub-transistor M12 are connected and commonly connected to the first double-gate signal input terminal VA; the working process of the light-sensing unit 12 includes a first stage. In the first stage, the first signal input terminal V1 provides a first voltage signal, the first double-gate signal input terminal VA provides a first fixed voltage signal, and the double-gate transistor M1 is turned on during a partial time period of this first stage. The connection point of the first ends of the first sub-transistor M11 and the second sub-transistor M12 is point P, and this point P is the middle part of the channel of the double-gate transistor M1; the second end of the first sub-transistor M11 is connected to the first signal input terminal V1, and the gate of the first sub-transistor M11 is connected to the first control terminal C1; the second end of the second sub-transistor M12 is connected to the first node N1, and the gate of the second sub-transistor M12 is connected to the first control terminal C1. The voltage signal provided by the first control terminal C1 controls the first sub-transistor M11 and the second sub-transistor M12 to conduct or turn off simultaneously. Optionally, each transistor in the light-sensing unit 11 is an NMOS, but it is not limited thereto.

[0053] The optional first fixed voltage signal is equal to the theoretical voltage at the first end of the first sub-transistor when the first transistor operates stably. After the circuit design of the light sensing unit 11 is completed, the electrical parameters of each component are determined. For example, electrical parameters such as the aspect ratio of each transistor are determined. Then, according to the equivalent circuit of the light sensing unit 11, the theoretical voltage Vp at point P in the middle of the channel of the first transistor M1 when it operates stably can be calculated. In an ideal state, point P of the first transistor M1 should be stable at this theoretical voltage Vp in the cut-off state. However, in reality, point P of the double-gate transistor M1 is floating in the cut-off state and the potential is unstable, resulting in leakage of the double-gate transistor M1 and affecting the potential of the output end of the double-gate transistor M1, that is, the first node N1. Based on this, the first fixed voltage signal provided by the first double-gate signal input terminal VA is designed to be the theoretical voltage Vp, so that point P of the first transistor M1 is stable at the theoretical voltage Vp in the cut-off state. Then, in reality, point P of the double-gate transistor M1 is stable at the theoretical voltage Vp when it is cut off, and the double-gate transistor M1 does not leak electricity and does not affect the potential of the first node N1. The detection accuracy can be improved.

[0054] Optionally, after the start time of the first stage, the first transistor switches from off to on, and before the end time of the first stage, the first transistor switches from on to off. In this embodiment, in the first stage, the first double-gate signal input terminal VA provides a first fixed voltage signal to stabilize the potential of point P of the double-gate transistor M1. Therefore, in this embodiment, the first stage can be defined as the potential stabilization stage of point P. In a partial time period of the first stage, the double-gate transistor M1 is on. The on stage of the first transistor M1 is the reset stage of the light sensing unit. Therefore, in this embodiment, a partial time period of the potential stabilization stage of point P is multiplexed as the reset stage.

[0055] Specifically, before the double-gate transistor M1 is turned on, the light sensing module first provides a first fixed voltage signal to the first double-gate signal input terminal VA. Then, during the turn-on process of the double-gate transistor M1, the first double-gate signal input terminal VA remains stable and does not jump, and does not affect the electrical signal flowing through point P in the middle of the channel of the double-gate transistor M1, so that the double-gate transistor M1 can operate stably in the on state. For a period of time after the double-gate transistor M1 is cut off, the first double-gate signal input terminal VA remains stable at the first fixed voltage signal, so that the middle part point P of the channel of the double-gate transistor M1 does not leak electricity, avoiding the influence of the leakage of point P on the first node N1.

[0056] Therefore, in this embodiment, it is designed that after the start time of the potential stabilization stage of point P, the first transistor M1 switches from off to on, and before the end time of the potential stabilization stage of point P, the first transistor M1 switches from on to off; that is, a partial time period of the potential stabilization stage of point P is multiplexed as the on stage of the first transistor M1. It can avoid the leakage of point P and thus reduce the influence on the first node N1.

[0057] The working process of the optional photosensing unit includes a second stage; in the second stage, a first voltage signal is provided at the first signal input terminal, the third transistor is turned on, and there is an overlap between the second stage and the first stage. The photosensing unit 11 includes a reading stage, in which the third transistor M3 is turned on during the reading stage, so the reading stage is the second stage. The first transistor M1 should be turned on during part of the reading stage, and the first transistor M1 is turned on during part of the stable potential stage of point P. Therefore, there is an overlap between the second stage and the first stage, that is, there is an overlap between the reading stage and the stable potential stage of point P.

[0058] Optionally, the start time of the second stage is earlier than the start time of the first stage, and the end time of the second stage is later than the end time of the first stage. That is, the start time of the reading stage is earlier than the start time of the stable potential stage of point P, and the end time of the reading stage is later than the end time of the stable potential stage of point P. Specifically, the potential at the signal output terminal OUT should be stable and unchanged when the third transistor M3 is turned off. The potential jump at point P in the middle of the channel of the double-gate transistor M1 may affect the potential stability of the signal output terminal OUT. Based on this, before the third transistor M3 is turned off, when the stable potential stage of point P ends, that is, the first double-gate signal input terminal VA jumps from the first fixed voltage signal to floating, the potential at point P in the middle of the channel will no longer jump after the third transistor M3 is turned off, which can ensure the stability of the potential at the signal output terminal OUT after the third transistor M3 is turned off and improve the detection accuracy. In other embodiments, the double-gate transistor can be an NMOS. Then, during the stable potential stage of point P, the first fixed voltage signal provided by the first double-gate signal input terminal can be a high level. Specifically, before the third transistor is turned off, the first double-gate signal input terminal can jump from a high level to floating or a low level.

[0059] Figure 5 Yes Figure 2 The timing diagram of the shown photosensing unit. As Figure 5 As shown, the working process of the photosensing unit 11 includes a first stage; in the first stage, a first voltage signal Vdd is provided at the first signal input terminal V1, a fixed voltage signal is provided at the double-gate signal input terminal VA, and the double-gate transistor M1 is turned on during part of the first stage. In this embodiment, the first stage is the stable potential stage t20 of point P, the turning-on stage of the double-gate transistor M3 is the reading stage t30, and the turning-on stage of the first transistor M1 is the reset stage t10.

[0060] Specifically, the turn-on period of the double-gate transistor M1 is t10, the turn-on period of the third transistor M3 is t30, and the period when the first double-gate signal input terminal VA provides a stable first fixed voltage signal is t20. It can be understood that during the light-sensing period, the turn-on period t10 of the double-gate transistor M1 is the reset period, the turn-on period t30 of the third transistor M3 is the reading period, and the period t20 when the first double-gate signal input terminal VA provides a stable first fixed voltage signal is the period when the potential at point P is stable. The reading period t30 includes the reset period t10. The turn-on period t31 of the third transistor M3 after the reset period t10 is the first reading period in the reading period t30. A partial time period of the period t20 when the potential at point P is stable is multiplexed as the reset period t10. In this embodiment, the second stage is the reading period t30, the first stage is the period t20 when the potential at point P is stable, and the second stage (t30) and the first stage (t20) overlap.

[0061] In the first stage of this embodiment, that is, the period t20 when the potential at point P is stable, the first signal terminal V1 provides the voltage signal Vdd, and the first double-gate signal input terminal VA provides a stable first fixed voltage signal. A partial time period of the period t20 when the potential at point P is stable is multiplexed as the reset period t10. The period t20 when the potential at point P is stable overlaps with the first reading period t31, and this overlapping period is marked as t11.

[0062] During the reset period t10, the first control terminal C1 provides a stable high-level signal to turn on the first transistor M1. The voltage signal Vdd provided by the first signal terminal V1 resets the first node N1 through the first transistor M1. During the reset period t10, the second control terminal C2 provides a stable high-level signal to turn on the third transistor M3.

[0063] During the overlapping period t11, the second control terminal C2 maintains a stable high-level signal to keep the third transistor M3 in the on state, and the first control terminal C1 provides a stable low-level signal to turn off the first transistor M1. The first double-gate signal input terminal VA provides the first fixed voltage signal to point P of the double-gate transistor M1. At this time, the potential at point P of the turned-off double-gate transistor M1 is stable. The gate of the double-gate transistor M1 is at a stable low potential, which turns off the double-gate transistor M1. The middle part P of the channel of the double-gate transistor M1 is at a stable potential. Then, the parasitic capacitance between the gate and the middle part of the channel of the double-gate transistor M1 will not affect the potential of the middle part of the channel. Based on this, the potential at the middle part P of the channel of the double-gate transistor M1 is stable in the off state and will not leak to the output terminal of the double-gate transistor M1, that is, the first node N1, solving the problem of potential jitter at the output terminal of the double-gate transistor in the off state in the prior art.

[0064] Optionally, the third transistor is a double-gate transistor. Among them, the second end of the first sub-transistor is connected to the second node, and the first end of the first sub-transistor is connected to the second double-gate signal input terminal; in the first stage, the second double-gate signal input terminal provides a second fixed voltage signal.

[0065] Figure 6 It is the circuit diagram of another photosensing unit provided by the embodiment of the present invention. As Figure 6 shown, the third transistor M3 is a double-gate transistor, so the double-gate transistor in this embodiment can be marked as M3; the second double-gate signal input terminal is VB, and the second double-gate signal input terminal VB provides a second fixed voltage signal. In this embodiment, the double-gate transistor M3 includes a first sub-transistor M31 and a second sub-transistor M32. The first end of the first sub-transistor M31 and the first end of the second sub-transistor M32 are connected and commonly connected to the second double-gate signal input terminal VB; the working process of the photosensing unit 11 includes a first stage; in the first stage, the first signal input terminal V1 provides a first voltage signal, the second double-gate signal input terminal VB provides a second fixed voltage signal, and the double-gate transistor M3 is turned on during a part of the time period of the first stage.

[0066] The second control terminal C2 provides a stable low potential to ensure that the double-gate transistor M3 is cut off. Then, there is a large parasitic capacitance between the gate of the double-gate transistor M3 and the middle part Q point of the channel. If the potential of the Q point is unstable, it will cause the Q point to slowly leak electricity to the output end of the double-gate transistor M3, that is, the signal output end OUT, resulting in the potential jitter of the signal output end OUT and affecting the photosensing detection accuracy.

[0067] In this embodiment, the connection point of the first end of the first sub-transistor M31 and the first end of the second sub-transistor M32 is the Q point, and the Q point is the middle part of the channel of the double-gate transistor M3; the second end of the first sub-transistor M31 is connected to the second node N2, and the gate of the first sub-transistor M31 is connected to the second control terminal C2; the second end of the second sub-transistor M32 is connected to the signal output end OUT, and the gate of the second sub-transistor M32 is connected to the second control terminal C2. The voltage signal provided by the second control terminal C2 controls the first sub-transistor M31 and the second sub-transistor M32 to be turned on or off simultaneously. Optionally, each transistor in the photosensing unit 11 is an NMOS, but it is not limited thereto.

[0068] The optional second fixed voltage signal is equal to the theoretical voltage at the first end of the first sub-transistor when the second transistor and the third transistor operate stably. After the circuit design of the light sensing unit 11 is completed, the electrical parameters of each component are determined. For example, the electrical parameters such as the aspect ratio of each transistor are determined. Then, according to the equivalent circuit of the light sensing unit 11, the theoretical voltage VQ at the middle part Q of the channel of the third transistor M3 when it operates stably can be calculated. Ideally, the Q point of the third transistor M3 should be stably at this theoretical voltage VQ in the cut-off state. However, in reality, the Q point of the double-gate transistor M3 is in a floating state when it is cut off, and the potential is unstable, resulting in leakage of the double-gate transistor M3, which affects the potential of the output end of the double-gate transistor M3, that is, the signal output end OUT. Based on this, the second fixed voltage signal provided by the second double-gate signal input terminal VB is designed to be the theoretical voltage VQ, so that the Q point of the third transistor M3 is stably at the theoretical voltage VQ in the cut-off state. Then, in reality, the potential of the Q point of the double-gate transistor M3 is stably at the theoretical voltage VQ when it is cut off, and the double-gate transistor M3 does not leak electricity and does not affect the potential of the signal output end OUT, which can improve the detection accuracy.

[0069] Optionally, the third transistor switches from off to on after the start time of the first stage and switches from on to off before the end time of the first stage. In this embodiment, in the first stage, the second double-gate signal input terminal VB provides a second fixed voltage signal to stabilize the potential of the Q point of the double-gate transistor M3. Therefore, in this embodiment, the first stage can be defined as the Q point potential stabilization stage. The double-gate transistor M3 is on during a partial time period of the first stage, and the on stage of the third transistor M3 is the reading stage of the light sensing unit. Therefore, a partial time period of the Q point potential stabilization stage in this embodiment is multiplexed as the reading stage.

[0070] Specifically, before the double-gate transistor M3 is turned on, the light sensing module first provides a second fixed voltage signal to the second double-gate signal input terminal VB. Then, during the turn-on process of the double-gate transistor M3, the second double-gate signal input terminal VB remains stable and does not jump, which will not affect the electrical signal flowing through the middle part Q of the channel of the double-gate transistor M3, enabling the double-gate transistor M3 to operate stably in the on state. For a period of time after the double-gate transistor M3 is turned off, the second double-gate signal input terminal VB remains stable at the second fixed voltage signal, so that the middle part Q of the channel of the double-gate transistor M3 does not leak electricity, avoiding the influence of the leakage of the Q point on the signal output end OUT.

[0071] Therefore, in this embodiment, it is designed that the third transistor M3 is switched from off to on after the start time of the Q-point potential stabilization stage, and the third transistor M3 is switched from on to off before the end time of the Q-point potential stabilization stage; that is, a partial time period of the Q-point potential stabilization stage is multiplexed as the on stage of the third transistor M3. This can avoid the leakage of the Q point, thereby reducing the influence on the signal output terminal OUT.

[0072] The working process of the optional photosensing unit includes a third stage; in the third stage, the first transistor is turned on, and a partial time period of the first stage is multiplexed as the third stage. The photosensing unit 11 includes a reset stage, in which the first transistor M1 is turned on during the reset stage. Therefore, the reset stage is the third stage, and a partial time period of the first stage is multiplexed as the third stage, that is, a partial time period of the Q-point potential stabilization stage is multiplexed as the reset stage.

[0073] Optionally, the start time of the third stage is later than the turn-on time of the third transistor, and the end time of the third stage is earlier than the turn-off time of the third transistor. The photosensing unit 11 further includes a reading stage, in which the third transistor M3 is turned on during the reading stage. And during a partial time period of the reading stage, the first transistor M1 should be turned on. Therefore, a partial time period of the reading stage is multiplexed as the reset stage, that is, the start time of the reset stage is later than the start time of the reading stage, and the end time of the reset stage is earlier than the end time of the reading stage.

[0074] Figure 7 Yes Figure 6 The timing diagram of the shown photosensing unit. As Figure 7 shown, the working process of the photosensing unit 11 includes a first stage; in the first stage, the first signal input terminal V1 provides a first voltage signal Vdd, the dual-gate signal input terminal VB provides a fixed voltage signal, and the dual-gate transistor M3 is turned on during a partial time period of this first stage. In this embodiment, the first stage is the Q-point potential stabilization stage t40, the turn-on stage of the dual-gate transistor M3 is the reading stage t30, and the turn-on stage of the first transistor M1 is the reset stage t10.

[0075] Specifically, the turn-on period of the first transistor M1 is t10, the turn-on period of the double-gate transistor M3 is t30, and the period when the second double-gate signal input terminal VB provides a stable second fixed voltage signal is t40. It can be understood that during the light sensing period, the turn-on period t10 of the first transistor M1 is the reset period, the turn-on period t30 of the double-gate transistor M3 is the reading period, the period t40 when the second double-gate signal input terminal VB provides a stable second fixed voltage signal is the Q-point potential stable period, and the period when the double-gate transistor M3 is in the cut-off state after the reading period t30 is the exposure period t32. The reading period t30 includes the reset period t10, and a partial time period of the Q-point potential stable period t40 is multiplexed as the reading period t30. In this embodiment, the third period is the reset period t10, the first period is the Q-point potential stable period t40, and the third period (t10) is located within the first period (t40).

[0076] During the Q-point potential stable period t40, the first signal terminal V1 provides a fixed voltage signal Vdd, and the second double-gate signal input terminal VB provides a second fixed voltage signal. The Q-point potential stable period t40 includes the reading period t30 and the reset period t10.

[0077] During the reset period t10, the first control terminal C1 provides a stable high-level signal to turn on the first transistor M1. The voltage signal Vdd provided by the first signal terminal V1 resets the first node N1 through the first transistor M1. During the reset period t10, the second control terminal C2 provides a stable high-level signal to turn on the third transistor M3.

[0078] During the reading period t30, the second control terminal C2 provides a stable high-level signal to turn on the double-gate transistor M3. The fixed voltage signal Vdd provided by the first signal terminal V1 flows through the second transistor M2 and the double-gate transistor M3, and the light sensing module reads the signal of the light sensing unit 11 through the signal output terminal OUT.

[0079] During the exposure period t32, the second control terminal C2 provides a stable low-level signal to turn off the double-gate transistor M3, and the first control terminal C1 provides a stable low-level signal to turn off the first transistor M1. The second double-gate signal input terminal VB provides a second fixed voltage signal to the Q point in the middle of the channel of the double-gate transistor M3, and at this time, the Q-point potential of the double-gate transistor M3 is stable. The gate of the double-gate transistor M3 is at a stable low potential to turn off the double-gate transistor M3, and the Q point in the middle of the channel of the double-gate transistor M3 is at a stable potential, so the parasitic capacitance between the gate and the middle of the channel of the double-gate transistor M3 will not affect the potential of the middle of the channel. Based on this, the Q-point potential in the middle of the channel of the double-gate transistor M3 is stable in the cut-off state and will not leak to the output terminal of the double-gate transistor, that is, the signal output terminal OUT, solving the problem of potential jitter at the output terminal of the double-gate transistor in the cut-off state in the prior art.

[0080] Figure 8 This is the circuit diagram of another photosensing unit provided by an embodiment of the present invention. As Figure 8 shown, it is optional that the first transistor M1 and the third transistor M3 are both dual-gate transistors. The first ends of the first sub-transistor M11 and the second sub-transistor M12 in the first transistor M1 are connected and commonly connected to the first dual-gate signal input terminal VA. The first ends of the first sub-transistor M31 and the second sub-transistor M32 in the third transistor M3 are connected and commonly connected to the second dual-gate signal input terminal VB. In other embodiments, it is also optional that the first transistor and the third transistor are both dual-gate transistors, but only one of the dual-gate transistors is connected to the dual-gate signal input terminal.

[0081] Figure 9 is Figure 8 the timing diagram of the shown photosensing unit. As Figure 9 shown, the working process of the photosensing unit 11 includes a reset stage t10, a P-point potential stabilization stage t20, a Q-point potential stabilization stage t40, and a reading stage t30.

[0082] In the reset stage t10, the first control terminal C1 is at a high level to turn on the first transistor M1, and the second control terminal C2 is at a high level to turn on the third transistor M3. The first dual-gate signal input terminal VA provides a first fixed voltage signal, and the second dual-gate signal input terminal VB provides a second fixed voltage signal. The first node N1 in the photosensing unit 11 is reset.

[0083] In the P-point potential stabilization stage t20, the first dual-gate signal input terminal VA provides a first fixed voltage signal. A partial time period of the P-point potential stabilization stage t20 is multiplexed as the reset stage t10. In the P-point potential stabilization stage t20, when the first transistor M1 is turned off, since the first dual-gate signal input terminal VA can stabilize the potential of the middle part P of the channel of the first transistor M1, the leakage of the P point can be eliminated, and the influence of the P-point leakage on the first node N1 can be reduced.

[0084] In the reading stage t30, the second control terminal C2 is at a high level to turn on the third transistor M3. The second dual-gate signal input terminal VB provides a second fixed voltage signal. A partial time period of the reading stage t30 is multiplexed as the reset stage t10.

[0085] In the Q-point potential stabilization stage t40, the second dual-gate signal input terminal VB provides a second fixed voltage signal. A partial time period of the Q-point potential stabilization stage t40 is multiplexed as the reading stage t30. In the Q-point potential stabilization stage t40, when the third transistor M3 is turned off, since the second dual-gate signal input terminal VB can stabilize the potential of the middle part Q of the channel of the third transistor M3, the leakage of the Q point can be eliminated, and the influence of the Q-point leakage on the signal output terminal OUT can be reduced.

[0086] The optional display panel includes a substrate, a dual-gate transistor, and a first connection electrode. The dual-gate transistor includes a first active layer. The dual-gate signal input terminal is electrically connected to the first connection electrode, and the first connection electrode is electrically connected to the middle portion of the first active layer. The first connection electrode is located between the substrate and the first active layer, or the first connection electrode is located on the side of the first active layer away from the substrate, or the first connection electrode is on the same layer as the first active layer.

[0087] Figure 10 It is a film stack diagram of the transistor in the photosensing unit. As Figure 10 shown, the photosensing unit includes a first transistor M1, a second transistor M2, and a third transistor M3. 102a is the active layer, 104 is the source-drain functional layer, and 106 is the gate functional layer.

[0088] Figure 11 It is Figure 10 a cross-sectional view along B-B'. As Figure 11 shown, the display panel includes a substrate 100, a dual-gate transistor 102, and a first connection electrode 103. The dual-gate transistor 102 includes a first active layer 102a. The dual-gate signal input terminal is electrically connected to the first connection electrode 103, and the first connection electrode 103 is electrically connected to the middle portion of the first active layer 102a. Optionally, the first connection electrode 103 is located between the substrate 100 and the first active layer 102a. The display panel includes a photosensing unit, and the photosensing unit includes a first transistor M1, a second transistor M2, and a third transistor M3. Optionally, the first transistor M1 is a dual-gate transistor, but not limited thereto. The first dual-gate signal input terminal VA is electrically connected to the first connection electrode 103, and the first connection electrode 103 is electrically connected to the middle portion of the channel of the first active layer 102a of the first transistor M1. Then, the photosensing module provides a first fixed voltage signal to the first connection electrode 103, which can stabilize the potential of point P in the middle of the channel when the first transistor M1 is turned off and reduce leakage.

[0089] Figure 12 It is Figure 10 another cross-sectional view along B-B'. As Figure 12 shown, optionally, the first connection electrode 103 is located on the side of the first active layer 102a away from the substrate 100. For example, the first connection electrode 103 can be on the same layer as the source-drain functional layer 104 or the gate functional layer, but not limited thereto.

[0090] Figure 13 It is another film stack diagram of the transistor in the photosensing unit. As Figure 13As shown, the optional first connection electrode 103 is on the same layer as the first active layer 102a. Taking the first transistor M1 and the third transistor M3 as double-gate transistors as an example, the photosensing unit includes the first sub-transistor M11 and the second sub-transistor M12 in the first transistor M1, the second transistor M2, and the first sub-transistor M31 and the second sub-transistor M32 in the third transistor M3. The display panel includes a source-drain functional layer 104, an active layer 105, and a gate functional layer 106. The active layers of the transistors in the photosensing unit are all located in the active layer 105, that is, the first active layer 102a is located in the active layer 105, and the gates of the transistors in the photosensing unit are all located in the gate functional layer 106.

[0091] As Figure 13 shown, the active layers of the first sub-transistor M11 and the second sub-transistor M12 in the first transistor are connected to form a double-gate transistor M1. The other end of the first sub-transistor M11 is connected to the first signal terminal V1, the other end of the second sub-transistor M12 is connected to the first node N1, and the gates of the first sub-transistor M11 and the second sub-transistor M12 are both connected to the first control terminal C1. Combining Figure 3 and Figure 4 it can be known that the active layer region between the projection of the gate of the first sub-transistor M11 on the active layer and the projection of the gate of the second sub-transistor M12 on the active layer is the middle part of the channel of the first transistor.

[0092] The second transistor M2 has a single-gate structure. The gate of the second transistor M2 is connected to the first node N1. One end of the second transistor M2 is connected to the first signal terminal V1, and the other end is connected to the active layer of the third transistor M3.

[0093] The active layers of the first sub-transistor M31 and the second sub-transistor M32 in the third transistor are connected to form a double-gate transistor M3. The active layer of the first sub-transistor M31 is connected to the active layer of the second transistor M2, the other end of the second sub-transistor M32 is connected to the signal output terminal OUT, and the gates of the first sub-transistor M31 and the second sub-transistor M32 are both connected to the second control terminal C2. Optionally, the first connection electrode 103 is on the same layer as the first active layer 102a and is connected to the middle part of the first active layer 102a.

[0094] Optionally, the display panel includes a gate functional layer. The gates of the double-gate transistors are located in the gate functional layer; the first connection electrode is located on the side of the gate functional layer away from the first active layer. Figure 14 is Figure 10 Another cross-sectional view along B-B'. As Figure 14 shown, optionally, the display panel includes a gate functional layer 106. The gates of the double-gate transistors are located in the gate functional layer 106; the first connection electrode 103 is located on the side of the gate functional layer 106 away from the first active layer 102a.

[0095] The optional display panel includes a source-drain functional layer, the source and drain of the double-gate transistor are located in the source-drain functional layer, and the source and drain of the double-gate transistor are electrically connected to the first active layer; the first connection electrode is located on the side of the source-drain functional layer facing away from the first active layer. Figure 15 Yes Figure 10 Another cross-sectional view along B-B', as Figure 15 shown, the optional display panel includes a source-drain functional layer 104, the source and drain of the double-gate transistor are located in the source-drain functional layer 104, and the source and drain of the double-gate transistor are electrically connected to the first active layer 102a; the first connection electrode 103 is located on the side of the source-drain functional layer 104 facing away from the first active layer 102a.

[0096] The optional display panel includes a second connection electrode; the signal output terminal is electrically connected to the second connection electrode. As Figure 15 shown, the optional display panel includes a second connection electrode 107, the signal output terminal OUT is electrically connected to the second connection electrode 107, and the fingerprint recognition module collects signals through the signal output terminal OUT of the light sensing unit and performs fingerprint recognition.

[0097] As Figure 15 shown, the optional first connection electrode 103 and the second connection electrode 107 are on the same layer.

[0098] As shown above, the first connection electrode is connected to the middle part of the first active layer of the double-gate transistor. The first connection electrode can be arranged in various ways. Optionally, the first connection electrode is on the same layer as a metal functional layer originally in the display panel, so the existing metal functional layer in the display panel is reused to make the first connection electrode, without the need to additionally prepare the film layer of the first connection electrode, and the thickness of the display panel is not increased. The double-gate transistor can be the first transistor M1, then the first connection electrode is connected to the first double-gate signal input terminal VA; or, the double-gate transistor can be the third transistor M3, then the first connection electrode is connected to the second double-gate signal input terminal VB.

[0099] The second connection electrode is connected to the signal output terminal of the third transistor. The second connection electrode can be arranged in various ways. Optionally, the second connection electrode is on the same layer as a metal functional layer originally in the display panel, so the existing metal functional layer in the display panel is reused to make the second connection electrode, without the need to additionally prepare the film layer of the second connection electrode, and the thickness of the display panel is not increased.

[0100] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display panel provided in any one of the above embodiments.

[0101] This embodiment is applicable to any display panel integrated with light sensing functions such as fingerprint recognition, for example, an organic light-emitting display panel with fingerprint recognition function, etc. The optional display panel further includes a fingerprint recognition module, and the fingerprint recognition module includes a light sensing unit. However, the type of the display panel is not limited thereto, and the fingerprint recognition function is only one example of the light sensing area and is not limited thereto.

[0102] In an embodiment of the present invention, the display panel includes a light sensing unit. The middle part of the channel of the double-gate transistor of the light sensing unit is connected to a fixed potential, and the fixed potential is greater than 0V and less than the first voltage signal Vdd provided by the first signal terminal. In this way, the influence of the parasitic capacitance on the middle part of the channel of the double-gate transistor can be eliminated, the stability of the output terminal potential of the double-gate transistor is improved, the signal jitter is reduced, and the detection accuracy is improved.

[0103] Figure 16 It is a schematic diagram of a display device provided by an embodiment of the present invention. As Figure 16 shown, the optional display device 1 is a mobile phone. However, in other embodiments, the optional display device may also be other electronic devices such as a tablet computer or a computer.

[0104] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A display panel, characterized in that, Comprising: A light sensing region, the light sensing region including light sensing units, and each light sensing unit including a first transistor, a second transistor, a third transistor, and a light sensing element; The first transistor is connected between a first signal input terminal and a first node, and a gate of the first transistor is connected to a first control terminal; The second transistor is connected between the first signal input terminal and a second node, and a gate of the second transistor is connected to the first node; The third transistor is connected between the second node and a signal output terminal, and a gate of the third transistor is connected to a second control terminal; The light sensing element is connected between a second signal input terminal and the first node; The first transistor and / or the third transistor is a double-gate transistor, the double-gate transistor including a first sub-transistor and a second sub-transistor, and a first end of the first sub-transistor and a first end of the second sub-transistor are connected and commonly connected to a double-gate signal input terminal; The operation process of the light sensing unit includes a first stage; In the first stage, the first signal input terminal provides a first voltage signal, the double-gate signal input terminal provides a fixed voltage signal, and the double-gate transistor is turned on during a partial time period of this stage.

2. The display panel according to claim 1, wherein The fixed voltage signal is less than the first voltage signal.

3. The display panel according to claim 1, wherein The first transistor is the double-gate transistor, wherein a second end of the first sub-transistor is connected to the first signal input terminal, and a first end of the first sub-transistor is connected to a first double-gate signal input terminal; In the first stage, the first double-gate signal input terminal provides a first fixed voltage signal.

4. The display panel according to claim 3, wherein The first fixed voltage signal is equal to the theoretical voltage of the first end of the first sub-transistor when the first transistor operates stably.

5. The display panel according to claim 3, wherein After the start time of the first stage, the first transistor is switched from off to on, and before the end time of the first stage, the first transistor is switched from on to off.

6. The display panel according to claim 3, wherein The operation process of the light sensing unit includes a second stage; In the second stage, the first signal input terminal provides the first voltage signal, the third transistor is turned on, and the second stage overlaps with the first stage.

7. The display panel according to claim 6, wherein The start time of the second stage is earlier than the start time of the first stage, and the end time of the second stage is later than the end time of the first stage.

8. The display panel according to claim 1, characterized in that, The third transistor is the double-gate transistor, wherein a second end of the first sub-transistor is connected to the second node, and a first end of the first sub-transistor is connected to a second double-gate signal input terminal; In the first stage, the second double-gate signal input terminal provides a second fixed voltage signal.

9. The display panel according to claim 8, wherein, The second fixed voltage signal is equal to the theoretical voltage of the first end of the first sub-transistor when the second transistor and the third transistor operate stably.

10. The display panel according to claim 8, wherein, After the start time of the first stage, the third transistor is switched from off to on, and before the end time of the first stage, the third transistor is switched from on to off.

11. The display panel according to claim 8, characterized in that, The operation process of the light sensing unit includes a third stage; In the third stage, the first transistor is turned on, and a partial time period of the first stage is multiplexed as the third stage.

12. The display panel according to claim 11, wherein The start time of the third stage is later than the turn-on time of the third transistor, and the end time of the third stage is earlier than the turn-off time of the third transistor.

13. The display panel according to claim 1, wherein, The display panel includes a substrate substrate, the dual-gate transistor, and a first connection electrode, and the dual-gate transistor includes a first active layer; The dual-gate signal input terminal is electrically connected to the first connection electrode, and the first connection electrode is electrically connected to the middle portion of the first active layer; The first connection electrode is located between the substrate substrate and the first active layer, or the first connection electrode is located on the side of the first active layer away from the substrate substrate, or the first connection electrode is on the same layer as the first active layer.

14. The display panel according to claim 13, wherein The display panel includes a gate functional layer, and the gate of the dual-gate transistor is located in the gate functional layer; The first connection electrode is located on the side of the gate functional layer away from the first active layer.

15. The display panel according to claim 13, wherein The display panel includes a source-drain functional layer, the source and drain of the dual-gate transistor are located in the source-drain functional layer, and the source and drain of the dual-gate transistor are electrically connected to the first active layer; The first connection electrode is located on the side of the source-drain functional layer away from the first active layer.

16. The display panel according to claim 13, wherein The display panel includes a second connection electrode; The signal output terminal is electrically connected to the second connection electrode.

17. The display panel according to claim 16, characterized in that, The first connection electrode and the second connection electrode are on the same layer.

18. The display panel according to claim 1, wherein The display panel further includes a fingerprint recognition module, and the fingerprint recognition module includes the light sensing unit.

19. A display device, characterized in that, A display panel according to any one of claims 1-18.

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