Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present invention provide a semiconductor device, including a source region, a drain region, and a channel region, located in a substrate, wherein the channel region is located between the source region and the drain region; a pair of depletion gates, spaced apart from each other, wherein the pair of depletion gates both overlap with the channel region, and a quantum dot qubit region is defined between the channel region and the pair of depletion gates; an accumulation gate, located above the pair of depletion gates and spanning the pair of depletion gates; and a superconducting resonator, laterally adjacent to the quantum dot qubit region. Embodiments of the present invention also provide a method of manufacturing a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of manufacturing the same. Background Art

[0002] Quantum computing refers to the field of research related to computing systems that use quantum mechanical phenomena to manipulate data. Several milestones have been achieved on the roadmap for building a scalable, silicon-based quantum computer. Quantum computing may involve initializing the states of N qubits (quantum bits), creating controlled entanglement between them, allowing these states to evolve, and reading out the states of the qubits after the evolution. A qubit is a system with two degenerate (i.e., equal-energy) quantum states, and the probability of finding it in any state is non-zero. Thus, N qubits can define an initial state, which is a combination of 2 N classical states. Summary of the Invention

[0003] Some embodiments of the present invention provide a semiconductor device, including a source region, a drain region, and a channel region, located in a substrate, wherein the channel region is located between the source region and the drain region; a pair of depletion gates, spaced apart from each other, wherein the pair of depletion gates both overlap the channel region, and a quantum dot qubit region is defined in the channel region and between the pair of depletion gates; a cumulative gate, located above the pair of depletion gates and spanning the pair of depletion gates; and a superconducting resonator, laterally adjacent to the quantum dot qubit region.

[0004] Some other embodiments of the present invention provide a semiconductor device, including: a source region, a drain region, and a channel region, located in a substrate, wherein the source region and the drain region are located on opposite sides of the channel region; a conductive resonator, located above the substrate and having a linear portion adjacent to the channel region in a top view; a pair of depletion gates, located above the channel region and extending in a direction not parallel to the linear portion of the conductive resonator in a top view; wherein the pair of depletion gates define a quantum dot qubit region in the channel region; and a cumulative gate, covering the pair of depletion gates and the quantum dot qubit region, wherein the cumulative gate is made of a superconducting material.

[0005] Some further embodiments of the present invention provide a method of manufacturing a semiconductor device, including: forming a channel region, a source region, and a drain region in a substrate; depositing a superconducting layer above the substrate to cover the channel region, the source region, and the drain region; patterning the superconducting layer to form a pair of depletion gates spanning the channel region; and forming a cumulative gate above the pair of depletion gates and the cumulative gate covering the channel region.

[0006] Some other embodiments of the present invention provide a superconducting qubit device and a method of manufacturing the same. Brief Description of the Drawings

[0007] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, it should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, for the sake of clear discussion, the dimensions of the various components may be increased or decreased arbitrarily.

[0008] Figure 1A is a top view of an electronic device according to some embodiments of the present invention;

[0009] Figure 1B is Figure 1A a cross-sectional view of the electronic device along line B-B;

[0010] Figure 1C is Figure 1A a cross-sectional view of the electronic device along line C-C;

[0011] Figures 2A to 8C shows a top view and a cross-sectional view of an intermediate stage in the formation of an electronic device according to some embodiments of the present invention;

[0012] Figure 9A is a top view of an electronic device according to some embodiments of the present invention;

[0013] Figure 9B is a cross-sectional view of the electronic device along line B-B;

[0014] Figure 9C is a cross-sectional view of the electronic device along line C-C;

[0015] Figures 10A to 14C shows a top view and a cross-sectional view of an intermediate stage in the formation of an electronic device according to some embodiments of the present invention;

[0016] Figure 15A is a top view of an electronic device according to some embodiments of the present invention;

[0017] Figure 15B is a cross-sectional view of the electronic device along line B-B;

[0018] Figure 15C is a cross-sectional view of the electronic device along line C-C;

[0019] Figure 16 shows the relationship between the simulated effective surface resistance and frequency of different materials according to some embodiments of the present invention. Detailed Description

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming the first component above or on the second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to easily describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0022] As used herein, "about", "approximately", "approximate", or "substantially" shall generally mean within 20%, or within 10%, or within 5% of a given value or range. The numerical values given herein are approximate values, meaning that the terms "about", "approximately", "approximate", or "substantially" can be inferred if not explicitly stated. Those of ordinary skill in the art will understand that dimensions may vary according to different technology nodes. Those of ordinary skill in the art will recognize that dimensions depend on the specific device type, technology generation, minimum feature size, etc. Thus, it is meant that the term is interpreted according to the technology being evaluated.

[0023] Embodiments of the present invention provide a semiconductor qubit device having a superconducting resonator adjacent to a quantum dot qubit region to achieve qubits with high efficiency and low heat generation. The qubits are configured to control and read out the spin of single carriers (electrons or holes) in a (semiconductor) substrate. In some embodiments, the transistors used in the qubits may be implemented on devices selected from the group including planar devices, multi-gate devices, FinFETs, nanosheet gate FETs, and all-around gate FETs.

[0024] Figure 1A is a top view of a device 100 according to some embodiments of the present invention, Figure 1B is Figure 1A a cross-sectional view of the device 100 along line B-B, andFigure 1C Yes Figure 1A Figure 1A is a cross-sectional view of device 100 along line C-C. Device 100 includes a substrate 110, a source region 112, a drain region 114, a channel region 116, a pair of depletion gates 132 and 134, a conductive resonator 135, and an accumulation gate 150. The source region 112 and the drain region 114 are located in the substrate 110. The channel region 116 is located in the substrate 110 and is between the source region 112 and the drain region 114. The depletion gates 132 and 134 are located above the channel region 116 and define a quantum dot qubit region 118 in the channel region 116 and between the depletion gates 132 and 134. In some embodiments, the quantum dot qubit region 118 may be interchangeably referred to as the quantum dot qubit region, which only allows a single carrier (electron or hole) to pass from the entrance of the quantum dot qubit region 118 (i.e., the region below the depletion gate 132) to the exit of the quantum dot qubit region 118 (i.e., the region below the depletion gate 134) before another carrier moves into the quantum dot qubit region 118. The conductive resonator 135 is laterally adjacent to the quantum dot qubit region 118. The accumulation gate 150 is located above the depletion gates 132 and 134 and covers the channel region 116. At least the conductive resonator 135 is a superconducting material, such as MoGe, NbN, TiN, Nb 3 Sn, TiAl, TaN, TiC, TaSi, Al, etc., so as to improve the local heat generation problem near the quantum dot qubit region 118. The superconducting resonator 135 also widens the Rabi frequency range of the device 100, which will be described in detail below.

[0025] Device 100 generates one qubit at a time in the quantum dot qubit region 118. During operation, an external magnetic field B0 is applied to the quantum dot qubit region 118. A voltage is applied to the accumulation gate 150, which conducts the channel region 116. Then a current flows from the source region 112 through the channel region 116 to the drain region 114. The depletion gates 132 and 134 are used to define the position of the quantum dot qubit region 118 and control the tunnel coupling between the source region 112 and the drain region 114. The controlled tunnel coupling only allows a single electron (or hole) to pass through the dot island 118 before any other electron (or hole) moves into the quantum dot qubit region 118. The single electron passing through the quantum dot qubit region 118 is called a qubit. The conductive resonator 135 is configured to generate a microwave source.

[0026] As described above, the conductive resonator 135 is a superconducting material. That is, the conductive resonator 135 has a critical temperature (i.e., superconducting transition temperature) below which the resistance (or effective surface resistance) suddenly drops to approximately zero. Since the device 100 operates at a temperature below the critical temperature of the conductive resonator 135, the conductive resonator 135 is superconducting during operation. With the low resistance, the local heating problem around the conductive resonator 135 (and near the quantum dot qubit region 118) can be improved, and the Johnson-Nyquist thermal noise in the quantum dot qubit region 118 can be reduced. Therefore, the coherence time of the qubit is increased, thereby improving the qubit fidelity. Additionally, the Rabi frequency of the qubit is proportional to the power of the microwave source applied to the conductive resonator 135. Since the conductive resonator 135 is superconducting, the conductive resonator 135 can withstand the high power of the microwave source due to the improved local heating problem, and microwave sources with a wider frequency range can be applied to the device 100, thereby enhancing the application of the device 100.

[0027] In some embodiments, the conductive resonator 135 is a type-II superconductor, which is a superconductor that exhibits an intermediate phase with a mixture of normal and superconducting properties at intermediate temperatures and fields above the superconducting phase. Type-II superconductors also have the characteristic of forming magnetic field vortices through the applied external magnetic field. This occurs above a certain critical magnetic field strength Hc1. The vortex density increases with the increase of the field strength. At the higher critical magnetic field Hc2, the superconducting properties are destroyed. The conductive resonator 135 can be made of MoGe, NbN, TiN, Nb 3 Sn, or other suitable type-II superconducting materials.

[0028] In some embodiments, the type-II superconductor used in the conductive resonator 135 is a single-crystal material, which provides good quality of superconducting properties. For example, the single-crystal type-II superconductor has a high critical temperature and a high critical magnetic field. Therefore, the electronic device 100 can be operated at high temperatures and high external magnetic fields without destroying the superconducting properties of the conductive resonator 135. For example, the critical magnetic field of the type-II superconductor (i.e., the conductive resonator 135 in the present invention) is higher than the external magnetic field B0, such that the conductive resonator 135 is superconducting during operation. In some embodiments, the critical magnetic field of the type-II superconductor is greater than about 0.1 tesla, for example, in the range of about 0.1 tesla to about 100 tesla.

[0029] In some embodiments, the conductive resonator 135 has a width W1 in the range of about 80 nm to about 200 nm. If the width W1 of the conductive resonator 135 is less than about 80 nm, the superconducting properties of the conductive resonator 135 may be lost, and thus there may be a local heating problem, which in turn reduces the readout fidelity of the qubit; if the width W1 of the conductive resonator 135 is greater than about 200 nm, the size of the device 100 may be large. In some embodiments, the linear portion 136 of the conductive resonator 135 has a length L1 in the range of about 500 nm to about 800 nm. If the length L1 of the conductive resonator 135 is less than about 500 nm, the magnetic field B1 generated by the conductive resonator 135 may be non-uniform near the quantum dot qubit region 118; if the length L1 of the conductive resonator 135 is greater than about 800 nm, the local heating problem may not be effectively improved. In some embodiments, the conductive resonator 135 has a thickness T1 in the range of about 40 nm to about 100 nm. If the thickness T1 of the conductive resonator 135 is less than about 40 nm, an external magnetic field may penetrate the conductive resonator 135 and destroy the superconducting properties of the conductive resonator 135 during operation; if the thickness T1 of the conductive resonator 135 is greater than about 100 nm, the surface current of the conductive resonator 135 hardly increases as the thickness T1 increases.

[0030] In some embodiments, the conductive resonator 135 includes a linear portion 136, a first inclined portion 137, and a second inclined portion 138. The first inclined portion 137 and the second inclined portion 138 are located on opposite sides of the linear portion 136, and both extend away from the quantum dot qubit region 118 in a direction inclined with respect to the linear portion 136 of the conductive resonator 135. Compared with the first inclined portion 137 and the second inclined portion 138, the linear portion 136 is closest to the quantum dot qubit region 118. The first inclined portion 137 and the second inclined portion 138 may be landing pads for contacts for connecting to an external power source. The distance D3 between the first inclined portion 137 and the second inclined portion 138 of the conductive resonator 135 is greater than the distance D4 between the depletion gates 132 and 134.

[0031] In a top view, the depletion gates 132 and 134 are spaced apart from each other and are located between the source region 112 and the drain region 114. That is, both the depletion gates 132 and 134 overlap with the channel region 116. The depletion gate 132 is located between the source region 112 and the depletion gate 134, and the depletion gate 134 is located between the depletion gate 132 and the drain region 114. In a top view, the depletion gates 132 and 134 do not overlap with the source region 112 and the drain region 114. In a top view, the depletion gates 132 and 134 extend in a direction not parallel to the linear portion 136 of the conductive resonator 135. The depletion gates 132 and 134 define a quantum dot qubit region 118 that is located between the depletion gates 132 and 134 and in the channel region 116. In some embodiments, the area of the quantum dot qubit region 118 is about 2250 nm 2 to about 2500 nm 2 . In other words, the depletion gate 132 is spaced apart from the depletion gate 134 by a distance D1, and the distance D1 is in the range of about 45 nm to about 50 nm. If the distance D1 exceeds this range, no qubit or more than one qubit may be occupied in the quantum dot qubit region 118.

[0032] The accumulation gate 150 is located above the conductive resonator 135 and the depletion gates 132 and 134. Additionally, the accumulation gate 150 covers the entire quantum dot qubit region 118. In some embodiments, the accumulation gate 150 extends from above the source region 112 to above the drain region 114. Thus, the accumulation gate 150 also covers the portions of the depletion gates 132 and 134 that are directly above the channel region 116. In some embodiments, the length L1 of the linear portion 136 of the conductive resonator 135 is greater than the length L2 of the accumulation gate 150. In some embodiments, the accumulation gate 150 has a thickness T2 that is greater than the thickness T1 of the conductive resonator 135. During the operation of turning on the channel region 116 by inducing an inversion layer on the top surface of the channel region 116, a high voltage is applied to the accumulation gate 150, and thus the accumulation gate 150 is designed to be thick enough to withstand the high voltage. In some embodiments, the thickness T2 of the accumulation gate 150 is in the range of about 30 nm to about 100 nm.

[0033] In some embodiments, the lateral distance D2 between the conductive resonator 135 and the accumulation gate 150 is in the range of about 15 nm to about 50 nm, such that the conductive resonator 135 has good control over the spins of qubits with low microwave source power, and the device 100 is easy to fabricate and has a high packaging density. Additionally, within such a range, there is still good electrical isolation between the conductive resonator 135 and the gates (i.e., the accumulation gate 150 and the depletion gates 132 and 134). If the lateral distance D2 is less than about 15 nm, current leakage may occur between the conductive resonator 135 and the gates, increasing noise and reducing controllability; if the lateral distance D2 is greater than about 50 nm, the microwave source power may increase, which may exceed the critical current of the conductive resonator 135 and destroy its superconducting properties.

[0034] In some embodiments, the accumulation gate 150 and / or the depletion gates 132 and 134 are made of the same superconducting material as the conductive resonator 135. That is, the accumulation gate 150 and / or the depletion gates 132 and 134 can be type-II superconductors and can be single crystals. Thus, the superconducting accumulation gate 150 and / or the superconducting depletion gates 132 and 134 also improve the local heating problem near the quantum dot qubit region 118. In some embodiments, the accumulation gate 150, the depletion gates 132 and 134, and the conductive resonator 135 are made of the same superconducting material, such that the accumulation gate 150, the depletion gates 132 and 134, and the conductive resonator 135 have the same critical temperature (i.e., superconducting transition temperature) and the same critical magnetic field. In some embodiments, the accumulation gate 150, the depletion gates 132 and 134, and the conductive resonator 135 are made of different superconducting materials. For example, the conductive resonator 135 has a critical temperature (and / or critical magnetic field) higher than that of the accumulation gate 150 (and / or the depletion gates 132 and 134).

[0035] In some embodiments, both the substrate 110 and the channel region 116 are of a first conduction type, while both the source region 112 and the drain region 114 are of a second conduction type opposite to the first conduction type. For example, the substrate 110 is a p-type silicon substrate (p-substrate). A p-type dopant can be introduced into the substrate 110 to form the p-substrate. The channel region 116 is a p-type region and has a doping concentration greater than that of the substrate 110. Both the source region 112 and the drain region 114 are n-type regions. In some other embodiments, both the substrate 110 and the channel region 116 are n-type, while both the source region 112 and the drain region 114 are p-type.

[0036] In some embodiments, the device 100 further includes a source contact 182 and a drain contact 184. The source contact 182 is connected to the source region 112, and an ohmic contact is formed at the interface between the source contact 182 and the source region 112. Similarly, the drain contact 184 is connected to the drain region 114, and an ohmic contact is formed at the interface between the drain contact 184 and the drain region 114. In some embodiments, the source contact 182 and the drain contact 184 are also superconducting materials. Since the details of the superconducting material have been described above, the description of this aspect will not be repeated below.

[0037] In some embodiments, the device 100 further includes a first dielectric layer 120 and a second dielectric layer 140. The first dielectric layer 120 is located between the substrate 110 and the depletion gates 132 and 134. Therefore, the first dielectric layer 120 provides good electrical isolation between the depletion gates 132 and 134 and the channel region 116. The second dielectric layer 140 covers the depletion gates 132 and 134 and the conductive resonator 135, and the accumulation gate 150 is located on the second dielectric layer 140. That is, the second dielectric layer 140 is located between the accumulation gate 150 and the depletion gates 132 and 134 to provide electrical isolation between the accumulation gate 150 and other conductive elements (i.e., the conductive resonator 135 and the depletion gates 132 and 134).

[0038] Figures 2A to 8C 1 shows a top view and a cross-sectional view of an intermediate stage in the formation of a device 100a according to some embodiments of the present invention. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. It should be understood that the same elements may be used in the following embodiments. Figures 2A to 8C Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or removed for additional embodiments of the method. The order of operations / processes may be interchanged.

[0039] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A ,and Figure 8A is a top view of some embodiments of a device 100a at an intermediate stage according to some embodiments of the present invention. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B ,and Figure 8B is a cross-sectional view of some embodiments along line BB of the device 100 a at an intermediate stage. Figure 2C , Figure 3C ,Figure 4C , Figure 5C , Figure 6C , Figure 7C , and Figure 8C are cross-sectional views of some embodiments along line C-C of device 100a in an intermediate stage.

[0040] Reference Figure 2A , Figure 2B , and Figure 2C . A substrate 110 is provided. In some embodiments, substrate 110 includes silicon (Si). Alternatively, substrate 110 may include germanium (Ge), silicon germanium, gallium arsenide (GaAs), or other suitable semiconductor materials. In some alternative embodiments, substrate 110 includes an epitaxial layer with or without dopants. Additionally, substrate 110 may include a semiconductor-on-insulator (SOI) structure having a buried dielectric layer therein. The buried dielectric layer may be, for example, a buried oxide (BOX) layer. The SOI structure may be formed by methods such as separation by implantation of oxygen technology, wafer bonding, selective epitaxial growth (SEG), or other suitable methods. In some embodiments, substrate 110 includes a p-type silicon substrate (p-substrate). For example, a p-type dopant is introduced into substrate 110 to form a p-substrate.

[0041] An implantation process is performed to introduce a first impurity into substrate 110 to form a well region 116 in substrate 110. The first impurity may be a p-type impurity or an n-type impurity. The n-type impurity may be phosphorus, arsenic, etc., and the p-type impurity may be boron, BF 2 etc. For example, well region 116 is a p-type region formed in a p-substrate. As previously discussed, at least a portion of well region 116 will serve as a channel region for device 100.

[0042] Then another implantation process is performed to introduce a second impurity into well region 116 to form a source region 112 and a drain region 114 in well region 116. The second impurity may be an n-type impurity or a p-type impurity. The n-type impurity may be phosphorus, arsenic, etc., and the p-type impurity may be boron, BF 2 etc. For example, source region 112 and drain region 114 are n-type regions formed in p-type well region 116 such that the portion of well region 116 between source region 112 and drain region 114 may be referred to as the channel region.

[0043] Reference Figure 3A , Figure 3B , and Figure 3C . A first gate dielectric layer 120 and a first conductive layer 130' are sequentially formed on Figure 1Aabove the structure in. In some embodiments, the first gate dielectric layer 120 includes silicon dioxide, silicon nitride, or other suitable materials. Alternatively, the first gate dielectric layer 120 can be a high-κ dielectric layer having a dielectric constant (κ) higher than that of SiO 2 , i.e., κ > 3.9. The first gate dielectric layer 120 can include LaO, AlO, ZrO, TiO, Ta 2 O 5 、Y 2 O 3 、SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3 (BST), Al 2 O 3 、Si 3 N 4 、nitride oxides (SiON), or other suitable materials. The first gate dielectric layer 120 is deposited by a suitable technique such as ALD, CVD, PVD, thermal oxidation, combinations thereof, or other suitable techniques.

[0044] The first conductive layer 130' is formed above the first gate dielectric layer 120. The first conductive layer 130' includes one or more layers of conductive materials. Examples of the first conductive layer 130' include type-II superconductors, including MoGe, NbN, TiN, Nb 3 Sn, or other suitable type-II superconductors. The first conductive layer 130' can be formed by physical vapor deposition (PVD) including sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable methods.

[0045] Refer to Figure 4A 、 Figure 4B 、and Figure 4C . A patterned photoresist layer PR1 is formed above the substrate 110 to cover portions of the first conductive layer 130' and expose other portions of the first conductive layer 130'.

[0046] Refer to Figure 5A 、 Figure 5B 、and Figure 5C . By using the patterned photoresist layer PR1 (see Figure 4A 、 Figure 4B 、and Figure 4C ) as an etching mask, for Figure 4A 、 Figure 4B 、and Figure 4CThe first conductive layer 130' in is patterned to form a pair of depletion gates 132, 134 and a conductive resonator 135. The patterning of the first conductive layer 130' can be implemented by using an etching process. In some embodiments, the etching process is a dry etching process using an etching gas such as CF 4 , SF 6 , their combinations, etc. After the etching process, the patterned photoresist layer PR1 is removed, and the removal method can be implemented, for example, by solvent stripping or plasma ashing. A pair of depletion gates 132 and 134 are formed between the source region 112 and the drain region 114. For example, the depletion gate 132 partially covers the source region 112, while the depletion gate 134 partially covers the drain region 114. A pair of depletion gates 132 and 134 are spaced apart from each other. The conductive resonator 135 is spaced apart from the depletion gates 132 and 134 and extends along a direction different from (e.g., substantially perpendicular to) the extending direction of the depletion gates 132 and 134.

[0047] Reference Figure 6A , Figure 6B , and Figure 6C . The second gate dielectric layer 140 and the second conductive layer 150' are sequentially formed over the first gate dielectric layer 120, the depletion gates 132, 134, and the conductive resonator 135. The second gate dielectric layer 140 covers the first gate dielectric layer 130, the depletion gates 132, 134, and the conductive resonator 135. In some embodiments, the second gate dielectric layer 140 can be a high-κ dielectric layer having a dielectric constant (κ) higher than that of SiO 2 , i.e., κ > 3.9. The second gate dielectric layer 140 can include LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3 (BST), Al 2 O 3 , Si 3 N 4 , silicon oxynitride (SiON), or other suitable materials. Alternatively, the second gate dielectric layer 140 can include silicon dioxide, silicon nitride, or other suitable materials. The second gate dielectric layer 140 is deposited by a suitable technique such as ALD, CVD, PVD, thermal oxidation, their combinations, or other suitable techniques.

[0048] The second conductive layer 150' is formed over the first gate dielectric layer 120. The second conductive layer 150' includes one or more layers of conductive material. Examples of the second conductive layer 150' include type-II superconductors, which include MoGe, NbN, TiN, Nb 3 Sn, or other suitable type-II superconductors. The second conductive layer 150' can be formed by physical vapor deposition (PVD) including sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable methods.

[0049] Reference Figure 7A , Figure 7B , and Figure 7C . A patterned photoresist layer PR2 is formed over the substrate 110 to cover portions of the second conductive layer 150' and expose other portions of the second conductive layer 150'.

[0050] Reference Figure 8A , Figure 8B , and Figure 8C . By using the patterned photoresist layer PR2 (see Figure 7A , Figure 7B , and Figure 7C ) as an etching mask, the second conductive layer 150' in Figure 7A , Figure 7B , and Figure 7C is patterned to form the stacked gate 150. The patterning of the second conductive layer 150' can be formed by using an etching process. In some embodiments, the etching process is a dry etching process using etching gases CF 4 , SF 6 , combinations thereof, etc. After the etching process, the patterned photoresist layer PR2 is removed, and the removal method can be implemented, for example, by solvent stripping or plasma ashing. The stacked gate 150 partially covers the depletion gates 132, 134, the channel region 116, the source region 112, and the drain region 114. Additionally, the stacked gate 150 is spaced apart from the conductive resonator 135 in a top view as shown in Figure 8A .

[0051] In Figures 8A to 8C , all of the conductive resonator 135, the depletion gates 132, 134, and the stacked gate 150 are superconducting materials. That is, the critical magnetic fields of all of the conductive resonator 135, the depletion gates 132, 134, and the stacked gate 150 are higher than the external magnetic field B0 (see Figure 1A ).

[0052] In some embodiments, the stacked gate is made of a conductive material rather than a superconducting material. Figure 9A is a top view of the device 100b according to some embodiments of the present invention,Figure 9B is a cross-sectional view of device 100b along line B-B, and Figure 9C is a cross-sectional view of device 100b along line C-C. The difference between device 100b and 100a (see Figures 8A to 8C ) lies in the material of the accumulation gate. In Figures 9A to 9C , device 100b includes an accumulation gate 150a made of a conductive material rather than a superconducting material. During operation, the conductive resonator 135 and the depletion gates 132, 134 are in the superconducting state, while the accumulation gate 150a is in the normal state. That is, during operation, the resistance (or effective surface resistance) of the accumulation gate 150a is greater than that of the conductive resonator 135 and the depletion gates 132, 134. In Figures 9A to 9C , the conductive resonator 135 and the depletion gates 132, 134 are superconducting materials, while the accumulation gate 150a is a (normal) conductive material (i.e., non-superconducting material), such as W, Ti, TiAlC, TaAlC, Co, TaC, HfTi, combinations thereof, etc. That is, the critical magnetic field of the conductive resonator 135 and the depletion gates 132, 134 is higher than the external magnetic field B0 (see Figure 1A ). In addition, the critical temperature of the conductive resonator 135 and the depletion gates 132, 134 is higher than the critical temperature of the accumulation gate 150a. The other components of device 100b are similar or identical to those of device 100a shown in Figures 8A to 8C , and thus, descriptions in this regard will not be provided hereinafter.

[0053] Figures 10A to 14C show a top view and a cross-sectional view of an intermediate stage in the formation of device 100c according to some embodiments of the present invention. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that additional operations may be provided before, during, and after the process shown in Figures 10A to 14C , and for additional embodiments of the method, some of the operations described below may be replaced or removed. The order of the operations / processes may be interchanged.

[0054] Figure 10A , Figure 11A , Figure 12A , Figure 13A , and Figure 14A are top views of some embodiments of device 100c in an intermediate stage according to some embodiments of the present invention. Figure 10B , Figure 11B , Figure 12B , Figure 13B , and Figure 14B are cross-sectional views of some embodiments of device 100c in an intermediate stage along line B-B. Figure 10C , Figure 11C, Figure 12C , Figure 13C , and Figure 14C are cross-sectional views of some embodiments along line C-C when the device 100c is in an intermediate stage.

[0055] Referring to Figure 10A , Figure 10B , and Figure 10C . First, implement the Figures 2A to 3C manufacturing process. Since all relevant manufacturing details are the same as or similar to those of the embodiment shown in Figures 2A to 3C , the description in this regard will not be repeated hereinafter. Subsequently, Figures 3A to 3C the first conductive layer 130' in Figures 10A to 10C is patterned into the conductive resonator 135, as shown in Figure 5A . The material, configuration, size, process, and / or operation of the conductive resonator 135 are similar to or the same as those of the conductive resonator 135 in

[0056] Referring to Figure 11A , Figure 11B , and Figure 11C . A protective layer HM1 is formed above the substrate 110 and covers the conductive resonator 135. Additionally, the protective layer HM1 exposes the portions of the first gate dielectric layer 120 directly above the source region 112 and the drain region 114. The material for forming the protective layer HM1 may include: oxide materials such as titanium oxide, silicon oxide, etc.; nitride materials such as silicon nitride, boron nitride, titanium nitride, tantalum nitride; carbide materials such as tungsten carbide, silicon carbide; semiconductor materials such as silicon; metals such as titanium, tantalum; or combinations thereof. Processes such as CVD, ALD, etc. can be used to form the protective layer HM1.

[0057] Referring to Figure 12A , Figure 12B , and Figure 12C . A conductive layer 170' is formed above the first gate dielectric layer 120 and the protective layer HM1. The conductive layer 170' includes one or more layers of (ordinary) conductive materials (i.e., non-superconducting materials). Examples of the conductive layer 170' include W, Ti, TiAlC, TaAlC, Co, TaC, HfTi, combinations thereof, etc. The conductive layer 170' can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods.

[0058] Referring to Figure 13A , Figure 13B , and Figure 13C . Figure 12A , Figure 12B , and Figure 12CThe conductive layer 160' therein is patterned to form a pair of depletion gates 132a and 134a. The patterning of the conductive layer 160' can be implemented using an etching process. A pair of depletion gates 132a and 134a are formed between the source region 112 and the drain region 114. For example, the depletion gate 132a partially covers the source region 112, while the depletion gate 134a partially covers the drain region 114. A pair of depletion gates 132a and 134a are spaced apart from each other. The conductive resonator 135 is spaced apart from the depletion gates 132a and 134a and extends in a direction different from (e.g., substantially perpendicular to) the extending direction of the depletion gates 132a and 134a. The depletion gates 132a, 134a and the conductive resonator 135 are made of different materials. For example, each of the depletion gates 132a and 134a has a resistance (or effective surface resistance) greater than that of the conductive resonator 135 (during operation). After forming the depletion gates 132a and 134a, the protective layer HM1 is removed by using, for example, an etching process (see Figure 12C ).

[0059] Reference Figure 14A , Figure 14B , and Figure 14C . Figures 13A to 13C The structure shown undergoes a process similar to that of the structure shown in Figures 6A to 8C . That is, the second gate dielectric layer 140 and the second conductive layer 150' are sequentially formed above the first gate dielectric layer 120, the depletion gates 132a, 134a, and the conductive resonator 135. A patterned photoresist layer PR2 is formed above the substrate 110 to cover a part of the second conductive layer 150' and expose other parts of the second conductive layer 150'. Subsequently, the second conductive layer 150' is patterned to form the accumulation gate 150 by using the patterned photoresist layer PR2 as an etching mask, as shown in Figure 14A and Figure 14B . The material, configuration, size, process, and / or operation of the accumulation gate 150 are similar or identical to those of the accumulation gate 150 in Figure 8A . The material, configuration, size, process, and / or operation of the second gate dielectric layer 140 are similar or identical to those of the second gate dielectric layer 140 in Figure 8A .

[0060] In Figures 14A to 14C , the conductive resonator 135 and the accumulation gate 150 are superconducting materials, while the depletion gates 132a, 134a are (ordinary) conductive materials (i.e., non-superconducting materials). That is, the critical magnetic fields of the conductive resonator 135 and the accumulation gate 150 are higher than the external magnetic field B0 (see Figure 1A) Additionally, the critical temperature of the conductive resonator 135 and the accumulation gate 150 is higher than that of the depletion gates 132a, 134a.

[0061] In some embodiments, the accumulation gate is made of a conductive material instead of a superconducting material. Figure 15A is a top view of the device 100d according to some embodiments of the present invention, Figure 15B is a cross-sectional view of the device 100d along line B-B, and Figure 15C is a cross-sectional view of the device 100d along line C-C. The difference between the devices 100d and 100c (see Figures 14A to 14C ) lies in the material of the accumulation gate. In Figures 15A to 15C , the device 100d includes an accumulation gate 150a made of a conductive material instead of a superconducting material. During operation, the conductive resonator 135 is in a superconducting state, while the accumulation gate 150a is in a normal state. That is, during operation, the resistance (or effective surface resistance) of the accumulation gate 150a is greater than that of the conductive resonator 135. Additionally, the conductive resonator 135 is a superconducting material, while the depletion gates 132a, 134a are (ordinary) conductive materials (i.e., non-superconducting materials). That is, the critical magnetic field of the conductive resonator 135 is higher than the external magnetic field B0 (see Figure 1A ). Additionally, the critical temperature of the conductive resonator 135 is higher than that of the depletion gates 132a, 134a and the accumulation gate 150a. The other components of the device 100d are similar or identical to those of the device 100c shown in Figures 14A to 14C , and thus, descriptions in this regard will not be provided hereinafter.

[0062] Figure 16 shows the relationship between the simulated effective surface resistance and frequency of different materials according to some embodiments of the present invention. In Figure 16 , line 12 represents the simulated effective surface resistance of aluminum in the normal state, line 14 represents the simulated effective surface resistance of NbN in the superconducting state, and line 16 represents the simulated effective surface resistance of MoGe in the superconducting state.

[0063] Based on the above discussion, it can be seen that the present invention provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed herein, and not all specific advantages are required for all embodiments. One advantage is that the superconducting resonator improves the local heating problem near the quantum dot qubit region. Another advantage is that a microwave source with a wide range of Rabi frequencies can be applied to the device, enhancing the applicability of the device.

[0064] According to some embodiments, a device includes a source region, a drain region, a channel region, a pair of depletion gates, an accumulation gate, and a superconducting resonator. The channel region is located between the source region and the drain region. The depletion gates are spaced apart from each other. The depletion gates each overlap with the channel region and define a quantum dot qubit region in the channel region and between the pair of depletion gates. The accumulation gate is located above the pair of depletion gates and passes through the pair of depletion gates. The superconducting resonator is laterally adjacent to the quantum dot qubit region.

[0065] According to some embodiments, a device includes a source region, a drain region, a channel region, a conductive resonator, a pair of depletion gates, and an accumulation gate. The source region and the drain region are located on opposite sides of the channel region. The conductive resonator is located above the substrate and has a linear portion adjacent to the channel region in a top view. The pair of depletion gates is located above the channel region and extends in a direction not parallel to the linear portion of the conductive resonator in a top view. The pair of depletion gates defines a quantum dot qubit region in the channel region. The accumulation gate covers the pair of depletion gates and the quantum dot qubit region. The accumulation gate is made of a superconducting material.

[0066] Some embodiments of the present invention provide a semiconductor device, which includes: a source region, a drain region, and a channel region, located in a substrate, wherein the channel region is located between the source region and the drain region; a pair of depletion gates, spaced apart from each other, wherein the pair of depletion gates each overlap with the channel region and define a quantum dot qubit region in the channel region and between the pair of depletion gates; an accumulation gate, located above the pair of depletion gates and spanning the pair of depletion gates; and a superconducting resonator, laterally adjacent to the quantum dot qubit region.

[0067] In some embodiments, the superconducting resonator is a type-II superconductor.

[0068] In some embodiments, the superconducting resonator is single-crystalline.

[0069] In some embodiments, the superconducting transition temperature of the superconducting resonator is higher than the superconducting transition temperature of the accumulation gate.

[0070] In some embodiments, the lateral distance between the superconducting resonator and the accumulation gate is in the range of about 15 nm to about 50 nm.

[0071] In some embodiments, the thickness of the accumulation gate is greater than the thickness of the superconducting resonator.

[0072] In some embodiments, the thickness of the superconducting resonator is in the range of about 40 nm to about 100 nm.

[0073] In some embodiments, the width of the superconducting resonator is in the range of about 80 nm to about 200 nm.

[0074] In some embodiments, the length of the superconducting resonator is in the range of about 500 nm to about 800 nm.

[0075] Some further embodiments of the present invention provide a semiconductor device, which includes: a source region, a drain region, and a channel region, located in a substrate, wherein the source region and the drain region are located on opposite sides of the channel region; a conductive resonator, located above the substrate, and having a linear portion adjacent to the channel region in a top view; a pair of depletion gates, located above the channel region, and extending in a direction not parallel to the linear portion of the conductive resonator in a top view; wherein the pair of depletion gates defines a quantum dot qubit region in the channel region; and an accumulation gate, covering the pair of depletion gates and the quantum dot qubit region, wherein the accumulation gate is made of a superconducting material.

[0076] In some embodiments, the superconducting material of the accumulation gate includes MoGe, NbN, Nb 3 Sn, or a combination thereof.

[0077] In some embodiments, the conductive resonator includes MoGe, NbN, Nb 3 Sn, or a combination thereof.

[0078] In some embodiments, in a top view, the linear portion of the conductive resonator has a length greater than the length of the accumulation gate.

[0079] In some embodiments, the conductive resonator further includes: a first inclined portion and a second inclined portion, located on opposite sides of the linear portion, and both extending away from the quantum dot qubit region in a direction inclined with respect to the linear portion of the conductive resonator, wherein the distance between the first inclined portion and the second inclined portion of the conductive resonator is greater than the distance between the pair of depletion gates.

[0080] According to some embodiments, a method includes forming a channel region, a source region, and a drain region in a substrate. Depositing a superconducting layer above the substrate to cover the channel region, the source region, and the drain region. Patterning the superconducting layer to form a pair of depletion gates spanning the channel region. Forming an accumulation gate above the pair of depletion gates, and the accumulation gate covers the channel region.

[0081] In some embodiments, patterning the superconducting layer also forms a conductive resonator adjacent to the pair of depletion gates.

[0082] In some embodiments, the thickness of the accumulation gate is greater than the thickness of the conductive resonator.

[0083] In some embodiments, the superconducting transition temperature of the pair of depletion gates is higher than the superconducting transition temperature of the accumulation gate.

[0084] In some embodiments, the accumulation gate is a type-II superconductor.

[0085] In some embodiments, a pair of depletion gates is single crystal.

[0086] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a source region, a drain region, and a channel region, located in a substrate, wherein the channel region is located between the source region and the drain region; a pair of depletion gates, spaced apart from each other, wherein the pair of depletion gates both overlap with the channel region, and a quantum dot qubit region is defined in the channel region and between the pair of depletion gates; an accumulation gate, located above the pair of depletion gates and spanning the pair of depletion gates; and a superconducting resonator, laterally adjacent to the quantum dot qubit region.

2. The semiconductor device according to claim 1, wherein, the superconducting resonator is a type-II superconductor.

3. The semiconductor device according to claim 1, wherein, the superconducting resonator is single-crystalline.

4. The semiconductor device according to claim 1, wherein, the superconducting transition temperature of the superconducting resonator is higher than the superconducting transition temperature of the accumulation gate.

5. The semiconductor device according to claim 1, wherein, the lateral distance between the superconducting resonator and the accumulation gate is in the range of 15 nm to 50 nm.

6. The semiconductor device according to claim 1, wherein, the thickness of the accumulation gate is greater than the thickness of the superconducting resonator.

7. The semiconductor device according to claim 1, wherein, the thickness of the superconducting resonator is in the range of 40 nm to 100 nm.

8. The semiconductor device according to claim 1, wherein, the width of the superconducting resonator is in the range of 80 nm to 200 nm.

9. The semiconductor device according to claim 1, wherein, the length of the superconducting resonator is in the range of 500 nm to 800 nm.

10. A semiconductor device, comprising: a source region, a drain region, and a channel region, located in a substrate, wherein the source region and the drain region are located on opposite sides of the channel region; a conductive resonator, located above the substrate and having a linear portion adjacent to the channel region in a top view; a pair of depletion gates, located above the channel region and extending in a direction not parallel to the linear portion of the conductive resonator in the top view; wherein the pair of depletion gates define a quantum dot qubit region in the channel region; and an accumulation gate, covering the pair of depletion gates and the quantum dot qubit region, wherein the accumulation gate is made of a superconducting material.

11. The semiconductor device according to claim 10, wherein, wherein the superconducting material of the cumulative gate includes MoGe, NbN, Nb 3 Sn, or a combination thereof.

12. The semiconductor device according to claim 10, wherein, The conductive resonator includes MoGe, NbN, Nb 3 Sn, or a combination thereof.

13. The semiconductor device according to claim 10, wherein, in the top view, the length of the linear portion of the conductive resonator is greater than the length of the accumulation gate.

14. The semiconductor device according to claim 10, wherein, the conductive resonator further comprises: A first inclined portion and a second inclined portion, located on opposite sides of the linear portion, and both extending away from the quantum dot qubit region in a direction inclined with respect to the linear portion of the conductive resonator, wherein a distance between the first inclined portion and the second inclined portion of the conductive resonator is greater than a distance between the pair of depletion gates.

15. A method of manufacturing a semiconductor device, comprising: forming a channel region, a source region, and a drain region in a substrate; depositing a superconducting layer over the substrate to cover the channel region, the source region, and the drain region; patterning the superconducting layer to form a pair of depletion gates spanning the channel region and a conductive resonator adjacent to the pair of depletion gates; and forming a cumulative gate over the pair of depletion gates and the cumulative gate covering the channel region, wherein the conductive resonator is laterally adjacent to a quantum dot qubit region defined by the pair of depletion gates in the channel region.

16. The method according to claim 15, wherein, The conductive resonator includes MoGe, NbN, Nb 3 Sn, or a combination thereof.

17. The method according to claim 16, wherein, the thickness of the cumulative gate is greater than the thickness of the conductive resonator.

18. The method according to claim 15, wherein, the superconducting transition temperature of the pair of depletion gates is higher than the superconducting transition temperature of the cumulative gate.

19. The method according to claim 15, wherein, the cumulative gate is a type-II superconductor.

20. The method according to claim 15, wherein, the pair of depletion gates is single-crystalline.

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