Display substrate and display device

Abstract

A display substrate comprises: a substrate (BS); a first conductive element (111) on the substrate (BS); a first planarization layer (121) on the first conductive element (111); a second conductive element (112) on the first planarization layer (121) and connected with the first conductive element (111) through a first via (V1) penetrating the first planarization layer (121); a second planarization layer (122) on the second conductive element (112); a conductive line (L1) on the second planarization layer (122); the second conductive element (112) is recessed at the first via (V1), so that the second conductive element (112) has a recessed portion (1121) and a peripheral portion (1122) outside the recessed portion (1121), the recessed portion (1121) has a bottom (112a) and a side (112b), the bottom (112a) is connected with the peripheral portion (1122) through the side (112b), and the side (112b) of the recessed portion (1121) has a rough surface configured to cause diffuse reflection of light irradiated thereon. A display device is also provided.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to a display substrate and a display device. Background Technology

[0002] With the continuous development of display technology, active-matrix organic light-emitting diode (AMOLED) display technology has been increasingly used in display devices such as mobile phones, tablets, and digital cameras due to its advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and high response speed.

[0003] Under-display camera technology is a new technology proposed to improve the screen-to-body ratio of display devices. Summary of the Invention

[0004] At least one embodiment of this disclosure relates to a display substrate and a display device.

[0005] At least one embodiment of this disclosure provides a display substrate, comprising: a substrate; a first conductive element located on the substrate; a first planarization layer located on the first conductive element; a second conductive element located on the first planarization layer and connected to the first conductive element through a first via through the first planarization layer; a second planarization layer located on the second conductive element; and a conductive line located on the second planarization layer; wherein the second conductive element is recessed at the first via, such that the second conductive element has a recessed portion and a peripheral portion located outside the recessed portion, the recessed portion having a bottom and a side portion, the bottom being connected to the peripheral portion through the side portion, and the side portion of the recessed portion having an uneven surface configured such that light incident thereon undergoes diffuse reflection.

[0006] For example, the first planarization layer has an uneven surface at a position corresponding to the side, and the second conductive element is conformally disposed thereon.

[0007] For example, the side portion has an angle with the substrate, and the angle is an acute angle.

[0008] For example, at least one of the bottom and the periphery of the second conductive element has an uneven surface.

[0009] For example, the surface of the side portion of the recess that is close to the substrate and the surface that is away from the substrate are both uneven surfaces.

[0010] For example, the surface of the second conductive element near the substrate is a smooth surface, while the side surface away from the substrate is an uneven surface.

[0011] For example, at least one of the bottom and the peripheral portion has an uneven surface facing away from the substrate.

[0012] For example, the display substrate further includes pixel units, each pixel unit including a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the light-emitting element. The pixel unit includes a first pixel unit and a second pixel unit. The display substrate includes a first display area and a second display area. The pixel circuit and the light-emitting element of the first pixel unit are both located in the first display area. The pixel circuit of the second pixel unit is located in the first display area. The light-emitting element of the second pixel unit is located in the second display area. The pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit through the conductive line.

[0013] For example, the second display area is a light-transmitting display area, and the orthographic projection of the pixel circuit of the first pixel unit on the substrate and the orthographic projection of the light-emitting element of the first pixel unit on the substrate at least partially overlap, while the orthographic projection of the pixel circuit of the second pixel unit on the substrate and the orthographic projection of the light-emitting element of the second pixel unit on the substrate do not overlap.

[0014] For example, the orthographic projection of the conductive line on the substrate overlaps with the orthographic projection of the pixel circuit of the first pixel unit on the substrate.

[0015] For example, the display substrate also includes a connecting element, through which the pixel circuit of the pixel unit is connected to the conductive line or to the light-emitting element of the first pixel unit.

[0016] For example, the connecting element includes a first connecting electrode and a second connecting electrode, which are connected together.

[0017] For example, the first conductive element includes the first connecting electrode, and the second conductive element includes a second connecting electrode connected to the first connecting electrode.

[0018] For example, the first conductive element and the first connecting electrode are located on the same layer, and the second conductive element and the second connecting electrode are located on the same layer.

[0019] For example, the pixel circuit includes a driving transistor, the driving transistor including a gate; the display substrate further includes: a first gate signal line connected to the gate of the driving transistor; a constant voltage line configured to provide a first constant voltage to the pixel circuit; and a shielding electrode connected to the constant voltage line, wherein the orthographic projection of the first gate signal line on the substrate falls within the orthographic projection of the shielding electrode on the substrate.

[0020] For example, the first conductive element includes the constant voltage line, and the second conductive element includes the shielding electrode connected to the constant voltage line.

[0021] For example, the first conductive element is located on the same layer as the constant voltage line, and the second conductive element is located on the same layer as the shielding electrode.

[0022] For example, the conductive lines are configured as multiple lines, and at least one of the multiple conductive lines overlaps with the orthographic projection of the first via on the substrate.

[0023] For example, the material of the second conductive element includes metal, and the material of the conductive wire includes a transparent conductive material.

[0024] At least one embodiment of this disclosure also provides a display substrate, comprising: a substrate including a first display area and a second display area; a pixel unit located on the substrate, wherein the pixel unit includes a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel unit including a first pixel unit and a second pixel unit, the pixel circuit and the light-emitting element of the first pixel unit being located in the first display area, the pixel circuit of the second pixel unit being located in the first display area, the light-emitting element of the second pixel unit being located in the second display area, the pixel circuit of the second pixel unit being connected to the light-emitting element of the second pixel unit via a conductive line; and a connecting element connected to the pixel circuit, the pixel circuit of the first pixel unit being connected to the light-emitting element of the first pixel unit via the connecting element. The light-emitting elements are connected, or the pixel circuit of the second pixel unit is connected to the conductive line through the connecting element, the connecting element including a first connecting electrode and a second connecting electrode; a first planarization layer located on the first connecting electrode, the second connecting electrode located on the first planarization layer and connected to the first connecting electrode through a via penetrating the first planarization layer; a second planarization layer located on the second connecting electrode, the conductive line located on the second planarization layer; the second connecting electrode is recessed at the via, such that the second connecting electrode has a recessed portion and a peripheral portion located outside the recessed portion, the recessed portion having a bottom and a side portion, the bottom being connected to the peripheral portion through the side portion, the side portion of the second connecting electrode having an uneven surface configured such that light incident thereon undergoes diffuse reflection.

[0025] For example, the pixel circuit includes a driving transistor, the driving transistor including a gate; the display substrate further includes: a first gate signal line connected to the gate of the driving transistor; a constant voltage line configured to provide a first constant voltage to the pixel circuit; and a shielding electrode connected to the constant voltage line, wherein the orthographic projection of the first gate signal line on the substrate falls within the orthographic projection of the shielding electrode on the substrate; a first planarization layer is located on the constant voltage line, the shielding electrode is located on the first planarization layer, a second planarization layer is located on the shielding electrode, and the shielding electrode is connected to the constant voltage line through a via penetrating the first planarization layer; the shielding electrode is recessed at the via connecting the shielding electrode and the constant voltage line, such that the shielding electrode has a recessed portion and a peripheral portion located outside the recessed portion, the recessed portion of the shielding electrode has a bottom and a side portion, the bottom of the shielding electrode is connected to the peripheral portion of the shielding electrode through the side portion of the shielding electrode, and the side portion of the shielding electrode has an uneven surface configured to cause diffuse reflection of light incident thereon.

[0026] At least one embodiment of this disclosure also provides a display device including any of the above-described display substrates.

[0027] For example, the display device also includes a light sensor located on one side of the display panel. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0029] Figure 1 This is a schematic diagram of a display panel.

[0030] Figure 2 A schematic diagram of a partial structure of a display panel is shown.

[0031] Figure 3 To form Figure 2 A schematic diagram of the exposure process for patterning a transparent conductive film during the process of creating the conductive lines shown. Figure 2 (Cross-sectional view at A1, A2, or A3).

[0032] Figure 4 A schematic diagram for forming a photoresist pattern.

[0033] Figure 5 This is a schematic diagram of the formation of conductive lines.

[0034] Figure 6 This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure.

[0035] Figure 7 This is a schematic diagram showing diffuse reflection of light irradiating the side portion of a second conductive element in a display substrate, as provided in an embodiment of the present disclosure.

[0036] Figure 8 A schematic diagram of a first planarization layer and a first via in a display substrate is provided in one embodiment of this disclosure.

[0037] Figure 9 This is a schematic diagram illustrating the formation of a first planarization layer during the fabrication of a display substrate, as provided in an embodiment of this disclosure.

[0038] Figure 10A This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure.

[0039] Figure 10B Formation provided for an embodiment of this disclosure Figure 10A A schematic diagram of the second conductive element in the display substrate shown.

[0040] Figure 10C This is a schematic diagram of a display substrate provided for another embodiment of the present disclosure.

[0041] Figure 10D This is a schematic diagram of a display substrate provided for another embodiment of the present disclosure.

[0042] Figure 11A This is a schematic diagram of a second conductive element in a display substrate provided for an embodiment of the present disclosure.

[0043] Figure 11B This is a schematic diagram of a second conductive element in a display substrate, provided for another embodiment of the present disclosure.

[0044] Figure 11C This is a schematic diagram of a partial structure of a display substrate provided in an embodiment of the present disclosure.

[0045] Figure 11D This is a schematic diagram of a partial structure of a display substrate provided in an embodiment of the present disclosure.

[0046] Figure 11E This is a schematic diagram of a partial structure of a display substrate provided in an embodiment of the present disclosure.

[0047] Figure 11F This is a schematic diagram of a partial structure of a display substrate provided in an embodiment of the present disclosure.

[0048] Figure 12A This is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure.

[0049] Figure 12B This is a layout diagram of pixel circuits in a display panel according to an embodiment of the present disclosure.

[0050] Figure 12C for Figure 12B A sectional view along line AB.

[0051] Figure 13A and Figure 13B This is a schematic diagram of a display device provided according to an embodiment of the present disclosure.

[0052] Figure 14 The structural layout of the pixel circuits before and after compression is shown. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0054] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0055] With the continuous development of mobile phone screens, full-screen phones and under-display camera technology have become hot topics. In order to improve the PPI (Pixels Per Inch) and transmittance of the camera area, the under-display camera area usually retains the light-emitting element, while the driving circuit of the light-emitting element is placed in other locations. For example, the driving circuit can adopt an external or compressed solution, and transparent conductive lines are usually used to connect the light-emitting element and the driving circuit to complete its driving light emission.

[0056] Figure 1 This is a schematic diagram of a display panel. (Example) Figure 1 As shown, the display panel includes a display area R0 and a peripheral area R3. The peripheral area R3 is a non-display area. The display area R0 includes a first display area R1 and a second display area R2. For example, hardware such as a light sensor (e.g., a camera) is disposed on one side of the display panel at a position corresponding to the second display area R2. For example, the second display area R2 is a light-transmitting display area, and the first display area R1 is a display area. For example, the first display area R1 is opaque and used only for display. The first display area R1 and the second display area R2 together constitute the display area of ​​the display panel.

[0057] like Figure 1As shown, the display panel includes a substrate BS and pixel units 100 located on the substrate BS. Pixel units 100 include a first pixel unit 101 and a second pixel unit 102. The first pixel unit 101 includes a first pixel circuit 10 and a first light-emitting element 30, and the second pixel unit 102 includes a second pixel circuit 20 and a second light-emitting element 40. The first pixel circuit 10 and the first light-emitting element 30 of the first pixel unit 101 are both located in a first display area R1, the second pixel circuit 20 of the second pixel unit 101 is located in the first display area R1, and the second light-emitting element 40 of the second pixel unit 102 is located in a second display area R2. For example, the first pixel circuit 10 can be called an in-situ pixel circuit, and the second pixel circuit 20 can be called a non-in-situ pixel circuit. Both the first pixel circuit 10 and the second pixel circuit 20 are driving circuits. Figure 1 As shown, in the second display area R2, the area between adjacent second light-emitting elements 40 is a light-transmitting sub-area, and the area where the second light-emitting elements 40 are located is a display sub-area.

[0058] For example, such as Figure 1 As shown, the display panel includes: a plurality of first pixel circuits 10, a plurality of second pixel circuits 20, and a plurality of first light-emitting elements 30 located in the first display area R1, and a plurality of second light-emitting elements 40 located in the second display area R2. For example, the plurality of second pixel circuits 20 may be spaced apart between the plurality of first pixel circuits 10.

[0059] To improve the light transmittance of the second display area R2, only a light-emitting element can be provided in the second display area R2, while the pixel circuit that drives the light-emitting element of the second display area R2 is located in the first display area R1. That is, the light transmittance of the second display area R2 is improved by separating the light-emitting element and the pixel circuit. In other words, no pixel circuit is provided in the second display area R2.

[0060] For example, such as Figure 1 As shown, at least one of the plurality of first pixel circuits 10 can be connected to at least one of the plurality of first light-emitting elements 30, and the orthographic projection of at least one first pixel circuit 10 on the substrate BS can at least partially overlap with the orthographic projection of at least one first light-emitting element 30 on the substrate BS. The at least one first pixel circuit 10 can be used to provide a driving signal to the connected first light-emitting element 30 to drive the first light-emitting element 30 to emit light.

[0061] Figure 1Taking the second pixel circuit 20, which drives the second light-emitting element 40 to emit light, located in the first display area R1 as an example, the display panel in this case can adopt a driving circuit compression scheme. In the driving circuit compression scheme, the size of the driving circuit in the first direction X is reduced, so that the first pixel circuit 10 and the second pixel circuit 20 can be placed in the first direction X, and the second pixel circuit 20 can be distributed among the first pixel circuit 10. For example, if the first direction X is the row direction, the second pixel circuit 20 is arranged at intervals in the first pixel circuit 10 in the same row. Of course, in other embodiments, the second pixel circuit 20 can also be located in the peripheral area R3, thereby forming an external driving circuit scheme.

[0062] For example, such as Figure 1 As shown, the first display area R1 can be located on at least one side of the second display area R2. For example, in some embodiments, the first display area R1 surrounds the second display area R2. That is, the second display area R2 can be surrounded by the first display area R1. The second display area R2 can also be located at other positions, and the location of the second display area R2 can be determined as needed. For example, the second display area R2 can be located at the top center of the substrate BS, or at the upper left corner or upper right corner of the substrate BS.

[0063] For example, such as Figure 1 As shown, at least one of the plurality of second pixel circuits 20 can be connected to at least one of the plurality of second light-emitting elements 40 via a conductive line L1. This at least one second pixel circuit 20 can be used to provide a driving signal to the connected second light-emitting element 40 to drive it to emit light. Figure 1 As shown, since the second light-emitting element 40 and the second pixel circuit 20 are located in different regions, there is no overlap between the orthographic projection of at least one second pixel circuit 20 on the substrate BS and the orthographic projection of at least one second light-emitting element 40 on the substrate BS.

[0064] For example, in this embodiment, the first display area R1 can be set as a non-transparent display area, and the second display area R2 can be set as a transparent display area. For instance, the first display area R1 is opaque, while the second display area R2 is transparent. Thus, the display panel provided in this embodiment does not require perforation; the necessary hardware structures, such as the photosensor, can be directly placed on one side of the display panel at the position corresponding to the second display area R2, laying a solid foundation for achieving a true full-screen display. Furthermore, since the second display area R2 only includes light-emitting elements and not pixel circuits, its light transmittance is improved, resulting in a better display effect.

[0065] For example, such as Figure 1 As shown, the second light-emitting element 40 and the second pixel circuit 20 connected to the second light-emitting element 40 are located in the same row. That is, the light emission signal of the second light-emitting element 40 comes from the second pixel circuit in the same row. For example, the pixel circuits of the pixel units in the same row are connected to the same gate line. Of course, in other embodiments, the second light-emitting element 40 and the second pixel circuit 20 connected to the second light-emitting element 40 may not be located in the same row.

[0066] like Figure 1 As shown, the pixel circuit (second pixel circuit 20) of the second pixel unit 102 is connected to the light-emitting element (second light-emitting element 40) of the second pixel unit 102 via a conductive line L1. For example, the conductive line L1 is made of a transparent conductive material. For example, the conductive line L1 is made of a conductive oxide material. For example, the conductive oxide material includes indium tin oxide (ITO), but is not limited to this.

[0067] like Figure 1 As shown, one end of the conductive line L1 is connected to the second pixel circuit 20, and the other end of the conductive line L1 is connected to the second light-emitting element 40. Figure 1 As shown, the conductive line L1 extends from the first display area R1 to the second display area R2.

[0068] Figure 2 A schematic diagram of a partial structure of a display panel is shown. Figure 3 To form Figure 2 A schematic diagram of the exposure process for patterning a transparent conductive film during the process of creating the conductive lines shown. Figure 2 (Cross-sectional view at A1, A2, or A3). Figure 4 A schematic diagram for forming a photoresist pattern. Figure 5 This is a schematic diagram illustrating the formation of conductive lines. (Example) Figure 2 and Figure 3 As shown, a first conductive element 111 is located on a substrate BS; a first planarization layer 121 is located on the first conductive element 111; a second conductive element 112 is located on the first planarization layer 121 and is connected to the first conductive element 111 through a first via V1 penetrating the first planarization layer 121; a second planarization layer 122 is located on the second conductive element 112. For example, Figure 3 The first via V1 shown includes Figure 2 The vias shown are V01 or V02. For example... Figure 3 As shown, forming the conductive line L1 includes forming a transparent conductive film F1 on the second planarization layer 122, forming a photoresist film 201 on the transparent conductive film F1, and exposing the photoresist film 201 using a mask 202 as a mask, thereby forming a photoresist retention portion 2011 and a photoresist removal portion 2012 on the photoresist film 201. Figure 4As shown, after the exposure process, a development process is performed. In the development process, the photoresist to be removed 2012 is removed, forming a photoresist pattern 201a. Figure 5 As shown, the transparent conductive film F1 is etched using the photoresist pattern 201a as a mask to form the conductive line L1. Figure 3 The second conductive element 112 in the middle can be Figure 2 The connecting element CE0 or shielding electrode SE is shown.

[0069] like Figure 2 As shown, the conductive lines L1 include multiple lines, including multiple first conductive lines L11 located in the first transparent conductive layer LY01 and multiple second conductive lines L12 located in the second transparent conductive layer LY02. An insulating layer may be disposed between the first transparent conductive layer LY01 and the second transparent conductive layer LY02. In other embodiments, three or more transparent conductive layers may be included to provide more conductive lines. An insulating layer is disposed between adjacent transparent conductive layers.

[0070] After the exposure process, the photoresist in the transparent conductive film experienced exposure breakage and thinning, leading to broken or thinned conductive lines after development and etching, resulting in dark spots in the display. Optical microscopy confirmed that the locations of the broken and thinned conductive lines were where the conductive lines crossed the first via V1 of the first planarization layer 121. Further focused ion beam (FIB) analysis of the cross-section at the first via V1 of the first planarization layer 121 revealed that below the broken or thinned locations of the conductive lines crossing the first via V1, there were bowl-shaped portions of the second conductive element 112. Therefore, if... Figure 3 As shown, the reason for the defects of broken and thinned conductive lines is that during the exposure process, the second conductive element 112 reflects and focuses light onto the photoresist retention portion 2011 of the photoresist located above the bowl-shaped portion of the second conductive element 112 (corresponding to the position of the first via V1), causing this portion of the photoresist to be exposed or partially exposed. After development, it is washed away, resulting in broken and thinned conductive lines formed after etching the transparent conductive film using the photoresist pattern 201a as a mask. Figures 3 to 5 As shown, the photoresist retention portion 2011 of the photoresist located in the middle position is partially irradiated by reflected light, causing the conductive lines below it to become thinner.

[0071] Figure 2 The first light-emitting element 30 is shown, denoted by the first electrode E1 of the first light-emitting element 30. Figure 2 Alternating rows of first and second pixel circuits are shown. In other embodiments, multiple rows of first pixel circuits may be arranged between adjacent rows of second pixel circuits.

[0072] Figure 2A second via V2 is also shown, which includes either via V21 or via V22. Both via V21 and via V22 are vias that penetrate at least one insulating layer. Figure 2 As shown, the first electrode E1 of the first light-emitting element 30 is connected to the connecting element CE0 through the via V21. Figure 2 As shown, one end of the conductive line L1 is connected to the connecting element CE0 through the via V22. The other end of the conductive line L1 is connected to the first electrode E1 of the second light-emitting element 40. That is, the connecting element CE0 is connected to one end of the conductive line L1 through the second via V2, or the connecting element CE0 is connected to the first electrode E1 of the first light-emitting element 30 through the second via V2. For example, the connecting element CE0 connected to the first electrode E1 of the first light-emitting element 30 can be called the first connecting element, and the connecting element CE0 connected to the conductive line L1 can be called the second connecting element.

[0073] The embodiments shown in the accompanying drawings of this disclosure provide a display panel connected to a second pixel circuit and a second light-emitting element via a conductive line L1. In other embodiments, a conductive line may be connected to multiple second light-emitting elements.

[0074] Figure 6 This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure. Figure 7 This is a schematic diagram showing diffuse reflection of light irradiating the side portion of a second conductive element in a display substrate, as provided in an embodiment of the present disclosure. Figure 8 A schematic diagram of a first planarization layer and a first via in a display substrate is provided in one embodiment of this disclosure. (See diagram below.) Figure 6 As shown, the display substrate includes: a substrate BS, a first conductive element 111, a first planarization layer 121, a second conductive element 112, a second planarization layer 122, and conductive lines L1. Figure 6 As shown, the first conductive element 111 is located on the substrate BS; the first planarization layer 121 is located on the first conductive element 111; the second conductive element 112 is located on the first planarization layer 121 and is connected to the first conductive element 111 through the first via V1 penetrating the first planarization layer 121; the second planarization layer 122 is located on the second conductive element 112; and the conductive line L1 is located on the second planarization layer 122.

[0075] For example, the materials of the first planarization layer 121 and the second planarization layer 122 include organic polymer materials, which include, but are not limited to, resins. For example, the materials of the first planarization layer 121 and the second planarization layer 122 include polymethyl methacrylate (PMMA) and polyimide (PI), but are not limited to these.

[0076] like Figure 6 As shown, the second conductive element 112 is recessed at the first via V1, such that the second conductive element 112 has a recessed portion 1121 and a peripheral portion 1122 located outside the recessed portion 1121. The recessed portion 1121 has a bottom 112a and a side portion 112b, and the bottom 112a is connected to the peripheral portion 1122 through the side portion 112b. Figure 6 As shown, the side portion 112b of the recess 1121 has an uneven surface configured to cause diffuse reflection of light incident upon it, thereby, as Figure 7 As shown, during the exposure of photoresist when forming conductive line L1, light gathered on the photoresist retention portion 2011 of the first via V1 is avoided or reduced, thereby preventing the conductive line L1 crossing the first via V1 from breaking or thinning at the first via V1, and avoiding dark spot defects during display.

[0077] In embodiments of this disclosure, the recess 1121 can be considered as the portion of the second conductive element 112 located within the first via V1. For example, the orthographic projection of the recess 1121 on the substrate BS overlaps with the orthographic projection of the first via V1 on the substrate BS.

[0078] like Figure 6 As shown, the uneven surface of the side portion 112b of the recessed portion 1121 is the surface of the side portion 112b that faces away from the substrate BS. Figure 6 As shown, the surface of the side portion 112b of the recessed portion 1121 near the substrate BS is also an uneven surface. For example, the uneven surface includes a plurality of protrusions, with recesses between adjacent protrusions.

[0079] The display substrate provided in the embodiments of this disclosure changes the surface roughness of the second conductive element 112 below the first via V1 of the first planarization layer 121, so that when light shines on the surface of the bowl-shaped portion of the second conductive element 112 during exposure, diffuse reflection occurs, eliminating light concentration and avoiding overexposure of photoresist that could cause the conductive lines to break and become thinner, thereby solving the problem of dark spot defects.

[0080] like Figure 8 As shown, the first planarization layer 121 has an uneven surface at the first via V1 to facilitate the formation of the side portion 112b of the second conductive element 112, which has an uneven surface.

[0081] For example, such as Figure 7 and Figure 8 As shown, the first planarization layer 121 has an uneven surface at the position of the corresponding side 112b, and the second conductive element 112 is conformally disposed thereon.

[0082] For example, such as Figure 6As shown, side portion 112b forms an angle θ with the substrate BS. Accordingly, as Figure 8 As shown, the portion of the first planarization layer 121 forming the first via V1 also has an angle θ with the substrate BS. In other words, the side portion 112b is inclined relative to the main surface of the substrate BS, and the portion of the first planarization layer 121 forming the first via V1 is inclined relative to the main surface of the substrate BS. The angle θ is an acute angle. For example, the angle θ is greater than or equal to 20 degrees and less than or equal to 80 degrees, but is not limited thereto. For example, the angle θ is greater than or equal to 30 degrees and less than or equal to 60 degrees, but is not limited thereto. The embodiments of this disclosure do not limit the value of the angle. For example, since the side portion 112b may not be smooth or may not be flat, the angle between the side portion 112b and the substrate BS may refer to the angle between the extension trend of the side portion 112b and the substrate BS, or the angle between the side portion 112b and the substrate BS may refer to the angle between the line connecting the two endpoints of the side portion 112b and the substrate BS. For example, since the portion of the first planarization layer 121 that forms the first via V1 may not be smooth or flat, the angle between the portion of the first planarization layer 121 that forms the first via V1 and the substrate BS can refer to the angle between the extension trend of the portion of the first planarization layer 121 that forms the first via V1 and the substrate BS. The angle between the portion of the first planarization layer 121 that forms the first via V1 and the substrate BS can refer to the angle between the line connecting the two endpoints of the portion of the first planarization layer 121 that forms the first via V1 and the substrate BS.

[0083] For example, such as Figure 6 As shown, in some embodiments, the bottom 112a of the recess 1121 refers to the portion of the recess 1121 that contacts the first conductive element 111, and the side 112b of the recess 1121 refers to the portion of the recess 1121 that contacts the portion of the first planarization layer 121 that forms the first via, but is not limited thereto.

[0084] The accompanying drawings of embodiments of this disclosure illustrate at least one of a first direction X, a second direction Y, and a third direction Z. The main surface of the substrate BS is the surface on which the various components are disposed. The first direction X and the second direction Y are parallel to the main surface of the substrate BS, and the third direction Z is perpendicular to the main surface of the substrate BS. For example, the first direction X and the second direction Y intersect. Further, for example, the first direction X is perpendicular to the second direction Y.

[0085] For example, such as Figure 6As shown, the peripheral portion 1122 is parallel to the substrate BS. In embodiments of this disclosure, the peripheral portion 1122 can be considered as the portion of the second conductive element 112 located outside the first via V1. For example, the orthographic projection of the peripheral portion 1122 on the substrate BS does not overlap with the orthographic projection of the first via V1 on the substrate BS.

[0086] For example, such as Figure 6 As shown, the first planarization layer 121 has a flat surface except for the portion located at the sidewall of the first via V1. For example, as Figure 6 As shown, the bottom 112a of the second conductive element 112 is parallel to the outer periphery 1122. That is, in some embodiments, the second conductive element 112 has an uneven surface only at the position corresponding to the sidewall of the first via V1.

[0087] For example, the material of the second conductive element 112 includes a metal, such as at least one of titanium, molybdenum, and aluminum, but is not limited thereto. For example, the material of the conductive line L1 includes a transparent conductive material, as described above, and will not be repeated here.

[0088] Figure 9 This is a schematic diagram illustrating the formation of a first planarization layer during the fabrication of a display substrate, as provided in one embodiment of this disclosure. Figure 9 As shown, after forming the first conductive element 111 on the substrate BS, a first planarization film 1210 is formed. The first planarization film 1210 is exposed using a half-tone mask 302. After the exposure process, a development process is performed to form... Figure 8 The first planarization layer 121 is shown. For example, as... Figure 9 As shown, the halftone mask 302 includes a light-transmitting area 3021, an opaque area 3023, and a halftone area 3022. The light transmittance of the halftone area 3022 is between that of the light-transmitting area 3021 and the opaque area 3023. Figure 9 The outline of the first planarization layer is shown by dashed lines.

[0089] Figure 10A This is a schematic diagram of a display substrate provided according to an embodiment of the present disclosure. For example... Figure 10A As shown, the surface of the portion of the first planarization layer 121 that forms the first via V1 is smooth; that is, the sidewalls of the first planarization layer 121 that form the first via V1 are smooth, not uneven. Correspondingly, the surface of the second conductive element 112 that contacts the first planarization layer 121 is also smooth. Figure 10A As shown, the surface of the side portion 112b of the second conductive element 112 that faces away from the substrate BS is uneven.

[0090] Figure 10B Formation provided for an embodiment of this disclosure Figure 10A A schematic diagram of the second conductive element in the display substrate shown. For example, as... Figure 10B As shown, after the intermediate element 1120 is formed, it is bombarded with ions. Figure 10B As shown, ion bombardment of the surface of the bowl-shaped structure at the location of the first via V1 of the first planarization layer 121 in the intermediate element 1120 causes the surface of the intermediate element 1120 to become rough and uneven, forming Figure 10A The second conductive element 112 is shown. (As shown) Figure 10B As shown, in the ion bombardment process, mask 402 is used as a mask to make a portion of the surface of the intermediate element 1120 uneven, while the rest of the surface of the intermediate element 1120 is smooth. Figure 10B As shown, the mask 402 includes a masking area 4022 and a non-masking area 4021. The non-masking area 4021 corresponds to the sidewall of the first via V1 of the first planarization layer 121, and the masking area 4022 corresponds to the remaining positions.

[0091] Figure 10C This is a schematic diagram of a display substrate provided for another embodiment of the present disclosure. Figure 10C The display substrate shown is Figure 10A Compared to the display substrate shown, the bottom 112a of the second conductive element 112 also has an uneven, rough surface.

[0092] Figure 10D This is a schematic diagram of a display substrate provided for another embodiment of the present disclosure. Figure 10D The display substrate shown is Figure 10A Compared to the display substrate shown, the bottom 112a and side 112b of the second conductive element 112 also have uneven, rough surfaces. For example, in Figure 10D In the display substrate shown, the second conductive element 112 has an uneven, rough surface at various locations, i.e., as shown... Figure 10D As shown, the recessed portion 1121, bottom 112a, side portion 112b, and peripheral portion 1122 of the second conductive element 112 all have uneven, rough surfaces. During the formation of... Figure 10C When the second conductive element 112 of the display substrate is shown, the non-shaded area 4021 of the mask corresponds to the bottom wall and side wall of the first via V1 of the first planarization layer 121, during the formation of Figure 10D When the second conductive element 112 of the display substrate is shown, the mask can be the same as the mask used to form the intermediate element 1120.

[0093] Figure 11AThis is a schematic diagram of a second conductive element in a display substrate provided for an embodiment of the present disclosure. Figure 11B This is a schematic diagram of a second conductive element in a display substrate, provided as another embodiment of this disclosure. Figure 11A Compared to the second conductive element 112 shown, Figure 11B The lower surface of the side portion 112b of the second conductive element 112 shown is smooth, not uneven. Figure 11A and Figure 11B The side portion 112b of the second conductive element 112 shown can diffusely reflect the light that shines on it, thereby avoiding defects such as broken or thinned conductive wires.

[0094] Figure 11C This is a schematic diagram of a partial structure of a display substrate provided in one embodiment of the present disclosure. For example... Figure 11C and Figure 2 As shown, the first conductive element 111 is Figure 2 The connecting electrode CE01 shown is the second conductive element 112. Figure 2 The connecting electrode CE02 is shown. The first electrode E1 of the light-emitting element of the first pixel unit is connected to the connecting electrode CE02 through the via V21. That is, the connecting electrode CE02 has a rough surface with unevenness.

[0095] Figure 11D This is a schematic diagram of a partial structure of a display substrate provided in one embodiment of the present disclosure. For example... Figure 11D and Figure 2 As shown, the first conductive element 111 is Figure 2 The connecting electrode CE01 shown is the second conductive element 112. Figure 2 The connecting electrode CE02 is shown. The conductive line L1 is connected to the connecting electrode CE02 through the via V22. That is, the connecting electrode CE02 has a rough surface with unevenness.

[0096] For example, refer to Figure 2 , Figure 11C and Figure 11D The first conductive element 111 and the connecting electrode CE01 are located on the same layer, and the second conductive element 112 and the connecting electrode CE02 are located on the same layer. In this case, the first conductive element 111 and the connecting electrode CE01 are the same component, and the second conductive element 112 and the connecting electrode CE02 are the same component; or, the first conductive element 111 refers to the constant voltage line L0, and the second conductive element 112 refers to the shielding electrode SE.

[0097] Figure 11E This is a schematic diagram of a partial structure of a display substrate provided in one embodiment of the present disclosure. For example... Figure 11E and Figure 2As shown, the first conductive element 111 is Figure 2 The constant voltage line L0 shown has a second conductive element 112. Figure 2 The shielding electrode SE shown is a structure with an uneven, rough surface.

[0098] For example, refer to Figure 2 and Figure 11E The first conductive element 111 is located on the same layer as the constant voltage line L0, and the second conductive element 112 is located on the same layer as the shielding electrode SE. In this case, the first conductive element 111 and the constant voltage line L0 are the same component, and the second conductive element 112 and the shielding electrode SE are the same component; or, the first conductive element 111 refers to the connecting electrode CE01, and the second conductive element 112 refers to the connecting electrode CE02.

[0099] refer to Figure 2 , Figures 11C to 11E The connecting electrode CE02 and the shielding electrode SE are located in the fourth conductive layer LY4, and the constant voltage line L0 and the connecting electrode CE01 are located in the third conductive layer LY3.

[0100] Figure 11F This is a schematic diagram of a partial structure of a display substrate provided in an embodiment of the present disclosure. For clarity, Figure 11F Only the conductive line L1 connected to the connecting element CE0 is shown; the other conductive lines are not shown. The other conductive lines can be found by referring to... Figure 2 .

[0101] For example, to prevent conductive lines from breaking or becoming thinner, the connection electrode CE02 or shielding electrode SE located in the fourth conductive layer LY4 of the display substrate adopts the aforementioned structure with an uneven, rough surface. In some embodiments, such as Figure 11F As shown, both the connection electrode CE02 and the shielding electrode SE located in the fourth conductive layer LY4 of the display substrate adopt the aforementioned structure with an uneven, rough surface. That is, at least one of the connection electrode CE02 or the shielding electrode SE located in the fourth conductive layer LY4 of the display substrate adopts the aforementioned structure with an uneven, rough surface.

[0102] For example, the second connecting electrode is recessed at the via where the second connecting electrode and the first connecting electrode are connected, such that the second connecting electrode has a recessed portion and a peripheral portion located outside the recessed portion. The recessed portion of the second connecting electrode has a bottom and a side portion. The bottom of the second connecting electrode is connected to the peripheral portion of the second connecting electrode through the side portion of the second connecting electrode. The side portion of the second connecting electrode has an uneven surface configured to cause diffuse reflection of light incident upon it.

[0103] For example, the shielding electrode is recessed at the via where the shielding electrode is connected to the constant voltage line, such that the shielding electrode has a recessed portion and an outer peripheral portion located outside the recessed portion. The recessed portion of the shielding electrode has a bottom and a side portion. The bottom of the shielding electrode is connected to the outer peripheral portion of the shielding electrode through the side portion of the shielding electrode. The side portion of the shielding electrode has an uneven surface configured to cause diffuse reflection of light incident upon it.

[0104] Of course, in some embodiments of the display substrate provided in this disclosure, the shielding electrode SE may not be provided. In this case, the first conductive element 111 may be the connecting electrode CE01, and the second conductive element 112 may be the connecting electrode CE02. In some embodiments of the display substrate provided in this disclosure, the second conductive element 112 may also be other elements located in the fourth conductive layer LY4. This element may be connected to elements in the first conductive layer LY1, the second conductive layer LY2, or the third conductive layer LY3 through vias. In this case, the elements in the fourth conductive layer LY4 may also have an uneven, rough surface to prevent the conductive line L1 crossing the via from breaking or becoming thinner. Figures 11C to 11E Insulating layers 131 and 132 are also shown. An insulating layer 131 is provided between the second conductive line L12 and the first conductive line L11. An insulating layer 132 is provided between the second conductive line L12 and the first electrode E1 of the light-emitting element.

[0105] like Figures 11C to 11E As shown, in some embodiments, the conductive line L1 is in contact with the upper surface of the second planarization layer 122, but is not limited thereto. For example, the upper surface of the second planarization layer 122 refers to the surface of the second planarization layer 122 that faces away from the substrate BS.

[0106] like Figures 11C to 11E As shown, in some embodiments, the second conductive element 112 is in contact with the upper surface of the first planarization layer 121, but is not limited thereto. For example, the upper surface of the first planarization layer 121 refers to the surface of the first planarization layer 121 that faces away from the substrate BS.

[0107] In the display panel provided in the embodiments of this disclosure, the shape of the protrusions and depressions in the uneven surface is not limited.

[0108] For example, refer to Figure 1 The display substrate also includes a pixel unit 100. The pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102. The pixel circuit 10 and the light-emitting element 30 of the first pixel unit 101 are both located in the first display area R1. The pixel circuit 20 of the second pixel unit 102 is located in the first display area R1. The light-emitting element 40 of the second pixel unit 102 is located in the second display area R2. The pixel circuit 20 of the second pixel unit 102 is connected to the light-emitting element 40 of the second pixel unit 102 through a conductive line L1.

[0109] For example, refer to Figure 1 The orthographic projection of the pixel circuit 10 of the first pixel unit 101 on the substrate BS and the orthographic projection of the light-emitting element 30 of the first pixel unit 101 on the substrate BS overlap at least partially, while the orthographic projection of the pixel circuit 20 of the second pixel unit 102 on the substrate BS and the orthographic projection of the light-emitting element 40 of the second pixel unit 102 on the substrate BS do not overlap.

[0110] refer to Figure 2 The orthographic projection of the conductive line L1 on the substrate BS overlaps with the orthographic projection of the pixel circuit 10 of the first pixel unit 101 on the substrate BS. Figure 2 The location of the shielding electrode can be considered as the location of the pixel circuit.

[0111] For example, refer to Figure 1 The display substrate also includes a connecting element CE0. The pixel circuit of the pixel unit 100 is connected to the conductive line L1 or to the light-emitting element 30 of the first pixel unit 101 through the connecting element CE0.

[0112] For example, refer to Figure 1 and Figure 2 The second conductive element 112 includes the portion of the connecting element CE0 connected to the conductive line L1, or, refer to Figure 2 The second conductive element 112 includes a portion of the connecting element CE0 that is connected to the light-emitting element 30 of the first pixel unit 101. For example, refer to... Figure 2 The connecting element CE0 includes a connecting electrode (first connecting electrode) CE01 and a connecting electrode (second connecting electrode) CE02. Connecting electrodes CE01 and CE02 can be connected through a via penetrating the insulating layer. For example, the material of connecting electrode CE01 includes metal, and the material of connecting electrode CE02 includes metal. For example, in some embodiments, Figure 3 The first conductive element 111 shown can be Figure 2 The connecting electrode CE01 shown is... Figure 3 The second conductive element 112 shown can be Figure 2 The connection electrode CE02 is shown. (As shown) Figure 2 As shown, the connecting electrode CE02 is connected to the connecting electrode CE01 through the via V01. For example, in some embodiments, Figure 3 The first conductive element 111 shown can be a constant voltage line L0. Figure 3 The second conductive element 112 shown can be Figure 2 The shielding electrode SE is shown. (As shown in the image) Figure 3 As shown, the shielding electrode SE is connected to the constant voltage line L0 through the via V02.

[0113] For example, refer to Figure 2 The conductive line L1 is configured as multiple lines, and at least one of the multiple conductive lines L1 overlaps with the orthographic projection of the first via V1 on the substrate BS.

[0114] Figure 6 , Figure 10A , Figure 10C , Figure 10D The display panel shown omits the components between the substrate and the first conductive element. Figure 11A and Figure 11B The display panel shown illustrates the structure of the second conductive element 112 and demonstrates how the diffuse reflection of the uneven surface avoids affecting the photoresist retention area.

[0115] Figure 12A This is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure. Figure 12B This is a layout diagram of pixel circuits in a display panel according to an embodiment of the present disclosure. Figure 12C for Figure 12B A sectional view along line AB.

[0116] Figure 12A The pixel circuit shown can be the pixel circuit of a low-temperature polysilicon (LTPS) AMOLED.

[0117] Figure 12A The pixel circuit of a pixel unit of the display panel is shown, such as Figure 12A As shown, pixel unit 100 includes pixel circuit 100a and light-emitting element 100b. Pixel circuit 100a is configured to drive light-emitting element 100b. For example, pixel circuit 100a is configured to provide driving current to drive light-emitting element 100b to emit light. For example, light-emitting element 100b is an organic light-emitting diode (OLED), and light-emitting element 100b emits red light, green light, blue light, or white light under the drive of its corresponding pixel circuit 100a. The color emitted by light-emitting element 100b can be determined as needed. Pixel circuit 100a includes the first pixel circuit 10 or the second pixel circuit 20 described above. Light-emitting element 100b includes the first light-emitting element 30 or the second light-emitting element 40 described above.

[0118] like Figure 12A and Figure 12BAs shown, pixel circuit 100a includes six switching transistors (T2-T7), one driving transistor T1, and one storage capacitor Cst. The six switching transistors are a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, and a second reset transistor T7. Light-emitting element 100b includes a first electrode E1 and a second electrode E2, and a light-emitting functional layer located between the first electrode E1 and the second electrode E2. For example, the first electrode E1 is the anode, and the second electrode E2 is the cathode. Typically, the threshold compensation transistor T3 and the first reset transistor T6 employ a dual-gate thin-film transistor (TFT) to reduce leakage current.

[0119] like Figure 12A and Figure 12BAs shown, the display panel includes a gate line GT, a data line DT, a first power line PL1, a second power line PL2, a light emission control signal line EML, an initialization signal line INT, and a reset control signal line RST. For example, the reset control signal line RST includes a first reset control signal line RST1 and a second reset control signal line RST2. The first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel unit 100, and the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel unit 100, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The gate line GT is configured to provide a scan signal SCAN to the pixel unit 100, the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 100, the light emission control signal line EML is configured to provide a light emission control signal EM to the pixel unit 100, the first reset control signal line RST1 is configured to provide a first reset control signal RESET1 to the pixel unit 100, and the second reset control signal line RST2 is configured to provide a scan signal SCAN to the pixel unit 100. For example, in a row of pixel units, the second reset control signal line RST2 can be connected to the gate line GT to be input to the scan signal SCAN. Alternatively, the second reset control signal line RST2 can also be input to the second reset control signal RESET2. The first initialization signal line INT1 is configured to provide a first initialization signal Vinit1 to the pixel unit 100. The second initialization signal line INT2 is configured to provide a second initialization signal Vinit2 to the pixel unit 100. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, the magnitude of which can be, for example, between the first voltage signal VDD and the second voltage signal VSS, but is not limited thereto. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 can both be less than or equal to the second voltage signal VSS. For example, in some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 are connected and both are configured to provide the initialization signal Vinit to the pixel unit 100; that is, the first initialization signal line INT1 and the second initialization signal line INT2 are both called initialization signal lines INT, and the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal, both being Vinit.

[0120] like Figure 12A and Figure 12B As shown, the driving transistor T1 is electrically connected to the light-emitting element 100b, and outputs a driving current to drive the light-emitting element 100b to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS.

[0121] For example, the light-emitting element 100b includes an organic light-emitting diode (OLED), which emits red, green, blue, or white light under the drive of its corresponding pixel circuit 100a. For example, a pixel includes multiple pixel units. A pixel may include multiple pixel units that emit different colors of light. For example, a pixel may include pixel units that emit red light, pixel units that emit green light, and pixel units that emit blue light, but is not limited to these. The number of pixel units included in a pixel and the light emission characteristics of each pixel unit can be determined as needed.

[0122] For example, such as Figure 12A and Figure 12B As shown, the gate T20 of the data writing transistor T2 is connected to the gate line GT, the first terminal T21 of the data writing transistor T2 is connected to the data line DT, and the second terminal T22 of the data writing transistor T2 is connected to the first terminal T11 of the driving transistor T1.

[0123] For example, such as Figure 12A and Figure 12B As shown, the gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, the first terminal T31 of the threshold compensation transistor T3 is connected to the second terminal T12 of the driving transistor T1, and the second terminal T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.

[0124] For example, such as Figure 12A and Figure 12B As shown, the gate T40 of the first light-emitting control transistor T4 is connected to the light-emitting control signal line EML, the first terminal T41 of the first light-emitting control transistor T4 is connected to the first power supply line PL1, and the second terminal T42 of the first light-emitting control transistor T4 is connected to the first terminal T11 of the driving transistor T1; the gate T50 of the second light-emitting control transistor T5 is connected to the light-emitting control signal line EML, the first terminal T51 of the second light-emitting control transistor T5 is connected to the second terminal T12 of the driving transistor T1, and the second terminal T52 of the second light-emitting control transistor T5 is connected to the first terminal E1 of the light-emitting element 100b.

[0125] like Figure 12A and Figure 12BAs shown, the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate of the driving transistor T1. The second reset transistor T7 is connected to the first terminal E1 of the light-emitting element 100b and is configured to reset the first terminal E1 of the light-emitting element 100b. The first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6. The second initialization signal line INT2 is connected to the first terminal E1 of the light-emitting element 100b through the second reset transistor T7. For example, the first initialization signal line INT1 and the second initialization signal line INT2 are connected so that they are input with the same initialization signal, but this is not a limitation. In some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 may also be isolated from each other and configured to input signals separately.

[0126] For example, such as Figure 12A and Figure 12B As shown, the first terminal T61 of the first reset transistor T6 is connected to the first initialization signal line INT1, and the second terminal T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1. The first terminal T71 of the second reset transistor T7 is connected to the second initialization signal line INT2, and the second terminal T72 of the second reset transistor T7 is connected to the first terminal E1 of the light-emitting element 100b. For example, as... Figure 12A As shown, the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RST1, and the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RST2.

[0127] like Figure 12A As shown, the first power line PL1 is configured to provide a first voltage signal VDD to the pixel circuit 100a; the pixel circuit also includes a storage capacitor Cst, the first terminal Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, and the second terminal Cb of the storage capacitor Cst is connected to the first power line PL1.

[0128] For example, such as Figure 12A As shown, the second power line PL2 is connected to the second electrode E2 of the light-emitting element 100b.

[0129] Figure 12A The diagram illustrates a first node N1, a second node N2, a third node N3, and a fourth node N4. For example, in some embodiments, reference is made to... Figure 12A A capacitor is formed between the first node N1 and the conductive line L1, and a capacitor is formed between the conductive line L1 and the fourth node N4. The conductive line L1 is coupled to the first node N1 and the fourth node N4 respectively, which causes brightness differences and creates display defects such as mura, affecting display quality.

[0130] like Figure 12B As shown, the driving transistor T1 includes a gate T10. (Reference) Figure 12B and 12C The storage capacitor Cst has a second electrode Cb with an opening OPN1. One end of the connecting electrode CE1 is connected to the gate T10 of the driving transistor T1 through the opening OPN1. The connecting electrode CE1 can also be called the first gate signal line SL1. Figure 12B As shown, the first gate signal line SL1 is connected to the gate T10 of the driving transistor T1.

[0131] like Figure 12B As shown, the first gate signal line SL1 is connected to the second gate signal line SL2. The gate T10 of the driving transistor T1, the first gate signal line SL1, and the second gate signal line SL2 constitute the gate signal section PT1. The potentials on the gate signal section PT1 are the same. Of course, in other embodiments, the second gate signal line SL2 may not be provided. In this case, the gate T10 of the driving transistor T1 and the first gate signal line SL1 constitute the gate signal section PT1. For example, the second gate signal line SL2 is the second terminal T62 of the first reset transistor T6.

[0132] refer to Figure 12B and Figure 12C To stabilize the potential on the gate signal section PT1, the display panel provided in the embodiments of this disclosure provides a shielding electrode SE and a constant voltage line L0, wherein the constant voltage line L0 is configured to provide a constant voltage to the pixel circuit. The shielding electrode SE is connected to the constant voltage line L0, thereby stabilizing the voltage on the shielding electrode SE and providing a shielding effect to prevent the conductive line L1 from affecting the potential on the gate signal section PT1. The orthographic projection of the first gate signal line SL1 on the substrate BS falls within the orthographic projection of the shielding electrode SE on the substrate BS.

[0133] refer to Figure 12B In order to make the shielding electrode play a better shielding role and increase the shielding amount, the orthogonal projection of the first gate signal line SL1 on the substrate BS falls completely within the orthogonal projection of the shielding electrode SE on the substrate BS.

[0134] For example, to mitigate mura and improve display quality, the distance between the orthographic projection of the first gate signal line SL1 onto the substrate BS and the boundary of the orthographic projection of the shielding electrode SE onto the substrate BS is greater than or equal to 1.75 μm. Because the area occupied by a pixel unit is limited, the distance of the shielding electrode SE extending beyond the first gate signal line SL1 can be limited. For example, in some embodiments, to achieve better shielding, the distance between the boundary of the orthographic projection of the first gate signal line SL1 onto the substrate BS and the boundary of the orthographic projection of the shielding electrode SE onto the substrate BS is greater than or equal to 2.33 μm.

[0135] like Figure 12B As shown, the display panel also includes a stop block BK, which is connected to the first power line PL1. The threshold compensation transistor T3 includes a first channel CN1 and a second channel CN2, which are connected by a conductive connection CP. The orthographic projection of the stop block BK on the substrate BS at least partially overlaps with the orthographic projection of the conductive connection CP of the threshold compensation transistor T3 on the substrate BS. Figure 12B As shown, the block BK of the adjacent column pixel unit is used to block the conductive connection part CP of the threshold compensation transistor T3 of the same column pixel unit.

[0136] For example, such as Figure 12B As shown, when the display panel includes a second gate signal line SL2, the second gate signal line SL2 is connected to the first gate signal line SL1, and the orthographic projection of the second gate signal line SL2 on the substrate BS falls within the orthographic projection of the stop block BK on the substrate BS. Further, for example, the boundary of the orthographic projection of the stop block BK on the substrate BS extends beyond the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS. For example, the distance by which the boundary of the orthographic projection of the stop block BK on the substrate BS extends beyond the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 1.75 μm. For example, the distance by which the boundary of the orthographic projection of the stop block BK on the substrate BS extends beyond the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 2.33 μm. Of course, in other embodiments, a shielding electrode SE can be used instead of the stop block BK, or the orthographic projection of the second gate signal line SL2 on the substrate BS falls within both the orthographic projection of the stop block BK on the substrate BS and the orthographic projection of the shielding electrode SE on the substrate BS.

[0137] For example, the first gate signal line SL1 and the second gate signal line SL2 are made of different materials. For example, the first gate signal line SL1 is made of a metal, while the second gate signal line SL2 is made of a conductive material formed by conductor-forming a semiconductor material.

[0138] For example, such as Figure 12BAs shown, to save wiring, the first power line PL1 is used as the constant voltage line L0. In other embodiments, to save wiring, the first initialization signal line INL1 or the second initialization signal line INL2 can also be used as the constant voltage line. Examples of the constant voltage line L0 are not limited to the first power line PL1, the first initialization signal line INL1, and the second initialization signal line INL2; any signal line that provides a constant voltage in the pixel circuit can be used as the constant voltage line L0. The embodiments of this disclosure are described using the first power line PL1 as the constant voltage line L0 as an example. When using a signal line that provides a constant voltage other than the first power line PL1 as the constant voltage line L0, the shape of the shielding electrode SE can be adjusted so that it is connected to the signal line that provides a constant voltage.

[0139] For example, in some embodiments, a pixel unit includes a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the light-emitting element and includes a driving transistor, which includes a gate. The display substrate further includes: a first gate signal line connected to the gate of the driving transistor; a constant voltage line configured to provide a first constant voltage to the pixel circuit; and a shielding electrode connected to the constant voltage line, wherein the orthographic projection of the first gate signal line on the substrate BS falls within the orthographic projection of the shielding electrode SE on the substrate BS. For example, the second conductive element 112 includes a portion of the shielding electrode SE connected to the constant voltage line L0.

[0140] For example, the orthographic projection of the conductive line L1 onto the substrate BS overlaps with the orthographic projection of the pixel circuit (first pixel circuit 10) of the first pixel unit 101 onto the substrate BS. For example, the shielding electrode SE is located between the conductive line L1 and the first gate signal line SL1. In embodiments of this disclosure, after the pixel circuit is formed, the shielding electrode SE is formed, then the conductive line L1 is formed, and then the light-emitting element is formed. Thus, the shielding electrode SE is located between the conductive line L1 and the first gate signal line SL1, and between the conductive line L1 and the gate T10 of the driving transistor.

[0141] For example, the orthographic projection of the conductive line L1 on the substrate BS overlaps with the orthographic projection of the first gate signal line SL1 in the pixel circuit of the first pixel unit 101.

[0142] Reference 12C and Figure 12BA buffer layer BL is disposed on the substrate BS, an isolation layer BR is disposed on the buffer layer BL, an active layer LY0 is disposed on the isolation layer BR, a first insulating layer ISL1 is disposed on the active layer LY0, a first conductive layer LY1 is disposed on the first insulating layer ISL1, a second insulating layer ISL2 is disposed on the first conductive layer LY1, a second conductive layer LY2 is disposed on the second insulating layer ISL2, a third insulating layer ISL3 is disposed on the second conductive layer LY2, and a third conductive layer LY3 is disposed on the third insulating layer ISL3. The third conductive layer LY3 includes a connection electrode CE01, which passes through the first insulating layer ISL1. 1. Vias H3 of the second insulating layer ISL2 and the third insulating layer ISL3 are connected to the second electrode T52 of the second light-emitting control transistor T5. A fourth insulating layer and a fifth insulating layer are disposed on the third conductive layer LY3. A fourth conductive layer LY4 is disposed on the fourth and fifth insulating layers. The fourth conductive layer LY4 includes a connecting electrode CE02. The connecting electrode CE02 is connected to a connecting electrode CE01 through a via H22 penetrating the fourth and fifth insulating layers. A sixth insulating layer is disposed on the fourth conductive layer LY4. The light-emitting element 100b (first light-emitting element 30) is connected to the connecting electrode CE02 through a via penetrating the sixth insulating layer. The light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer located between the first electrode E1 and the second electrode E2. For example, the connecting element CE0 includes a connecting electrode CE01 and a connecting electrode CE02.

[0143] like Figure 12B As shown, one end of the connecting electrode CE1 is connected to the gate T10 of the driving transistor T1 through via H1, and the other end of the connecting electrode CE1 is connected to the second terminal T62 of the first reset transistor T6 through via H2. One end of the connecting electrode CE2 is connected to the first initialization signal line INL1 through via H4, and the other end of the connecting electrode CE2 is connected to the first terminal T61 of the first reset transistor T6 through via H5. One end of the connecting electrode CE3 is connected to the second initialization signal line INL2 through via H6, and the other end of the connecting electrode CE3 is connected to the first terminal T71 of the second reset transistor T7 through via H7. The first power line PL1 is connected to the first terminal T41 of the first light-emitting control transistor T4 through via H8. The first power line PL1 is connected to the second terminal Cb of the storage capacitor Cst through via H9. The first power line PL1 is connected to the stop block BK through via Hk. The data line DT is connected to the first terminal T21 of the data writing transistor T2 through via H0.

[0144] For example, in the manufacturing process of a display panel, a self-aligned process is used to conduct the semiconductor pattern layer using the first conductive layer LY1 as a mask. The semiconductor pattern layer can be formed by patterning a semiconductor thin film. For example, ion implantation is used to heavily dope the semiconductor pattern layer, thereby making the portion of the semiconductor pattern layer not covered by the first conductive layer LY1 conductive, forming the source region (first pole T11) and drain region (second pole T12) of the driving transistor T1, the source region (first pole T21) and drain region (second pole T22) of the data writing transistor T2, the source region (first pole T31) and drain region (second pole T32) of the threshold compensation transistor T3, the source region (first pole T41) and drain region (second pole T42) of the first light-emitting control transistor T4, the source region (first pole T51) and drain region (second pole T52) of the second light-emitting control transistor T5, the source region (first pole T61) and drain region (second pole T62) of the first reset transistor T6, and the source region (first pole T71) and drain region (second pole T72) of the second reset transistor T7. The portion of the semiconductor patterned layer covered by the first conductive layer LY1 retains semiconductor properties, forming the channel region of the driving transistor T1, the channel region of the data writing transistor T2, the channel region of the threshold compensation transistor T3, the channel region of the first light-emitting control transistor T4, the channel region of the second light-emitting control transistor T5, the channel region of the first reset transistor T6, and the channel region of the second reset transistor T7. For example, as... Figure 12B As shown, the second terminal T72 of the second reset transistor T7 and the second terminal T52 of the second light-emitting control transistor T5 are integrally formed; the first terminal T51 of the second light-emitting control transistor T5, the second terminal T12 of the driving transistor T1, and the first terminal T31 of the threshold compensation transistor T3 are integrally formed; the first terminal T11 of the driving transistor T1, the second terminal T22 of the data writing transistor T2, and the second terminal T42 of the first light-emitting control transistor T4 are integrally formed; the second terminal T32 of the threshold compensation transistor T3 and the second terminal T62 of the first reset transistor T6 are integrally formed. In some embodiments, such as Figure 12B As shown, the first electrode T71 of the second reset transistor T7 and the first electrode T61 of the first reset transistor T6 can be integrally formed.

[0145] For example, the channel region of the transistor used in this embodiment can be monocrystalline silicon, polycrystalline silicon (e.g., low-temperature polycrystalline silicon), or metal-oxide-semiconductor (MODS) materials (e.g., IGZO, AZO, etc.). In one embodiment, the transistor is a P-type low-temperature polycrystalline silicon (LTPS) thin-film transistor. In another embodiment, the threshold compensation transistor T3 and the first reset transistor T6, which are directly connected to the gate of the driving transistor T1, are MODS thin-film transistors, that is, the channel material of the transistor is a MODS material (e.g., IGZO, AZO, etc.). MODS thin-film transistors have lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.

[0146] For example, the transistors used in the embodiments of this disclosure may include various structures, such as top-gate, bottom-gate, or dual-gate structures. In one embodiment, the threshold compensation transistor T3 and the first reset transistor T6, which are directly connected to the gate of the driving transistor T1, are dual-gate thin-film transistors, which can help reduce the gate leakage current of the driving transistor T1.

[0147] For example, the display panel also includes a pixel definition layer and spacers. The pixel definition layer has openings configured to define the light-emitting area (light-emitting region, effective light-emitting area) of the pixel unit. The spacers are configured to support a fine metal mask during the formation of the light-emitting functional layer.

[0148] For example, the opening in the pixel definition layer is the light-emitting area of ​​the pixel unit. The light-emitting functional layer is located above the first electrode E1 of the light-emitting element 100b, and the second electrode E2 of the light-emitting element 100b is located on the light-emitting functional layer. For example, an encapsulation layer is disposed on the light-emitting element 100b. The encapsulation layer includes a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. For example, the first and third encapsulation layers are inorganic material layers, and the second encapsulation layer is an organic material layer. For example, the first electrode E1 is the anode of the light-emitting element 100b, and the second electrode E2 is the cathode of the light-emitting element 100b, but this is not limited to these examples.

[0149] For example, such as Figure 12B As shown, the orthographic projection of the gate T10 of the driving transistor T1 onto the substrate BS falls within the orthographic projection of the shielding electrode SE onto the substrate BS.

[0150] For example, such as Figure 12BAs shown, when the display panel includes a second gate signal line SL2, the second gate signal line SL2 is connected to the first gate signal line SL1, and the orthographic projection of the second gate signal line SL2 on the substrate BS also falls within the orthographic projection of the shielding electrode SE on the substrate BS. Further, for example, the boundary of the orthographic projection of the shielding electrode SE on the substrate BS extends beyond the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS. For example, the distance by which the boundary of the orthographic projection of the shielding electrode SE on the substrate BS extends beyond the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 1.75 μm. For example, the distance by which the boundary of the orthographic projection of the shielding electrode SE on the substrate BS extends beyond the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 2.33 μm.

[0151] For example, such as Figure 12B As shown, the orthographic projections of the gate T10 of the driving transistor T1, the first gate signal line SL1, and the second gate signal line SL2 on the substrate BS all fall within the orthographic projection of the shielding electrode SE on the substrate BS.

[0152] For example, such as Figure 12B As shown, the orthographic projection of the shielding electrode SE on the substrate BS overlaps with the orthographic projection of the second gate signal line SL2 on the substrate BS, and the orthographic projection of the block BK on the substrate BS overlaps with the orthographic projection of the second gate signal line SL2 on the substrate BS. Therefore, in Figure 12B In the display panel shown, the shielding electrode SE and the stop block BK form a double layer of shielding for the second gate signal line SL2.

[0153] For example, such as Figure 12B As shown, the orthographic projection of the shielding electrode SE on the substrate BS overlaps with the orthographic projection of the block BK on the substrate BS.

[0154] Of course, in other embodiments, the stop block BK may not be provided, or the orthographic projection of the stop block BK on the substrate BS may not overlap with the orthographic projection of the second gate signal line SL2 on the substrate BS.

[0155] For example, such as Figure 12B As shown, the orthographic projection of the stop block BK on the substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 on the substrate BS, and the orthographic projection of the shielding electrode SE on the substrate BS partially overlaps with the orthographic projection of the first gate signal line SL1 on the substrate BS. Therefore, the stop block BK and the shielding electrode SE together provide shielding for the gate signal section PT1. Of course, in some other embodiments, the stop block BK may not be provided, or the orthographic projection of the stop block BK on the substrate BS may not overlap with the orthographic projection of the second gate signal line SL2 on the substrate BS.

[0156] For example, such as Figure 12B As shown, the left-side block BK extends to the left-side pixel unit of the pixel unit shown in the figure, blocking the conductive connection portion CP of its threshold compensation transistor T3, while the right-side block BK extends from the block BK connected to the right-side pixel unit shown in the figure.

[0157] like Figure 12B As shown, the channels of each transistor and the first and second electrodes located on both sides of the channel are located in the active layer LY0; the first reset control signal line RST1, the gate line GT, the gate T10 of the driving transistor (the first electrode Ca of the storage capacitor Cst), the light emission control signal line EML, and the second reset control signal line RST2 are located in the first conductive layer LY1; the first initialization signal line INL1, the second electrode Cb of the storage capacitor Cst, and the second initialization signal line INL2 are located in the second conductive layer LY2; the data line DT, the first power line PL1, the connection electrode CE1, the connection electrode CE2, the connection electrode CE3, and the connection electrode CE01 are located in the third conductive layer LY3; and the shielding electrode SE is located in the fourth conductive layer LY4.

[0158] like Figure 12B As shown, the first initialization signal line INL1, the first reset control signal line RST1, the gate line GT, the light emission control signal line EML, the second initialization signal line INL2, and the second reset control signal line RST2 all extend along the first direction X, as follows. Figure 12B As shown, both the data line DT and the first power line PL1 extend along the second direction Y.

[0159] In the embodiments of this disclosure, the orthographic projection of element A on the substrate BS falling within the orthographic projection of element B on the substrate BS means that the orthographic projection of element A on the substrate BS completely falls within the orthographic projection of element B on the substrate BS. That is, the orthographic projection of element A on the substrate BS covers the orthographic projection of element B on the substrate BS, and the area of ​​the orthographic projection of element A on the substrate BS is less than or equal to the area of ​​the orthographic projection of element B on the substrate BS.

[0160] For example, in some embodiments of this disclosure, each pixel circuit 100a is provided with the shielding electrode SE as described above. That is, both the first pixel circuit 10 of the first pixel unit 101 and the second pixel circuit 20 of the second pixel unit 102 are provided with the shielding electrode SE as described above. However, this is not the case; for example, in other embodiments, each pixel circuit 100a is not provided with a shielding electrode SE.

[0161] For example, the transistors in the pixel circuits of the embodiments of this disclosure are all thin-film transistors. For example, the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, and the fourth conductive layer LY4 are all made of metallic materials. For example, the first conductive layer LY1 and the second conductive layer LY2 are formed of metallic materials such as nickel and aluminum, but are not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are formed of materials such as titanium, molybdenum, and aluminum, but are not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are structures formed of three sub-layers of Ti / Al / Ti, respectively, but are not limited thereto. For example, the substrate can be a glass substrate or a polyimide substrate, but is not limited thereto, and can be selected as needed. For example, the buffer layer BL, the isolation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, the fourth insulating layer IS4, the fifth insulating layer IS5, the sixth insulating layer, the insulating layer 131, and the insulating layer 132 are all made of insulating materials. The materials of the first electrode E1 and the second electrode E2 of the light-emitting element can be selected as needed. In some embodiments, the first electrode E1 may be at least one of a transparent conductive metal oxide and silver, but is not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto. For example, the first electrode E1 may have a structure with three sublayers stacked: ITO-Ag-ITO. In some embodiments, the second electrode E2 may be a metal with low work function, and may be at least one of magnesium and silver, but is not limited thereto.

[0162] For example, Figure 12C The fourth insulating layer IS4 and the fifth insulating layer ISL5 can correspond to the first planarization layer 121, and the sixth insulating layer can be the second planarization layer 122. In some embodiments, the fourth insulating layer IS4 may not be provided, that is, the fifth insulating layer ISL5 can correspond to the first planarization layer 121. The first planarization layer 121 and the second planarization layer 122 may each include multiple sublayers.

[0163] For example, referring to the layout diagrams and cross-sectional views of embodiments of this disclosure, the display panel provided in at least one embodiment of this disclosure can be manufactured using the following methods.

[0164] (1) A buffer layer BL and an isolation layer BR are formed on the substrate BS.

[0165] (2) A semiconductor thin film is formed on the isolation layer BR.

[0166] (3) Patterning the semiconductor thin film to form a semiconductor pattern layer.

[0167] (4) A first insulating film is formed on the semiconductor patterned layer.

[0168] (5) A first conductive film is formed on the first insulating film, and the first conductive film is patterned to form a first conductive layer LY1.

[0169] (6) The semiconductor pattern layer is doped using the first conductive layer LY1 as a mask to form the active layer LY0.

[0170] (7) A second insulating film is formed on the first conductive layer LY1.

[0171] (8) A second conductive film is formed on the second insulating layer ISL2, and the second conductive film is patterned to form the second conductive layer LY2.

[0172] (9) A third insulating film is formed on the second conductive layer LY2.

[0173] (10) Patterning at least one of the first insulating film, the second insulating film, and the third insulating film to form a via while forming the first insulating layer ISL1, the second insulating layer ISL2, and the third insulating layer ISL3.

[0174] (11) A third conductive film is formed and the third conductive film is patterned to form a third conductive layer LY3. Each component in the third conductive layer LY3 is connected to the component located below it through vias.

[0175] (12) Form the fourth insulating film and the fifth insulating film, and pattern the fourth insulating film and the fifth insulating film, and form the fourth insulating layer and the fifth insulating layer at the same time as forming the via.

[0176] (13) Form a fourth conductive film and pattern the fourth conductive film to form a fourth conductive layer LY4.

[0177] (14) Form at least one insulating layer and form at least one transparent conductive layer, the transparent conductive layer including conductive line L1.

[0178] (15) Forming the first electrode E1 of the light-emitting element.

[0179] (16) Form the pixel definition layer and spacer layer PS.

[0180] (17) Forming a light-emitting functional layer.

[0181] (18) Forms the second electrode E2 of the light-emitting element.

[0182] (19) Form an encapsulation layer.

[0183] Of course, in the display panel provided in the embodiments of this disclosure, the shielding electrode SE may not be provided.

[0184] In the embodiments of this disclosure, the first conductive layer LY1 can be referred to as the first gate layer, the second conductive layer LY2 can be referred to as the second gate layer, the third conductive layer LY3 can be referred to as the first source / drain layer, and the fourth conductive layer LY4 can be referred to as the second source / drain layer.

[0185] At least one embodiment of this disclosure provides a display device including any of the above-described display substrates.

[0186] Figure 13A and Figure 13B This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Figure 13A and Figure 13B As shown, the sensor SS is located on one side of the display substrate DS and within the second display area R2. Ambient light can be transmitted through the second display area R2 and sensed by the sensor SS. Figure 13B As shown, the side of the display panel without the sensor SS is the display side, where images can be displayed. For example, the sensor may include a photosensor located on one side of the display panel. In this type of display device, hardware such as photosensors (e.g., cameras) can be placed in the light-transmitting display area, eliminating the need for punch holes and facilitating the realization of a true full-screen display.

[0187] For example, the second display area R2 can be rectangular, and the area of ​​the sensor SS projected onto the substrate BS can be less than or equal to the area of ​​the inscribed circle of the second display area R2. That is, the size of the area where the sensor SS is located can be less than or equal to the size of the inscribed circle of the second display area R2. For example, if the size of the area where the sensor SS is located is equal to the size of the inscribed circle of the second display area R2, then the shape of the area where the sensor SS is located can be circular. Of course, in some embodiments, the second display area R2 can also be other shapes besides rectangles, such as circles or ellipses.

[0188] For example, the display device is a full-screen display device with an under-display camera. For example, the display device includes OLED or products that include OLED. For example, the display device includes any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator, which contains the above-mentioned display panel.

[0189] For example, embodiments of this disclosure are not limited to Figure 12A The specific pixel circuit shown can be replaced with other pixel circuits capable of compensating for the driving transistors. Based on the description and teachings of this disclosure, other configurations that can be readily conceived by those skilled in the art without inventive effort are all within the scope of this disclosure.

[0190] The above description uses a 7T1C pixel circuit as an example, and the embodiments of this disclosure include, but are not limited to, this. It should be noted that the embodiments of this disclosure do not limit the number of thin-film transistors or capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure; the embodiments of this disclosure do not limit this. Of course, the display panel may also include a pixel circuit with fewer than 7 transistors.

[0191] In related technologies, the pixel circuits (including the first pixel circuit 10 and the second pixel circuit 20) and the first light-emitting element 30 have the same pitch. For example, the width is generally about 30 micrometers (μm) to 32 μm, and the length is about 60 μm to 65 μm. However, in the embodiments of this disclosure, in order to provide sufficient space for the second pixel circuit 20 without reducing the number of pixels in the first display area R1, each pixel circuit can be compressed along the first direction X (e.g., the gate line extension direction, also known as the lateral direction), so that the width of the pixel circuit in the first direction is smaller than the width of the first light-emitting element 30; or, the first light-emitting element 30 can be extended along the first direction X, so that the width of the first light-emitting element 30 in the first direction X is larger than the width of the first pixel circuit 10. In this way, under the premise that the substrate BS has the same size, there can be more free space in the first display area R1, and correspondingly, the second pixel circuit 20 for driving the second light-emitting element 40 located in the second display area R2 can be set in this free space.

[0192] For example, the width of each pixel circuit can differ from the width of the first light-emitting element 30 by approximately 4 μm. Taking a compressed pixel circuit with a width difference of 4 μm as an example... Figure 14 The block layout of the pixel circuitry before and after compression is shown. (Reference) Figure 14As can be seen, the pixel circuit may include a driving structure and a connecting element CE0 for connecting to the first electrode (anode) of the light-emitting element. The size of the connecting element CE0 can represent the size of the pixel circuit. Before compression, both the pixel circuit and the light-emitting element have a width of 1-100 μm and a height of 2-100 μm. The size of the light-emitting element after compression can remain unchanged compared to before compression. For example, the size of the second light-emitting element 40 can be equal to or smaller than the size of the first light-emitting element 20. The height of the pixel circuit after compression remains unchanged, but the width is narrowed by 1-20 μm. Thus, every few columns of compressed pixel circuits will have one or more additional columns of compressed pixel circuits. This design is used throughout the entire screen to achieve full-screen compression. For example, these additional columns can be selected to connect to the second light-emitting element 40 within the second display area R2 to control the second light-emitting element 40 to emit light. In some embodiments, multiple columns of pixel circuits near the periphery of the second display area R2 are selected as the second pixel circuit 20 connected to the second light-emitting element 40. This allows for normal display without changing the resolution of the display panel. That is, it fully utilizes the existing space of the display panel to achieve normal display. The effect achieved by compressing the size of the pixel circuit is that the number of light-emitting elements (including the first light-emitting element 30 and the second light-emitting element 40) remains unchanged. Consequently, compared with before compression, there is no significant difference in display effect, and the display panel has a better display effect.

[0193] In embodiments of this disclosure, elements located in the same layer may be formed from the same film layer using the same patterning process. For example, elements located in the same layer may be located on the surface of the same element that is away from the substrate.

[0194] It should be noted that, for clarity, the thickness of layers or regions is magnified in the drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "below" another element, the element may be located "directly" on or "below" the other element, or there may be intermediate elements present.

[0195] In the embodiments of this disclosure, the patterning or patterning process may include only photolithography, or it may include both photolithography and etching steps, or it may include other processes such as printing or inkjet printing to form a predetermined pattern. Photolithography refers to processes including film formation, exposure, and development, using photoresist, photomasks, and exposure machines to form patterns. The appropriate patterning process can be selected based on the structure formed in the embodiments of this disclosure.

[0196] Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0197] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: Substrate A first conductive element is located on the substrate. A first planarization layer is located on the first conductive element; The second conductive element is located on the first planarization layer and is connected to the first conductive element through a first via penetrating the first planarization layer; A second planarization layer is located on the second conductive element; as well as Conductive lines are located on the second planarization layer, wherein... The second conductive element is recessed at the first via, such that the second conductive element has a recessed portion and a peripheral portion located outside the recessed portion. The recessed portion has a bottom and a side portion, and the bottom is connected to the peripheral portion through the side portion. The sides of the recess have uneven surfaces configured to cause diffuse reflection of light incident upon them.

2. The display substrate according to claim 1, wherein, The first planarization layer has an uneven surface at a position corresponding to the side portion, and the second conductive element is conformally disposed thereon.

3. The display substrate according to claim 1, wherein, The side portion has an angle with the substrate, and the angle is an acute angle.

4. The display substrate according to claim 1, wherein, At least one of the bottom and the periphery of the second conductive element has an uneven surface.

5. The display substrate according to claim 1, wherein, The surface of the side portion of the recess that is close to the substrate and the surface that is away from the substrate are both uneven surfaces.

6. The display substrate according to claim 1, wherein, The surface of the second conductive element near the substrate is a smooth surface, while the side surface away from the substrate is an uneven surface.

7. The display substrate according to claim 6, wherein, At least one of the bottom and the peripheral portion has an uneven surface facing away from the substrate.

8. The display substrate according to any one of claims 1-7, further comprising pixel units, wherein, The pixel unit includes a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the light-emitting element. The pixel unit includes a first pixel unit and a second pixel unit. The display substrate includes a first display area and a second display area. The pixel circuit and the light-emitting element of the first pixel unit are both located in the first display area. The pixel circuit of the second pixel unit is located in the first display area. The light-emitting element of the second pixel unit is located in the second display area. The pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit through the conductive line.

9. The display substrate according to claim 8, wherein, The second display area is a light-transmitting display area, where the orthographic projection of the pixel circuit of the first pixel unit on the substrate and the orthographic projection of the light-emitting element of the first pixel unit on the substrate at least partially overlap, and the orthographic projection of the pixel circuit of the second pixel unit on the substrate and the orthographic projection of the light-emitting element of the second pixel unit on the substrate do not overlap.

10. The display substrate according to claim 8, wherein, The orthographic projection of the conductive line on the substrate overlaps with the orthographic projection of the pixel circuit of the first pixel unit on the substrate.

11. The display substrate according to claim 8, further comprising a connecting element, wherein, The pixel circuit of the pixel unit is connected to the conductive line or to the light-emitting element of the first pixel unit through the connecting element.

12. The display substrate according to claim 11, wherein, The connecting element includes a first connecting electrode and a second connecting electrode, which are connected together.

13. The display substrate according to claim 12, wherein, The first conductive element includes the first connecting electrode, and the second conductive element includes a second connecting electrode connected to the first connecting electrode.

14. The display substrate according to claim 12, wherein, The first conductive element and the first connecting electrode are located on the same layer, and the second conductive element and the second connecting electrode are located on the same layer.

15. The display substrate according to claim 8, wherein, The pixel circuit includes a driving transistor, and the driving transistor includes a gate; The display substrate further includes: The first gate signal line is connected to the gate of the driving transistor; A constant voltage line is configured to provide a first constant voltage to the pixel circuit; and The shielding electrode is connected to the constant voltage line, and the orthogonal projection of the first gate signal line on the substrate falls within the orthogonal projection of the shielding electrode on the substrate.

16. The display substrate according to claim 15, wherein, The first conductive element includes the constant voltage line, and the second conductive element includes the shielding electrode connected to the constant voltage line.

17. The display substrate according to claim 15 or 16, wherein, The first conductive element is located on the same layer as the constant voltage line, and the second conductive element is located on the same layer as the shielding electrode.

18. The display substrate according to any one of claims 1-7, wherein, The conductive lines are configured as multiple lines, and at least one of the multiple conductive lines overlaps with the orthographic projection of the first via on the substrate.

19. The display substrate according to any one of claims 1-7, wherein, The material of the second conductive element includes metal, and the material of the conductive wire includes transparent conductive material.

20. A display substrate, comprising: The substrate includes a first display area and a second display area; A pixel unit, located on the substrate, includes a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the light-emitting element. The pixel unit includes a first pixel unit and a second pixel unit. The pixel circuit and the light-emitting element of the first pixel unit are both located in a first display area. The pixel circuit of the second pixel unit is located in the first display area, and the light-emitting element of the second pixel unit is located in the second display area. The pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit via a conductive line. A connecting element is connected to the pixel circuit. The pixel circuit of the first pixel unit is connected to the light-emitting element of the first pixel unit through the connecting element. Alternatively, the pixel circuit of the second pixel unit is connected to the conductive line through the connecting element. The connecting element includes a first connecting electrode and a second connecting electrode. A first planarization layer is located on the first connecting electrode, and a second connecting electrode is located on the first planarization layer and connected to the first connecting electrode through a via penetrating the first planarization layer; A second planarization layer is located on the second connecting electrode, and the conductive line is located on the second planarization layer. The second connecting electrode is recessed at the via, such that the second connecting electrode has a recessed portion and a peripheral portion located outside the recessed portion. The recessed portion has a bottom and a side portion, and the bottom is connected to the peripheral portion through the side portion. The side portion of the second connecting electrode has an uneven surface configured such that light incident upon it undergoes diffuse reflection.

21. The display substrate according to claim 20, wherein, The pixel circuit includes a driving transistor, and the driving transistor includes a gate; The display substrate further includes: The first gate signal line is connected to the gate of the driving transistor; A constant voltage line is configured to provide a first constant voltage to the pixel circuit; and A shielding electrode is connected to the constant voltage line, and the orthographic projection of the first gate signal line on the substrate falls within the orthographic projection of the shielding electrode on the substrate. Wherein, the first planarization layer is located on the constant voltage line, the shielding electrode is located on the first planarization layer, the second planarization layer is located on the shielding electrode, and the shielding electrode is connected to the constant voltage line through a via penetrating the first planarization layer; The shielding electrode is recessed at the via where it connects to the constant voltage line, such that the shielding electrode has a recessed portion and a peripheral portion outside the recessed portion. The recessed portion of the shielding electrode has a bottom and a side portion, and the bottom and the peripheral portion of the shielding electrode are connected through the side portion of the shielding electrode. The side portion of the shielding electrode has an uneven surface configured such that light incident upon it undergoes diffuse reflection.

22. A display device comprising a display substrate according to any one of claims 1-21.

23. The display device according to claim 22, further comprising a photosensor, wherein, The photosensor is located on one side of the display substrate.

Images