Successive approximation register analog-to-digital converter

Abstract

A successive approximation register-type analog-to-digital converter (SAR ADC) is disclosed, configured to receive an analog input signal and provide a digital output signal. The SAR ADC includes a capacitor bank for continuously providing multiple signal levels based on sample values ​​of the analog input signal, wherein each of the multiple signal levels is an indicator of a corresponding bit in a corresponding sample of the digital output signal. Furthermore, the SAR ADC includes control circuitry configured to cause the capacitor bank to provide multiple signal levels representing dynamically scaled versions of the sample values ​​of the analog input signal. In some embodiments, a corresponding selector for each capacitor in the capacitor bank is controlled to charge the capacitor using either the sample value of the analog input signal or a sample value of the inverse version of the analog input signal. The setting of the corresponding selector corresponds to a digital representation of a scaled value of the dynamically scaled version of the sample values ​​of the analog input signal (e.g., the sample value of an oscillator signal). Corresponding methods, receivers, and wireless communication devices are also disclosed.

Description

Technical Field

[0001] This disclosure generally relates to the field of successive approximation register-type analog-to-digital converters (SAR ADCs). More specifically, this disclosure relates to mixer implementations associated with SAR ADCs. Background Technology

[0002] Many typical radio frequency receivers include the following functions: (e.g., by applying mixers) downconverting the received radio frequency signal, and (e.g., by applying a successive approximation register analog-to-digital converter, i.e., a SAR ADC) converting the received radio frequency signal to an analog-to-digital signal.

[0003] If downconversion is performed in the digital domain, the analog-to-digital converter (ADC) typically needs to have a relatively large bandwidth, which can lead to high ADC complexity and / or inefficient use of ADC resources (e.g., ADC hardware such as ADC circuitry and / or subsystems) and / or high power consumption.

[0004] If the downconversion is performed in the analog domain, the downconverter can be implemented using a harmonic suppression mixer (HRM) or a corresponding function, which may result in high downconversion complexity and / or high power consumption.

[0005] Therefore, (for example, for RF receivers) alternative methods are needed for downconversion and analog-to-digital conversion. Summary of the Invention

[0006] It should be emphasized that when the term "comprising" (which may be replaced by "including") is used in this specification, it refers to the presence of the described features, elements, steps, or components, but does not exclude the presence or addition of one or more other features, elements, steps, components, or combinations thereof. As used herein, the singular forms "a," "an," and "described" are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0007] Generally, the arrangements mentioned in this article should be understood as physical products; for example, devices. Physical products may include one or more components, such as control circuits in the form of one or more controllers, one or more processors, etc.

[0008] Some embodiments are intended to address, mitigate, or eliminate at least some of the above or other disadvantages.

[0009] The first aspect is a successive approximation register-type SAR analog-to-digital converter (ADC) configured to receive an analog input signal and provide a digital output signal. The SAR ADC includes a capacitor bank for continuously providing multiple signal levels based on sample values ​​of the analog input signal, wherein each of the multiple signal levels is an indicator of a corresponding bit in a corresponding sample of the digital output signal. The SAR ADC also includes control circuitry configured to cause the capacitor bank to provide multiple signal levels representing dynamically scaled versions of the sample values ​​of the analog input signal.

[0010] In some embodiments, the control circuitry is configured to dynamically control the appropriate selector for each capacitor in the capacitor bank to charge the capacitor using either a sample value of the analog input signal or the opposite version of a sample value of the analog input signal.

[0011] In some embodiments, the settings of the corresponding selectors correspond to a digital representation of the scaled value of a dynamically scaled version of the sample values ​​of the analog input signal.

[0012] In some embodiments, each sample of the digital output signal is a quantized representation of the corresponding sample of a dynamically scaled version of the analog input signal sample value.

[0013] In some embodiments, a dynamically scaled version of the sample values ​​of the analog input signal represents the sample values ​​of the analog input signal multiplied by the sample values ​​of the oscillator signal.

[0014] In some embodiments, each sample of the digital output signal is a quantized representation of the corresponding sample of the analog input signal that has been mixed with the oscillator signal.

[0015] In some embodiments, the oscillator signal is a sinusoidal signal.

[0016] In some embodiments, the sample value set of the oscillator signal includes at least three different values.

[0017] In some embodiments, the SAR ADC further includes a comparator configured to determine the bit value of the digital output signal based on a corresponding signal level provided by a capacitor bank.

[0018] In some embodiments, the capacitance of each capacitor in the capacitor bank is equal to the base capacitance multiplied by a non-negative integer power of 2.

[0019] In some embodiments, the capacitors in the capacitor bank have different capacitances, including a base capacitance and capacitances that increase by a factor of two in succession.

[0020] In some embodiments, the SAR ADC also includes an additional capacitor that can be controlled to change the scaling of the sample values ​​of the analog input signal.

[0021] In some embodiments, the control circuitry is configured to control a selector for the additional capacitor to charge the additional capacitor using a sample value of the analog input signal or the opposite version of a sample value of the analog input signal.

[0022] In some embodiments, the additional capacitor has a base capacitance.

[0023] In some embodiments, the control circuit is configured to cause operation in a mixing mode or a non-mixing mode, wherein operation in the non-mixing mode is caused by applying a static scaling value.

[0024] In some embodiments, the SAR ADC includes: a first capacitor bank and a second capacitor bank, configured to continuously provide a first signal level and a second signal level, wherein the first signal level and the second signal level serve as differential signal levels for determining a digital output signal.

[0025] In some embodiments, the SAR ADC includes a first additional capacitor and a second additional capacitor, wherein the control circuitry is configured to: control a first selector of the first additional capacitor to charge the first additional capacitor using a sample value of an opposite version of the analog input signal; and control a second selector of the second additional capacitor to charge the second additional capacitor using a sample value of the analog input signal.

[0026] In some embodiments, the SAR ADC further includes a noise shaping network configured to provide an integral of the signal level provided by the capacitor bank in order to adjust the digital output signal.

[0027] The second aspect is a receiver that includes the SAR ADC described in the first aspect.

[0028] The third aspect is a wireless communication device that includes the SAR ADC according to the first aspect.

[0029] The fourth aspect is a method for operating a successive approximation register-type SAR analog-to-digital converter (ADC), which is configured to receive an analog input signal and provide a digital output signal. The SAR ADC includes a capacitor bank for continuously providing multiple signal levels based on sample values ​​of the analog input signal, wherein each of the multiple signal levels is an indicator of a corresponding bit in a corresponding sample of the digital output signal.

[0030] The method includes enabling a capacitor bank to provide multiple signal levels representing dynamically scaled versions of sample values ​​of an analog input signal.

[0031] In some embodiments, enabling the capacitor bank to provide multiple signal levels includes: dynamically controlling a corresponding selector for each capacitor in the capacitor bank to charge the capacitor using a sample value of an analog input signal or an inverse version of a sample value of an analog input signal.

[0032] In some embodiments, enabling the capacitor bank to provide multiple signal levels includes: setting a corresponding selector to a digital representation of a scaled value corresponding to a dynamically scaled version of a sample value of an analog input signal.

[0033] In some embodiments, the method further includes controlling an additional capacitor to change the scaling of the sample values ​​of the analog input signal.

[0034] In some embodiments, the method further includes configuring the operation of the SAR ADC in a mixing mode or a non-mixing mode, wherein configuring the operation in the non-mixing mode includes applying a static scaling value.

[0035] In some embodiments, any of the above aspects may additionally have features that are the same as or correspond to any of the multiple features described above with respect to any other aspect.

[0036] One advantage of some embodiments is that they provide alternative methods for downconversion and analog-to-digital conversion.

[0037] One advantage of some embodiments is that they achieve a combination of downconversion and analog-to-digital conversion.

[0038] One advantage of some embodiments is that the functionality of the harmonic suppression mixer (HRM) is embedded within the SAR ADC.

[0039] Some of the advantages of these embodiments are that the complexity of downconversion and / or analog-to-digital conversion (i.e., individual complexity and / or combined complexity) is improved (e.g., reduced) compared to other methods used for downconversion and analog-to-digital conversion.

[0040] Some of the advantages of these embodiments are that the power consumption of downconversion and / or analog-to-digital conversion (i.e., individual and / or combined complexity) is improved (e.g., reduced) compared to other methods used for downconversion and analog-to-digital conversion.

[0041] One advantage of some embodiments is that ADC resources are used more efficiently compared to other methods used for downconversion and analog-to-digital conversion.

[0042] One advantage of some embodiments is that, since the ADC function is inherently applied to the down-converted signal material due to the mixing of the analog samples, the SAR ADC can include noise shaping (NS) functionality. Compared to other ADC methods, the application of NS can reduce ADC resolution requirements and / or improve ADC accuracy. Attached Figure Description

[0043] Other objects, features, and advantages will become apparent from the following detailed description of embodiments with reference to the accompanying drawings. The drawings are not necessarily drawn to scale, but rather focus on illustrating exemplary embodiments.

[0044] Figure 1 This is a schematic block diagram showing an example SAR ADC;

[0045] Figure 2 This is a schematic block diagram illustrating an example SAR ADC according to some embodiments;

[0046] Figure 3 This is a set of schematic block diagrams illustrating example control signal generators according to some embodiments;

[0047] Figure 4 This is a signal diagram illustrating example control signals according to some embodiments;

[0048] Figure 5 This is a collection of schematic block diagrams and signal diagrams illustrating example SAR ADCs and corresponding noise shaping principles according to some embodiments;

[0049] Figure 6 This is a schematic block diagram illustrating an example device according to some embodiments;

[0050] Figure 7 This is a schematic block diagram illustrating an example receiver according to some embodiments;

[0051] Figure 8 This is a flowchart illustrating example method steps according to some embodiments; and

[0052] Figure 9 It is a signal atlas illustrating various principles and results based on some embodiments. Detailed Implementation

[0053] As mentioned above, it should be emphasized that when the term "comprising" (which can be replaced by "including") is used in this specification, it refers to the presence of the described features, elements, steps, or components, but does not exclude the presence or addition of one or more other features, elements, steps, components, or combinations thereof. As used herein, the singular forms "a," "an," and "described" are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0054] Embodiments of this disclosure will now be described and illustrated more fully with reference to the accompanying drawings. However, the solutions disclosed herein can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0055] As mentioned above, a typical radio frequency receiver includes the following functions: down-converting the received radio frequency signal and performing analog-to-digital conversion on the received radio frequency signal.

[0056] When performing downconversion in the digital domain, analog-to-digital converters (ADCs) typically require a relatively large bandwidth.

[0057] For example, using a conventional ADC to convert intermediate frequency (IF) signals can be very inefficient because—since the bandwidth of the IF signal typically corresponds to a small fraction of the IF frequency—the ADC bandwidth would usually require a Nyquist frequency much larger than the IF frequency. Furthermore, a conventional ADC will typically provide roughly the same signal-to-noise ratio (SNR) over the entire frequency range up to the ADC's Nyquist frequency, while the signal under consideration uses only a small fraction of that spectrum.

[0058] When downconversion is performed in the analog domain, the downconverter typically needs to function as a harmonic suppression mixer (HRM) or perform the corresponding function, which can result in high downconversion complexity and / or high power consumption.

[0059] For example, an HRM may require additional circuitry (buffers and / or amplifiers) to terminate the mixer port to achieve the desired harmonic suppression level.

[0060] The following describes embodiments of alternative methods for downconversion and analog-to-digital conversion.

[0061] Some implementations suggest combining a SAR ADC (e.g., a noise-shaping NS ADC) with HRM functionality.

[0062] Some implementations are based on the observation that SAR ADCs provide highly matched systems that can also function as HRMs (capacitive digital-to-analog converters, C-DACs, for SAR ADCs). Therefore, the linearity of the C-DAC can be used for both HRM and ADC functions.

[0063] In some embodiments, downconversion and analog-to-digital conversion are combined by manipulating the SAR ADC input.

[0064] These methods may have one or more of the following (or other) advantages: relatively low complexity, relatively low power consumption, and efficient utilization of ADC resources.

[0065] Although this document describes embodiments using examples of differential architectures, it should be noted that corresponding non-differential (single-ended) architectures can be equally applied to some embodiments.

[0066] Generally, all the switches described in this article can be considered as examples of selectors, and it should be noted that selectors can be implemented in other ways by means of switches.

[0067] Figure 1 An example SAR ADC 100 is schematically illustrated and can serve as a starting point for some embodiments. The example SAR ADC 100 is based on: capacitive digital-to-analog converter (C-DAC) technology; mature ADC technology (which can operate at high sampling rates) with high energy efficiency, and good scalability through aggressively extended complementary metal-oxide-semiconductor (CMOS) technology. Figure 1 The variant of the C-DAC-based SAR ADC shown is based on so-called substrate sampling.

[0068] It should be noted that various methods exist for implementing C-DAC-based SAR ADCs, and all of these methods can be applied to some embodiments. Typically, a C-DAC-based SAR ADC has one or more capacitive digital-to-analog converters, each of which includes a capacitor bank (e.g., a capacitor array) that also serves as a sampling capacitor.

[0069] The SAR ADC 100 is configured to receive analog input signals and provide digital output signals, as is well known in the art.

[0070] The signals used by the SAR ADC 100 include common-mode voltage signals (V... cm 101. Analog input signal (V) ip )102 and the opposite version of the analog input signal (V im 103. First reference voltage signal (V) ref_p )104 and the second reference voltage signal (V ref_m 105.

[0071] Typically, the voltage of the opposite version of the analog input signal is opposite to the voltage of the analog input signal associated with a predetermined voltage level. For example, the opposite version of the analog input signal could be a version of the analog input signal with reverse polarity. Alternatively or additionally, the analog input signal and its opposite version could be in the form of V... cm Centered on (i.e., V) ip =V cm +b and V im =V cm -b).

[0072] Typically, the analog input signal and its opposite version together form a differential signal.

[0073] Typically, the first reference voltage signal has a higher voltage than the second reference voltage signal. For example, the second reference voltage signal may be a reversed version of the first reference voltage signal. Alternatively or additionally, the first and second reference voltage signals may be in V... cm Centered on (i.e., V) ref_p =V cm +c and V ref_m =V cm -c).

[0074] Typically, the first reference voltage signal and the second reference voltage signal together form a differential signal.

[0075] The SAR ADC includes two capacitor banks 110 and 120. Typically, the capacitance of each capacitor in capacitor banks 110 and 120 is equal to the base capacitance (C) multiplied by a non-negative power of 2 (i.e., 2...). x C, Similarly, capacitors in a capacitor bank typically have different capacitances; including a base capacitance and capacitances that increase by a factor of two in succession. Therefore, capacitors 111, 112...116 in capacitor bank 110 can have capacitances C1, C2...C2...C1 ... x C (for example, C, 2C...32C when the capacitor bank includes six capacitors; that is, providing a six-bit ADC), and the same applies to capacitors 121, 122...126 in capacitor bank 120.

[0076] As is well known in the art, capacitor banks can be used to continuously provide multiple (corresponding) signal levels 152, 153 based on sample values ​​of an analog input signal, wherein each provided signal level is an indicator of a corresponding bit in a corresponding sample of a digital output signal 163. The SAR ADC 100 includes a comparator 150 configured to determine a bit value 159 of the digital output signal 163 based on the signal levels 152, 153 provided by the capacitor banks.

[0077] The SAR ADC also includes control circuitry (e.g., SAR logic) 160, which is configured to cause capacitor banks 110, 120 to provide multiple signal levels 152, 153 representing sample values ​​of the analog input signal. This can be achieved by providing control signals 161, 162 to switch arrays 130, 140, wherein each switch array controls the charging of capacitors in the corresponding capacitor bank of capacitor banks 110, 120.

[0078] The SAR ADC 100 is fully differential, therefore both sides ( Figure 1 The operations of the upper and lower parts are complementary, as will be explained below.

[0079] During the sampling phase, the analog input signal 102 is sampled on capacitor bank 110. This is done by sampling the base plates of capacitors 111, 112...116. Figure 1 The upper capacitor side in the middle is connected to V. ip 102 and the top plate of capacitors 111, 112...116 ( Figure 1 The lower capacitor side is connected to the common-mode voltage signal V. cm This is achieved using 101. The base plates of capacitors 111, 112...116 are connected to V. ip 102 is achieved by closing the leftmost switch of each capacitor 111, 112...116 in the switch array 130 while keeping the other switches in the switch array 130 open. The top plates of capacitors 111, 112...116 are connected to the common-mode voltage signal V. cm 101 is achieved by closing switch 151.

[0080] Similarly, in the sampling phase, the opposite version 103 of the analog input signal is sampled on capacitor bank 120. This is done by sampling the base plates of capacitors 121, 122...126 ( Figure 1 The lower capacitor side in the middle is connected to V. im 103 and the top plate of capacitors 121, 122...126 ( Figure 1 The upper capacitor side is connected to the common-mode voltage signal V. cm This is achieved using 101. The base plates of capacitors 121, 122...126 are connected to V. im 103 is achieved by closing the leftmost switch of each capacitor 121, 122...116 in the switch array 140 while keeping the other switches in the switch array 140 open. The top plates of capacitors 121, 122...126 are connected to the common-mode voltage signal V. cm 101 is achieved by closing switch 151.

[0081] In the next stage (conversion stage), the base plates of capacitors 111, 112...116 are switched to V. cm 101, and the top plate and V cm 101 Disconnect. Connect the base plates of capacitors 111, 112...116 to V. cm 101 is achieved by closing the rightmost switch of each capacitor 111, 112...116 in the switch array 130 while keeping the other switches in the switch array 130 open. The top plates of capacitors 111, 112...116 are connected to V... cmDisconnection 101 is achieved by disconnecting switch 151. As a result, an analog input signal sample is applied to the comparator input, causing a voltage drop at the positive input terminal 152 of the comparator when V... ip =V cm At +b, the voltage V cm -b=2V cm -V ip .

[0082] Similarly, in the next phase, the base plates of capacitors 121, 122...126 were switched to V. cm 101, and the top plate and V cm 101 Disconnect. Connect the base plates of capacitors 121, 122...126 to V. cm 101 is achieved by closing the rightmost switch of each capacitor 121, 122...126 in the switch array 140 while keeping the other switches in the switch array 140 open. The top plates of capacitors 121, 122...126 are connected to V... cm Disconnection 101 is achieved by disconnecting switch 151. Consequently, the opposite version of the analog input signal sample is applied to the comparator input, causing a situation at the comparator's negative input 153 where V... im =V cm At -b, the voltage V cm +b=2V cm -V im .

[0083] Then, comparator 150 is triggered and outputs decision 159 based on differential inputs 152 and 153. Typically, this decision is a bit decision. When the differential input is positive, the bit decision can be "1", and when the differential input is negative, the bit decision can be "0" (in various implementations, a zero differential input can be mapped to either "0" or "1"). The first comparator decision for the analog input signal sample can correspond to the most significant bit (MSB) of the digital representation 163 of the analog input signal sample value.

[0084] After each comparator decision, the base plate of one of capacitors 111, 112...116 is switched to V. ref_p 104 or V ref_m 105, while the top plate remains in line with V. cm 101 Disconnect. Connect the base plate of one of capacitors 111, 112...116 to V. ref_ p 104 or V ref_m105 is achieved by closing the third or second switch counting from the right of the relevant capacitors 111, 112...116 in the switch array 130 while keeping the other switches in the switch array 130 open. Consequently, the voltage exhibited at the positive input terminal 152 of the comparator changes accordingly.

[0085] Therefore, after each comparator decision, the base plate of one of capacitors 121, 122...126 is switched to V. ref_ m 105 or V ref_p 104, while the top plate remains in line with V. cm 101 Disconnect. Connect the base plate of one of capacitors 121, 122...126 to V. ref_m 105 or V ref_p 104 is achieved by closing the third or second switch counting from the left of the relevant capacitors 121, 122...126 in the switch array 140 while keeping the other switches in the switch array 140 open. Consequently, the voltage at the negative input terminal 153 of the comparator changes accordingly.

[0086] Therefore, the differential input of comparator 150 has changed, and comparator 150 is triggered again and outputs a new decision 159 based on the differential inputs 152 and 153. The second comparator decision for the analog input signal sample can correspond to the bit after the MSB (i.e., MSB-1) of the digital representation 163 of the analog input signal sample value.

[0087] The iteration alternately connects the base plate of the relevant capacitor to V. ref_m or V ref_p This triggers the comparator to make a decision until a final decision is made on a sample of the analog input signal; typically, this corresponds to the least significant bit (LSB) of the 163-bit digital representation of the analog input signal sample value. Then, the capacitor bank can be reset and a new sample of the analog input signal can be loaded for processing.

[0088] Figure 2 This schematically illustrates a method based on some embodiments. Figure 1 Example of SAR ADC 100: SAR ADC 200.

[0089] and Figure 1Similarly, SAR ADC 200 is configured to receive an analog input signal and provide a digital output signal. However, when SAR ADC 100 in the figure is configured to provide a digital output signal 163 as a sampled and quantized representation of the analog input signal, SAR ADC 200 is configured to provide a digital output signal for each sample of the analog input signal as a scaled quantized representation of the analog input signal sample. Therefore, each sample of the digital output signal is a quantized representation of the corresponding sample of a dynamically scaled version of the analog input signal sample value.

[0090] Scaling is achieved by modifying and controlling the switch array, as detailed below.

[0091] By dynamically controlling the scaling and selecting an appropriate scaling value, the SAR ADC 200 can be configured to provide a digital output signal as a sampled and quantized representation of the analog input signal mixed with the oscillator signal. Therefore, a mixing function is embedded in the SAR ADC 200.

[0092] and Figure 1 Similarly, the signals used by the SAR ADC 200 include common-mode voltage signals (V... cm 201. Analog input signal (V) ip )202 and the opposite version of the analog input signal (V im )203, First reference voltage signal (V ref_p )204 and the second reference voltage signal (V ref_m )205.

[0093] Similarly with Figure 1 Similarly, the SAR ADC 200 includes two capacitor banks 210 and 220. Capacitor banks 210 and 220 correspond exactly to... Figure 1 The capacitor banks 110 and 120. Therefore, the capacitors 211...216 of the capacitor bank 210 can have C, 2C...2 x The capacitance of C, and the same applies to capacitors 221...226 in capacitor bank 220.

[0094] The SAR ADC 200 is fully differential, therefore both sides ( Figure 2 The operations of the upper and lower parts are complementary, similar to the previous combination. Figure 1 Explanation.

[0095] Similarly Figure 1 The SAR ADC 200 includes a comparator 250, which is configured to determine the bit value 259 of the digital output signal 263 based on signal levels 252, 253 provided by the capacitor bank.

[0096] Further similar to Figure 1 The SAR ADC 200 also includes a control circuit 260 configured to cause capacitor banks 210 and 220 to provide multiple signal levels based on the analog input signal. Figure 1 Instead, control circuitry 260 is configured to enable capacitor banks 210, 220 to provide multiple signal levels representing dynamically scaled versions of sample values ​​of the analog input signal.

[0097] This can be achieved by providing control signals 261 and 262 to switch arrays 230 and 240, wherein each switch array controls the charging of capacitors in the corresponding capacitor bank of capacitor banks 210 and 220. It is worth noting that switch arrays 230 and 240 are... Figure 1 The difference in the switch array lies in the fact that the leftmost switches 231...236; 221...226 of each capacitor in capacitors 211...216 are operable to provide an analog input signal (V) to their corresponding capacitor. ip )202 and the opposite version of the analog input signal (V im Any one of 203.

[0098] The scaling of the sample values ​​of the analog input signal is achieved by having the scaling value s represent the position of the leftmost switch controlling each capacitor during the sampling phase.

[0099] For example, if the scaling value s can be represented as 111111, then all switches 231...236 can be configured such that the base plates of all capacitors 211...216 are connected to V. ip 202, and all corresponding switches in switch array 240 can be configured such that the base plates of all capacitors 221...226 are connected to V. im 203.

[0100] Then, if the scaling value s can be represented as 111110, then switches 231...236 can be set such that the base plates of all capacitors 211...216 are connected to V. ip 202 (except for connection to V) im Apart from capacitor 211 of 203, all corresponding switches in switch array 240 can be configured such that the base plates of all capacitors 221...226 are connected to V. im 203 (except for connection to V) ip (Except for capacitor 221 in 202).

[0101] The corresponding settings for the switch array can be applied to other scaling value representations.

[0102] Therefore, control circuit 260 is configured to control a corresponding selector (e.g., switches 231...236) for each capacitor in the capacitor bank to use the analog input signal V. ip 202 sample values ​​or the inverse version V of the analog input signal im The sample value of 203 charges the capacitor so that the setting of the corresponding selector corresponds to the digital representation of the scaling value s of the analog input signal sample value.

[0103] In some embodiments, the scaling value is selected as a digital representation of a sample of the oscillator signal (e.g., a sine wave). Typically, the sampling time corresponds to the sampling time of the analog input signal. Preferably, the frequency of the oscillator signal satisfies the Nyquist limit associated with the sampling frequency (i.e., the set of sample values ​​of the oscillator signal includes at least three distinct values).

[0104] Then, a dynamically scaled version of the sample values ​​of the analog input signal represents the sample values ​​of the analog input signal multiplied by the sample values ​​of the oscillator signal; thus providing a mixing of the analog input signal and the oscillator signal. Therefore, each sample of the digital output signal is a quantized representation of the corresponding sample of the analog input signal mixed with the oscillator signal. It can be noted that the mixing function applies to the analog domain samples (before quantization), which may improve the accuracy of the mixing operation.

[0105] During the sampling phase, a dynamically scaled version of the analog input signal is sampled on capacitor bank 210. This is achieved by sampling the base plates of capacitors 211...216 ( Figure 2 The upper capacitor side in the middle is connected to V. ip 202 or V im 203 (depending on the applicable scaling value) and the top plate of capacitors 211...216 ( Figure 2 The lower capacitor side is connected to the common-mode voltage signal V. cm This is achieved using 201. The base plates of capacitors 211...216 are connected to V. ip 202 or V im 203 is achieved by controlling the position of the switch of each capacitor in capacitors 231...236 while keeping the other switches in switch array 230 open. The top plates of capacitors 211...216 are connected to the common-mode voltage signal V. cm 201 is achieved by closing switch 251.

[0106] Similarly, during the sampling phase, a dynamically scaled version of the opposite version of the analog input signal is sampled on capacitor bank 220. This is achieved by sampling the base plates of capacitors 221...226 ( Figure 2 The lower capacitor side in the middle is connected to V. ip 202 or V im203 — depending on the applicable scaling value (reversing the polarity of each capacitor compared to capacitor bank 210) — and the top plate of capacitors 221...226 ( Figure 2 The upper capacitor side is connected to the common-mode voltage signal V. cm This is achieved using 201. The base plates of capacitors 221...226 are connected to V. ip 202 or V im 203 is achieved by controlling the position of the leftmost switch of each capacitor 221...226 in the switch array 240 while keeping the other switches in the switch array 240 open. The top plates of capacitors 221...226 are connected to the common-mode voltage signal V. cm 201 is achieved by closing switch 251.

[0107] In the next stage (conversion stage), the base plates of capacitors 211...216 are switched to V. cm 201, and the top plate and V cm 201 Disconnect. Connect the base plate of capacitors 211...216 to V. cm 201 is achieved by closing the rightmost switch of each capacitor 211...216 in the switch array 230 while keeping the other switches in the switch array 230 open. The top plates of capacitors 211...216 are connected to V... cm Disconnection 201 is achieved by disconnecting switch 251. As a result, a scaled analog input signal sample is applied to the comparator input, causing a voltage drop at the positive input 252 of the comparator when V... ip =V cm At +b, the voltage V cm -sb=V cm -s(V ip -V cm ).

[0108] Similarly, in the next stage, the base plates of capacitors 221...226 were switched to V. cm 201, and the top plate and V cm 201 Disconnect. Connect the base plate of capacitors 221...226 to V. cm 201 is achieved by closing the rightmost switch of each capacitor 221...226 in the switch array 240 while keeping the other switches in the switch array 240 open. The top plates of capacitors 211...216 are connected to V... cm Disconnection 201 is achieved by disconnecting switch 251. Consequently, a scaled, inverse version of the analog input signal sample is applied to the comparator input, causing a change at the comparator's negative input 253 when V... im =Vcm At -b, the voltage V cm +sb=V cm -s(V im -V cm ).

[0109] Then, in combination with the above Figure 1 In the same manner described, comparator 250 is triggered and outputs decision 259 based on differential inputs 252 and 253.

[0110] After each comparator decision, the base plate of one of capacitors 211...216 is switched to V. ref_p 204 or V ref_ m 205, while the top plate remains in line with V. cm 201 Disconnect. Connect the base plate of one of capacitors 211…216 to V. ref_p 204 or V ref_ m 205 is achieved by closing the third or second switch counting from the right of the relevant capacitors 211...216 in the switch array 230 while keeping the other switches in the switch array 230 open. Consequently, the voltage exhibited at the positive input terminal 252 of the comparator changes accordingly.

[0111] Therefore, after each comparator decision, the base plate of one of capacitors 221...226 switches to V. ref_m 205 or V ref_p 204, while the top plate remains in line with V. cm 201 Disconnect. Connect the base plate of one of capacitors 221...226 to V. ref_m 205 or V ref_p 204 is achieved by closing the third or second switch counting from the left of the relevant capacitors 221...226 in the switch array 240 while keeping the other switches in the switch array 240 open. Consequently, the voltage exhibited at the negative input terminal 153 of the comparator changes accordingly.

[0112] Then, comparator 250 is triggered again and outputs a new decision 259 based on the differential inputs 252 and 253, in conjunction with the above. Figure 1 In the same manner described, the base plates of the relevant capacitors are iteratively connected to V. ref_m or V ref_p This triggers the comparator to make a decision until a final decision is made on the analog input signal sample; then, the capacitor bank can be reset and a new dynamically scaled sample of the analog input signal can be loaded for processing.

[0113] If it is desired to be able to represent zero-valued dynamically scaled samples of the analog input signal (i.e., the scaled value and / or the analog input signal sample value is equal to zero), a suitable method includes using additional capacitors 217 and 227 for each of the capacitor banks 210 and 220. Typically, each of the additional capacitors 217 and 227 has the base capacitance (C) of the corresponding capacitor bank.

[0114] The purpose of the additional capacitors is (e.g., by changing the grid of the quantization level) to change the scaling of the quantization level, so that a particular quantization level represents a dynamically scaled sample of the zero values ​​of the analog input signal. This can be achieved by controlling the additional capacitors 217 and 227 to bias (i.e., change) the scaling of the sample values ​​of the analog input signal.

[0115] During the sampling phase, V im 203 was sampled on the additional capacitor 217, while V ip 202 is sampled on the additional capacitor 227. This is done by sampling the base plate of capacitor 217 ( Figure 2 The upper capacitor side in the middle is connected to V. im 203 and the top plate of capacitor 217 ( Figure 2 The lower capacitor side is connected to the common-mode voltage signal V. cm 201, and by using the base plate of capacitor 227 ( Figure 2 The lower capacitor side in the middle is connected to V. ip 202 and the top plate of capacitor 227 ( Figure 2 The upper capacitor side is connected to the common-mode voltage signal V. cm This is achieved using 201. The base plates of capacitors 217 and 227 are connected to V respectively. im 203 and V ip 202 is achieved by closing switch 237 of capacitor 217 (and correspondingly capacitor 227) while keeping the other switches of capacitors 217 and 227 open. The top plates of capacitors 217...227 are connected to the common-mode voltage signal V. cm 201 is achieved by closing switch 251.

[0116] Therefore, the control circuit is configured to control a selector (e.g., switch 237) for the additional capacitor to use the analog input signal V. ip 202 sample values ​​or the inverse version V of the analog input signal im The sample value of 203 is used to charge the additional capacitors 217 and 227.

[0117] In the next stage (conversion stage); the base plates of the relevant capacitors of the capacitor bank are alternately connected to V. ref_m or V ref_pDuring the period when the comparator is triggered to make a decision, the base plates of capacitors 217 and 227 are switched to V. cm 201, and the top plate and V cm 201 Disconnect. Connect the base plates of capacitors 217 and 227 to V. cm 201 is achieved by closing the rightmost switch of each of capacitors 217 and 227 while keeping the other switches of capacitors 217 and 227 open. The top plates of capacitors 217 and 227 are connected to V... cm Disconnection 201 is achieved by disconnecting switch 251.

[0118] By applying the additional capacitor as described above, the voltage at the positive input terminal 252 of the comparator becomes V. cm -(s-β)(V ip -V cm Instead of the first read of (MSB) V cm -s(V ip -V cm And the voltage at the negative input terminal 253 of the comparator becomes V. cm -(s-β)(V im -V cm ) instead of V cm -s(V im -V cm Therefore, the scaling used to provide signal levels 252 and 253 to comparator 250 is changed, and the differential input of the comparator is changed by 2β(V). ip -V im This allows zero-value samples to be included in the quantization level.

[0119] The parameter β is proportional to the size of the additional capacitors 217 and 227. For example, for an N-bit binary-scaled SARADC, this parameter can be defined as β = α / 2. N , where α represents the proportionality constant.

[0120] For example, a scaling value of +24 can be represented by 101100 (assuming a 6-bit ADC), switches 236...231 are connected to 202, 203, 202, 202, 203, 203 respectively, and the charges of capacitors 216...211 and the additional capacitor 217 will correspond to 44V. ip +19V im +V im =24V ip , where V im =-V ip , of which 44V ip This is due to the capacitor connected to 202, 19V. imThis is due to the capacitor connected to 203, and V im This is due to the addition of capacitors.

[0121] Therefore, according to some embodiments, one or more additional capacitors are introduced that have reduced switching capability compared to the capacitors in the capacitor bank used as both sampling capacitors and DAC capacitors.

[0122] It should be noted that the additional capacitors 217 and 227 are optional and may be absent in some embodiments.

[0123] In some embodiments, the SAR ADC 200 can operate in either a mixing mode or a non-mixing mode. The mixing mode can be implemented by operating the SAR ADC as described above, while the non-mixing mode can be implemented by applying static (i.e., non-dynamic, no difference between samples) scaling values.

[0124] If additional capacitors 217 and 227 are present, the non-mixing mode may include allowing them to continue operating to alter the scaling of the sample values ​​of the analog input signal as described above, or the non-mixing mode may include statically (i.e., during the sampling phase and during the conversion phase) connecting the base plates of capacitors 217 and 227 to V. cm 201. Connect the base plates of capacitors 217 and 227 to V. cm 201 is achieved by closing the rightmost switch of each of capacitors 217 and 227 while keeping the other switches of capacitors 217 and 227 open.

[0125] Therefore, according to some embodiments, the C-DAC weights of the SAR ADC (typically designed to be well-matched) are reused to perform harmonic suppression mixing as part of the SAR ADC sampling phase. Different mixing frequencies can be obtained by changing the oversampling rate of the equivalent oscillator frequency and / or by changing the sampling rate of the SAR ADC.

[0126] According to some embodiments, an additional capacitor may be added during sampling for activation. The additional capacitor is not used during the conversion phase. The additional capacitor alters the quantization level grid, which can, for example, be used to achieve a suitable representation of the sinusoidal sampling gain sequence to ensure efficient harmonic suppression.

[0127] In SAR ADCs, combining techniques with noise shaping according to some embodiments can further improve effective resolution without adding more cycles to the SAR ADC conversion stage.

[0128] Figure 3 Some example control signal generators according to some embodiments are schematically shown.

[0129] exist Figure 3 In part (a), the binary code generator 370 is presented as having control signal outputs 371, 372, 373, 374, 375, and 376, which output set bits when triggered by the sampled signal 379. During the sampling phase, the set of bits 371, 372, 373, 374, 375, and 376 can correspond to scaling values ​​and can be used to control the positions of switches 231...236 (the same applies to switch array 240). For example, bit 371 can control switch 231, while bit 376 can be used to control switch 236; and the same applies to bits and switches between them. If the capacitor bank has a different number of capacitors than six, the size of the set of bits (i.e., the number of control signals 371...376) can be adjusted accordingly.

[0130] exist Figure 3 In part (b), the possible implementations of using scaling bit 386 (e.g., bits from any of the outputs 371, 372, 373, 374, 375, 376) to control the corresponding switches in switches 231...236 of switch array 230 are provided by Figure 3 The switch 331 in part (b) is used to represent this.

[0131] When the value of scaling bit 386 is "0" and AND gates 380 and 390 are triggered by sampling signal 389, the output 383 of AND gate 380 is "0" and the output 393 of AND gate 390 is "1". Therefore, switch 331 and analog input signal V... ip 302 disconnects and connects to the opposite version V of the analog input signal. im 303.

[0132] When the value of scaling bit 386 is "1" and AND gates 380 and 390 are triggered by sampling signal 389, the output 383 of AND gate 380 is "1" and the output 393 of AND gate 390 is "0". Thus, switch 331 is connected to the analog input signal V. ip 302, and the opposite version V of the analog input signal. im 303 Disconnection.

[0133] To control the switching of switch array 240, the corresponding arrangement can be used interchangeably with 302 and 303 (or equivalently with 380 and 390).

[0134] Therefore, control signals 371...376 can be used to connect each capacitor of the capacitor bank to either the analog input signal or the opposite version of the analog input signal by strobing the asynchronous sampling signal 389 (which may, for example, come from SAR logic 260) and the binary code generated by the binary code generator block 370.

[0135] Figure 4 Example control signals according to some embodiments are shown in the form of a timing diagram. Signal 479 represents the sampled signal (and...). Figure 3 Compared to sampling signals 379 and 389. During the sampling phase, signals 471, 472, 473, 474, 475, and 476 can represent dynamically changing scaling values ​​and can be used to control the positions of switches 231...236 (switching array 240 is similar). Signals 471, 472, 473, 474, 475, and 476 can, for example, correspond to... Figure 3 The set of bits 371, 372, 373, 374, 375, and 376 in part (a). If the capacitor bank has a number of capacitors other than six, the number of signals 471...476 can be adjusted accordingly. Figure 4 The specific example shown corresponds to the following scaling values ​​(e.g., sample values ​​for a sine signal):

[0136] Scaling value Bit pattern (376...371) 24 101100 58 111101 58 111101 24 101100 -24 010100 -58 000011 -58 000011 -24 010100

[0137] The scaling values ​​in the table above illustrate how the sampling gain varies with frequency f. LO And N samples per cycle s The next (i.e., f) LO N s The sampling frequency (equal to the sampling rate of the SAR ADC) varies with the sinusoidal signal (e.g., the local oscillator LO signal). G is the ideal scaling value for the maximum coefficient value. The quantization is scaled to the values ​​in the table above (i.e., the possible scaling values ​​are limited by the sampling gain level available to the capacitor array in the SAR ADC). To find a suitable quantization scaling value that provides efficient harmonic suppression, one can scan... G searches for configurations that meet the HR requirements under consideration.

[0138] By applying a scaling value to the SAR ADC input signal as described above (e.g., in a discrete-time series synchronized with the SAR ADC sampling), the frequency transformation f of the synthesized SAR ADC input signal is obtained. LO .

[0139] Figure 5 This schematically illustrates a method based on some embodiments. Figure 2 Example of SAR ADC 200: SAR ADC500.

[0140] Figure 5 Section (a) shows an overview of the SAR ADC 500. Figure 5 In Figure 2 The corresponding reference numerals in the accompanying drawings will not be described in further detail. It should be understood that, in conjunction with... Figure 2 The description of the features corresponding to these reference numerals also applies to... Figure 5 .

[0141] and Figure 2 Conversely, the SAR ADC 500 includes noise shaping networks 554 and 556, which are configured to provide integrals 555 and 557 of the signal levels 252 and 253 provided by capacitor banks 210 and 220. This integral is used to adjust the digital output signal 263.

[0142] The SAR ADC 500 includes a comparator 550 configured to determine the bit value 259 of the digital output signal 263 based on signal levels 252 and 253 provided by capacitor banks 210 and 220, and also based on integrals 555 and 557 provided by noise shaping networks 554 and 556.

[0143] Figure 5 Section (b) illustrates an example implementation of the noise shaping network 554. Another noise shaping network 556 can be implemented in a corresponding manner. Figure 5 Part (c) shows a timing diagram including the following signals: a sampled signal 513 with a period of 510 (and... Figure 3 Sampling signals 379, 389 and Figure 4 Compared to 479), comparator trigger signal 558, and control signals 511 and 512 for switches 501 and 502 for noise shaping network 554.

[0144] Sampling period from combination Figure 2 The operation described for the sample begins. Switch 503 is controlled by sampling signal 513 and closes during the sampling phase. This discharges capacitor 505.

[0145] After a conversion cycle indicated by multiple pulses of the comparator trigger signal 558, the residual voltage V res It remains in capacitor bank 210. Switch 501 then closes, as shown in 511. When 501 is closed, it has capacitance C. NS1 Capacitor 505 is connected to 252 and charged by capacitor bank 210, wherein the total capacitance C bank When switch 501 is opened again, capacitor 505 will have a voltage corresponding to V. res C bank / (C NS1 +C bank The voltage of the charge.

[0146] Subsequently, switch 502 closes, as shown in 512, and capacitor 505 dumps its charge onto a capacitor with capacitance C. NS2The voltage V integrated across capacitor 504 is thus effectively achieved through passive integration. int It is fed to comparator 550, as shown in 555, and used by comparator 550 during the bit transition of the next sample.

[0147] Comparator 550 to V int The use of this method can be based on any suitable approach. For example, compensation can be performed by designing the amplification stage at the comparator inputs of the received signals 555 and 557 to have a different (e.g., larger) gain than the amplification stage at the comparator inputs of the received signals 252 and 253. This different gain can be achieved by adjusting the size of the input transistors of comparator 550. Alternatively or additionally, dynamic or passive gain enhancement circuitry can be used in the input paths 555 and 557.

[0148] Therefore, comparator 550 has two input types: one input type 252, 253, which can be connected (e.g., connected) to, for example, a combination of Figure 2 The capacitor bank described; and another input type, which can be connected (e.g., connected) to the noise shaping networks 554, 556 for receiving integrals 555, 557.

[0149] The limitation of passive integrals is that only V res Part of the integration is on capacitor 504 (i.e., capacitor 504 carries V). res The integral and attenuated version). This attenuation κ can be compensated (e.g., when determining the size of the input transistors of comparator 550, by taking V into account). int The relative gain between the voltages of 252 and 253 is compensated for, as indicated above.

[0150] Figure 5 Part (d) illustrates a functional representation of the operation of the noise shaping networks 554 and 556 combined with comparator 550. The signal levels 252 and 253 provided by the capacitor bank are controlled by V... input 580 indicates that the ADC output is determined by D. out 592 indicates.

[0151] Research Figure 5 The functional representation of part (d) in the z-domain, the adder 581 from the input V input (z)580 minus ADC output D out (z)592. When switch 501 is closed, the output V of adder 581 is... res (z)582 is amplified by (1-a) times in amplifier 583.

[0152] When switch 502 is closed, passive integrator 593 amplifies the output of amplifier 583 by a factor of a in amplifier 584, and then inputs it to adder 585, which also receives input through (1-a)z. -1 The feedback block 587 passes the adder output 586.

[0153] The output V of the passive integrator 593 int (z)586 and input V input (z)580 together enters the 2-path comparator 594. The output V of the passive integrator 593 int (z)586 achieves κz -1 The input V is passed from block 588 and then added to adder 589. input (z)580. The result is added to the quantization noise Q(z)591 in adder 590 and provided as the ADC output D. out (z)592.

[0154] Output 592 quantizes the input voltage 580 and V. int The results of previous samples can be written as

[0155] D out (z)=V input (z)+Q(z)+κz -1 V int (z),

[0156] Among them, D out Q(z) is the ADC output after bit transformation and before the closed noise shaping loop, while Q(z) represents the quantization noise of the ADC before noise shaping.

[0157] When switch 501 is closed, capacitor 505 is loaded.

[0158] V NS1 =V res (z)C bank / (C NS1 +C bank ).

[0159] When switch 502 is closed

[0160] C NS1 V NS1 (n)+C NS2 V int (n-1)=(C NS1 +C NS2 V int (n),

[0161] This led to

[0162] Vint (z)=V res (z)a(1-a) / (1-(1-a)z -1 ),

[0163] or

[0164] V res (z)=V input (z)-D out (z).

[0165] Based on the above results, we can obtain

[0166] D out (z)=V input (z)+Q(z)(1-z -1 (1-a)) / (1+(1-a)(κa-1)z -1 ).

[0167] If κ = 1 / a, then the poles are removed, and first-order noise shaping is achieved. Zero is located at 1-a, and a = C. NS1 / (C NS1 +C bank C NS2 =C bank =C and C NS1 The value of C / 3 includes a = 1 / 4 and zero at 0.75. The Bode plot of this example shows that this implementation has a noise transfer function of -12dB at low frequencies; resulting in a reduction of approximately 12dB in quantization noise—depending on the bandwidth.

[0168] Figure 6 An example device 610 according to some embodiments is schematically shown. This device includes a SAR ADC 600 (e.g., combined with...). Figure 2 and Figure 5 (Any SAR ADC described). Apparatus 610 may be, for example, a receiver or a wireless communication device (e.g., user equipment—such as user equipment UE or station STA—or network node—such as base station BS or access point AP).

[0169] Figure 7 An example receiver (RX) 710 according to some embodiments is schematically shown. The device includes a SAR ADC 700 (e.g., combined with...). Figure 2 and Figure 5 As described in any SAR ADC, the SAR ADC 700 implements mixing with the oscillator signal 799, wherein the mixing function is embedded within the analog-to-digital converter, as described elsewhere herein.

[0170] Figure 8An example method 800 according to some embodiments is shown. Method 800 is used to operate a SAR ADC (e.g., in conjunction with...). Figure 2 and Figure 5 (Any SAR ADC described).

[0171] As shown in step 820, the method includes: providing a capacitor bank to a comparator with multiple signal levels representing dynamically scaled versions of sample values ​​of an analog input signal. This can be achieved by controlling a corresponding selector for each capacitor in the capacitor bank to charge the capacitor using either a sample value of the analog input signal or a sample value of the opposite version of the analog input signal, as shown in optional sub-step 822. Typically, the corresponding selector is set to a digital representation corresponding to the scaling value.

[0172] The SAR ADC can operate in mixed mode or non-mixed mode according to some embodiments, as shown in optional steps 801 and 802.

[0173] When operating in mixing mode, scaling can correspond to sample values ​​of the oscillator signal, as shown in optional step 811. Therefore, a dynamically scaled version of the sample values ​​of the analog input signal includes a representation of the sample values ​​of the analog input signal multiplied by the sample values ​​of the oscillator signal.

[0174] When operating in non-mixing mode, static scaling values ​​can be used, as shown in optional step 812.

[0175] If an offset quantization level is desired (e.g., to dynamically scale samples to represent zero values ​​of the analog input signal), the method may further include controlling an additional capacitor to change the scaling of the sample values ​​of the analog input signal, as shown in optional step 830.

[0176] Figure 9 It is a signal atlas illustrating various principles and results based on some embodiments.

[0177] The techniques according to some embodiments have been simulated using state-of-the-art CMOS process design kits, where key components (such as switches and capacitors) are represented by accurate electrical models. A 6-bit SAR ADC is implemented by adding the following functions to achieve the method proposed herein: additional capacitors 217, 227, a binary code generator 370, and signal gating 380, 390 using the output of the binary code generator; however, no noise shaping capability is provided.

[0178] Figure 9 Parts (a) and (b) show the power spectral density of the ADC output and sampling points 921, 922, 923, and 924 when the ADC input is a DC signal. The sampling frequency is 375 MHz, N s=8, and the synthesized LO frequency—corresponding to the frequency of the ADC output—is 375 / 8 = 46.875MHz. For the graph in part (a), the x-axis ranges from 0Hz to 18.10 Hz. 7 The power spectrum in section (a) shows that the third harmonic 912 is approximately 64 dB lower than the expected fundamental component 911.

[0179] A simulation was also performed for a 20.51MHz sine wave input. The resulting ADC output frequency became 46.875±20.51MHz. Figure 9 Section (c) shows the power spectral density of the ADC output. The x-axis ranges from 0 Hz to 19.10 Hz. 7 The power spectrum in section (c) shows that the third harmonic 933 is just below the expected fundamental components 931 and 932.

[0180] The described embodiments and their equivalents can be implemented in hardware. For example, the embodiments can be executed by a dedicated circuit (e.g., an application-specific integrated circuit (ASIC)). The dedicated circuit may be associated with or included in a device such as a wireless communication device (e.g., a user equipment or a network node).

[0181] Embodiments may appear within electronic devices (e.g., wireless communication devices) that include arrangements, circuitry, and / or logic according to any of the embodiments described herein. Alternatively or additionally, electronic devices (e.g., wireless communication devices) may be configured to perform methods according to any of the embodiments described herein.

[0182] Generally, unless explicitly given and / or implied by the context, all terms used herein will be interpreted according to their common meaning in the relevant technical field.

[0183] Various embodiments have been referenced herein. However, those skilled in the art will recognize that numerous variations of the described embodiments will still fall within the scope of the claims.

[0184] For example, the method embodiments described herein disclose example methods by means of steps performed in a specific order. However, it should be recognized that these events may occur in another order without departing from the scope of the claims. Furthermore, although some method steps have been described as being performed sequentially, they may be performed in parallel. Therefore, unless it must be explicitly stated that a step is after or before another step and / or implicitly stated that a step must be after or before another step, the steps of any method disclosed herein need not be performed in the exact order disclosed.

[0185] Similarly, it should be noted that the division of functional blocks into specific units in the description of the embodiments is by no means intended to be restrictive. Rather, these divisions are merely examples. A functional block described herein as a single unit may be divided into two or more units. Moreover, a functional block described herein as two or more units may be merged into fewer (e.g., a single) units.

[0186] Where appropriate, any feature of any embodiment disclosed herein may be applied to any other embodiment. Similarly, any advantage of any embodiment may be applied to any other embodiment, and vice versa.

[0187] Therefore, it should be understood that the details of the described embodiments are merely examples presented for illustrative purposes and are intended to include all variations that fall within the scope of the claims.

Claims

1. A successive approximation register-type SAR analog-to-digital converter (ADC), the SAR ADC being configured to receive an analog input signal (202) and provide a digital output signal (263), the SAR ADC comprising: Capacitor banks (210, 220) are used to continuously provide multiple signal levels (252, 253) based on sample values ​​of the analog input signal, wherein each of the multiple signal levels is an indicator of a corresponding bit in a corresponding sample of the digital output signal; and The control circuit (260) is configured to cause the capacitor bank to provide a dynamically scaled version of the plurality of signal levels representing sample values ​​of the analog input signal in such a way that: Dynamically control the corresponding selectors (231, 236) of each capacitor (211, 216, 221, 226) of the capacitor bank to charge the capacitor using a sample value of the analog input signal (202) or the opposite version (203) of the sample value of the analog input signal, and The corresponding selector is set to a digital representation of the scaling value corresponding to a dynamically scaled version of the sample value of the analog input signal.

2. The SAR ADC according to claim 1, wherein, Each sample of the digital output signal is a quantized representation of the corresponding sample of a dynamically scaled version of the sample value of the analog input signal.

3. The SAR ADC according to claim 1 or 2, wherein, The dynamically scaled version of the sample value of the analog input signal represents the sample value of the analog input signal multiplied by the sample value of the oscillator signal.

4. The SAR ADC according to claim 3, wherein, Each sample of the digital output signal is a quantized representation of the corresponding sample of the analog input signal that has been mixed with the oscillator signal.

5. The SAR ADC according to claim 3, wherein, The oscillator signal is a sinusoidal signal.

6. The SAR ADC according to claim 3, wherein, The sample value set of the oscillator signal includes at least three different values.

7. The SAR ADC according to claim 1 or 2 further includes a comparator (250) configured to determine the bit value (259) of the digital output signal (263) based on the corresponding signal levels (252, 253) provided by the capacitor bank.

8. The SAR ADC according to claim 1, wherein, The capacitance of each capacitor in the capacitor bank is equal to the base capacitance multiplied by a non-negative integer power of 2.

9. The SAR ADC according to claim 8, wherein, The capacitors in the capacitor bank have different capacitances, including a base capacitance and capacitances that increase in multiples of two.

10. The SAR ADC of claim 8 or 9 further includes an additional capacitor (217, 227) capable of controlling the scaling of the sample values ​​of the analog input signal.

11. The SAR ADC according to claim 10, wherein, The control circuit is configured to control the selector (237) of the additional capacitor to charge the additional capacitor using a sample value of the analog input signal (202) or a sample value of the opposite version (203) of the analog input signal.

12. The SAR ADC according to claim 10, wherein, The additional capacitor has the basic capacitance.

13. The SAR ADC according to claim 1 or 2, wherein, The control circuit is configured to cause operation in either a mixing mode or a non-mixing mode, wherein operation in the non-mixing mode is caused by applying a static scaling value.

14. The SAR ADC of claim 10, comprising: The first capacitor bank (210) and the second capacitor bank (220) are configured to continuously provide a first signal level (252) and a second signal level (253), wherein the first signal level (252) and the second signal level (253) are differential signal levels used to determine the digital output signal (263).

15. The SAR ADC of claim 14, comprising a first additional capacitor (217) and a second additional capacitor (227), wherein, The control circuit is configured to: control a first selector (237) of the first additional capacitor (217) to charge the first additional capacitor using a sample value of the opposite version (203) of the analog input signal; and control a second selector of the second additional capacitor (227) to charge the second additional capacitor using a sample value of the analog input signal (202).

16. The SAR ADC according to claim 1 or 2, further comprising: Noise shaping networks (554, 556) are configured to provide integrals (555, 557) of the signal levels (252, 253) provided by the capacitor banks (210, 220) in order to adjust the digital output signal (263).

17. A receiver comprising a SAR ADC (200, 500, 600, 700) according to any one of claims 1 to 16.

18. A wireless communication device comprising a SAR ADC (200, 500, 600, 700) according to any one of claims 1 to 16.

19. A method for operating a successive approximation register-type SAR analog-to-digital converter (ADC), wherein the SAR ADC is configured to receive an analog input signal and provide a digital output signal, wherein, The SAR ADC includes a capacitor bank for continuously providing multiple signal levels based on sample values ​​of the analog input signal, wherein each of the multiple signal levels is an indicator of a corresponding bit in a corresponding sample of the digital output signal, and the method includes: The capacitor bank (820) provides a dynamically scaled version of the sample values ​​of the analog input signal by means of the following: Dynamically control (822) the corresponding selector of each capacitor in the capacitor bank to charge the capacitor using a sample value of the analog input signal or a sample value of the opposite version of the analog input signal, and The corresponding selector is set to a digital representation of the scaling value corresponding to a dynamically scaled version of the sample value of the analog input signal.

20. The method according to claim 19, wherein, The dynamically scaled version of the sample values ​​of the analog input signal includes a representation of the sample values ​​of the analog input signal multiplied by the sample values ​​of the oscillator signal.

21. The method of claim 19 or 20, further comprising controlling (830) an additional capacitor to change the scaling of the sample values ​​of the analog input signal.

22. The method according to claim 19 or 20, further comprising configuring the operation of the SAR ADC in a mixing mode (801) or a non-mixing mode (802), wherein, Operations configured in non-mixing mode include applying static scaling values.

23. The method according to claim 19 or 20, wherein, The SAR ADC includes a first capacitor bank and a second capacitor bank, configured to continuously provide a first signal level and a second signal level, and the method further includes providing the first signal level and the second signal level as differential signal levels for determining the digital output signal (263).

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