Aging test method, system, and electronic device

Abstract

The present disclosure provides a wafer aging test method, system and electronic device. The wafer aging test method comprises: obtaining a test pass rate of a plurality of test units of a target chip particle at the end of an i-th aging time period, the test pass rate being a proportion of test units with a test result of pass in the plurality of test units, i being an integer greater than 1; determining a failure distribution model corresponding to the target chip particle according to the test pass rates corresponding to the first i aging time periods of the target chip particle; determining a target aging time corresponding to the target chip particle according to the failure distribution model; when the current time is less than the target aging time, continuing current aging test of the target chip particle in the next aging time period, and when the current time is greater than or equal to the target aging time, stopping the current aging test of the target chip particle. The embodiments of the present disclosure can determine a suitable current aging time for each chip particle, thereby improving the reliability of the chip product.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of wafer testing, and in particular, to a burn-in test method, system and electronic device. BACKGROUND

[0002] Failure problems of chip particles are inevitable in use, therefore, burn-in test (BI test) is usually performed on chip particles after wafer production is completed, the purpose is to make poor quality chip particles fail as soon as possible in an accelerated burn-in test environment, and to retain stable and reliable chip particles.

[0003] The prior art usually determines a fixed time as the burn-in time through experimental results of a large number of chip particles. Since different products have differences, the fixed burn-in time cannot effectively distinguish the differences between chip particles or the abnormalities in the production process, and some chip particles may have problems of over-burn-in or under-burn-in, which finally leads to that the burn-in test cannot achieve the expected effect.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to provide a burn-in test method, system and electronic device, which at least partially overcomes the problem of under-burn-in or over-burn-in of different wafers and chip particles in the wafer burn-in test process due to the limitations and defects of the related art.

[0006] According to a first aspect of an embodiment of the present disclosure, a burn-in test method is provided, comprising: obtaining a test pass rate of a plurality of test units of a target chip particle at the end of an i-th burn-in time period, the test pass rate being a proportion of test units with a test result of pass in the plurality of test units, i being an integer greater than 1; determining a failure distribution model corresponding to the target chip particle according to test pass rates corresponding to the first i burn-in time periods of the target chip particle; determining a target burn-in time corresponding to the target chip particle according to the failure distribution model; when a current time is less than the target burn-in time, continuing current burn-in test of the target chip particle in a next burn-in time period, and when the current time is greater than or equal to the target burn-in time, stopping the current burn-in test of the target chip particle.

[0007] In an example embodiment of the present disclosure, the determining the failure distribution model corresponding to the target chip particle according to the test pass rates corresponding to the target chip particle in the first i aging time periods comprises: obtaining the i test pass rates corresponding to the first i aging time periods and test times corresponding to the i test pass rates; inputting the i test pass rates and the test times corresponding to the i test pass rates into a preset formula to determine a constant of the failure distribution model, the preset formula at least comprising a Weibull distribution formula, and the failure distribution model being a model with time as a variable; and determining the failure distribution model according to the constant of the failure distribution model.

[0008] In an example embodiment of the present disclosure, the determining the target aging time corresponding to the target chip particle according to the failure distribution model comprises: setting a time corresponding to a value of the failure distribution model equal to a preset failure probability as the target aging time.

[0009] In an example embodiment of the present disclosure, the determining the target aging time corresponding to the target chip particle according to the failure distribution model comprises: determining the target aging time according to a first tangent of a curve of the failure distribution model.

[0010] In an example embodiment of the present disclosure, the determining the target aging time according to the first tangent of the curve of the failure distribution model comprises: determining an abscissa corresponding to a first intersection of the first tangent and an X axis as the target aging time.

[0011] In an example embodiment of the present disclosure, the determining the target aging time according to the first tangent of the curve of the failure distribution model comprises: determining a first intersection of the first tangent and an X axis; and determining an abscissa of a point on the curve of the failure distribution model closest to the first intersection as the target aging time.

[0012] In an example embodiment of the present disclosure, the determining the target aging time according to the first tangent of the curve of the failure distribution model comprises: determining a first intersection of the first tangent and an X axis; and determining a preset multiple of an abscissa of a point on the curve of the failure distribution model closest to the first intersection as the target aging time.

[0013] In an example embodiment of the present disclosure, the determining the target aging time according to the first tangent of the curve of the failure distribution model comprises: determining a second tangent of the curve of the failure distribution model, the X coordinate of the intersection point of the second tangent and the curve of the failure distribution model being greater than the X coordinate of the intersection point of the first tangent and the curve of the failure distribution model; determining a second intersection point of the first tangent and the second tangent; and determining the horizontal coordinate of the point on the curve of the failure distribution model closest to the second intersection point as the target aging time.

[0014] In an example embodiment of the present disclosure, the determining the target aging time according to the first tangent of the curve of the failure distribution model comprises: determining a second tangent of the curve of the failure distribution model, the X coordinate of the intersection point of the second tangent and the curve of the failure distribution model being greater than the X coordinate of the intersection point of the first tangent and the curve of the failure distribution model; determining a second intersection point of the first tangent and the second tangent; and determining a preset multiple of the horizontal coordinate of the point on the curve of the failure distribution model closest to the second intersection point as the target aging time.

[0015] In an example embodiment of the present disclosure, the determining the target aging time according to the first tangent of the curve of the failure distribution model comprises: determining a second tangent of the curve of the failure distribution model, the X coordinate of the intersection point of the second tangent and the curve of the failure distribution model being greater than the X coordinate of the intersection point of the first tangent and the curve of the failure distribution model; determining a second intersection point of the first tangent and the second tangent; and determining a preset multiple of the horizontal coordinate of the point on the curve of the failure distribution model closest to the second intersection point as the target aging time.

[0016] In an example embodiment of the present disclosure, the number of the plurality of test units of the target chip particle is such that when the failure probability reaches a preset value, the confidence is greater than or equal to 0.95, the confidence being obtained according to the failure probability and the number of the test units.

[0017] In an example embodiment of the present disclosure, the target chip particle is one of a plurality of chip particles in a target wafer, and the method further comprises: stopping the environmental aging test on the target wafer when all the plurality of chip particles in the target wafer reach the corresponding target aging time.

[0018] According to a second aspect of the embodiments of the present disclosure, there is provided an aging test system, comprising: a test result acquisition component configured to acquire a test pass rate of a plurality of test units of a target chip particle at the end of an i th aging time period, the test pass rate being a proportion of test units with a test result of pass in the plurality of test units, i being an integer greater than 1; a failure model fitting component configured to determine a failure distribution model corresponding to the target chip particle according to test pass rates of the target chip particle in the previous i aging time periods; an aging time determination component configured to determine a target aging time corresponding to the target chip particle according to the failure distribution model; and an aging time control component configured to continue current aging test of the target chip particle in a next aging time period when a current time is less than the target aging time, and stop the current aging test of the target chip particle when the current time is greater than or equal to the target aging time.

[0019] According to a third aspect of the present disclosure, there is provided an electronic device, comprising: a memory; and a processor coupled to the memory, the processor being configured to execute a method according to any one of the preceding aspects based on instructions stored in the memory.

[0020] According to a fourth aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon a program which, when executed by a processor, implements an aging test method according to any one of the preceding aspects.

[0021] The embodiments of the present disclosure can determine a suitable aging time for each chip particle by generating a failure distribution model corresponding to a target chip particle according to test pass rates of a plurality of test units of the target chip particle at the end of each aging time period, and then determining a target aging time corresponding to the target chip particle, and determining whether to continue current aging test of the target chip particle according to the target aging time, thereby avoiding the problem of under-aging or over-aging of some wafers or chip particles caused by using a uniform aging time in the related art, and effectively improving the reliability of chip products.

[0022] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is apparent that the accompanying drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor based on these drawings.

[0024] Figure 1is a flowchart of an aging test method in an example embodiment of the present disclosure.

[0025] Figure 2 is a diagram for determining a target aging time in one embodiment of the present disclosure.

[0026] Figure 3 is a diagram for determining a target aging time in another embodiment of the present disclosure.

[0027] Figure 4 is a diagram for determining a target aging time in one embodiment of the present disclosure.

[0028] Figure 5 is a diagram for determining a target aging time in one embodiment of the present disclosure.

[0029] Figure 6 is a block diagram of an aging test system in an example embodiment of the present disclosure.

[0030] Figure 7 is a block diagram of an electronic device in an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, the example embodiments can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or

[0032] In addition, the accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0033] The example embodiments of the present disclosure will now be described in detail below with reference to the accompanying drawings. The example embodiments of the present disclosure are not limited to the examples set forth herein and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the present disclosure can be practiced without one or more of the specific details, or

[0034] The example embodiments of the present disclosure will now be described in detail below with reference to the accompanying drawings. The example embodiments of the present disclosure are not limited to the examples set forth herein and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the present disclosure can be practiced without one or more of the specific details, orFigure 1 is a flowchart of an aging test method in an example embodiment of the present disclosure.

[0035] Referring to Figure 1 , the aging test method 100 can include:

[0036] Step S1, obtaining a test pass rate of a plurality of test units of a target chip particle at the end of an i th aging time period, the test pass rate being a proportion of test units with a test result of pass in the plurality of test units, i being an integer greater than 1;

[0037] Step S2, determining a failure distribution model corresponding to the target chip particle according to test pass rates corresponding to the previous i aging time periods of the target chip particle;

[0038] Step S3, determining a target aging time corresponding to the target chip particle according to the failure distribution model;

[0039] Step S4, continuing current aging test of the target chip particle in a next aging time period when a current time is less than the target aging time, and stopping current aging test of the target chip particle when the current time is greater than or equal to the target aging time.

[0040] Embodiments of the present disclosure generate a failure distribution model corresponding to a target chip particle according to test pass rates of a plurality of test units of the target chip particle at the end of each aging time period, and then determine a target aging time corresponding to the target chip particle, to determine whether to continue current aging test of the target chip particle according to the target aging time. This can determine a suitable aging time for each chip particle, avoiding the problem of insufficient aging or excessive aging of some wafers or chip particles caused by using a unified aging time in related technologies, and effectively improving the reliability of chip products.

[0041] Related technologies generally perform experiments in advance, and determine an aging time length that meets a condition of a failure probability (or test pass rate) according to aging test results of a large number of chip particles (dies) as an aging time length of all wafers in a subsequent actual test process. Determining that the failure probability meets the preset condition requires that the confidence of the failure probability be greater than or equal to 0.95.

[0042] The relationship between the sample number n of the aging test result and the confidence C of the failure probability F is:

[0043] C=1-R n (1)

[0044] Wherein, R=1-F, F*1000000 is PPM (parts per million, the number of failed samples in one million samples). Assuming R is 0.999 and F is 0.001, the sample number n needs to reach 2994 to make the confidence reach or be higher than 0.95. The wafer with the largest size currently contains 900 chip particles (dies), so in the related art, a large number of product batches of wafers need to be used for experiments to obtain a number of experimental results (for example, 2994) to meet the confidence requirement, which requires a long test period and high cost.

[0045] In addition, there are differences in the production process of each chip particle, and setting the same aging time for a large number of chip particles will cause some chip particles to be over-aged or under-aged.

[0046] In the embodiments of the present disclosure, the aging time is determined in units of chip particles, and each chip particle is aged using the aging time corresponding to the chip particle, so that each chip particle can be properly aged and over-aging or under-aging can be avoided.

[0047] The determination method of the aging time corresponding to a chip particle is described below by taking one chip particle (i.e., a target chip particle) as an example. It can be understood that the method can be applied to each chip particle on a wafer, that is, different aging times can be set for different chip particles on a wafer. Since the wafer aging test includes environmental aging test and current aging test, the environmental aging test needs to be performed on the entire wafer, so the aging time of the chip particle determined in the embodiments of the present disclosure refers to the current aging time, and when all the chip particles in a wafer reach the current aging time, the environmental aging test of the wafer as a whole is ended after the current aging is ended.

[0048] Next, each step of the aging test method 100 is described in detail.

[0049] In step S1, the test pass rate of a plurality of test units of the target chip particle at the end of the i th aging time period is obtained, the test pass rate is the proportion of test units with a test result of pass in the plurality of test units, and i is an integer greater than 1.

[0050] In the embodiments of the present disclosure, the target chip particle is first divided into a plurality of test units to meet the confidence requirement. Generally, one chip particle has a plurality of banks, and each bank contains a plurality of storage arrays. The division of the test units can be based on the storage arrays or the banks, and only the number of test units needs to reach a preset value (for example, 2994), and the present disclosure does not limit the specific division method of the test units.

[0051] Secondly, Method 100 is executed during the actual testing of the wafer, and the target aging time of a target chip particle is determined in real time, rather than determined by pre-testing. Therefore, Method 100 can save the cost of conducting wafer aging time determination experiments, and not only has better aging effect, but also improves the efficiency of aging test and reduces the cost of aging test.

[0052] To determine the target aging time of the target chip in real time, this embodiment sets multiple aging time periods during the aging test process, each period being of equal duration. During the aging test, after each aging time period is completed, multiple test units of the target chip are tested once. The test result is either pass or fail. The ratio of the number of test units that pass to the number of test units participating in the current test is the pass rate at the current time, and the ratio of the number of test units that fail to the number of test units participating in the current test is the failure probability at the current time.

[0053] In step S2, the failure distribution model corresponding to the target chip particle is determined based on the test pass rate of the target chip particle in the first i aging time periods.

[0054] Assume the test pass rate at the end of the i-th aging period is R(t) i The pass rate at the end of the (i-1)th aging period is R(t). i-1 ), and so on, based on multiple test pass rates, we can obtain the test pass rate curve R(t), where t is the aging time and t is a variable. From the above definition, we can see that the failure probability curve F(t) can be expressed by the following formula based on the test pass rate curve R(t):

[0055] F(t)=1-R(t) (2)

[0056] F(t) refers to unreliability, also known as the failure probability function. Its standard definition is "the probability that a product cannot perform its intended function within a specified time and under specified conditions." It is a function corresponding to reliability R(t), and at any given moment, F(t) + R(t) = 1. It is the integral of the failure density function f(x) over a period of time, and is a cumulative function.

[0057] Next, the failure probability curve is fitted to obtain a failure distribution model (i.e., failure distribution function). This failure distribution model describes how the failure probability of the target chip changes over time with the current number of test units. Based on this failure distribution model, the aging time corresponding to when the failure probability and confidence level reach the preset value can be determined. This aging time is the target aging time that corresponds to the target chip and can achieve the best aging effect.

[0058] A Weibull distribution model, a normal distribution model, or a lognormal distribution model, etc. can be used to calculate the failure distribution model.

[0059] In one embodiment of the present disclosure, the failure distribution model is determined as λ(t) using a Weibull distribution model as an example. λ(t) is also referred to as failure rate, and its standard definition is "the probability of products that have not failed at a certain time failing in the next unit time", that is, the possibility of product failure at a certain time is an instantaneous function. However, when the unit time is lengthened, the failure rate will become the cumulative function F(t) in the unit time. The Weibull distribution model includes two forms of three parameters and two parameters, and the three-parameter Weibull distribution model can be converted into the two-parameter Weibull distribution model. In the present embodiment, the three-parameter Weibull distribution model or the two-parameter Weibull distribution model can be used. The parameters of the three-parameter Weibull distribution model include β, η, and γ, wherein β is a shape parameter, the value of β is greater than 0, determines the shape of the distribution curve, η is a scale parameter, the value of η is greater than 0, and plays a role in amplifying and reducing the scale of the horizontal coordinate, and γ is a position parameter, the value of γ is greater than or equal to 0, and determines the starting position of the distribution curve. When the value of γ is 0, the three-parameter Weibull distribution model is converted into the two-parameter Weibull distribution model. The failure distribution function of the two-parameter Weibull distribution model is shown in formula (3):

[0060]

[0061] The formula (2) is transformed to obtain:

[0062]

[0063] The natural logarithm of both sides of formula (4) is obtained:

[0064]

[0065] The natural logarithm of both sides of formula (5) is obtained again:

[0066] ln[-ln(1-F(t))]=βlnt-βlnη (6)

[0067] Since F(t) and t can be obtained based on the current test results, the values of β and η can be obtained by measuring F(t) corresponding to multiple time points t.

[0068] Let x=lnt, y=ln[-ln(1-F(t))], and a plurality of groups of x and y are obtained according to a plurality of measurement results, and thus the values of β and η can be quickly fitted according to the following formula:

[0069]

[0070]

[0071] wherein x and y are both based on the current time point (i.e. the time at the end of the ith aging time period), and are the average value of x and the average value of y corresponding to each aging time period that has been tested, and n is the number of units tested, i.e. the sample size. The values of β and η can be obtained from the x and y values obtained from the previous measurements, and can then be brought into equation (9) to obtain the value of the fitted failure distribution function λ(t):

[0072]

[0073] From the λ(t) curve, the predicted failure probability F(t) at any time point t can be obtained, whether t is a past time, a current time or a future time. It can be understood that since the λ(t) curve is fitted, the value of F(t) can be close to the measured value, but not necessarily equal to the measured value.

[0074] At step S3, a target aging time corresponding to the target chip particle is determined according to the failure distribution model.

[0075] In one embodiment, the time at which the failure probability reaches a preset standard value can be determined as the target aging time of the target chip particle according to the failure distribution model.

[0076] Suppose the confidence C is required to reach 0.95, and the sample size n (the number of units tested in the target chip particle) is 3000. According to equation (1), the failure probability F needs to reach 0.0002, i.e. Fspec=200PPM.

[0077] Setting λ(t) in equation (9) to reach the above Fspec at time T, then we have:

[0078]

[0079] According to the value of the above Fspec and the values of β and η, the value of T can be obtained, which is the target aging time of the target chip particle.

[0080] In another embodiment, the target aging time can also be determined according to the tangent of the λ(t) curve.

[0081] Figure 2 is a schematic diagram for determining the target aging time in one embodiment of the present disclosure.

[0082] Reference Figure 2, the curve λ(t) is a monotonically decreasing curve, representing that the failure probability decreases as time increases, i.e., the ratio of the test units that fail the test to the test units that participate in the test decreases. Since the test units that fail the test are removed from the later test, the number of the test units that participate in the test decreases. In addition, since the test units with poor performance fail rapidly in the early stage of the aging test, the number of the test units that fail the test decreases as the test time increases.

[0083] In Figure 2 In the embodiment shown in FIG. 8, the intersection of the tangent line of the failure distribution function and the X-axis is determined as the target aging time. As shown in FIG. 8, the tangent line of the failure distribution function λ(t) is a, the intersection of the tangent line a and the X-axis is A, and the time T1 corresponding to the point A (i.e., the horizontal coordinate of the point A) is the target aging time. Figure 2 In the embodiment shown in FIG. 8, the intersection of the tangent line of the failure distribution function and the X-axis is determined as the target aging time. As shown in FIG. 8, the tangent line of the failure distribution function λ(t) is a, the intersection of the tangent line a and the X-axis is A, and the time T1 corresponding to the point A (i.e., the horizontal coordinate of the point A) is the target aging time.

[0084] The tangent line a can be obtained according to at least three points on λ(t). In one embodiment, a straight line can be fitted as the tangent line a according to at least three points on λ(t). In another embodiment, the tangent line of the curve connected by at least three points on λ(t) can be obtained. The number of points used to determine the tangent line a and the method can be various, and the present disclosure does not make special limitations thereon.

[0085] Figure 3 FIG. 9 is a schematic diagram of determining the target aging time in another embodiment of the present disclosure.

[0086] Referring to Figure 3 In another embodiment, the time corresponding to the intersection A of the tangent line a of the failure distribution function λ(t) and the X-axis to the nearest point B of the curve λ(t) can be set as the target aging time.

[0087] The shortest distance between the point A and the curve λ(t) can be calculated, and then the position of the point B on the curve λ(t) can be determined according to the shortest distance, and the horizontal coordinate T2 of the point B is set as the target aging time.

[0088] According to Figure 3 The target aging time determined according to the embodiment shown in FIG. 8 is relatively long, and the problem of insufficient aging can be avoided.

[0089] In another embodiment of the present disclosure, the horizontal coordinate T2 of the point B can also be multiplied by a coefficient α to obtain the target aging time T3:

[0090] T3 = α * T2 (11)

[0091] To further avoid the problem of insufficient aging. The coefficient can be flexibly adjusted according to the quality stability of the production line. For example, when the quality of the production line is stable, the target aging time can be shortened, and the coefficient is set to be less than 1. When the quality of the production line is unstable, the target aging time can be increased, and the coefficient is set to be greater than 1, for example, 2. Those skilled in the art can set the above-mentioned coefficient, and the present disclosure is not limited thereto.

[0092] Figure 4 is a schematic diagram for determining the target aging time in an embodiment of the present disclosure.

[0093] Reference Figure 4 In still another embodiment, the target aging time can be determined according to the intersection C of two tangent lines of the curve λ(t). The tangent line a of the curve λ(t) can be determined according to a plurality of sampling points of an earlier time, and the tangent line b of the failure distribution function λ(t) can be determined according to a plurality of sampling points of a later time, that is, the X coordinate of the sampling point of the tangent line b is greater than the X coordinate of the sampling point of the tangent line a. In some embodiments, the sampling point of the tangent line a can include the point with the maximum Y coordinate on the curve λ(t), and the sampling point of the tangent line b can include the point with the minimum Y coordinate on the curve λ(t), as shown in Figure 4 The method for determining the tangent line according to the sampling points can be the same as the embodiment shown in Figure 2 , and the present disclosure will not be repeated here.

[0094] After determining the tangent line a and the tangent line b, the intersection C of a and b can be determined, and then the abscissa T4 of the intersection C can be set as the target aging time.

[0095] Figure 5 is a schematic diagram for determining the target aging time in an embodiment of the present disclosure.

[0096] Reference Figure 5 In still another embodiment, the abscissa T5 of the shortest point D of the curve λ(t) from the intersection C of the tangent line a and the tangent line b can be set as the target aging time.

[0097] Or further, multiply the time point T5 corresponding to the point D by a coefficient α to obtain the target aging time, and the coefficient α can be set according to the quality stability of the production line.

[0098] The above method for determining the target aging time is only an example, and there can be many methods for determining the target aging time according to the failure distribution model (failure distribution function), and the present disclosure does not make special limitations thereto.

[0099] In step S4, when the current time is less than the target aging time, continue to perform current aging test on the target chip particle for the next aging time period, and when the current time is greater than or equal to the target aging time, stop the current aging test on the target chip particle.

[0100] According to the test result obtained at the current time (i.e. at the end of the i th aging time period), the target aging time corresponding to the target chip particle is determined in real time. If the current time has exceeded the target aging time, it means that the failure probability of the target chip particle has reached the target value at this time, and the current aging of the target chip particle needs to be stopped to avoid over-aging of the target chip particle. However, the environmental aging test may not be stopped because other chip particles on the same wafer may still need to continue the aging test. If the current time has not reached the target aging time, the aging test of the target chip particle in the next aging time period is continued to avoid under-aging.

[0101] After all chip particles on the target wafer where the target chip particle is located reach the target aging time, the environmental aging test of the target wafer is stopped.

[0102] In summary, the wafer aging test method provided by the embodiments of the present disclosure can analyze the appropriate target aging time in real time according to the stage test situation of the chip particle, and can specifically age the chip particle to avoid under-aging or over-aging of some chip particles caused by using a uniform aging time, and can effectively improve the stability of the chip based on the production of the chip particle. In addition, since the test is performed in real time and the aging is controlled in real time, there is no need to use a large number of wafers for testing in advance, and the testing cost required in the related art can be saved.

[0103] Corresponding to the above method embodiments, the present disclosure also provides an aging test system which can be used to execute the above method embodiments.

[0104] Figure 6 is a block diagram of an aging test system in an exemplary embodiment of the present disclosure.

[0105] Reference Figure 6 , the aging test system 600 can include:

[0106] The test result acquisition component 61 is configured to acquire the test pass rate of the plurality of test units of the target chip particle at the end of the i th aging time period, the test pass rate being the proportion of test units with a test result of pass in the plurality of test units, and i being an integer greater than 1;

[0107] The failure model fitting component 62 is configured to determine the failure distribution model corresponding to the target chip particle according to the test pass rates of the target chip particle in the previous i aging time periods;

[0108] The aging time determination component 63 is configured to determine the target aging time corresponding to the target chip particle according to the failure distribution model;

[0109] The aging time control component 64 is configured to continue the current aging test on the target chip particle in the next aging time period when the current time is less than the target aging time, and stop the current aging test on the target chip particle when the current time is greater than or equal to the target aging time.

[0110] Since the functions of the apparatus 600 have been described in detail in the corresponding method embodiments, the present disclosure will not be repeated here.

[0111] It should be noted that although several components or units for performing actions are mentioned in the above detailed description, such division into components or units is not mandatory. Indeed, two or more components or units described above as separate can be implemented as a single component or unit in accordance with the embodiments of the present disclosure. Conversely, a component or unit described above as single can be implemented as multiple components or units in accordance with the embodiments of the present disclosure.

[0112] In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

[0113] Those skilled in the art can understand that various aspects of the present disclosure can be implemented as a system, a method or a program product. Therefore, various aspects of the present disclosure can be embodied as a complete hardware embodiment, a complete software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects, which can be collectively referred to as "circuitry", "component" or "system" herein.

[0114] The electronic device 700 according to this embodiment of the present disclosure will be described below with reference to Figure 7 Figure 7 The electronic device 700 shown is merely an example and should not be taken as limiting the functionality or use of embodiments of the present disclosure.

[0115] As shown in Figure 7 The electronic device 700 is in the form of a general computing device. The components of the electronic device 700 can include, but are not limited to, the at least one processing unit 710 described above, the at least one storage unit 720 described above, and a bus 730 connecting different system components, including the storage unit 720 and the processing unit 710.

[0116] The storage unit stores program code that can be executed by the processing unit 710, so that the processing unit 710 performs the steps described in the "Exemplary Method" section of the present specification according to various exemplary embodiments of the present disclosure. For example, the processing unit 710 can perform the method as shown in the embodiments of the present disclosure.

[0117] ​The storage unit 720 can include a readable medium in the form of volatile storage such as random access memory (RAM) 7201 and / or cache memory 7202, and also possibly non-volatile storage such as read only memory (ROM) 7203.

[0118] The storage unit 720 can also include a program / utility 7204 having a set of program components 7205 including, but not limited to: an operating system, one or more applications, other program components, and program data, each of which or a combination thereof can include implementation of a network environment.

[0119] The bus 730 can represent one or more of several types of bus structures, including a storage bus or bus controller, a peripheral bus, a graphics acceleration bus, a processor or local bus using any of a variety of bus architectures.

[0120] The electronic device 700 can also communicate with one or more external devices 800 such as a keyboard or pointing device, a Bluetooth device, etc.; other devices such as printers, scanners, etc.; and / or various devices to enable a user to interact with the electronic device 700 in various ways (e.g., a digital camera, etc.). Such input devices can be coupled through the input / output (I / O) interface(s) 750. Finally, the electronic device 700 can communicate with one or more networks, such as one or more areas networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet, via the network adapter 760. As indicated above, the network adapter 760 can be communicatively coupled to the other components of the electronic device 700 via the bus 730. It will be appreciated that various components (e.g., those not specifically shown) can be used in conjunction with the electronic device 700. For example, various types of storage devices, including devices based on RAM, hard disk, or other devices, can be utilized. Other devices can include devices that enable communications between the electronic device 700 and other electronic devices, such as a wireless communication device, a modem, etc.

[0121] Those skilled in the art will readily understand that the example embodiments described herein can be implemented by software and / or by software in combination with the necessary hardware. Thus, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash disk, a mobile hard disk, etc.) or a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to perform the methods according to the embodiments of the present disclosure.

[0122] In the exemplary embodiments of the present disclosure, a computer readable storage medium having stored thereon a program product capable of implementing the above-described method of the specification is also provided. In some possible implementations, various aspects of the present application can also be implemented in the form of a program product including program code, which, when run on a terminal device, causes the terminal device to perform the steps described in the above "Exemplary Method" section according to various exemplary embodiments of the present application.

[0123] The program product for implementing the above-described method according to the embodiments of the present application can take a portable compact disc read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present application is not limited thereto, and in the present document, the readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus or device.

[0124] The program product can take any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium, for example, can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or any combination thereof. More specific examples (non-exhaustive list) of the readable storage medium include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0125] The computer readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, in which readable program code is borne. Such propagated data signal can take many forms, including but not limited to electro-magnetic signal, optical signal or any suitable combination thereof. The readable signal medium can also be any readable medium that is not a readable storage medium and that can transmit, propagate or transport for use by or in connection with an instruction execution system, apparatus or device program.

[0126] The program code contained on the readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination thereof.

[0127] The program code may, for example, be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's computing device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device or entirely on the remote computing device or server. In the latter scenario, the remote computing device can be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computing device, for example, through the Internet using an Internet Service Provider.

[0128] Furthermore, the above-described diagrams are merely schematic illustrations of the processes included in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It is readily understood that the processes shown in the above-described diagrams do not indicate or limit the time sequence of the processes. In addition, it is readily understood that the processes can be executed synchronously or asynchronously, for example, in a plurality of modules.

[0129] Other embodiments of the disclosure will be apparent to those of ordinary skill in the art from a consideration of the specification and practice of the disclosure disclosed herein. The specification and examples given herein are only intended to be illustrative and are not intended to limit the true scope and spirit of the present disclosure. The true scope and spirit of the present disclosure are indicated by the following claims.

Claims

1. An aging test method, characterized in that, include: Set multiple aging time periods, each with an equal duration; The test pass rate of multiple test units of the target chip is obtained at the end of the i-th aging time period. The test pass rate is the proportion of test units with a pass result among the multiple test units, where i is an integer greater than 1. The failure distribution model corresponding to the target chip particle is determined based on the test pass rate of the target chip particle in the first i aging time periods. The target aging time corresponding to the target chip particle is determined based on the failure distribution model. If the current time is less than the target aging time, continue the current aging test for the target chip for the next aging period. If the current time is greater than or equal to the target aging time, stop the current aging test for the target chip.

2. The aging test method as described in claim 1, characterized in that, The step of determining the failure distribution model corresponding to the target chip particle based on the test pass rate of the target chip particle in the first i aging time periods includes: Obtain the i test pass rates corresponding to the end of the first i aging time periods and the test time corresponding to the i test pass rates; The pass rates of the i tests and the test times corresponding to the i test pass rates are substituted into a preset formula to determine the constants of the failure distribution model. The preset formula includes at least the Weibull distribution formula, and the failure distribution model is a model in which time is the variable. The failure distribution model is determined based on the constants of the failure distribution model.

3. The aging test method as described in claim 1, characterized in that, Determining the target aging time corresponding to the target chip particle based on the failure distribution model includes: The time when the value of the failure distribution model equals the preset failure probability is set as the target aging time.

4. The aging test method as described in claim 1, characterized in that, Determining the target aging time corresponding to the target chip particle based on the failure distribution model includes: The target aging time is determined based on the first tangent line of the curve of the failure distribution model.

5. The aging test method as described in claim 4, characterized in that, Determining the target aging time based on the first tangent line of the curve of the failure distribution model includes: The x-coordinate corresponding to the first intersection point of the first tangent line and the first X-axis is determined as the target aging time.

6. The aging test method as described in claim 4, characterized in that, Determining the target aging time based on the first tangent line of the curve of the failure distribution model includes: Determine the first intersection point of the first tangent line and the X-axis; The x-coordinate of the point on the curve of the failure distribution model that is closest to the first intersection point is determined as the target aging time.

7. The aging test method as described in claim 4, characterized in that, Determining the target aging time based on the first tangent line of the curve of the failure distribution model includes: Determine the first intersection point of the first tangent line and the X-axis; The target aging time is determined by a preset multiple of the abscissa of the point on the curve of the failure distribution model that is closest to the first intersection point.

8. The aging test method as described in claim 4, characterized in that, Determining the target aging time based on the first tangent line of the curve of the failure distribution model includes: Determine a second tangent line to the curve of the failure distribution model, wherein the X-coordinate of the intersection point of the second tangent line and the curve of the failure distribution model is greater than the X-coordinate of the intersection point of the first tangent line and the curve of the failure distribution model; Determine the second intersection point of the first tangent and the second tangent; The x-coordinate corresponding to the second intersection point is determined as the target aging time.

9. The aging test method as described in claim 4, characterized in that, Determining the target aging time based on the first tangent line of the curve of the failure distribution model includes: Determine a second tangent line to the curve of the failure distribution model, wherein the X-coordinate of the intersection point of the second tangent line and the curve of the failure distribution model is greater than the X-coordinate of the intersection point of the first tangent line and the curve of the failure distribution model; Determine the second intersection point of the first tangent and the second tangent; The x-coordinate of the point on the curve of the failure distribution model that is closest to the second intersection point is determined as the target aging time.

10. The aging test method as described in claim 4, characterized in that, Determining the target aging time based on the first tangent line of the curve of the failure distribution model includes: Determine a second tangent line to the curve of the failure distribution model, wherein the X-coordinate of the intersection point of the second tangent line and the curve of the failure distribution model is greater than the X-coordinate of the intersection point of the first tangent line and the curve of the failure distribution model; Determine the second intersection point of the first tangent and the second tangent; The target aging time is determined by a preset multiple of the abscissa of the point on the curve of the failure distribution model that is closest to the second intersection point.

11. The aging test method as described in claim 1, characterized in that, The number of test units in the target chip is such that when the failure probability reaches a preset value, the confidence level is greater than or equal to 0.95, and the confidence level is obtained based on the failure probability and the number of test units.

12. The aging test method as described in claim 1, characterized in that, The target chip is one of multiple chip chips in the target wafer, and the method further includes: When all the chip particles of the target wafer have reached the corresponding target aging time, the environmental aging test on the target wafer is stopped.

13. An aging test system, characterized in that, include: The test result acquisition component sets multiple aging time periods, each with an equal duration, and acquires the test pass rate of multiple test units of the target chip at the end of the i-th aging time period. The test pass rate is the percentage of test units among the multiple test units whose test results are passed, where i is an integer greater than 1. The failure model fitting component is configured to determine the failure distribution model corresponding to the target chip particle based on the test pass rate of the target chip particle in the first i aging time periods. The aging time determination component is configured to determine the target aging time corresponding to the target chip particle based on the failure distribution model. The aging time control component is configured to continue the current aging test of the target chip for the next aging time period when the current time is less than the target aging time, and to stop the current aging test of the target chip when the current time is greater than or equal to the target aging time.

14. An electronic device, characterized in that, include: Memory; as well as A processor coupled to the memory, the processor being configured to execute the aging test method as described in any one of claims 1-12 based on instructions stored in the memory.

15. A computer-readable storage medium having a program stored thereon that, when executed by a processor, implements the aging test method as described in any one of claims 1-12.

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