An adjustable adaptive bias structure

Abstract

The application discloses a kind of adjustable adaptive bias structure, applied to electronic circuit design field, including mainly by adjustable attenuation unit The adjustable power distribution module, mainly by capacitor, transistor differential pair and current mirror The adjustable power-current conversion module, mainly by transistor Current subtraction circuit module, output is the bias voltage of radio frequency amplifier or other nonlinear active device.The application is applicable to CMOS process, also applicable to other silicon-based or compound semiconductor process, utilize the difference of different device radio frequency power-direct current conversion characteristics, and through digital or analog signal control, realize that the adjustment direction and adjustment degree controllable power adaptive bias voltage, to reach the linearization compensation of radio frequency amplifier or system with different power characteristics.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit design, and particularly relates to an adjustable adaptive bias structure. BACKGROUND

[0002] Today, wireless communication technology is developing rapidly, and the requirements for channel capacity and data transmission rate are increasing. In order to utilize the high-frequency spectrum resources and improve the spectrum utilization rate, high-speed wireless communication systems are mostly deployed in high-frequency microwave bands and millimeter wave bands, and high-order modulation technology is adopted. This puts high requirements on the linearity of wireless receivers and transmitters.

[0003] Amplifiers are the most important linearity limiting modules in receivers and transmitters. Especially power amplifiers, whose linearization technology is widely concerned. After decades of development, various linearization technologies including predistortion, adaptive control, feedback, feedforward and digital processing have been developed. In the design of high-frequency microwave and millimeter wave CMOS or GaAs integrated circuits, since the receiver and transmitter are required to be absolutely stable, short response time, wide bandwidth and low circuit cost, the adaptive bias technology is more suitable. The existing adaptive bias technology usually only aims at the power characteristics of single-stage class-A or class-AB power amplifiers. Its technical idea is to provide a bias voltage that increases with the increase of power, so as to compensate for the decrease of gain with the increase of power in the high-power interval of the amplifier. However, more and more application scenarios have put forward new requirements for the linearity of transceivers, and the traditional idea is difficult to meet the requirements. For example, in a multi-functional module cascade system, a receiver with a large dynamic range, or a wideband transceiver circuit with several octaves of bandwidth, only class-A amplifiers cannot meet the requirements of high input linearity, wide bandwidth, low noise and low power consumption at the same time. The non-linear distortion introduced by multi-stage class-AB or class-B amplifiers is more complex than that of single-stage amplifiers, and the traditional adaptive bias technology cannot solve it well.

[0004] Monolithic microwave integrated circuits usually adopt high electron mobility transistor (HEMT) processes such as gallium arsenide (GaAs) and gallium nitride (GaN), but their process cost is relatively high, and they cannot be integrated with low-cost CMOS digital logic circuits, so they are difficult to be widely applied to 5G mobile communication, automotive radar and civil satellite communication markets. On the other hand, CMOS technology performs well in integration and cost, but its power supply voltage and breakdown voltage are both low, which seriously affects its performance at high power. SUMMARY

[0005] Technical purposes: the existing adaptive bias technology is only applicable to class A or AB power amplifier, aiming at the defect of narrow adaptability, the application discloses a kind of adjustable adaptive bias structure, the difference of the conversion characteristics of two different devices radio frequency power-direct current is extracted, and the power adaptive bias voltage with controllable adjustment direction and adjustment degree is output by digital or analog control, to realize the linearization of radio frequency amplifier or circuit system with different power characteristics, with very small area and power consumption.

[0006] Technical scheme: to achieve the above object, the application provides the following technical scheme:

[0007] An adjustable adaptive bias structure includes an adjustable power distribution module mainly composed of an adjustable attenuation unit, a first adjustable power-current conversion module and a second adjustable power-current conversion module mainly composed of a capacitor, a transistor differential pair and a current mirror, and a current subtraction circuit module mainly composed of a transistor, wherein,

[0008] The adjustable power distribution module is connected to the input signal of the adjustable adaptive bias structure, and is used for power distribution of the input signal of the adjustable adaptive bias structure.

[0009] The input end of the first adjustable power-current conversion module is connected to one output end of the adjustable power distribution module, for converting the detected power signal into a direct current signal, and then converting it into a voltage signal through a current mirror and setting it as an output end.

[0010] The input end of the second adjustable power-current conversion module is connected to another output end of the adjustable power distribution module, for converting the detected power signal into a direct current signal, and then converting it into a voltage signal through a current mirror and setting it as an output end.

[0011] The two input ends of the current subtraction circuit module are respectively connected to the output ends of the first adjustable power-current conversion module and the second adjustable power-current conversion module, for taking out the difference between the direct current signal one and the direct current signal two, and converting it into a voltage signal, and outputting as the output signal of the adjustable adaptive bias structure, i.e. power adaptive voltage.

[0012] As preferred, the adjustable power distribution module includes adjustable attenuation units with the same structure, i.e. a first amplitude control module and a second amplitude control module, and two groups of amplitude control signals and input ends of the first amplitude control module and the second amplitude control module are connected in parallel, wherein the amplitude control signal is connected with the corresponding amplitude control module; the input end of the adjustable power distribution module is connected to the input end of the adjustable adaptive bias structure, the output end of the first amplitude control module is connected to the first output end of the adjustable power distribution module, and the output end of the second amplitude control module is connected to the second output end of the adjustable power distribution module.

[0013] As a preferred, the first amplitude control module is a switch resistance array, including n+1 parallel array units and a digital control signal corresponding to each array unit, V d0 - V dn , the digital control signal is used to control the array unit to be in the on state or the off state. The nth array unit is connected to the corresponding digital control signal V dn , where n∈N.

[0014] As a preferred, the array unit structure of the first amplitude control module is the same, which is the series structure of CMOS transistor switch and resistance. The first array unit includes a first resistance, a first transistor, a second resistance, a third resistance, a second transistor and a fourth resistance, wherein one end of the first resistance and the third resistance is connected to the input end of the first amplitude control unit, the other end is connected to the source of the first transistor and the second transistor, the drain of the first transistor and the second transistor is connected to the output end of the first amplitude control unit, and the gate of the first transistor and the second transistor is connected to the digital control signal through the second resistance and the fourth resistance respectively.

[0015] As a preferred, the element values of different array units of the first amplitude control module are not necessarily the same.

[0016] The digital control signal changes the attenuation degree of the two power by controlling the number of on units in the first and second amplitude control modules respectively, and adjusts the output power of the two output ends of the adjustable power distribution module. In theory, more array units can achieve more fine adjustment.

[0017] As a preferred, the first adjustable power-current conversion module includes a first NMOS tube, a second NMOS tube, a first PMOS tube, a fifth resistance, a sixth resistance, a first capacitor and a second capacitor, and the first PMOS tube is used as a current mirror; one end of the first capacitor and the second capacitor is connected to the input end of the first adjustable power-current conversion module, the other end is connected to the gate of the first NMOS tube and the second NMOS tube, the source of the first NMOS tube and the second NMOS tube is connected to the ground, the drain of the first NMOS tube and the second NMOS tube is connected to the drain of the first PMOS tube, the source of the first PMOS tube is connected to the power supply, the drain and the gate of the first PMOS tube are connected to the output end of the first adjustable power-current conversion module, and the gate of the first NMOS tube and the second NMOS tube is connected to the bias voltage V b1 .

[0018] As preferred, the first capacitor and the second capacitor are the same, the first NMOS tube and the second NMOS tube are the same, the fifth resistor and the sixth resistor are the same, and the bias voltage V b1 is an adjustable voltage.

[0019] As preferred, the second adjustable power-current conversion module comprises a second PMOS tube, a third PMOS tube, a third NMOS tube, a seventh resistor, an eighth resistor, a third capacitor and a fourth capacitor, the third NMOS tube being a current mirror; one end of the third capacitor and the fourth capacitor is connected to the input end of the second adjustable power-current conversion module, the other end is connected to the gate of the third PMOS tube and the gate of the second PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are connected to the power supply, the drain of the second PMOS tube and the drain of the third PMOS tube are connected to the drain of the third NMOS tube, the source of the third NMOS tube is connected to the ground, the drain and the gate of the third NMOS tube are connected to the output end of the second adjustable power-current conversion module, and the gate of the second PMOS tube and the gate of the third PMOS tube are connected to the bias voltage V b2 through the eighth resistor and the seventh resistor respectively.

[0020] As preferred, the third capacitor and the fourth capacitor are the same, the second PMOS tube and the third PMOS tube are the same, the seventh resistor and the eighth resistor are the same, and the bias voltage V b2 is an adjustable voltage.

[0021] The adjustable power-current conversion module converts the differential mode radio frequency power into common mode direct current, and copies the current to the rear stage circuit through the current mirror; when the input power is very small, the static direct current of the adjustable power-current conversion module is used as the current mirror of the bias current of the rear stage circuit; when the input power increases, the current of the current mirror increases. Since the NMOS tube and the PMOS tube are used as the power detection device respectively, the output direct current of the first power-current conversion module and the second power-current conversion module has different characteristics with the change of the input power, and the difference can be used to realize the current which is controllable in the direction and amplitude of the input power.

[0022] As preferred, the current subtraction circuit module comprises a fourth PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a fifth capacitor, the gate of the fourth PMOS tube is connected to the first input end of the current subtraction circuit module, the source is connected to the power supply, and the drain is connected to the drain of the fifth NMOS tube; the gate of the fourth NMOS tube is connected to the second input end of the current subtraction circuit module, the source is connected to the ground, and the drain is connected to the drain of the fifth NMOS tube; the source of the fifth NMOS tube is connected to the ground, the drain and the gate are connected, and after being connected through the parallel fifth capacitor, the drain and the gate are used as the output end of the adjustable adaptive bias structure.

[0023] The fifth NMOS tube takes out the current difference of the fourth PMOS tube and the fourth NMOS tube, and converts into the bias voltage of the amplifier.

[0024] As preferred, the fifth capacitor can be realized by the parasitic capacitor of the layout, and high-frequency signals superimposed in the bias voltage are filtered out.

[0025] As preferred, the structure can be applied to CMOS process, BiCMOS process, SOI process or III-IV compound semiconductor process.

[0026] Advantages:

[0027] 1. The application realizes flexible adaptive bias adjustment by using the difference of the radio frequency power-direct current conversion characteristics of different devices, the output bias voltage can be set to incremental, decremental, first increasing and then decreasing mode with the power increasing, and the static working point, voltage variation amplitude and variation starting power point of the output voltage can be adjusted, the linearization of the radio frequency amplifier and system with different power characteristics can be realized, and the application range of the adaptive bias technology is expanded.

[0028] 2. In the application, the input power and bias point of the active device can be adjusted, and the adaptability to the deviation of process, voltage, temperature and the like is improved.

[0029] 3. The application adopts small-size transistors, the power consumption is very small, the input and output impedance is high, and the radio frequency signal channel is almost not affected. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 It is a schematic diagram of the total structure of the application;

[0031] Figure 2 It is a circuit structure diagram example of the application;

[0032] Figure 3 It is Figure 2 a circuit structure diagram example of the amplitude control module;

[0033] Figure 4 It is Figure 2 a schematic diagram of the output current of the adjustable power-current conversion module;

[0034] Figure 5 It is a schematic diagram of different adaptive modes of the application;

[0035] Figure 6 It is a schematic diagram of the improvement result of one amplitude nonlinearity of the application. DETAILED DESCRIPTION

[0036] For further illustrating the technical solutions disclosed by the present application, the following will be described in detail in combination with the drawings and specific embodiments. Those skilled in the art should know that the preferred and improved solutions made without departing from the spirit of the present application fall within the protection scope of the present application, and the common techniques in the art are not described and explained in detail in the specific embodiments.

[0037] As shown in Figure 1 , the present application provides an adjustable adaptive bias structure 100, which comprises an adjustable power distribution module 110 mainly composed of an adjustable attenuation unit, a first adjustable power-current conversion module 120 mainly composed of a capacitor, a differential pair of transistors and a current mirror, a second adjustable power-current conversion module 130, and a current subtraction circuit module 140 mainly composed of transistors. The adjustable adaptive bias structure 100 converts a small part of power or detected voltage coupled from the radio frequency signal path, and outputs a power adaptive voltage as a bias voltage of an amplifier or other active device in the radio frequency path. Figure 1 The adjustable adaptive bias structure 100 detects the input power of the amplifier, and other nodes of the radio frequency signal path can also be detected according to the actual situation of the circuit and layout, and the position of the detection node does not affect the effectiveness of the present application.

[0038] The coupling of the radio frequency signal can be achieved in various ways, for example, a transformer or a coupler can be used to couple out a signal for power distribution, as shown in Figure 1 and Figure 2 , a transformer with two secondary coils can also be used to directly couple out two signals, or it can be directly connected in parallel to the radio frequency signal path to detect the voltage. The first method is used in this example, and modifications can be made according to the actual situation of the circuit and layout, which will not be described here.

[0039] As shown in Figure 2 , the adjustable power distribution module 110 in the present application is composed of a first amplitude control module 111 and a second amplitude control module 112, and the two amplitude control modules are the same structure. The two sets of amplitude control signals of the first amplitude control module 111 and the second amplitude control module 112 are connected in parallel to the input end, the amplitude control signals are digital control signals, and the input end inputs analog control signals; wherein, the two sets of amplitude control signals are respectively connected with the first amplitude control module 111 and the second amplitude control module 112, as shown in the attached Figure 2 , the two sets of amplitude control signals are two sets of digital signals, which are amplitude control 1 and amplitude control 2, and each of amplitude control 1 and amplitude control 2 is an independent digital signal. V d0 - V dn), amplitude control 1 controls the first amplitude control module 111, and amplitude control 2 controls the second amplitude control module 112; the input end of the adjustable power distribution module 110 is connected to the input end V of the adjustable adaptive bias structure 100 IN +, V IN -; the output end of the first amplitude control module 111 is connected to the first output end V1+ and V1- of the adjustable power distribution module 110, and the output end of the second amplitude control module 112 is connected to the second output end V2+ and V2- of the adjustable power distribution module 110, that is, the input ends of the first amplitude control module 111 and the second amplitude control module 112 are connected in parallel to the input end V of the adjustable adaptive bias structure provided by the application IN +, V IN - of the application, receive the input power coupled from the radio frequency signal path, and output the power with two unequal amplitudes to the first output end V1+ and V1- and the second output end V2+ and V2- through the digital control signals for controlling the amplitudes of the two paths, respectively.

[0040] As shown in Figure 3 , both of the amplitude control modules in the application are switch resistance arrays, the signal path includes n+1 array units connected in parallel, n∈N (natural number set), each array unit is controlled by a corresponding digital signal V d0 - V dn , and each array unit has the same structure. The array unit is a series structure of CMOS transistor switches and resistors. Taking the first array unit as an example, the first array unit includes a first resistor 151, a first transistor 152, a second resistor 153, a third resistor 154, a second transistor 155, and a fourth resistor 156. The first transistor 152 and the second transistor 155 are switch tubes, the source of the first transistor 152 and the source of the second transistor 155 are connected in series with the first resistor 151 and the third resistor 154 to connect the input end of the amplitude control unit 111, the drain of the first transistor 152 and the drain of the second transistor 155 are connected to the output end of the amplitude control unit 111, and the gate of the first transistor 152 and the gate of the second transistor 155 are connected through the second resistor 153 and the fourth resistor 156, respectively, and are controlled by the first digital control signal V d0 . When the array unit is turned on, the resistor and the on switch tube are connected in parallel into the signal path, the path impedance decreases, and the attenuation of the output power decreases; when the array unit is turned off, the path impedance increases, and the attenuation of the output power increases. The element values of the array units do not have to be the same, and can be selected according to actual needs. In some embodiments of the application, different element values of the array are used to achieve a larger adjustment range with fewer control bits, for example: set n=5, V d0 to Vd5 Connect 5-bit register REG, REG = 11111 for full on, REG = 00000 for full off. When the element value of each array unit is the same, set the on series impedance as Z, and the off impedance as infinite. When REG = 00001, the array impedance is Z; when REG = 11111, the array impedance is Z / 5. With the increase of the number of on array, the impedance decreases, the attenuation decreases, and the impedance changes in the range [Z / 5, +∞]. When the element value of each array unit is set to be different, assuming V d0 to V d4 The controlled array impedance is Z, Z / 2, Z / 4, Z / 8, Z / 16 respectively, and the impedance change range corresponding to REG = 11111 to REG = 00000 is [Z / 31, +∞], which is larger than the case of the same array unit. In this embodiment, the maximum attenuation is about 25dB.

[0041] Two sets of amplitude control signals (amplitude control 1 and amplitude control 2) change the attenuation degree of the two power by controlling the number of on array units in the first and second amplitude control modules respectively, adjust the output power of the two output ends of the adjustable power distribution module, and the two outputs do not have to be proportional, and the value does not need to have a specific rule. In principle, as long as the difference between the two output powers can be realized, the difference between the first output and the second output needs to be realized by digital control in use. The element value design must be matched with its load, that is, the size of the power-current conversion module. The value rule in the design is generally that the impedance of the n+1th array unit is twice that of the nth array unit. In theory, more array units can achieve more precise adjustment.

[0042] As Figure 2 shown, the first adjustable power-current conversion module 120 in the application mainly consists of a capacitor, a transistor differential pair and a current mirror, including a first NMOS tube 121, a second NMOS tube 122, a first PMOS tube 123, a fifth resistor 124, a sixth resistor 125, a first capacitor 126 and a second capacitor 127. The first NMOS tube 121 and the second NMOS tube 122 are a common source configuration transistor differential pair, the gate of the first NMOS tube 121 and the gate of the second NMOS tube 122 are connected to the bias voltage V b1, the gate of the first NMOS transistor 121 and the gate of the second NMOS transistor 122 are connected to the first output end V1+, V1- of the first amplitude control module 111 output through the first capacitor 126 and the second capacitor 127 respectively, as the differential input end V1+, V1- of the first adjustable power-current conversion module 120, the source of the first NMOS transistor 121 and the source of the second NMOS transistor 122 are grounded, and the drain of the first NMOS transistor 121 and the drain of the second NMOS transistor 122 are connected to the drain of the first PMOS transistor 123. The pair of NMOS differential pairs of the first NMOS transistor 121 and the second NMOS transistor 122 are power detection devices, and the direct current component of the common mode output end output current increases with the amplitude of the differential input end radio frequency signal, and within a certain input amplitude range, the output current is approximately proportional to the square of the input radio frequency signal amplitude, and the current is saturated when the amplitude is small or large, as shown in Figure 4 The first PMOS transistor 123 is a current mirror, and the source is connected to the power supply, and the drain and the gate are connected. The output current of the NMOS differential pair is converted into a voltage through the first PMOS transistor 123 and connected to the output end V p . Adjusting the bias voltage V b1 of the differential pair will change the power-current conversion characteristics of the NMOS differential pair and the intermediate node voltage of the NMOS transistor-PMOS transistor, and directly reflected in the output end V p .

[0043] As shown in Figure 2 , the second adjustable power-current conversion module 130 in the application mainly consists of capacitors, transistor differential pairs and current mirrors, including the second PMOS transistor 131, the third PMOS transistor 132, the third NMOS transistor 133, the seventh resistance 134, the eighth resistance 135, the third capacitor 136 and the fourth capacitor 137. The second PMOS transistor 131 and the third PMOS transistor 132 are a differential pair in common source configuration, the gate of the second PMOS transistor 131 and the gate of the third PMOS transistor 132 are connected to the bias voltage V b2 through the eighth resistance 135 and the seventh resistance 134 respectively, the gate of the third PMOS transistor 132 and the gate of the second PMOS transistor 131 are connected to the differential input end V2+, V2- through the third capacitor 136 and the fourth capacitor 137 respectively, the source of the second PMOS transistor 131 and the source of the third PMOS transistor 132 are connected to the power supply, and the drain of the second PMOS transistor 131 and the drain of the third PMOS transistor 132 are connected to the drain of the third NMOS transistor 133. The pair of PMOS differential pairs of the second PMOS transistor 131 and the third PMOS transistor 132 are power detection devices, and the direct current component of the common mode output end output current increases with the amplitude of the differential input end radio frequency signal, and within a certain input amplitude range, the output current is approximately proportional to the square of the input radio frequency signal amplitude, and the current is saturated when the amplitude is small or large, as shown inFigure 4 The third NMOS transistor 133 is a current mirror, whose source is connected to ground, and whose drain and gate are connected together. The output current of the PMOS differential pair is converted to voltage by the third NMOS transistor 133 and connected to the output terminal V n . The bias voltage V b2 of the differential pair is adjusted. The power-current conversion characteristic of the PMOS differential pair and the intermediate node voltage of the NMOS transistor-PMOS transistor will be changed, and directly reflected in the output terminal V n .

[0044] Figure 4 The output current of the first and second adjustable power-current conversion modules in this example is given as a function of power, and the difference between the two. Figure 4 The first current in the figure corresponds to the bias current of the first adjustable power-current conversion module 120, and the second current corresponds to the bias current of the second adjustable power-current conversion module 130. The bias current of the first adjustable power-current conversion module 120 is higher, and the slope in the current-power linear variation interval is smaller. The bias current of the second adjustable power-current conversion module 130 is lower, and the slope in the current-power linear variation interval is larger. The bias currents of the two are adjusted by the bias voltage V b1 , V b2 . The higher the bias voltage, the higher the bias current. The starting power point at which the current enters the linear variation interval is adjusted by the digital control signal of the adjustable power distribution module 110.

[0045] It should be noted that the adjustable power-current conversion module converts the differential mode radio frequency power into common mode direct current, and copies the current to the rear stage circuit through the current mirror. When the input power is very small, the static direct current is used as the current mirror of the bias current of the rear stage circuit. When the input power increases, the current of the current mirror increases. This example uses two kinds of power-current conversion modules based on NMOS and PMOS, i.e. using NMOS and PMOS as power detection devices, using the different I-V characteristics and impedance characteristics of NMOS and PMOS to generate detection currents with different slopes and detection ranges. That is, the output direct current of the first and second power-current conversion modules has different variation characteristics with input power, and the difference can be used to realize a current that is controllable in both direction and amplitude with input power. It should be pointed out that in principle, the two power-current conversion modules can also use the same structure, and different transistor biases and sizes are designed to achieve specific detection current differences.

[0046] As Figure 2As shown, the current subtraction circuit module 140 in the application is mainly composed of transistors, including a fourth PMOS transistor 141, a fourth NMOS transistor 142, a fifth NMOS transistor 143 and a fifth capacitor 144, the gate of the fourth PMOS transistor 141 is the first input end of the current subtraction circuit module 140, connected with the output end V p of the first adjustable power-current conversion module 120, the source of the fourth PMOS transistor 141 is connected with a power supply, and the drain of the fourth PMOS transistor 141 is connected with the drain of the fifth NMOS transistor 143; the gate of the fourth NMOS transistor 142 is the second input end of the current subtraction circuit module 140, connected with the output end V n of the second adjustable power-current conversion module 130, the source of the fourth NMOS transistor 142 is connected with the ground, and the drain of the fourth NMOS transistor 142 is connected with the drain of the fifth NMOS transistor 143; the fifth NMOS transistor 143 is a current mirror, the source of which is connected with the ground, the drain and the gate of which are connected, and the drain is connected to the output end V OUT , that is, the output power adaptive voltage. The drain of the fourth PMOS transistor 141 outputs a mirror current of the first power-current conversion module 120, and the drain of the fourth NMOS transistor 142 outputs a mirror current of the second power-current conversion module 130, and the current difference of the two flows into the drain of the fifth NMOS transistor 143, which is converted into a gate voltage, and after filtering out high-frequency signals through the fifth capacitor 144, the gate voltage is used as the bias of the device to be optimized. The fifth capacitor 144 is also used as a filter capacitor, and the parasitic of the layout can also be used to filter out high-frequency signals superimposed in the bias voltage.

[0047] Figure 5 The output voltage of the adjustable adaptive bias structure example in the application changes with the power. Through the digital signal control of the adjustable power distribution module 110, the two amplitude control modules (111, 112) are respectively controlled by different digital signals, and the greater the attenuation, the smaller the power distributed to the power-current conversion module behind. The example can be set to three modes to adapt to amplifiers or systems with different power characteristics:

[0048] Mode one: all control positions of the second amplitude control module are 0 (for example, 5-bit control, that is, REG2=00000), that is, the array is completely disconnected, the signal attenuation amplitude of this path is the largest, and the power distributed to the second adjustable power-current conversion module 130 is attenuated the most, that is, mode one is realized. The output of this mode is similar to the traditional adaptive bias structure, and the output voltage rises after the input power exceeds a certain value, which is suitable for the increase of the compression point of a class amplifier and the amplitude linearization under high power;

[0049] Mode 2: Mode 2 is an intermediate state between Mode 1 and Mode 3. Both amplitude control modules have intermediate control bits (e.g., 5-bit control, REG1 and REG2 can both be 10000). Power allocation ensures that the starting point of the current linear interval of the first adjustable power-current conversion module 120 precedes the starting point of the current linear interval of the second adjustable power-current conversion module 130, such as... Figure 4 As shown, this implements mode two, where the output voltage first rises and then falls with power, suitable for linearization of multi-stage amplifier cascade systems with low bias or broadband transceiver circuits with several octaves of bandwidth.

[0050] Mode 3: All control positions of the first amplitude control module are set to 0 (e.g., 5-bit control, i.e., REG1=00000), meaning the entire array is disconnected. This channel experiences the maximum signal attenuation, maximizing the attenuation of the power allocated to the first adjustable power-to-current conversion module 120, thus achieving Mode 3. The output voltage decreases after the input power exceeds a certain value, suitable for amplitude linearization of Class B amplifiers. In all three modes, the output voltage's quiescent operating point, power change threshold, amplitude of change, and power range can be adjusted via the digital control signal of the adjustable power distribution module 110 and the bias control signals of the first and second adjustable power-to-current conversion modules 120 and 130.

[0051] Figure 6 A diagram illustrating the beneficial effects of this example in Mode 2 is provided. For example... Figure 6 As shown, the system to be optimized is a multi-stage cascaded broadband system. Under a fixed bias, due to the nonlinearity caused by the low bias and second harmonic, its gain first decreases and then increases with power. When the input power increases to -7.5dBm, the gain has decreased by nearly 1dB, resulting in poor linearity. The adjustable adaptive bias structure of this invention is used, set to mode two, and the bias variation range is adjusted so that the original gain decrease segment coincides with the bias increase segment, and vice versa. The gain variation of the system to be optimized is effectively compensated, the input 1dB compression point is increased to 2.5dBm, and the amplitude change before the compression point is less than 0.3dB, significantly improving linearity.

[0052] It should be noted that the circuit structure in this invention can be applied to CMOS technology, BiCMOS technology, SOI technology, or III-IV group compound semiconductor technology, etc.

[0053] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An adjustable adaptive bias structure, characterized in that: It includes an adjustable power distribution module (110), a first adjustable power-to-current conversion module (120), a second adjustable power-to-current conversion module (130), and a current subtraction circuit module (140), wherein, The adjustable power distribution module (110) is connected to the input signal of the adjustable adaptive bias structure (100) and is used to distribute the power of the input signal of the adjustable adaptive bias structure. It has two output terminals. The input terminal of the first adjustable power-to-current conversion module (120) is connected to one output terminal of the adjustable power distribution module (110) to convert the detected power signal into a DC current signal and then convert it into a voltage signal through a current mirror and set it as the output terminal. The input terminal of the second adjustable power-to-current conversion module (130) is connected to another output terminal of the adjustable power distribution module (110) to convert the detected power signal into a DC current signal and then into a voltage signal through a current mirror and set it as the output terminal. The two input terminals of the current subtraction circuit module (140) are respectively connected to the output terminals of the first adjustable power-current conversion module (120) and the second adjustable power-current conversion module (130) to extract the difference between DC current signal one and DC current signal two, and convert it into a voltage signal, which is output as the output signal of the adjustable adaptive bias structure (100), namely the power adaptive voltage.

2. The adjustable adaptive bias structure according to claim 1, characterized in that: The adjustable power distribution module (110) includes adjustable attenuation units with identical structures, namely a first amplitude control module (111) and a second amplitude control module (112). The two sets of amplitude control signals of the first amplitude control module (111) and the second amplitude control module (112) are connected in parallel with their input terminals. The two sets of amplitude control signals are respectively connected to the first amplitude control module (111) and the second amplitude control module (112). The input terminal of the adjustable power distribution module (110) is connected to the input terminal (V) of the adjustable adaptive bias structure (100). IN +、V IN -); The output of the first amplitude control module (111) is connected to the first output (V1+, V1-) of the adjustable power distribution module (110), and the output of the second amplitude control module (112) is connected to the second output (V2+, V2-) of the adjustable power distribution module (110).

3. The adjustable adaptive bias structure according to claim 2, characterized in that: The first amplitude control module (111) is a switched resistor array, including n+1 parallel array units and digital control signals corresponding to each array unit. The digital control signal is used to control the array unit to be in an on or off state; the nth array unit is connected to the corresponding digital control signal. , where n∈N.

4. The adjustable adaptive bias structure according to claim 3, characterized in that: The array unit structure of the first amplitude control module (111) is the same, which is a series structure of CMOS transistor switches and resistors. The first array unit includes a first resistor (151), a first transistor (152), a second resistor (153), a third resistor (154), a second transistor (155), and a fourth resistor (156). One end of the first resistor (151) and the third resistor (154) are connected to the input terminal of the first amplitude control module (111), and the other end is connected to the source of the first transistor (152) and the second transistor (155), respectively. The drain of the first transistor (152) and the second transistor (155) are connected to the output terminal of the first amplitude control module (111). The gate of the first transistor (152) and the second transistor (155) are connected to the first digital control signal through the second resistor (153) and the fourth resistor (156), respectively. .

5. The adjustable adaptive bias structure according to claim 3, characterized in that: The values ​​of different array unit elements in the first amplitude control module (111) do not need to be the same; they can be selected according to actual needs.

6. The adjustable adaptive bias structure according to claim 1, characterized in that: The first adjustable power-to-current conversion module (120) includes a first NMOS transistor (121), a second NMOS transistor (122), a first PMOS transistor (123), a fifth resistor (124), a sixth resistor (125), a first capacitor (126), and a second capacitor (127). The first PMOS transistor (123) serves as a current mirror. One end of the first capacitor (126) and the second capacitor (127) are connected to one input terminal (V1+, V1-) of the first adjustable power-to-current conversion module (120), and the other end is respectively connected to... The gates of the first NMOS transistor (121) and the second NMOS transistor (122), and the sources of the first NMOS transistor (121) and the second NMOS transistor (122) are grounded together. The drains of the first NMOS transistor (121) and the second NMOS transistor (122) are connected to the drain of the first PMOS transistor (123). The source of the first PMOS transistor (123) is connected to the power supply. The drain and gate of the first PMOS transistor (123) are connected and connected to the output terminal (V) of the first adjustable power-to-current conversion module (120). p The gates of the first NMOS transistor (121) and the second NMOS transistor (122) are connected to the bias voltage V through the fifth resistor (124) and the sixth resistor (125), respectively. b1 .

7. The adjustable adaptive bias structure according to claim 6, characterized in that: The first capacitor (126) and the second capacitor (127) are the same, the first NMOS transistor (121) and the second NMOS transistor (122) are the same, the fifth resistor (124) and the sixth resistor (125) are the same, and the bias voltage V b1 It is an adjustable voltage.

8. The adjustable adaptive bias structure according to claim 1, characterized in that: The second adjustable power-to-current conversion module (130) includes a second PMOS transistor (131), a third PMOS transistor (132), a third NMOS transistor (133), a seventh resistor (134), an eighth resistor (135), a third capacitor (136), and a fourth capacitor (137). The third NMOS transistor (133) serves as a current mirror. One end of the third capacitor (136) and the fourth capacitor (137) is connected to the other input terminal (V2+, V2-) of the second adjustable power-to-current conversion module (130), and the other end is connected to the third PMOS transistor (131), the fourth NMOS transistor (132), the fifth NMOS transistor (133), the sixth NMOS transistor (134), the seventh resistor (135), the eighth resistor (136), the eighth resistor (137), the third capacitor (136), and the fourth capacitor (137). The gates of the three PMOS transistors (132) and the second PMOS transistor (131) are connected together. The sources of the second PMOS transistor (131) and the third PMOS transistor (132) are connected to the same power supply. The drains of the second PMOS transistor (131) and the third PMOS transistor (132) are connected to the drain of the third NMOS transistor (133). The source of the third NMOS transistor (133) is grounded. The drain and gate of the third NMOS transistor (133) are connected and connected to the output terminal (V) of the second adjustable power-to-current conversion module (130). n The gates of the second PMOS transistor (131) and the third PMOS transistor (132) are respectively connected to the bias voltage V through the eighth resistor (135) and the seventh resistor (134). b2 .

9. An adjustable adaptive bias structure according to claim 8, characterized in that: The third capacitor (136) and the fourth capacitor (137) are the same, the second PMOS transistor (131) and the third PMOS transistor (132) are the same, the seventh resistor (134) and the eighth resistor (135) are the same, and the bias voltage V b2 It is an adjustable voltage.

10. An adjustable adaptive bias structure according to claim 1, characterized in that: The current subtraction circuit module (140) includes a fourth PMOS transistor (141), a fourth NMOS transistor (142), a fifth NMOS transistor (143), and a fifth capacitor (144). The gate of the fourth PMOS transistor (141) is connected to the first input terminal (V) of the current subtraction circuit module (140). p The source of the fourth PMOS transistor (141) is connected to the power supply, and the drain of the fourth PMOS transistor (141) is connected to the drain of the fifth NMOS transistor (143); the gate of the fourth NMOS transistor (142) is connected to the second input terminal (V) of the current subtraction circuit module (140). n The source of the fourth NMOS transistor (142) is grounded, and the drain of the fourth NMOS transistor (142) is connected to the drain of the fifth NMOS transistor (143); the source of the fifth NMOS transistor (143) is grounded, and the drain and gate of the fifth NMOS transistor (143) are connected together, and the output terminal (V) of the adjustable adaptive bias structure (100) is connected through a fifth capacitor (144) in parallel. OUT ).

11. An adjustable adaptive bias structure according to claim 10, characterized in that: The fifth capacitor (144) can be implemented by the parasitic capacitance of the layout.

12. The adjustable adaptive bias structure according to claim 1, characterized in that: The structure can be applied to CMOS, BiCMOS, SOI, or III-IV group compound semiconductor processes.

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