A MAC data processing method and device, and a storage medium

Abstract

The application discloses a MAC data processing method and device, and a storage medium. The method comprises the following steps: preprocessing a to-be-processed packet in a first clock cycle, and obtaining at least two multi-byte data based on the preprocessed to-be-processed packet; the to-be-processed packet is data in a first format; the at least two multi-byte data are respectively stored in corresponding buffers, and the relevant information of each multi-byte data is pressed into a FIFO corresponding to each buffer; the relevant information of each byte data is used for obtaining a target packet from the corresponding buffer and FIFO; and the at least two multi-byte data are converted into data in a second format according to the at least two multi-byte data and the relevant information of each multi-byte data.

Description

TECHNICAL FIELD

[0001] The present application relates to network technology, and in particular, to a MAC data processing method and device, and a storage medium. BACKGROUND

[0002] Ethernet has been widely used and rapidly developed for a long time. Its transmission rate has been from 10M, 100M, 1000Mbps to 10Gbps (Giga Bit Per-Second, 109bits per second), 40Gbps and 100Gbps, and even to 25Gbps, 50Gbps, 200Gbps and 400Gbps at present. At present, the Ethernet Technology Consortium (ETC) supported by the industry has announced the completion of the 800Gb Ethernet technology specification. The new specification is based on many technologies used in the current high-end 400Gb Ethernet protocol, and the new specification is officially called 800GBASE-R. The Ethernet Technology Consortium that designed it also played an important role in developing 25Gb, 50Gb and 100Gb Ethernet protocols.

[0003] The 800Gb Ethernet technology specification adds new media access controllers (MACs) and physical coding sublayers (PCSs). The new specification adjusts these functions to distribute data using 8 106.25Gbps physical links. The channels can be copper twisted pairs or optical cables, a bundle of optical fibers or optical waves. The 800GBASE-R specification is built on two 400Gb PCSs to create a single MAC running at a total rate of 800Gbps. The new standard provides half the latency of the 400G Ethernet specification, but the new specification also reduces the network forward error correction overhead running at 50Gbps, 100Gbps and 200Gbps by half. By reducing latency, 800Gb Ethernet meets the speed requirements of latency-sensitive applications such as high-performance computing and artificial intelligence. These applications need to move large amounts of data as quickly as possible.

[0004] The frame structure of an Ethernet MAC layer message is shown in Figure 4 When a MAC receives a message, it will check the CRC of the message. According to the result of the CRC check, the MAC marks whether the message has an error in the transmission process. After completing the CRC check, the CRC field has no effect on the internal function processing of the chip, so usually after the MAC completes the CRC check, the CRC field is stripped off.

[0005] The following is an example of a packet length of 129 bytes, since the system side uses a data bit width of 128 bytes, 129 bytes need to be transmitted in 2 clock cycles, the first clock cycle transmits 128 bytes, including 3 bytes of CRC, and the second clock cycle transmits 1 byte of CRC, as shown in Figure 5 The existing method is to latch the 128-byte data transmitted in the first clock cycle, and process it only when the 1-byte data in the second clock cycle arrives. The reason is that the 128-byte data transmitted in the first clock cycle does not have the End of Packet (EOP) flag, so it is not known whether the 128-byte data in the current clock cycle contains the CRC field. The data in the second clock cycle has the EOP flag, and only when the data in the second clock cycle arrives, it is known that the data packet in the first clock cycle contains a 3-byte CRC field, and the CRC stripping operation can be performed.

[0006] This method needs to latch the data in the first clock cycle completely, and for lower rate MACs using smaller data bit width, latching data will not consume too many flip-flops. However, for 800G, latching data at 128-byte bit width will consume more resources, increasing the chip area. At the same time, since the data in the first clock cycle cannot be processed in the current clock cycle, it has to wait for the data in the next clock cycle to arrive, which increases the data delay of the chip. SUMMARY

[0007] To solve the existing technical problems, the embodiments of the present application provide a MAC data processing method and device, and a storage medium.

[0008] The technical solution of the present application is as follows:

[0009] The embodiments of the present application provide a MAC data processing method, which comprises:

[0010] Preprocessing the to-be-processed packet in the first clock cycle, and obtaining at least two multi-byte data based on the preprocessed to-be-processed packet; the to-be-processed packet is data in a first format;

[0011] Storing the at least two multi-byte data in corresponding buffers respectively, and pushing the relevant information of each multi-byte data into a first-in-first-out queue (FIFO) corresponding to each buffer; the relevant information of each byte data is used to obtain a target packet from the corresponding buffer and FIFO;

[0012] According to the at least two multi-byte data and the related information of each multi-byte data, the at least two multi-byte data are converted into data in a second format.

[0013] In the scheme, the MAC has an analysis module, and the pre-processing of the to-be-processed packet in the first clock cycle comprises:

[0014] The analysis module analyzes 128-byte data of the to-be-processed packet in units of 8-byte data to determine whether the corresponding 8-byte data contains a preamble and the correctness of the preamble.

[0015] The control character S is determined as a packet start flag SOP, and the control character T is determined as a packet end flag EOP.

[0016] The number of valid bytes in the 8-byte data and the packet content are determined.

[0017] In the scheme, the number of multi-byte data is four.

[0018] The at least two multi-byte data are obtained based on the pre-processed to-be-processed packet, and the obtaining comprises:

[0019] The analysis module generates four 32-byte data based on each 8-byte data after pre-processing and corresponding information, and determines the related information corresponding to each 32-byte data; the related information comprises: whether corresponding to SOP, whether corresponding to EOP, and the number of valid bytes.

[0020] Correspondingly, the storing of the at least two multi-byte data into corresponding buffers and the pushing of the related information of each multi-byte data into a first-in-first-out queue FIFO corresponding to each buffer comprise:

[0021] Each 32-byte data is stored into a corresponding buffer.

[0022] The related information of each 32-byte data is pushed into a FIFO corresponding to the corresponding buffer.

[0023] In the scheme, the MAC has a buffer control module; the buffer control module is related to the number of buffers; and the number of buffers is related to the number of multi-byte data.

[0024] The target packet is obtained from the corresponding buffer and FIFO based on the related information of each byte data, and the obtaining comprises:

[0025] The buffer control module determines whether the corresponding FIFO contains SOP and / or EOP based on the related information in the corresponding FIFO, to determine whether the corresponding buffer contains a complete packet in the corresponding clock cycle.

[0026] The buffer control module reads only the determined complete message as a target message based on the determined SOP and EOP.

[0027] In the above scheme, the conversion of the at least two multi-byte data into the second format data according to the at least two multi-byte data and the relevant information of each multi-byte data comprises:

[0028] The second format data is generated according to high 8 byte data of a first clock cycle and first 120 byte data of a second clock cycle.

[0029] The second clock cycle is a next clock cycle of the first clock cycle.

[0030] The high 8 byte data is used to represent whether the next clock cycle has an EOP and the number of valid bytes when the EOP exists.

[0031] The MAC data processing device provided by the embodiment of the application comprises an analysis module, a conversion module, at least two buffers and a FIFO corresponding to each buffer.

[0032] The analysis module is used to pre-process a to-be-processed message in a first clock cycle and obtain at least two multi-byte data based on the pre-processed to-be-processed message.

[0033] The at least two multi-byte data are stored in corresponding buffers respectively, and relevant information of each multi-byte data is pushed into a first-in-first-out queue FIFO corresponding to each buffer.

[0034] The conversion module is used to convert the at least two multi-byte data into second format data according to the at least two multi-byte data and the relevant information of each multi-byte data.

[0035] In the above scheme, the analysis module is used to analyze 128 byte data of the to-be-processed message in units of 8 byte data to determine whether the corresponding 8 byte data contains a preamble and the correctness of the preamble.

[0036] A control character S is determined as a message start flag SOP, and a control character T is determined as a message end flag EOP.

[0037] The number of valid bytes in the 8 byte data and the message content are determined.

[0038] The conversion module is configured to generate data in a second format according to the high 8-byte data of the first clock cycle and the first 120-byte data of the second clock cycle.

[0039] The second clock cycle is a next clock cycle of the first clock cycle.

[0040] The high 8-byte data is used to represent whether the next clock cycle has an EOP and the number of valid bytes when the EOP exists.

[0041] The embodiment of the present application further provides an electronic device, comprising a processor and a memory for storing a computer program capable of running on the processor,

[0042] The processor is configured to execute the steps of the above method when running the computer program.

[0043] The embodiment of the present application further provides a storage medium having a computer program stored thereon, and the computer program is executed by a processor to implement the steps of the above method.

[0044] The MAC data processing method, device and storage medium provided by the embodiment of the present application, the method comprises: preprocessing a to-be-processed packet in a first clock cycle, and obtaining at least two multi-byte data based on the preprocessed to-be-processed packet; the to-be-processed packet is data in a first format; the at least two multi-byte data are respectively stored in corresponding buffers, and the relevant information of each multi-byte data is pushed into the FIFO corresponding to each buffer; the relevant information of each byte data is used to obtain a target packet from the corresponding buffer and FIFO; and the at least two multi-byte data are converted into data in a second format according to the at least two multi-byte data and the relevant information of each multi-byte data. In this way, when data is read from the buffer, the data can be read in units of 32 bytes, and it is not necessary to read 128 bytes of data each time, so that the data latching can be effectively reduced, the use of flip-flops can be greatly reduced, and the area of a chip can be saved. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 An overall implementation architecture schematic diagram of an 800G Ethernet medium access controller (MAC) is provided for the embodiment of the present application.

[0046] Figure 2 A schematic diagram of 128-byte containing two data packets is provided for the embodiment of the present application.

[0047] Figure 3 A schematic diagram of the maximum case of latched data is provided for the embodiment of the present application.

[0048] Figure 4A schematic diagram of an Ethernet MAC layer frame structure provided for an embodiment of the present application is shown in Figure 1.

[0049] Figure 5 A schematic diagram of a 129-byte message transmission timing on the system side provided for an embodiment of the present application is shown in Figure 2.

[0050] Figure 6 A schematic diagram of left shifting 8 bytes of current clock cycle data provided for an embodiment of the present application is shown in Figure 3.

[0051] Figure 7 A flowchart of a MAC data processing method provided for an embodiment of the present application is shown in Figure 4.

[0052] Figure 8 A structural schematic diagram of a MAC data processing device provided for an embodiment of the present application is shown in Figure 5. DETAILED DESCRIPTION

[0053] The present application will be further described in detail below with reference to embodiments.

[0054] An architecture for implementing 800G Ethernet MAC in the case of 800GMII interface data bit width of 128 bytes is provided in an embodiment of the present application. The architecture divides the 128-byte data of the 800GMII interface into 4 pieces of 32-byte data and stores them in 4 independent 32-byte buffers.

[0055] When reading data from the buffer, the data can be read in units of 32 bytes, without reading 128-byte data each time, which can effectively reduce data latching, greatly reduce the use of flip-flops, and save chip area. In addition, when converting 800GMII interface data into system-side message format, the data of the next clock cycle is identified as the EOP of the message in the current clock cycle, so that when performing message CRC stripping, the data of the current clock cycle does not need to be latched, and the message stripping CRC operation is performed only when the data of the next clock cycle arrives, which can eliminate the use of latching data flip-flops and reduce chip area. At the same time, since the current data does not need to be latched and the message stripping CRC operation is performed only when the next data arrives, the data delay can be effectively reduced.

[0056] The present application aims to provide an architecture for implementing 800G Ethernet MAC in the case of 800GMII interface data bit width of 128 bytes. It is implemented in two parts: dividing 128-byte data into 4 pieces of 32-byte data for independent storage, and using the current clock cycle to identify whether the data of the next clock cycle is the EOP of the message. It includes the following steps:

[0057] 1. Divide 128-byte data into 4 pieces of 32-byte data for independent storage.

[0058] As shown in Figure 1 , 128 bytes data of 800 GMII interface is sent to 16 800 GMII parsing modules respectively, and 8 bytes data is input to each 800 GMII parsing module. For example, bytes 0-7 are input to 800 GMII parsing module 0, bytes 8-15 are input to 800 GMII parsing module 1, and so on, and bytes 120-127 are input to 800 GMII parsing module 15. Each 800 GMII parsing module is responsible for checking whether the respective 8 bytes contains a preamble, checking the correctness of the preamble, parsing the control character / S / as the start of packet (SOP) of the packet, parsing / T / as the end of packet (EOP) of the packet, and obtaining the number of valid bytes in the 8 bytes data and the content of the 8 bytes data.

[0059] After the 800 GMII interface is parsed, 128 bytes data is divided into 4 32 bytes and written into 4 buffers respectively. Bytes 0-31 are written into buffer 0, bytes 32-63 are written into buffer 1, bytes 64-95 are written into buffer 2, and bytes 96-127 are written into buffer 3. At the same time, the SOP / EOP / valid byte number information corresponding to each 32 bytes and the address of the write buffer are compressed into the corresponding first in first out queue (FIFO).

[0060] When the FIFO is not empty, it is determined whether to pop out the FIFO and read the buffer according to the information that is about to be popped out of each FIFO. Since the length of the packet received from the chip port can be relatively short, more than one packet can be contained in 128 bytes, and the system side can only process one data packet in one clock cycle. If 128 bytes of data are read out in one clock cycle, and the 128 bytes of data contain more than one data packet, the remaining data packet data needs to be latched until the next clock cycle to be processed. This requires a large number of flip-flops to latch data, and up to 120 bytes of data need to be latched. In the present application, 4 32-byte buffers are used for on-demand reading, and not all 128 bytes are read at once, which can minimize the number of flip-flops to latch data, and at most only 16 bytes of data need to be latched.

[0061] As shown in Figure 2 , 128 bytes contain 2 data packets, data packet 0 is written into buffer 3 and buffer 2, and data packet 1 is written into buffer 1 and buffer 0, and this information is reflected by the data stored in the FIFO. Figure 1The buffer read control module 3 obtains the 32 bytes (SOP) of data packet 0 from FIFO3, pops the information from FIFO3, and reads the data from buffer 3. Similarly, the buffer read control module 2 obtains the 32 bytes (EOP) of data packet 0 from FIFO2, pops the information from FIFO2, and reads the data from buffer 2. Simultaneously, it instructs the buffer read control module 1 / 0 not to read data from buffer 1 / 0, as a complete data packet has already been read in this clock cycle, and there is no need to read data from subsequent buffers. Thus, no data needs to be latched in this clock cycle, eliminating the need for a latch trigger.

[0062] Based on the principle of buffer reading, it is not difficult to conclude that Figure 3 The data sequence shown represents the case requiring the most latched data, totaling 16 bytes. In this sequence, data packet 0 occupies buffers 3 / 2 / 1 and the high 8 bytes of buffer 0, while the low 16 bytes of buffer 0 contain the data of data packet 1.

[0063] Since the system uses a data bit width of 128 bytes, buffer 3, buffer 2, buffer 1 and buffer 0 will all be read out at once. However, buffer 0 also contains 16 bytes of data for the next data packet. These 16 bytes of data cannot be transmitted in the current clock cycle and need to be latched and transmitted in the next clock cycle.

[0064] 2. The current clock cycle indicates whether the data in the next clock cycle is the EOP of this message.

[0065] The frame structure of an Ethernet MAC layer message is as follows: Figure 4 As shown, each message contains a 4-byte CRC checksum field. When the MAC receives a message, it performs a CRC check on that message. Based on the CRC check result, the MAC marks whether the message contained an error during transmission. After the CRC check is completed, the CRC field has no actual function in the chip's internal processing; therefore, it is usually removed after the MAC completes the CRC check.

[0066] The following example illustrates a message length of 129 bytes. Since the system uses a data width of 128 bytes, the 129 bytes need to be transmitted over two clock cycles. The first clock cycle transmits 128 bytes, including a 3-byte CRC, and the second clock cycle transmits a 1-byte CRC. Figure 5 As shown.

[0067] The present application proposes a method for identifying whether the data of the next clock cycle is the EOP of the packet to solve the above two problems. The data of the next clock cycle is identified as the EOP in the current clock cycle, and the number of bytes of the valid data of the next clock cycle. The key of the present application is how to get whether the next clock cycle is the EOP and the number of bytes of the valid data of the next clock cycle in the current clock cycle.

[0068] To solve the above problems, in the embodiment of the present application, the original 800 GMII interface 128 byte data is left shifted by 8 bytes, the removed 8 bytes are latched, and the low 120 bytes of the data of the next clock cycle are spliced into 128 byte data, and the high 8 byte data is latched again, and the first 120 bytes of the data of the next clock cycle are spliced into 128 byte data, and so on, as shown in the figure. Figure 6 In this way, the 128 byte data of the current clock cycle and the high 8 byte data of the next clock cycle can be seen in each clock cycle, and according to the 128 byte data of the current clock cycle and the high 8 byte data of the next clock cycle, whether the current clock cycle and the next clock cycle have the EOP and the number of bytes of the valid data when the EOP is known, and then whether the current 128 byte data contains the CRC field can be determined.

[0069] Here, the high 8 bytes refer to the 8 bytes from the left to the right; and the low 120 bytes refer to the 120 bytes from the right to the left.

[0070] The embodiment of the present application provides a MAC data processing method, as shown in the figure. Figure 7 The method comprises the following steps.

[0071] Step 701, preprocessing the to-be-processed packet in the first clock cycle, and obtaining at least two multi-byte data based on the preprocessed to-be-processed packet; the to-be-processed packet is data in a first format;

[0072] Step 702, storing the at least two multi-byte data in the corresponding buffer respectively, and pressing the relevant information of each multi-byte data into the first-in-first-out queue (FIFO) corresponding to each buffer; the relevant information of each byte data is used to obtain the target packet from the corresponding buffer and FIFO;

[0073] Step 703, converting the at least two multi-byte data into data in a second format according to the at least two multi-byte data and the relevant information of each multi-byte data.

[0074] The data in the first format is the original to-be-processed packet format, such as the application 800G Ethernet (MAC) scene, and the packet with 128 byte data.

[0075] In an embodiment, the MAC has a parsing module;

[0076] In step 701, the pre-processing of the to-be-processed packet in the first clock cycle includes:

[0077] The parsing module parses the 128-byte data of the to-be-processed packet in units of 8-byte data to determine whether the corresponding 8-byte data contains a preamble and the correctness of the preamble;

[0078] determining a control character S as a packet start flag SOP and a control character T as a packet end flag EOP; and

[0079] determining the number of valid bytes in the 8-byte data and the packet content.

[0080] The parsing module can be in the 800 GMII interface, and the parsing module can include 16 800 GMII parsing modules, each of which inputs 8-byte data and processes the 8-byte data respectively.

[0081] For example, bytes 0-7 are input to the 800 GMII parsing module 0, bytes 8-15 are input to the 800 GMII parsing module 1, and so on, and bytes 120-127 are input to the 800 GMII parsing module 15.

[0082] Each 800 GMII parsing module is responsible for checking whether the respective 8-byte data contains a preamble and checking the correctness of the preamble, while also parsing the control character / S / into the SOP of the packet, parsing the / T / into the EOP of the packet, and obtaining the number of valid bytes in the 8-byte data and the packet content of the 8-byte data.

[0083] In an embodiment, the number of multi-byte data is 4; for a 128-byte data packet, the multi-byte data is 32-byte data.

[0084] The at least two multi-byte data based on the pre-processed to-be-processed packet includes:

[0085] The parsing module generates four 32-byte data from each of the 8-byte data after pre-processing and the corresponding information, and determines the relevant information corresponding to each of the 32-byte data; the relevant information includes whether there is a SOP, whether there is an EOP, and the number of valid bytes.

[0086] Correspondingly, the storing of the at least two multi-byte data in the corresponding buffer and the pressing of the relevant information of each multi-byte data into the first-in-first-out queue FIFO corresponding to each buffer include:

[0087] each of the 32-byte data is stored into a corresponding buffer;

[0088] the relevant information of each of the 32-byte data is pushed into a corresponding FIFO corresponding to the buffer.

[0089] Here, after the parsing module of the 800 GMII interface is parsed, 128-byte data is divided into four 32-byte data and written into four buffers respectively.

[0090] Among them, byte 0-31 is written into buffer 0, byte 32-63 is written into buffer 1, byte 64-95 is written into buffer 2, and byte 96-127 is written into buffer 3.

[0091] At the same time, the SOP / EOP / valid byte number information corresponding to each 32-byte and the address of the write buffer are pushed into the corresponding FIFO.

[0092] When the FIFO is not empty, according to the information that each FIFO is about to pop out, it can be determined whether to pop out the FIFO and read the buffer. Since the length of the message received from the chip port may be relatively short, one 128-byte data may contain more than one data message, and the system side can only process one data message in one clock cycle. If all the 128-byte data is read out in one clock cycle, and the 128-byte data contains more than one data message, the remaining data message data needs to be latched until the next clock cycle to process. Therefore, a large number of flip-flops are required to latch data, and up to 120 bytes of data need to be latched.

[0093] And through the above method provided by the embodiment of the application, the 128-byte data is not read out at one time, and the flip-flops for latching data can be reduced to the maximum, and up to only 16 bytes of data will be latched.

[0094] In combination with the above description as shown in Figure 2 , it is assumed that 128-byte data contains two data messages, data message 0 is written into buffer 3 and buffer 2, and data message 1 is written into buffer 1 and buffer 0, and this information is reflected by the data stored in the FIFO. Figure 1The buffer read control module 3 in the MAC gets the 32 bytes as the SOP of the data packet 0 from the FIFO 3, pops the information of the FIFO 3, and reads the data of the buffer 3; the buffer read control module 2 gets the 32 bytes as the EOP of the data packet 0 from the FIFO 2, pops the information of the FIFO 2, and reads the data of the buffer 2, and at the same time, tells the buffer read control module 1 / 0 not to read the data in the buffer 1 / 0, because a complete data packet is read in this clock cycle, and there is no need to read the data in the following buffer.

[0095] Therefore, no data is latched in this clock cycle, and the use of the latch flip-flop is saved.

[0096] In practical application, the MAC has a buffer control module; the buffer control module is related to the number of buffers; the number of buffers is related to the number of multi-byte data;

[0097] In an embodiment, the target packet is obtained from the corresponding buffer and FIFO based on the related information of each byte data, including:

[0098] The buffer control module determines whether the corresponding buffer contains the SOP and / or the EOP based on the related information in the corresponding FIFO, to determine whether the corresponding buffer is the complete packet in the corresponding clock cycle;

[0099] The buffer control module reads only the determined complete packet as the target packet based on the determined SOP and EOP as the condition.

[0100] That is, the SOP and EOP are used as trigger conditions to inform that only the determined complete packet can be read as the target packet.

[0101] In an embodiment, the at least two multi-byte data are converted into data in a second format according to the at least two multi-byte data and the related information of each multi-byte data, including:

[0102] The high 8-byte data in the first clock cycle and the first 120-byte data in the second clock cycle are used to generate the data in the second format;

[0103] The second clock cycle is the next clock cycle of the first clock cycle.

[0104] The high 8-byte data is used to represent whether the next clock cycle has the EOP, and the number of valid bytes when the EOP exists.

[0105] Correspondingly, the first 120 bytes of data of the first clock cycle and the high 8 bytes of the previous clock cycle of the first clock cycle generate data of a corresponding second format. The high 8 bytes of the previous clock cycle are used to represent whether the first clock cycle has an EOP and the number of valid bytes when the first clock cycle has an EOP.

[0106] It is considered that the CRC field has no effect on the function processing of the chip in actual application, and can be stripped, but needs to be confirmed, that is, it needs to be understood whether the CRC field is contained in the data, and the data bit width used by the system side is 128 bytes, and if the 129-byte message needs to be transmitted in two clock cycles, 128 bytes are transmitted in the first clock cycle, including 3 bytes of CRC, and 1 byte of CRC is transmitted in the second clock cycle (as shown in Figure 5 The present application proposes a method for identifying whether the data of the next clock cycle is the EOP of the message to solve the above two problems.

[0107] In the current clock cycle, whether the data of the next clock cycle is the EOP, and the number of valid bytes of the next clock cycle are identified. The key problem is how to get whether the next clock cycle is the EOP and the number of valid bytes of the next clock cycle in the current clock cycle.

[0108] Through the above method, the original 128-byte data on the 800 GMII interface is left shifted by 8 bytes, and the shifted 8 bytes are latched and spliced with the low 120 bytes of the data of the next clock cycle to form 128-byte data, and the high 8 bytes of the data of the next clock cycle are latched and spliced with the low 120 bytes of the data of the next clock cycle to form 128-byte data, and so on, as shown in Figure 6 .

[0109] In this way, the 128-byte data of the current clock cycle and the high 8 bytes of the data of the next clock cycle can be seen in each clock cycle, and whether the current clock cycle and the next clock cycle have an EOP and the number of valid bytes when the EOP is known according to the 128-byte data of the current clock cycle and the high 8 bytes of the data of the next clock cycle, and then it can be judged whether the current 128-byte data contains the CRC field.

[0110] It should be noted that the above method is particularly suitable for 800G (corresponding to 128-byte data bit width, that is, the example of the 128-byte data to be processed message) Ethernet and above 800G Ethernet scenarios, so that the use of flip-flops can be greatly reduced, and the chip area is saved. Of course, it can also be used in less than 800G Ethernet scenarios, which is not limited here.

[0111] Figure 8 Another structure diagram of a MAC data processing device provided by an embodiment of the present application is shown in FIG. 2. As shown in FIG. 2, the device comprises: Figure 8

[0112] a parsing module, a conversion module, at least two buffers and a FIFO corresponding to each of the buffers;

[0113] The parsing module is configured to pre-process a to-be-processed packet in a first clock cycle, and obtain at least two multi-byte data based on the pre-processed to-be-processed packet. The to-be-processed packet is data in a first format.

[0114] The at least two multi-byte data are respectively stored in the corresponding buffers, and the relevant information of each of the multi-byte data is pushed into the FIFO corresponding to each of the buffers. The relevant information of each of the byte data is used to obtain a target packet from the corresponding buffer and FIFO.

[0115] The conversion module is configured to convert the at least two multi-byte data into data in a second format according to the at least two multi-byte data and the relevant information of each of the multi-byte data.

[0116] Specifically, the parsing module is configured to parse 128-byte data of the to-be-processed packet in units of 8-byte data to determine whether the corresponding 8-byte data contains a preamble and the correctness of the preamble.

[0117] A control character S is determined as a packet start flag SOP, and a control character T is determined as a packet end flag EOP.

[0118] The number of valid bytes in the 8-byte data and the packet content are determined.

[0119] Specifically, the conversion module is configured to generate data in the second format according to the at least two multi-byte data in the first clock cycle and high 8-byte data in a second clock cycle.

[0120] The second clock cycle is a next clock cycle of the first clock cycle.

[0121] The high 8-byte data is used to represent the number of valid bytes in the next clock cycle.

[0122] Figure 8 The device shown in FIG. 2 can also implement other steps in the method shown in FIG. 1, which will not be described in detail here. Figure 1 The device shown in FIG. 2 can also implement other steps in the method shown in FIG. 1, which will not be described in detail here.

[0123] ​The electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor.

[0124] The method disclosed by the embodiments of the present application can be applied to a processor or implemented by the processor. The processor can be an integrated circuit chip with a signal processing capability.

[0125] The embodiments of the present application further provide a storage medium, specifically a computer storage medium, and more specifically a computer readable storage medium. The storage medium stores computer instructions, i.e., a computer program. The computer instructions are executed by a processor to implement the method provided by one or more of the technical solutions.

[0126] In the several embodiments provided by the present application, it should be understood that the disclosed method and intelligent device can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There can be another division during actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling, or direct coupling or communication connection between each component can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or in other forms.

[0127] In addition, the technical solutions disclosed by the embodiments of the present application can be combined arbitrarily without conflict.

[0128] The above description is only the preferred embodiments of the present application, and is not used to limit the protection range of the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection range of the present application.

Claims

1. A MAC data processing method, characterized by, The method comprises: preprocessing a to-be-processed packet in a first clock cycle, obtaining at least two multi-byte data based on the preprocessed to-be-processed packet; the to-be-processed packet is data in a first format; storing the at least two multi-byte data in corresponding buffers respectively, and pushing relevant information of each multi-byte data into a first-in-first-out queue (FIFO) corresponding to each buffer; the relevant information of each byte data is used to obtain a target packet from the corresponding buffer and FIFO; converting the at least two multi-byte data into data in a second format according to the at least two multi-byte data and the relevant information of each multi-byte data; wherein the converting the at least two multi-byte data into data in a second format according to the at least two multi-byte data and the relevant information of each multi-byte data comprises: generating data in a second format according to high 8-byte data of the first clock cycle and first 120-byte data of a second clock cycle; the second clock cycle is a next clock cycle of the first clock cycle; the high 8-byte data is used to represent whether the next clock cycle has an EOP and the number of valid bytes when the EOP exists.

2. The method of claim 1, wherein, The MAC has an analysis module, and the preprocessing the to-be-processed packet in the first clock cycle comprises: the analysis module analyzes 128-byte data of the to-be-processed packet in units of 8-byte data to determine whether the corresponding 8-byte data contains a preamble and the correctness of the preamble; determining a control character S as a packet start flag SOP and a control character T as a packet end flag EOP; and determining the number of valid bytes in the 8-byte data and the packet content.

3. The method of claim 1, wherein, The number of multi-byte data is four; the obtaining at least two multi-byte data based on the preprocessed to-be-processed packet comprises: the analysis module generates four 32-byte data according to each 8-byte data after preprocessing and corresponding information, and determines relevant information corresponding to each 32-byte data; the relevant information includes whether there is a SOP, whether there is an EOP, and the number of valid bytes; correspondingly, the storing the at least two multi-byte data in corresponding buffers respectively and the pushing the relevant information of each multi-byte data into a first-in-first-out queue (FIFO) corresponding to each buffer comprises: storing each 32-byte data in a corresponding buffer; pushing the relevant information of each 32-byte data into a FIFO corresponding to the corresponding buffer.

4. The method of claim 1, wherein, The MAC has a buffer control module; the buffer control module is related to the number of buffers; the number of buffers is related to the number of multi-byte data; the relevant information of each byte data is used to obtain a target packet from the corresponding buffer and FIFO, which comprises: the buffer control module determines whether the corresponding FIFO contains a SOP and / or an EOP based on the relevant information in the corresponding FIFO, to determine whether the corresponding buffer contains a complete packet in the corresponding clock cycle; The buffer control module reads only the complete messages determined by the SOP and EOP as the target messages.

5. A MAC data processing apparatus, characterized by, include: A parsing module, a conversion module, at least two buffers, and a FIFO corresponding to each buffer; The parsing module is used to preprocess the message to be processed in the first clock cycle and obtain at least two multi-byte data based on the preprocessed message to be processed. The message to be processed is data in a first format; In addition, the at least two multi-byte data are stored into their respective buffers, and the relevant information of each multi-byte data is pushed into the first-in-first-out (FIFO) queue corresponding to each buffer; the relevant information of each byte data is used to obtain the target message from the corresponding buffer and FIFO. A conversion module is used to convert the at least two multi-byte data into data in a second format based on the at least two multi-byte data and the relevant information of each of the multi-byte data. The conversion module is further configured to generate data in a second format based on the high 8 bytes of data in the first clock cycle and the first 120 bytes of data in the second clock cycle; wherein the second clock cycle is the next clock cycle after the first clock cycle; the high 8 bytes of data are used to characterize whether the next clock cycle has an EOP, and the number of valid bytes when an EOP is present.

6. The apparatus of claim 5, wherein, The parsing module is used to parse the 128 bytes of data in the message to be processed in 8-byte units to determine whether the corresponding 8-byte data contains a preamble and the correctness of the preamble; The control character S is designated as the start of message (SOP), and the control character T is designated as the end of message (EOP); and, Determine the number of valid bytes and message content in the 8-byte data.

7. An electronic device, comprising: include: The processor and the memory used to store computer programs that can run on the processor. When the processor is used to run the computer program, it performs the steps of the method described in any one of claims 1 to 4.

8. A storage medium having stored thereon a computer program, characterized in that When the computer program is executed by a processor, it implements the steps of the method described in any one of claims 1 to 4.

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