A read-write test method and device, computer storage medium and electronic equipment

Abstract

The embodiment of the application provides a read-write test method and device, a computer storage medium and an electronic device, the method comprises the following steps: receiving a data instruction sent by a memory controller, determining a physical storage address corresponding to the data instruction; when the data instruction indicates a read operation, performing the read operation on a target storage object in a memory module, and receiving a target read value sent by the memory module; obtaining a target write value of the target storage object in the memory module in a last write operation; comparing the target read value with the target write value, and determining a test result of the target storage object in the memory module according to a comparison result. In this way, the data instruction sent by the memory controller can directly determine the physical storage address of the storage object, and then the subsequent test is performed by using the physical storage address, so that it is not necessary to reestablish an address mapping relationship for different system control platforms, and the flexibility and universality of the read-write test can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory testing, and particularly relates to a read-write test method and device, a computer storage medium and an electronic device. BACKGROUND

[0002] In servers, personal computers and various consumer electronics, dynamic random access memory (DRAM) is generally used as a memory component to provide temporary data storage functions. According to the data storage principle of DRAM, DRAM needs to be continuously refreshed during use to maintain data stability.

[0003] At present, a test application program (such as a Stress APP tool) is generally used to perform read-write testing on DRAM to ensure the stability and reliability of the memory. Since the Stress APP tool needs to use logical storage addresses to perform read-write testing, if one or more data errors occur, the Stress APP tool needs to be parsed to determine the physical storage address at which the error occurs. In other words, for different system platforms, the Stress APP tool needs to be redesigned to have address mapping relationships and corresponding test parameters, and the development cycle is very long. In addition, the Stress APP tool may have compatibility problems, thereby resulting in poor flexibility and universality of the Stress APP tool. SUMMARY

[0004] The present application provides a read-write test method and device, a computer storage medium and an electronic device, which can directly use physical storage addresses to perform read-write testing on a memory module, thereby improving the flexibility and compatibility of read-write testing.

[0005] The technical solution of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a read-write test method applied to a read-write test device, and the method comprises the following steps.

[0007] Receiving a data instruction sent by a memory controller, and determining a physical storage address corresponding to the data instruction;

[0008] When the data instruction indicates a read operation, performing a read operation on a target storage object in the memory module, and receiving a target read value sent by the memory module; wherein the target storage object in the memory module is determined according to the physical storage address;

[0009] Obtaining a target write value of the target storage object in the memory module in a last write operation;

[0010] The target read value is compared with the target write value, and a test result of the target storage object in the memory module is determined according to a comparison result.

[0011] In some embodiments, the method further comprises: when the data instruction indicates a write operation, determining the target write value according to the data instruction; and performing a write operation on the target storage object in the memory module to write the target write value into the target storage object in the memory module.

[0012] In some embodiments, the read-write test device comprises a first storage unit and a second storage unit; and the method further comprises: after the target write value is determined, storing the physical storage address and the target write value in the first storage unit correspondingly; and after the target read value is determined, storing the physical storage address and the target read value in the second storage unit correspondingly.

[0013] In some embodiments, the comparison of the target read value with the target write value and the determination of the test result of the target storage object in the memory module according to a comparison result comprises:

[0014] The target write value corresponding to the physical storage address is obtained from the first storage unit, and the target read value corresponding to the physical storage address is obtained from the second storage unit; in a case where the target write value is the same as the target read value, it is determined that the target storage object in the memory module is in a normal state; or in a case where the target write value is different from the target read value, it is determined that the target storage object in the memory module is in an abnormal state.

[0015] In some embodiments, the method further comprises: in a case where the target write value is the same as the target read value, or in a case where the target write value is different from the target read value and no system recovery instruction is received, returning the target read value to the memory controller; or in a case where the target write value is different from the target read value and a system recovery instruction is received, performing data recovery processing on the target storage object in the memory module.

[0016] In some embodiments, the data recovery processing on the target storage object in the memory module comprises:

[0017] A rewrite operation is performed on the target storage object in the memory module to write the target write value into the target storage object in the memory module; a re-read operation is performed on the target storage object in the memory module, and a corrected read value sent by the memory module is received; and in a case where the corrected read value is the same as the target write value, the corrected read value is returned to the memory controller.

[0018] In some embodiments, the method further comprises: according to the first storage unit and the second storage unit, counting the read-write times of each storage object in the memory module; after controlling the memory controller to be in the idle state, determining a to-be-processed storage object according to the read-write times of each storage object in the memory module; and performing read-write test processing on the to-be-processed storage object based on the preset test mode, so that the read-write times of each storage object in the memory module meet the preset requirement.

[0019] In some embodiments, after performing read-write test processing on the to-be-processed storage object based on the preset test mode, the method further comprises:

[0020] obtaining, from the first storage unit, an effective write value corresponding to the to-be-processed storage object; wherein the effective write value refers to a target write value in a last write operation of the to-be-processed storage object before the memory controller is in the idle state; performing write processing on the to-be-processed storage object to write the effective write value into the to-be-processed storage object; and controlling the memory controller to exit the idle state.

[0021] In a second aspect, the embodiments of the present application provide a read-write test device, comprising:

[0022] a parsing control unit configured to receive a data instruction sent by the memory controller, determine a physical storage address corresponding to the data instruction, and when the data instruction indicates a read operation, perform a read operation on a target storage object in the memory module and receive a target read value sent by the memory module; wherein the target storage object in the memory module is determined according to the physical storage address;

[0023] a comparison unit configured to obtain a target write value of the target storage object in the memory module in a last write operation, and compare the target read value with the target write value to determine a test result of the target storage object in the memory module according to a comparison result.

[0024] In some embodiments, the parsing control unit is further configured to, when the data instruction indicates a write operation, determine a target write value according to the data instruction, and perform a write operation on the target storage object in the memory module to write the target write value into the target storage object in the memory module.

[0025] In some embodiments, the read-write test device further comprises a first storage unit and a second storage unit; wherein the first storage unit is configured to store write values of each storage object in the memory module; and the second storage unit is configured to store read values of each storage object in the memory module.

[0026] Correspondingly, the parsing control unit is further configured to, after determining the target write value, store the physical storage address and the target write value in the first storage unit correspondingly; and after determining the target read value, store the physical storage address and the target read value in the second storage unit correspondingly.

[0027] In some embodiments, the comparison unit is specifically configured to obtain a target write value corresponding to the physical storage address from the first storage unit; obtain a target read value corresponding to the physical storage address from the second storage unit; and determine that the target storage object in the memory module is in a normal state in a case where the target write value and the target read value are the same; or determine that the target storage object in the memory module is in an abnormal state in a case where the target write value and the target read value are different.

[0028] In some embodiments, the read-write test device further comprises an output unit; the output unit is configured to generate an alarm information in a case where the target write value and the target read value are different, and display the alarm information on a preset display screen; wherein the alarm information is used to indicate that the target storage object in the memory module is in an abnormal state.

[0029] In some embodiments, the analysis control unit is further configured to return the target read value to the memory controller in a case where the target write value and the target read value are the same, or in a case where the target write value and the target read value are different and no system recovery instruction is received; or perform data recovery processing on the target storage object in the memory module in a case where the target write value and the target read value are different and a system recovery instruction is received.

[0030] In some embodiments, the analysis control unit is further configured to perform a rewrite operation on the target storage object in the memory module to write the target write value into the target storage object in the memory module; perform a re-read operation on the target storage object in the memory module and receive a corrected read value sent by the memory module; and return the corrected read value to the memory controller in a case where the corrected read value and the target write value are the same.

[0031] In some embodiments, the read-write test device further comprises a test mode unit; the test mode unit is configured to provide a preset test mode; the comparison unit is further configured to count the read-write times of each storage object in the memory module according to the first storage unit and the second storage unit; and the analysis control unit is further configured to determine a to-be-processed storage object according to the read-write times of each storage object in the memory module after controlling the memory controller to be in an idle state; and perform read-write test processing on the to-be-processed storage object based on the preset test mode, so that the read-write times of each storage object in the memory module meet a preset requirement.

[0032] In some embodiments, the parsing control unit is further configured to: obtain, after performing the read-write test processing on the to-be-processed storage object based on the preset test mode, an effective write value corresponding to the to-be-processed storage object from the first storage unit; perform write processing on the to-be-processed storage object to write the effective write value into the to-be-processed storage object; and control the memory controller to exit the idle state; wherein the effective write value refers to a target write value in a last write operation of the to-be-processed storage object before the memory controller is in the idle state.

[0033] In some embodiments, the read-write test device further comprises a data selector; and the parsing control unit is further configured to: send the first selection instruction to the data selector; or send the second selection instruction to the data selector.

[0034] The data selector is configured to: control the parsing control unit and the memory controller to be in the connected state after receiving the first selection instruction; or control the parsing control unit and the memory module to be in the connected state after receiving the second selection instruction.

[0035] In a third aspect, an embodiment of the present application provides a computer storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the method according to the first aspect are implemented.

[0036] In a fourth aspect, an embodiment of the present application provides an electronic device, which comprises the read-write test device according to the second aspect.

[0037] The embodiments of the present application provide a read-write test method and device, a computer storage medium and an electronic device. The data instruction sent by the memory controller is received, and the physical storage address corresponding to the data instruction is determined. When the data instruction indicates a read operation, a read operation is performed on a target storage object in the memory module, and a target read value sent by the memory module is received. The target storage object in the memory module is determined according to the physical storage address. A target write value of the target storage object in the memory module in a last write operation is obtained. The target read value and the target write value are compared, and a test result of the target storage object in the memory module is determined according to a comparison result. In this way, the physical storage address of the storage object can be directly determined by the data instruction sent by the memory controller, and subsequent tests are performed by using the physical storage address, without the need to re-establish an address mapping relationship for different system control platforms. In addition, the read-write test method only involves operations on the memory controller and the memory module, without the need to interact with an external operating system, and there is no compatibility problem, which can improve the flexibility and universality of the read-write test. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 FIG. 1 is a flowchart of a read-write test method according to an embodiment of the present application.

[0039] Figure 2 A flowchart of another read-write test method provided for the embodiments of the present application is shown in FIG. 8;

[0040] Figure 3 A structural diagram of a read-write test device provided for the embodiments of the present application is shown in FIG. 9;

[0041] Figure 4 A structural diagram of another read-write test device provided for the embodiments of the present application is shown in FIG. 10;

[0042] Figure 5 A structural diagram of still another read-write test device provided for the embodiments of the present application is shown in FIG. 11;

[0043] Figure 6 A structural diagram of Module 1 provided for the embodiments of the present application is shown in FIG. 12;

[0044] Figure 7 A structural diagram of Module 2 provided for the embodiments of the present application is shown in FIG. 13;

[0045] Figure 8 A structural diagram of an electronic device provided for the embodiments of the present application is shown in FIG. 14. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, but not to limit the application. In addition, it should be noted that only the parts related to the application are shown in the drawings for the convenience of description.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing the embodiments of the present application only and is not intended to limit the present application.

[0048] In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0049] It should be noted that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0050] The following explains the English words and their abbreviations involved in the embodiments of the present application.

[0051] Dynamic Random Access Memory, DRAM: Dynamic Random Access Memory;

[0052] Memory Down: Memory soldered to the motherboard;

[0053] Dual Inline Memory Module, DIMM: Dual Inline Memory Module;

[0054] RDIMM: Registered Dual Inline Memory Module;

[0055] LRDIMM: Low Profile Dual In-line Memory Module;

[0056] UDIMM: Unbuffered Dual Channel Memory Module;

[0057] SODIMM: Small Outline Dual Inline Memory Module;

[0058] Memory: Memory, Memory Module;

[0059] Cell: Storage unit in a memory module, also known as a storage object;

[0060] Temporarily Store: Temporary storage space;

[0061] Memory Controller: Memory Controller;

[0062] DIMM Slot: DIMM Slot;

[0063] Rank: Logical block in memory;

[0064] Bank: Physical block in memory;

[0065] Row Address: Row Address;

[0066] Column Address: Column Address;

[0067] Pre-Charge: Pre-Charge;

[0068] Refresh: Refresh;

[0069] Central Processing Unit, CPU: Central Processing Unit;

[0070] JEDEC: Semiconductor industry standard designated by JEDEC;

[0071] Raw Card: Memory card type

[0072] Serial Presence Detect, SPD: Serial Presence Detect information

[0073] Field Programmable Gate Array, FPGA: Field Programmable Gate Array

[0074] Application Specific Integrated Circuit, ASIC: Special Application Integrated Circuit

[0075] Idle: Idle state

[0076] For the semiconductor industry, DRAM is an important electronic device that can provide storage functions for terminal devices. Specifically, since DRAM is a dynamic random memory device, the charge of storing data can only keep the data for a certain period of time. At room temperature, the retention time of a typical cell capacitor is about 64 milliseconds. Therefore, in order to ensure normal data storage, it is necessary to periodically refresh the storage unit to keep the data stable.

[0077] During normal operation of the terminal device, the CPU usually places the running data and the temporary data in the operation in the memory, that is, the memory can be understood as a large-capacity temporary storage. If the data is not kept intact in the memory, the operating system will read the data incorrectly when reading the data, which will cause the entire system to crash or restart.

[0078] For terminal devices, the memory controller sends corresponding instructions to the DRAM to achieve data writing and reading. Specifically, in the working process of DARM, the memory controller (Memory Controller) sends the following parameters to the memory DRAM in turn: (1) Select Memory Controller; (2) Select DIMM Slot; (3) Select Rank address; (4) Select Bank Address, Row Address; (5) Select Column Address for read / write operation; (6) Other operation content, such as Pre-Charge / Refresh operation.

[0079] Generally, servers, notebook computers and various consumer electronic products involve DRAM devices for storing a large amount of data temporarily involved in the process of CPU operation. Therefore, the data error of DRAM storage will bring disastrous failure to the electronic products, such as system shutdown, system restart.

[0080] Therefore, the read and write test (also known as stress test) of the memory is an important test of the memory for testing the reliability and stability of the DRAM. At present, the general Stress APP tools include MemtestX86, Primer95, Memtester, StressAPP, etc. However, in the actual test, it is found that these software involves the system compatibility and software upgrade problems; moreover, the error address of the same test position in the memory reported by different Stress APPs can be different, and it is very possible that the Stress APP occurs error when analyzing the address; furthermore, if multiple errors occur in the memory, the system can be shut down or restarted, at this time, the Stress APP also hangs, which brings great disturbance to the system analysis; in addition, these Stress APPs are developed under a specific operating system, so the compatibility of the operating system and the compatibility of the CPU need to be considered during development, and the development cycle is quite long; finally, the several Stress APPs shown above have no way to control the stress pressure applied to each address in the memory (i.e. the read and write times of each address can be different), which leads to the final test result not being accurate enough.

[0081] Based on this, the embodiment of the present application provides a read-write test method, and the basic idea is: receiving a data instruction sent by a memory controller, determining a physical storage address corresponding to the data instruction; when the data instruction indicates a read operation, performing a read operation on a target storage object in a memory module, and receiving a target read value sent by the memory module; wherein the target storage object in the memory module is determined according to the physical storage address; obtaining a target write value of the target storage object in the memory module in the last write operation; comparing the target read value with the target write value, and determining a test result of the target storage object in the memory module according to the comparison result. In this way, the data instruction sent by the memory controller can directly determine the physical storage address corresponding to the data instruction, and then the subsequent test is performed by using the physical storage address, without the need to reestablish the address mapping relationship for different system control platforms; secondly, the read-write test method only involves the operation of the memory controller and the memory module, without the need to interact with the external system control platform, and there is no compatibility problem, which can improve the flexibility and universality of the read-write test; in addition, the read-write test method also has an error correction mechanism, which can correct the read-write errors found in time to avoid system crash; finally, the read-write test method also has a pressure balancing mechanism, which can ensure that the read-write pressure of different storage units is the same, and improve the test accuracy.

[0082] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0083] In an embodiment of the present application, referring to Figure 1 which shows a flowchart of a read-write test method provided by an embodiment of the present application. As Figure 1 indicated, the method can include:

[0084] S101: receiving a data instruction sent by a memory controller, and determining a physical storage address corresponding to the data instruction.

[0085] It should be noted that the read-write test method provided by the embodiment of the present application is applied to a read-write test device, or a terminal device integrated with the read-write test device. The terminal device can be various types of devices with a memory module in the implementation process. For example, the terminal device can be a device such as a smart phone, a tablet computer, a palm computer, a television, a projector, a personal computer, a personal digital assistant (PDA), a wearable device, etc., which is not limited here.

[0086] The read-write test device is a hardware module connected between a memory controller and a memory module (e.g., a DIMM). Specifically, the memory module includes a plurality of storage objects (or cells), and the memory controller can send different instructions to the memory module to perform read / write operations on different storage objects.

[0087] It should be noted that, in the actual write or read operation of the memory module by the memory controller, the memory module needs to be operated by sending the actual physical address of the target storage object. On this basis, since the read-write test device is set in the form of hardware between the memory controller and the memory module, the read-write test device can receive and analyze the data instruction sent by the memory controller, and determine the corresponding physical storage address according to the data instruction.

[0088] For example, when the memory module is composed of a plurality of DIMMs, the data instruction issued by the memory controller at least includes the following addresses: memory channel address (Memory Channel), DIMM position (DIMM Position), memory Rank address (Rank Selection), memory Bank address (Bank Selection), row address (Row Address Selection), and column address (Column Address Selection). The above addresses also constitute the physical storage address of this data instruction.

[0089] In other words, in the related art, the read-write test of the memory module generally needs to be realized by a Stress APP, and the Stress APP needs to test the memory module according to the logical storage address, and when an error is found, the physical storage address needs to be determined through further address analysis. The embodiment of the present application develops a read-write test device from the perspective of hardware, which is set between the memory controller and the memory module. Through the read-write test device, the physical storage address can be directly obtained by analyzing the data instruction issued by the memory controller, and then the subsequent test is performed by using the physical storage address instead of the logical storage address. Therefore, even in different operating systems, it is not necessary to re-establish the address mapping relationship, thereby improving the universality and flexibility of the stress test.

[0090] S102: When the data instruction indicates a read operation, performing a read operation on a target storage object in the memory module and receiving a target read value sent by the memory module; wherein the target storage object in the memory module is determined according to the physical storage address.

[0091] It should be noted that there are multiple different storage objects (Cells) in the memory module, which are distinguished by physical storage addresses. Therefore, when the data instruction indicates a read operation, the read-write test device can control the memory module to perform a read operation according to the physical storage address, so as to obtain the target read value of the target storage object.

[0092] S103: Obtain the target write value of the target storage object in the memory module in the last write operation.

[0093] It should be noted that the read-write test device has a separate storage space for storing the write value of each storage object in the memory module in the last write operation.

[0094] S104: Compare the target read value and the target write value, and determine the test result of the target storage object in the memory module according to the comparison result.

[0095] It should be noted that the target read value and the target write value should be the same on the premise that the target storage object is in a normal state. Therefore, according to the actual comparison result of the target read value and the target write value, the test result of the target storage object can be determined.

[0096] In some embodiments, the method can further include:

[0097] When the data instruction indicates a write operation, determining the target write value according to the data instruction;

[0098] Performing a write operation on the target storage object in the memory module to write the target write value into the target storage object in the memory module.

[0099] It should be noted that when the data instruction indicates a write operation, the read-write test device needs to parse the data instruction to determine the target write value, and then write the target write value into the target storage object.

[0100] It should also be noted that the read-write test device can set a separate storage space for storing the data required during the test. Therefore, in some embodiments, the read-write test device includes a first storage unit and a second storage unit. Accordingly, the method can further include:

[0101] After determining the target write value, store the physical storage address and the target write value in the first storage unit correspondingly;

[0102] After determining the target read value, store the physical storage address and the target read value in the second storage unit correspondingly.

[0103] It should be noted that the first storage unit is configured to store the physical storage address and the to-be-written value (e.g., the target write value) in all write operations; and the second storage unit is configured to store the physical storage address and the actually read value (e.g., the target read value) in all read operations.

[0104] In this way, by comparing the write value and the read value of the same physical storage address in the first storage unit and the second storage unit, the read-write test result of the storage object can be obtained. Therefore, in some embodiments, the comparing the target read value with the target write value and determining the test result of the target storage object in the memory module according to the comparison result can include:

[0105] obtaining the target write value corresponding to the physical storage address from the first storage unit;

[0106] obtaining the target read value corresponding to the physical storage address from the second storage unit;

[0107] in a case where the target write value is the same as the target read value, determining that the target storage object in the memory module is in a normal state; or in a case where the target write value is different from the target read value, determining that the target storage object in the memory module is in an abnormal state.

[0108] It should be understood that the same storage object actually undergoes repeated read-write processes, that is, one physical storage address in the first storage unit can have multiple write values, and one physical storage address in the second storage unit can have multiple read values. In the embodiments of the present application, the target write value refers to the write value in the last write operation for the physical storage address before the read operation corresponding to the target read value occurs.

[0109] In particular, in some embodiments, the read-write test device can only include the first storage unit, and the target read value obtained by the read operation on the target storage object can be compared with the target write value stored in the first storage unit immediately, and then the test result of this time can be obtained.

[0110] It should be further noted that, for the terminal device, in order to save the calculation amount, the read-write test device is enabled only when the read-write test is needed. That is, when the system is in a normal working state, the memory controller is directly connected with the memory module, at this time, the memory controller directly issues data instructions to the memory module to perform corresponding read / write operations; when the system is in a read-write test state, the memory controller is connected with the memory module through the read-write test device, at this time, the memory controller needs to issue data instructions to the read-write test device, and the read-write test device controls the memory module to perform corresponding read / write operations, and the read-write test device also performs other test operations.

[0111] The read-write test process is described in detail below.

[0112] First, the memory controller issues a data instruction, which assumes that the data instruction indicates writing "1" to the storage object at address A. At this time, the read-write test device stores address A and the write value "1" in the first storage unit and controls the memory module to write "1" to the storage unit corresponding to address A.

[0113] Then, when the memory controller issues a data instruction again, and the data instruction indicates reading address 1, the read-write test device controls the memory module to read the storage object at address A. Assuming that the read value "1" is obtained, the read-write test device stores address A and the read value "1" in the second storage unit at this time.

[0114] Finally, the read value and the write value are compared. At this time, the write value "1" and the read value "1" are the same, indicating that the storage object indicated by address A is in a normal state. Conversely, if the read value is "0", it indicates that the storage object indicated by address A is in an abnormal state.

[0115] When the target storage object is in an abnormal state, an alarm mechanism can also be set to remind the staff. Therefore, in some embodiments, when the target write value and the target read value are different, the method can further include:

[0116] generating an alarm information; wherein the alarm information is used to indicate that the target storage object in the memory module is in an abnormal state; and displaying the alarm information on a preset display screen.

[0117] Exemplarily, the preset display screen can be divided into left and right parts, one part for real-time display of the write values of different storage objects in the memory module, and the other part for real-time display of the read values of different storage objects in the memory module. If the target write value and the target read value of a certain storage object are found to be different, the staff can be reminded through pop-up messages, highlighted markings, red box warnings, etc.

[0118] In some embodiments, the method further includes:

[0119] In the case where the target write value and the target read value are the same, or in the case where the target write value and the target read value are different and no system recovery instruction is received, the target read value is returned to the memory controller; or, in the case where the target write value and the target read value are different and a system recovery instruction is received, data recovery processing is performed on the target storage object in the memory module.

[0120] It should be noted that after obtaining the target read value, the read-write test device also needs to return the target read value to the memory controller, so as to complete the command closed loop of the memory controller, otherwise the memory controller will appear an error. However, if a large number of storage objects or an important storage object has a data error, directly returning the read value may cause the system to crash. Therefore, the embodiment of the present application also sets a system recovery mechanism. Here, the system recovery mechanism can be enabled or disabled according to user demand.

[0121] Specifically, if the target write value and the target read value are the same, that is, the target storage object is in a normal state, the target read value can be directly returned to the memory controller. If the target write value and the target read value are different, and no system recovery instruction sent by the user is received, the target read value is also returned to the memory controller. If the target write value and the target read value are different, and the system recovery instruction sent by the user is received, the data recovery processing is performed on the target storage object.

[0122] It should be further noted that the data recovery processing specifically means trying to re-write and re-read the target storage object. Therefore, in some embodiments, the data recovery processing on the target storage object in the memory module can include:

[0123] performing a re-write operation on the target storage object in the memory module to write the target write value into the target storage object in the memory module;

[0124] performing a re-read operation on the target storage object in the memory module, and receiving a corrected read value sent by the memory module;

[0125] in a case where the corrected read value is the same as the target write value, returning the corrected read value to the memory controller.

[0126] It should be noted that if the corrected read value is different from the target write value, the above steps can be repeated, or an error corrected read value is returned to the memory controller, or a staff is reminded to handle.

[0127] In this way, through the system recovery mechanism, the situation of too many data errors and system downtime can be avoided, and the stability of the system is improved.

[0128] It should be further noted that in the related art, the read-write times of each storage unit in the memory module can be different, which leads to different read-write pressures of different storage units, thereby affecting the test results. In order to solve this problem, in some embodiments, as shown in Figure 2 the method can further include:

[0129] S201: According to the first storage unit and the second storage unit, the read-write times of each storage object in the memory module are counted.

[0130] S202: After the memory controller is controlled to be in the idle state, a storage object to be processed is determined according to the read-write times of each storage object in the memory module.

[0131] S203: The storage object to be processed is subjected to read-write test processing based on a preset test mode, so that the read-write times of each storage object in the memory module meet a preset requirement.

[0132] It should be noted that, according to the foregoing content, if a write operation is performed on a storage object, a write value will be added to the physical storage address of the storage object in the first storage unit; if a read data operation is performed on a storage object, a read value will be added to the physical storage address of the storage object in the second storage unit. Therefore, according to the number of data stored in the first storage unit and the second storage unit, the read-write times of different storage objects can be counted. Then, the storage object with fewer read-write times is determined as the storage object to be processed, and the storage object to be processed is subjected to read-write test processing alone, so that the read-write times of different storage objects are approximately the same.

[0133] It should be noted that the read-write times can refer to the read times, the write times, the sum of the read times and the write times, or the read-write times can also include the read times and the write times at the same time. Correspondingly, the preset test mode can indicate the specific process of how to determine the read-write times according to the read-write times of the storage object to be processed. The parameters of the preset test mode can be defined by the user.

[0134] In addition, a threshold value (for example, 5 times, 10 times) can be set according to actual needs, and if the read-write times of two storage objects in the memory module differ by no more than the threshold value, it is considered that the read-write times of different storage objects meet the preset requirement.

[0135] It should be further noted that, since the pressure balancing mechanism is provided by the read-write test device 30, it is irrelevant to the memory controller. Therefore, after the storage objects to be processed with fewer read-write times are determined, the memory controller 31 needs to be controlled to enter the idle state, and the control right of the memory module 32 is handed over to the read-write test device 30, so that the read-write test device 30 performs read-write test processing on the storage objects to be processed by using the preset test mode.

[0136] In some embodiments, after the read-write test processing on the storage object to be processed based on the preset test mode, the method can further include:

[0137] an effective write value corresponding to the storage object to be processed is obtained from the first storage unit; wherein the effective write value refers to a target write value in the last write operation of the storage object to be processed before the memory controller is in the idle state;

[0138] performing write processing on the to-be-processed storage object to write a valid write value into the to-be-processed storage object;

[0139] The memory controller is controlled to exit the idle state.

[0140] It should be further noted that, for the memory controller, the write value in the to-be-processed storage object needs to remain unchanged, otherwise the system will crash. Therefore, before the memory controller is controlled to exit the idle state, the previous valid write value needs to be written back to the to-be-processed storage object.

[0141] In this way, by providing a stress balancing mechanism, the case that the read-write stress of different storage objects is different can be avoided, and the reliability of the test result is improved.

[0142] In the related art, a memory bar is generally tested by a stress test tool (Stress APP) to test the stability and reliability of the memory. However, on the one hand, since the Stress APP tool needs to use a logical storage address to perform read-write testing, if one or more data input / output channel signals (generally referred to as DQ signals) are wrong during the testing process, the Stress APP needs to be parsed according to an address mapping parsing relationship to know the address of the data that has occurred an error, and if the system platform is replaced, the Stress APP needs to be redeveloped to establish a new address mapping parsing relationship to correctly locate the error; on the other hand, the Stress APP also needs to consider the compatibility of the operating system and other issues, and therefore needs to be constantly updated, which causes the generalizability to be not very friendly; on the other hand, when too many errors occur, the error correction capability of the system platform may be exceeded, at which time the system has crashed, and the Stress APP has also crashed, that is, the Stress APP cannot cope with the case of too many errors; on the other hand, the existing Stress APP has no good way to count and guarantee the stress result of each address in the memory.

[0143] In order to solve the problems existing when the memory module runs read-write testing, an embodiment of the present application develops a module from a hardware perspective, which can test the stress of different storage objects in the Memory and can balance the stress of each storage object, avoiding the problem that the testing cannot be performed due to the long development and verification period of the Stress APP.

[0144] Specifically, since the system is in the actual write or read operation of the Memory, is through the actual physical storage address to send the Memory operation, the specific command sending order is generally: Memory Channel, Rank Selection & DIMM Position, Bank Selection, Row Address Selection and Column Address Selection.

[0145] Therefore, a read-write test device capable of analyzing the Memory command can be established between the Memory Controller and the Memory, and the write and read data are recorded according to the recording mode of Memory Channel, Rank Selection (DIMM Selection), Bank Selection, Row Address Selection and Column Address Selection, that is, the first storage unit is used to store the write value in the write operation, and the second storage unit is used to store the read value in the read operation. Then, the write value and the read value are compared, and the comparison result is displayed and output on the display screen.

[0146] In this way, if there is error data, the specific physical address of the error data can be directly displayed, without additional address analysis. In addition, according to the first storage unit and the second storage unit, the Stress of different addresses can be counted, and the addresses with small Stress are tested separately by using the preset test mode, so as to ensure that the Stress of each address is the same or approximately the same. In this way, by counting the Stress of each address in the memory, the addresses with small Stress can be tested separately, so as to ensure that the Stress of each address in the memory is equal or as equal as possible. In addition, the data recovery mechanism can also be used to avoid system downtime or restart due to too much error data.

[0147] The embodiment of the present application provides a read-write test method, data instructions sent by a memory controller are received, a physical storage address corresponding to the data instructions is determined; when the data instructions indicate a read operation, a target storage object in a memory module is subjected to the read operation, and a target read value sent by the memory module is received; wherein the target storage object in the memory module is determined according to the physical storage address; a target write value of the target storage object in the memory module in a last write operation is acquired; the target read value and the target write value are compared, and a test result of the target storage object in the memory module is determined according to a comparison result. In this way, the data instructions sent by the memory controller can directly determine the physical storage address corresponding to the data instructions, and subsequent tests are further performed by using the physical storage address, so that it is not necessary to reestablish an address mapping relationship for different system control platforms; secondly, the read-write test method only involves operations on the memory controller and the memory module, and it is not necessary to interact with an external system control platform, so that there is no compatibility problem, and flexibility and universality of the read-write test can be improved; in addition, the read-write test method further has an error correction mechanism, read-write errors found can be corrected in time, and system collapse can be avoided; finally, the read-write test method further has a pressure balancing mechanism, and the read-write pressure of different storage units can be ensured to be the same, and test accuracy can be improved.

[0148] In another embodiment of the present application, referring to Figure 3 which shows a structural schematic diagram of a read-write test device 30 provided by the embodiment of the present application. As Figure 3 indicated, the read-write test device 30 can include:

[0149] The analysis control unit 301 is configured to receive data instructions sent by a memory controller, determine a physical storage address corresponding to the data instructions, and when the data instructions indicate a read operation, perform a read operation on a target storage object in a memory module, and receive a target read value sent by the memory module; wherein the target storage object in the memory module is determined according to the physical storage address;

[0150] The comparison unit 302 is configured to acquire a target write value of the target storage object in the memory module in a last write operation, and compare the target read value with the target write value, and determine a test result of the target storage object in the memory module according to a comparison result.

[0151] It should be noted that the embodiment of the present application provides a read-write test device 30 from the perspective of hardware, which is arranged between a memory controller and a memory module, and the read-write test device 30 can analyze data instructions sent by the memory controller, so as to determine a physical storage address corresponding to the data instructions, and then perform subsequent tests by using the physical storage address, rather than using a logical storage address, so that it is not necessary to establish an address mapping relationship, and universality is improved.

[0152] Reference is made to Figure 4 , which shows a structure diagram of another read-write test device 30 provided by an embodiment of the present application. As shown in Figure 4 , the read-write test device 30 is connected between a memory controller 31 and a memory module 32. The memory module 32 contains a plurality of storage objects, and the memory controller 31 can send different instructions to the memory module 32 through the read-write test device 30 to implement read / write operations on different storage objects.

[0153] The read-write test device 30 includes an analysis control unit 301 and a comparison unit 302. Specifically, after the read-write test device 30 receives a data instruction sent by the memory controller 31, the analysis control unit 301 analyzes the data instruction to determine a physical storage address, and controls the memory module 32 to perform a corresponding read / write operation according to the data instruction. The comparison unit 302 is used to compare a target write value and a target read value of a target storage object, so as to determine a test result.

[0154] Here, the physical storage address at least includes one of the following: a channel address, a dual in-line memory module slot address, a memory Rank address, a memory Bank address, a row address, and a column address.

[0155] It should be further noted that, in some embodiments, the analysis control unit 301 is further configured to, when the data instruction indicates a write operation, determine a target write value according to the data instruction; and perform a write operation on a target storage object in the memory module to write the target write value into the target storage object in the memory module.

[0156] That is, after the read-write test device 30 receives a data instruction sent by the memory controller 31, if the data instruction indicates a write operation, the analysis control unit 301 performs a write operation on a target storage object in the memory module 32 according to the physical storage address, and stores the physical storage address and the target write value; if the data instruction indicates a read operation, the analysis control unit 301 performs a read operation on the target storage object in the memory module 32 according to the physical storage address, to obtain a target read value returned by the memory module 32, and stores the physical storage address and the target read value; then, the comparison unit 302 compares the target write value and the target read value to determine a test result of the target storage object.

[0157] The read-write test device 30 can set a separate storage space to store the physical storage address / write value or the physical storage address / read value.

[0158] As Figure 4As shown, the read-write test device 30 can further include a first storage unit 303 and a second storage unit 304. Correspondingly, the analysis control unit 301 is further configured to store the physical storage address and the target write value in the first storage unit 303 after determining the target write value, and store the physical storage address and the target read value in the second storage unit 304 after determining the target read value.

[0159] It should be noted that the first storage unit 303 is configured to store the write value of each storage object in the memory module 32, and the second storage unit 304 is configured to store the read value of each storage object in the memory module 32.

[0160] In some embodiments, the comparison unit 302 is specifically configured to acquire the target write value corresponding to the physical storage address from the first storage unit 303, acquire the target read value corresponding to the physical storage address from the second storage unit 304, and determine that the target storage object in the memory module 32 is in a normal state in the case that the target write value and the target read value are the same, or determine that the target storage object in the memory module 32 is in an abnormal state in the case that the target write value and the target read value are different.

[0161] In some embodiments, as shown in Figure 4 The read-write test device 30 further includes an output unit 305.

[0162] The output unit 305 is configured to generate an alarm information in the case that the target write value and the target read value are different, and display the alarm information on a preset display screen.

[0163] It should be noted that the alarm information is configured to indicate that the target storage object in the memory module 32 is in an abnormal state, so as to remind the staff to handle. In addition, the preset display screen can be divided into two parts, i.e., left and right parts, to display the write value and the read value corresponding to different storage objects in real time.

[0164] In order to complete the logic loop of the memory controller, if the memory controller 31 issues a data instruction indicating a read operation, the read-write test device 30 needs to return the read value to the memory controller 31. However, if there are many data errors, it may cause the memory controller 31 to crash. In order to solve this problem, in some embodiments, the read-write test device 30 further has a system recovery mechanism. Specifically, the analysis control unit 301 is further configured to return the target read value to the memory controller 31 in the case that the target write value and the target read value are the same, or in the case that the target write value and the target read value are different and no system recovery instruction is received, or perform data recovery processing on the target storage object in the memory module 32 in the case that the target write value and the target read value are different and a system recovery instruction is received.

[0165] It should be noted that the system recovery mechanism can be enabled or disabled according to user needs, so that the data recovery processing is performed on the target storage object only when a data error (the target write value is different from the target read value) occurs and a system recovery instruction is received; otherwise, the obtained target read value is returned to the memory controller 31. Of course, in other embodiments, the system recovery mechanism can also be designed to be always enabled, that is, as long as a data error occurs, the data recovery processing is performed on the target storage object.

[0166] In addition, a data recovery button can be provided in the read-write test device 30, and if the user presses the data recovery button, it is determined that a system recovery instruction is received.

[0167] It should be further noted that the essence of the data recovery processing is to perform rewriting and re-reading processing on the target storage object. Therefore, in some embodiments, the analysis control unit 301 is further configured to perform rewriting operation on the target storage object in the memory module 32 to write the target write value into the target storage object in the memory module 32, perform re-reading operation on the target storage object in the memory module 32, and receive the corrected read value sent by the memory module 32; and return the corrected read value to the memory controller 31 in the case that the corrected read value is the same as the target write value.

[0168] In the related art, the read-write times of different storage objects in the test process can be different, which affects the accuracy of the test result. Therefore, in some embodiments, the read-write test device 30 can further include a test mode unit 306. Specifically,

[0169] The test mode unit 306 is configured to provide a preset test mode.

[0170] The comparison unit 302 is further configured to count the read-write times of each storage object in the memory module 32 according to the first storage unit and the second storage unit.

[0171] The analysis control unit 301 is further configured to determine a to-be-processed storage object according to the read-write times of each storage object in the memory module 32 after controlling the memory controller 31 to be in an idle state, and perform read-write test processing on the to-be-processed storage object based on the preset test mode, so that the read-write times of each storage object in the memory module 32 meet the preset requirements.

[0172] It should be noted that according to the data in the first storage unit 303 and the data in the second storage unit 304, the read-write times of different storage objects can be counted, and then the read-write test processing is performed on the storage objects with less read-write times, so that the read-write times of different storage objects meet the preset requirements.

[0173] It should be noted that the preset test mode defines the specific method of read-write test processing, such as the default write value, the sequence of write and read operations, etc., and the preset test mode can be modified according to the user's needs.

[0174] In addition, the read-write test device 30 further comprises a power management unit 307 for powering the read-write test device. In this way, since the read-write test device 30 has a separate power supply scheme, it can still play a control role after the memory controller 31 enters the idle state.

[0175] It should be further noted that after the read-write times of different storage objects meet the preset requirements, the read-write test device 30 also needs to return the control to the memory controller 31 when the read-write times of each storage object meet the preset requirements, that is, the memory controller 31 exits the idle state. However, the values in the to-be-processed storage objects must be consistent before the memory controller 31 enters the idle state and after the memory controller 31 exits the idle state, otherwise the memory controller 31 will crash.

[0176] Therefore, in some embodiments, the analysis control unit 31 is further configured to, after performing the read-write test processing on the to-be-processed storage object based on the preset test mode, obtain the valid write value corresponding to the to-be-processed storage object from the first storage unit 303; perform write processing on the to-be-processed storage object to write the valid write value into the to-be-processed storage object; and control the memory controller 31 to exit the idle state.

[0177] It should be noted that the valid write value refers to the target write value in the last write operation of the to-be-processed storage object before the memory controller 31 enters the idle state.

[0178] It should be further noted that in order to facilitate the staff to master the test situation, the output unit 305 is further configured to display the read-write times of each storage object in the memory module 32 on the preset display screen 33.

[0179] From the above, it can be seen that for the read-write test device 30, first, a data path is formed with the memory controller 31, so as to receive and analyze the data instructions sent by the memory controller 31; then, a data path is formed with the memory module 32, so as to perform read / write operations on the target storage object; finally, a data path is formed with the memory controller 32 again, so as to return the operation result of the data instruction.

[0180] In other words, the read-write test device 30 needs to form data paths with the memory controller 31 and the memory module 32 in turn. In order to achieve this purpose, in some embodiments, the read-write test device 30 further comprises a data selector;

[0181] The parsing control unit 301 is further configured to send a first selection instruction to the data selector, or send a second selection instruction to the data selector.

[0182] The data selector is configured to control the parsing control unit and the memory controller to be in a connected state after receiving the first selection instruction, or control the parsing control unit and the memory module to be in a connected state after receiving the second selection instruction.

[0183] It should be noted that, in addition to setting the data selector, a software control method can also be used to achieve the above purpose.

[0184] In the related art, according to the data storage principle of DRAM, the time for DRAM to keep data stable is limited, so DRAM needs to be constantly refreshed to keep data stable. In other words, if the data retention time (Retention) of the overall storage unit (Cell) in the DRAM is not enough, or the Retention of part of the Cell is not enough, it will cause important data to be lost, for example, the data bits (Data Bits) change from 1 to 0, or from 0 to 1. When the data bits change unexpectedly, it may cause the entire system to crash or the system to restart. Therefore, the read-write test of DRAM is an important performance test, but the existing read-write test device has various problems.

[0185] Therefore, the embodiment of the present application provides a read-write test device 30, which can be integrated into the motherboard of a terminal device, or as a separate module. In particular, the read-write test device 30 has a completely independent operating system, and it has a separate power supply system. There are four main functions:

[0186] (1) Through the read-write test device 30, the stress of each address in the memory module can be determined during the stress test, and then the stress of each address (according to the Channel / DIMM / Rank / Row address) can be displayed on the display screen. At the same time, when error data is tested, the information of the error address is displayed on the display screen.

[0187] (2) According to the stress size of the Channel / DIMM / Rank / Row address statistics, a specific test mode is selected to test the address with small stress, so as to ensure that the stress of each address is equal or approximately equal.

[0188] (3) The Stress APP function can be improved and replaced, and the development cycle of the Stress APP due to platform upgrade and compatibility can be saved, and the specific information of the error data can be located through the hardware method.

[0189] (4) When the system finds one or more error data, the data recovery setting can be set to ensure the stability of the operating system.

[0190] The embodiment of the present application provides a read-write test device, which comprises an analysis control unit, a comparison unit and a memory module. The analysis control unit is used for receiving a data instruction sent by a memory controller and determining a physical storage address corresponding to the data instruction; and when the data instruction indicates a read operation, performing a read operation on a target storage object in the memory module and receiving a target read value sent by the memory module; wherein the target storage object in the memory module is determined according to the physical storage address. The comparison unit is used for obtaining a target write value of the target storage object in the memory module in a last write operation; and comparing the target read value with the target write value, and determining a test result of the target storage object in the memory module according to a comparison result. In this way, the data instruction sent by the memory controller can directly determine the physical storage address corresponding to the data instruction, and then the physical storage address is used for subsequent testing, so that it is not necessary to reestablish an address mapping relationship for different system control platforms. In addition, the read-write test method only involves the memory controller and the memory module, and does not need to interact with an external system control platform, so that there is no compatibility problem, and the flexibility and universality of the read-write test can be improved.

[0191] In another embodiment, referring to Figure 5 , a structural schematic diagram of another read-write test device 30 provided by the embodiment of the present application is shown. The application scenario comprises a memory controller 31, the read-write test device 30 and at least one memory module (DIMM or Memory Down) 32.

[0192] As shown in Figure 5 , the read-write test device 30 is arranged between the memory controller 31 and the memory module 32. The read-write test device 30 is a completely independent control system, which comprises a controller, a power supply and power management unit (equivalent to the power management unit 307 in Figure 4 ), a data recovery button, a display screen, a storage unit, a test mode unit (or referred to as a Pattern unit), a calculation / comparison unit and an output unit (not shown) and the like. Wherein, the principle of the controller can be FPGA or customized CPU, and the storage unit can comprise a write data storage unit 1 (equivalent to the first storage unit 303 in Figure 4 ), a read data storage unit 2 (equivalent to the second storage unit 304 in Figure 4 ).

[0193] It should be understood that Figure 5The structure of the read / write test device 30 in the middle references the physical structure of some modules, rather than a strictly functional structure. For example, Figure 5 The part of the controller that performs analytical control is equivalent to Figure 4 The parsing control unit 301 in the middle, Figure 5 The controller and the calculation / comparison unit together function as equivalent to Figure 4 Comparison unit 302 in the middle, Figure 5 The controller and some devices capable of performing data output (in the middle) Figure 5 (Not shown) Functionally equivalent to Figure 4 Output unit 305 in the middle.

[0194] In practical applications, the memory controller 31 may have multiple data channels. For each channel, a separate read / write test device 30 can be set up to locate the address where a data error occurs in the memory module 32 and to perform error correction. To improve device efficiency, a separate controller (e.g., ...) can be set up for each channel. Figure 5 (Controller 0, Controller N, etc. in the system), while sharing other parts.

[0195] In summary, the embodiments of this application involve various electronic products, including servers, computers, and consumer platforms, all of which utilize memory (e.g., DRAM, LR / RDIMM, UDIMM, SODIMM, etc.). Data integrity within memory significantly impacts the overall system operation, especially in server applications where memory data integrity is paramount. The read / write testing device 30 provided in this application can quickly and accurately locate the erroneous data address when erroneous data occurs in memory (e.g., during normal read / write or stress testing), thereby effectively improving the stability and reliability of memory and helping to ensure the smooth progress of functional and stress tests. Furthermore, the read / write testing device 30 can also statistically analyze the actual stress pressure of stored objects in each Rank / Bank of the memory. Based on the statistically analyzed stress pressure, it performs individual stress tests on addresses with low stress according to a specific pattern, ensuring that the stress of each address is equal or similar. Additionally, when multiple data errors occur, it can correct the erroneous data and greatly contribute to the stable operation of the operating system.

[0196] The read-write test device 30 can be implemented by two different hardware structures, which are referred to as Module 1 and Module 2. In other words, in the following embodiments, both Module 1 and Module 2 are essentially read-write test devices 30 and can perform the same functions, and the main difference between them is that: (1) Module 1 is relatively more complex in hardware and higher in cost, and takes more time, but the software is slightly simpler; (2) Module 2 is more complex in software, but lower in hardware cost. In particular, the controller in Module 1 and Module 2 has the function of parsing the data instructions (or referred to as Command) of the memory controller 31.

[0197] Please refer to Figure 6 , which shows the structure diagram of Module 1 provided by the embodiments of the present application. As Figure 6 shown, Module 1 includes a controller, a data recovery button, a high-speed data selector (High Speed Mux), a power supply and power management unit, a first storage unit (or referred to as a write data storage unit 1), a second storage unit (or referred to as a read data storage unit 2), and a test mode unit. At the same time, the controller integrates a comparison unit, an output unit, and a parsing control unit. Among them, the parsing control unit is mainly used to parse the Command and control the high-speed data selector. In particular, the controller can be implemented by, for example, FPGA or ASIC, etc.

[0198] In Figure 6 , the data path between the high-speed data selector and the memory controller 31 is referred to as A, the data path between the high-speed data selector and the controller is referred to as B, and the data path between the high-speed data selector and the memory module is referred to as C.

[0199] As Figure 6 shown, when writing data, the high-speed data selector first controls AB to be turned on, so that the memory controller 31 issues data instructions (generally including CMD signals / CA signals / CTL signals / DQ signals / DQS signals) to the controller; the high-speed data selector then controls BC to be turned on, so that the controller issues control signals (generally Control Signals) to the memory module 32 to control the memory module 32 to write data; conversely, when reading data, the high-speed data selector first controls CB to be turned on, so that the controller controls the memory module 32 to read data; the high-speed data selector then controls AB to be turned on, so that the controller returns the reading result to the memory controller 31.

[0200] That is, Module 1 has independent power supply and power management unit, and can switch the data path of memory controller 31, read-write test device 30 and memory module 32 through high-speed data selector. In this way, read-write test device 30 can collect data instructions and other information between memory controller 31 and memory module 32, and save these information. Then, by comparing the write and read information before and after, the comparison results can be displayed on the display screen by means of data comparison output unit, for example, the address of error data can be displayed. In addition, read-write test device 30 counts the read-write times of each address (i.e. the size of pressure), so as to carry out individual test more targetedly.

[0201] In particular, each type of DIMM has a Raw Card defined in JEDEC, and the Raw Card type information can be obtained by reading the SPD information on the DIMM. If the test result indicates that there is error data, the location of the error data on the DIMM (i.e. the location of the storage object where the error occurs) can be located according to the Raw Card information and the address of the error data, and these error location information can be displayed on the display screen.

[0202] For Module 1, the specific control logic is divided into the following parts:

[0203] (1) The controller in Module 1 can analyze the Command command between memory controller 31 and memory module 32, and separate the read and write instructions according to the Command command of memory controller 31. When storing data, the physical storage address needs to be formed according to Channel, DIMM Slot, Rank, Banks, Row, Column and other information, so as to record.

[0204] (2) Write operation, after the controller in Module 1 analyzes the write command, the controller records all the write data, and stores the write data into the first storage unit according to Channel, DIMM Slot, Rank, Banks, Row, Column. At the same time, the controller switches the high-speed data selector from the original BA path to the BC path, and the controller writes all the write values (records data in order) into the specified storage object in memory module 32.

[0205] (3) Read operation, after the controller in Module 1 parses the read command, the high-speed data selector switches to BC channel, the controller reads the data, and stores the read data into the second storage unit according to Channel, DIMM Slot, Rank, Banks, Row, Column; then, the read data and the data in the first storage unit are compared (for the same Channel, DIMM Slot, Rank, Banks, Row, Column). If no error occurs, the controller switches the high-speed data selector from CB channel to BA channel, and if one or more data errors are found, the error information can be displayed on the display screen, and the corresponding Channel, DIMM Slot, Rank, Banks, Row, Column, etc. information can be displayed simultaneously.

[0206] In particular, if the read operation is for multiple storage objects, when the read operation continues according to the read command, if the subsequently read data and the previously written data are compared and new errors are found, the error information can be displayed on the display screen, and the corresponding Channel, DIMM Slot, Rank, Banks, Row, Column, etc. information can be displayed simultaneously.

[0207] (3.1) Error recovery mechanism (or system recovery mechanism), if the controller finds one or more data errors, the user can press the data recovery button (equivalent to sending a system recovery instruction), the controller can re-write the memory once and re-read it, if the read data is consistent with the written data, the controller can switch the high-speed data selector from the original BC channel to the BA channel, or from the original BC channel to the CA channel according to the actual needs, at this time the memory controller 31 is directly connected to the memory module 32.

[0208] (3.2) If the data recovery button is not pressed when the data error occurs, the controller automatically switches the high-speed data selector from the BC channel to the BA channel.

[0209] (4) For the staff, through the recorded Channel, DIMM Slot, Rank, Banks, Row, Column, etc. information and the corresponding DIMM Row Card information (obtained through SPD information), the DIMM on the grain can be found, and the DIMM and the grain position where the error occurs can be displayed on the display screen.

[0210] (5) using the comparison unit to count the data in the first storage unit and the second storage unit, determining the read-write times of each address according to the result of the comparison unit, and obtaining the statistical result of the Stress size of different addresses. According to the statistical result, the addresses with small Stress pressure are subjected to specific stress testing. The method is as follows: first, make the memory controller 31 enter the Idle mode, at this time the memory controller 31 does not operate the DRAM, since the Module1 has a separate power supply and power management unit, so the Module1 can work normally and can operate the memory module 32; then, according to the Stress test result of different addresses in the memory before, the Module1 performs separate stress testing on the addresses with small Stress pressure according to the preset test mode, the preset test mode can be provided by the test mode unit, so that the Stress pressure of each address is equal or approximately equal; finally, when the stress testing module exits the operation on the DRAM, the stress testing module writes the data written in the first storage unit into the DRAM.

[0211] In this way, through the Module1, the entire function of the read-write testing device 30 can be realized.

[0212] Please refer to Figure 7 , which shows the structure schematic diagram of the Module2 provided by the embodiment of the application. As Figure 7 shown, the Module2 includes a controller, a data recovery button, a power supply and power management unit, a display screen, a first storage unit, a second storage unit, a test mode unit; at the same time, the controller integrates a comparison unit, an output unit and an analysis control unit. Among them, the analysis control unit is mainly used for analyzing the Command command and playing a control role.

[0213] For the Module2, the specific control logic is divided into the following parts:

[0214] (1) when the host board is running, the Module2 always plays the role of analyzing the data information between the memory controller 31 and the memory module 32 and the Memory control command; according to the Command command information of the memory controller 31, the written and read data is recorded separately, and recorded according to the information such as Channel, DIMM Slot, Rank, Banks, Row, Column, etc.

[0215] (2) write operation, when the controller in the Module2 analyzes the write command, the controller records all the written data, and stores the written data into the first storage unit according to Channel, DIMM Slot, Rank, Banks, Row, Column;

[0216] (3) Read operation, when the controller in Module2 parses a read command, the controller reads data, and stores the read data into the second storage unit according to Channel, DIMM Slot, Rank, Banks, Row, Column, and compares the data in the first storage unit (for the same Channel, DIMM Slot, Rank, Banks, Row, Column), if one or more data are found to be different, the display screen can display error information, and display corresponding Channel, DIMM Slot, Rank, Banks, Row, Column, and other information.

[0217] Then, in a subsequent read operation, if the data is compared and new error information is found, the display screen can display error information, and display corresponding Channel, DIMM Slot, Rank, Banks, Row, Column, and other information.

[0218] (4) Error recovery mechanism, when the controller finds one or several data, the data recovery button on Module2 can be pressed immediately, and the controller can re-write the memory (at this time, the memory controller 31 does not operate the memory module 32), and then read the memory data;

[0219] (5) Through the recorded Channel, DIMM Slot, Rank, Banks, Row, Column, and Row Card information of the corresponding DIMM, the particles on the DIMM can be found, and the display can display the DIMM and particle position where the error occurs.

[0220] (6) According to the results of the comparison unit, the read and write times of each address are counted, and the statistical results of the Stress size of different addresses are obtained. According to the statistical results, the addresses with small Stress pressure are tested with a specific Pattern stress test. The method is as follows: first, the memory controller 31 enters the idle mode, at this time, the memory controller 31 does not operate the DRAM, but since the power supply and power management unit of Module2 are separate, Module2 can work normally and can operate the memory module 32, according to the Stress test results of different addresses in the memory, Module2 can perform separate stress test on the addresses with small Stress pressure according to the preset test mode. The preset test mode can select one or several Pattern units in the stress test module, so as to ensure that the Stress pressure of each address is equal or approximately equal, when Module2 exits the operation of DRAM, Module2 writes the data previously written into the first storage unit into the DRAM.

[0221] In Figure 7 DQ / DQS are respectively signals related to data, and CMD / CA / CTL are signals related to command, address and control.

[0222] In this way, all functions of the read-write test device 30 can also be realized through the Module 2.

[0223] In summary, the embodiments of the present application are to protect a mechanism module capable of testing the stress size of a memory and ensuring that the stress sizes of each are equal. Specifically, the embodiments of the present application provide a read-write test device 30 having the following functions: on one hand, the read-write test device 30 can detect whether there is error data when the memory module is performing stress testing, and the physical address information of the error data can be directly observed through the display screen; on the other hand, the read-write test device 30 can count the stress size of each address, and select a specific test mode for stress testing of the address with a small stress size, so as to ensure that the stress sizes of each address are equal or similar; on the other hand, when the memory is performing stress testing, the read-write test device 30 records the address according to the hardware physical method, without considering the compatibility of the Stress APP system, and without problems such as being unable to locate the error address or inaccurate location when data error occurs; on the other hand, when the memory module 32 sends data error, the read-write test device 30 can correct the error data, preventing system downtime or restart.

[0224] The embodiments of the present application provide a read-write test method, and the specific implementation method of the foregoing embodiments is described in detail. As can be seen from the foregoing description, the data instruction sent by the memory controller can directly determine the physical storage address corresponding to the data instruction, and then the physical storage address is used for subsequent testing, without the need to reestablish the address mapping relationship for different system control platforms; secondly, the read-write test method only involves the operation of the memory controller and the memory module, without the need to interact with the external system control platform, and without compatibility problems, which can improve the flexibility and universality of read-write testing; in addition, the read-write test method also has an error correction mechanism, which can correct the read-write errors found in time to avoid system crashes; finally, the read-write test method also has a stress balancing mechanism, which can ensure that the read-write stress of different storage units is the same, thereby improving the testing accuracy.

[0225] In another embodiment of the present application, based on the composition schematic diagram of the read-write test device 30, referring to Figure 8 which shows a composition structure schematic diagram of an electronic device 40 provided by the embodiments of the present application. As Figure 8As shown, the electronic device 40 at least includes the read-write test device 30 of any one of the preceding embodiments.

[0226] For the electronic device 40, since it includes the read-write test device 30, the data instruction sent by the memory controller can directly determine the physical storage address corresponding to the data instruction, and then use the physical storage address for subsequent testing, without the need to re-establish the address mapping relationship for different system control platforms; secondly, the read-write test method only involves operating the memory controller and the memory module, without interacting with the external system control platform, and there is no compatibility problem, which can improve the flexibility and universality of read-write testing; in addition, the read-write test method also has an error correction mechanism, which can correct the read-write errors found in time to avoid system crashes; finally, the read-write test method also has a pressure balancing mechanism, which can ensure that the read-write pressure of different storage units is the same, improving the testing accuracy.

[0227] It can be understood that in the foregoing embodiments, the "unit" can be a part of a circuit, a part of a processor, a part of a program or software, etc., and of course can also be a module, and can also be non-modular. Moreover, the components in the present embodiment can be integrated in one processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software function module.

[0228] If the integrated unit is realized in the form of a software function module and is not sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present embodiment can be embodied in the form of a software product, the computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method of the present embodiment. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0229] Therefore, the present embodiment provides a computer storage medium, which stores a computer program, and the computer program is executed by a plurality of processors to implement the steps of the method of any one of the foregoing embodiments.

[0230] The above is only a preferred embodiment of the present application, and is not intended to limit the protection scope of the present application.

[0231] It should be noted that, in the present application, the terms "comprising", "containing" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or apparatus that comprises a list of elements does not only include those elements, but can also include other elements not expressly listed or inherent to such process, method, article or apparatus. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0232] The above-mentioned sequence numbers of the embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0233] The methods disclosed in the several method embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments.

[0234] The features disclosed in the several product embodiments provided by the present application can be combined arbitrarily without conflict to obtain new product embodiments.

[0235] The features disclosed in the several method or device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method or device embodiments.

[0236] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A read-write test method, characterized by, The method is applied to a read-write test device, and the method comprises the following steps: receiving a data instruction sent by a memory controller, and determining a physical storage address corresponding to the data instruction; when the data instruction indicates a read operation, performing a read operation on a target storage object in a memory module, and receiving a target read value sent by the memory module; wherein the target storage object in the memory module is determined according to the physical storage address; obtaining a target write value of the target storage object in the memory module in a last write operation; comparing the target read value with the target write value, and determining a test result of the target storage object in the memory module according to a comparison result; the method further comprises the following steps: when the data instruction indicates a write operation, determining the target write value according to the data instruction; performing a write operation on the target storage object in the memory module, so as to write the target write value into the target storage object in the memory module; the read-write test device comprises a first storage unit and a second storage unit; the method further comprises the following steps: after the target write value is determined, storing the physical storage address and the target write value corresponding to each other into the first storage unit; after the target read value is determined, storing the physical storage address and the target read value corresponding to each other into the second storage unit.

2. The read-write test method of claim 1, wherein, the comparing the target read value with the target write value, and determining the test result of the target storage object in the memory module according to the comparison result, comprises the following steps: obtaining the target write value corresponding to the physical storage address from the first storage unit; obtaining the target read value corresponding to the physical storage address from the second storage unit; in a case where the target write value is the same as the target read value, determining that the target storage object in the memory module is in a normal state; or in a case where the target write value is different from the target read value, determining that the target storage object in the memory module is in an abnormal state.

3. The read-write test method of claim 2, wherein, the method further comprises the following steps: in a case where the target write value is the same as the target read value, or in a case where the target write value is different from the target read value and no system recovery instruction is received, returning the target read value to the memory controller; or in a case where the target write value is different from the target read value and the system recovery instruction is received, performing data recovery processing on the target storage object in the memory module.

4. The read-write test method of claim 3, wherein, the performing data recovery processing on the target storage object in the memory module, comprises the following steps: performing a rewrite operation on the target storage object in the memory module, so as to write the target write value into the target storage object in the memory module; performing a re-read operation on the target storage object in the memory module, and receiving a corrected read value sent by the memory module; in a case where the corrected read value is the same as the target write value, returning the corrected read value to the memory controller.

5. The read-write test method of claim 1, wherein, the method further comprises the following steps: according to the first storage unit and the second storage unit, counting read-write times of each storage object in the memory module; After the memory controller is controlled to be in the idle state, a storage object to be processed is determined according to a read-write frequency of each storage object in the memory module; A read-write test process is performed on the storage object to be processed based on a preset test mode, so that the read-write frequency of each storage object in the memory module meets a preset requirement.

6. The read-write test method of claim 5, wherein, After the read-write test process based on the preset test mode is performed on the storage object to be processed, the method further comprises: An effective write value corresponding to the storage object to be processed is obtained from the first storage unit; wherein the effective write value refers to a target write value in a last write operation of the storage object to be processed before the memory controller is in the idle state; A write process is performed on the storage object to be processed to write the effective write value into the storage object to be processed; The memory controller is controlled to exit the idle state.

7. A read-write test apparatus characterized by comprising: Comprises: The analysis control unit is used for receiving the data instruction sent by the memory controller, determining the physical storage address corresponding to the data instruction; And when the data instruction indicates a read operation, a read operation is performed on a target storage object in the memory module, and a target read value sent by the memory module is received; wherein the target storage object in the memory module is determined according to the physical storage address; The comparison unit is used for obtaining a target write value in a last write operation of the target storage object in the memory module; and comparing the target read value with the target write value, and determining a test result of the target storage object in the memory module according to the comparison result; The analysis control unit is also used for determining the target write value according to the data instruction when the data instruction indicates a write operation; performing a write operation on the target storage object in the memory module to write the target write value into the target storage object in the memory module; The read-write test device further comprises a first storage unit and a second storage unit; wherein, The first storage unit is used for storing the write value of each storage object in the memory module; The second storage unit is used for storing the read value of each storage object in the memory module; Correspondingly, the analysis control unit is also used for storing the physical storage address and the target write value corresponding to each other in the first storage unit after the target write value is determined; and storing the physical storage address and the target read value corresponding to each other in the second storage unit after the target read value is determined.

8. The read-write test device according to claim 7, wherein The comparison unit is specifically used for obtaining the target write value corresponding to the physical storage address from the first storage unit; and obtaining the target read value corresponding to the physical storage address from the second storage unit; And in the case that the target write value and the target read value are the same, it is determined that the target storage object in the memory module is in a normal state; or in the case that the target write value and the target read value are different, it is determined that the target storage object in the memory module is in an abnormal state.

9. The read-write test apparatus according to claim 8, wherein The read-write test device further comprises an output unit; The output unit is configured to generate an alarm information when the target write value is different from the target read value, and display the alarm information on a preset display screen. The alarm information is used to indicate that a target storage object in the memory module is in an abnormal state.

10. The read-write test device according to claim 8, wherein The analysis control unit is further configured to return the target read value to the memory controller when the target write value is the same as the target read value, or when the target write value is different from the target read value and no system recovery instruction is received, or perform data recovery processing on the target storage object in the memory module when the target write value is different from the target read value and the system recovery instruction is received.

11. The read-write test device according to claim 10, wherein The analysis control unit is further configured to perform a rewrite operation on the target storage object in the memory module to write the target write value into the target storage object in the memory module, perform a re-read operation on the target storage object in the memory module, and receive a corrected read value sent by the memory module, and return the corrected read value to the memory controller when the corrected read value is the same as the target write value. The read-write test device further comprises a test mode unit. The test mode unit is configured to provide a preset test mode.

12. The read-write test apparatus according to claim 11, wherein The comparison unit is further configured to count the read-write times of each storage object in the memory module according to the first storage unit and the second storage unit. The analysis control unit is further configured to determine a to-be-processed storage object according to the read-write times of each storage object in the memory module after controlling the memory controller to be in an idle state, perform read-write test processing on the to-be-processed storage object based on the preset test mode, so that the read-write times of each storage object in the memory module meet a preset requirement. The analysis control unit is further configured to obtain an effective write value corresponding to the to-be-processed storage object from the first storage unit after performing the read-write test processing on the to-be-processed storage object based on the preset test mode, perform write processing on the to-be-processed storage object to write the effective write value into the to-be-processed storage object, and control the memory controller to exit the idle state.

13. The read-write test apparatus according to claim 12, wherein The effective write value refers to a target write value in a last write operation of the to-be-processed storage object before the memory controller is in the idle state. The read-write test device further comprises a data selector. The analysis control unit is further configured to send a first selection instruction to the data selector, or send a second selection instruction to the data selector. The data selector is configured to control the analysis control unit and the memory controller to be in a connected state after receiving the first selection instruction, or control the analysis control unit and the memory module to be in a connected state after receiving the second selection instruction.

14. The read-write test apparatus of claim 7, wherein, ​ ​ ​ 15. A computer storage medium, comprising, The computer storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 6.

16. An electronic device, comprising: The electronic device comprises the read-write test device in any one of claims 7 to 14.

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