Energy analysis attack mitigation method, electronic device, and storage medium
By randomizing the location and number of algorithm interfaces in embedded security products, energy fluctuations are masked, solving the problem of preventing energy analysis attacks in embedded security products and improving security and reliability.
Patent Information
- Application Number
- CN202211487488.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-21
- Publication Date
- 2025-11-28
- Estimated Expiration
- 2042-11-21
AI Technical Summary
Embedded security products lack the ability to defend against power analysis attacks due to the lack of protection in existing processor hardware designs, resulting in high costs and cumbersome operation, requiring the replacement of processor chips and hardware designs.
By determining the number of interference algorithm interfaces and the target location number based on a random number sequence and a preset length of the algorithm interface list, an index number queue is generated, and the position of the target algorithm interface in the list of interfaces to be run is randomized to mask energy fluctuations and reduce the success rate of energy analysis attacks.
It effectively reduces the success rate of power analysis attacks, ensures the security and reliability of embedded security products, and avoids the high cost and complex operation of replacing processor chips.
Smart Images
Figure CN115774879B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of computers, and in particular to an energy analysis attack mitigation method, an electronic device, and a storage medium. BACKGROUND
[0002] An energy analysis attack is a kind of non-intrusive attack, which generally collects the overall energy consumption of a cryptographic module from a power supply end or a circuit ground end, and then performs energy analysis to extract information corresponding to the operation of a security function, such as a key. A general processor chip hardware design has a function of mitigating energy analysis attacks, but in embedded security products, the processor hardware design does not have the ability to prevent energy analysis attacks, at which time the processor chip and hardware design need to be replaced, which increases the cost and is cumbersome to operate.
[0003] Therefore, there is an urgent need to provide an embedded security product with a method for mitigating energy analysis attacks in non-intrusive attacks, so as to effectively reduce the success rate of energy analysis attacks and ensure the security and reliability of the embedded security product. SUMMARY
[0004] To overcome the problems in the related art, the present application provides an energy analysis attack mitigation method, an electronic device, and a storage medium. The energy analysis attack mitigation method can effectively reduce the success rate of energy analysis attacks and ensure the security and reliability of the embedded security product.
[0005] The first aspect of the present application provides an energy analysis attack mitigation method, comprising:
[0006] Based on the preset list length of the random number sequence and the to-be-run algorithm interface list, the number of interference algorithm interfaces and the target position number of the target algorithm interface in the to-be-run algorithm interface list are determined;
[0007] Based on the random number sequence, the number of interference algorithm interfaces, and the pointer list length of the algorithm interface function list, an index number queue is determined. Each algorithm interface in the algorithm interface function list is provided with a corresponding index number;
[0008] Based on the target position number, the index number queue, and the algorithm interface function list, the to-be-run algorithm interface list is determined.
[0009] In an embodiment, based on the preset list length of the random number sequence and the to-be-run algorithm interface list, the number of interference algorithm interfaces and the target position number of the target algorithm interface in the to-be-run algorithm interface list are determined, comprising:
[0010] A first random number is obtained from the random number sequence;
[0011] determine the number of interference algorithm interfaces based on the first random number and the preset list length;
[0012] obtain a second random number in the random number sequence;
[0013] determine the target position number based on the second random number and the preset list length.
[0014] In an embodiment, determining the number of interference algorithm interfaces based on the first random number and the preset list length comprises:
[0015] performing modulo operation on the first random number and the preset list length to obtain the number of interference algorithm interfaces.
[0016] In an embodiment, determining the target position number based on the second random number and the preset list length comprises:
[0017] performing modulo operation on the sum of the second random number and 1 of the preset list length to obtain the target position number.
[0018] In an embodiment, the number of interference algorithm interfaces is N, and N is a positive integer;
[0019] determining the index number queue based on the random number sequence, the number of interference algorithm interfaces, and the pointer list length of the algorithm interface function list comprises:
[0020] obtaining N random numbers in the random number sequence in sequence;
[0021] determining N index numbers based on the N random numbers and the pointer list length in sequence;
[0022] determining the index number queue based on the generation order of the N index numbers and the N index numbers.
[0023] In an embodiment, determining the N index numbers based on the N random numbers and the pointer list length in sequence comprises:
[0024] performing modulo operation on the N random numbers and the pointer list length in sequence to obtain the N index numbers in sequence.
[0025] In an embodiment, determining the to-be-run algorithm interface list based on the target position number, the index number queue, and the algorithm interface function list comprises:
[0026] adding the target algorithm interface into the to-be-run algorithm interface list according to the target position number;
[0027] determining each algorithm interface corresponding to each index number in the index number queue in the algorithm interface function list as an interference algorithm interface in sequence;
[0028] The respective interference algorithm interfaces are sequentially added to the to-be-run algorithm interface list.
[0029] In an embodiment, after determining the to-be-run algorithm interface list based on the target position number, the index number queue, and the algorithm interface function list, the method comprises:
[0030] The respective algorithm interfaces in the to-be-run algorithm interface list are sequentially run.
[0031] The second aspect of the application provides an electronic device, comprising:
[0032] a processor; and
[0033] a memory having stored executable codes, which, when executed by the processor, cause the processor to perform the method described above.
[0034] The third aspect of the application provides a non-transitory machine-readable storage medium having stored executable codes, which, when executed by a processor of an electronic device, cause the processor to perform the method described above.
[0035] The technical solution provided by the application can have the following beneficial effects:
[0036] By determining the number of interference algorithm interfaces and the target position number of the target algorithm interface in the to-be-run algorithm interface list based on the random number sequence and the preset list length of the to-be-run algorithm interface list, the position of the target algorithm interface in the to-be-run algorithm interface list and the number of interference algorithm interfaces are randomized; and then the index number queue is determined based on the random number sequence, the number of interference algorithm interfaces, and the pointer list length of the algorithm interface function list, wherein each algorithm interface in the algorithm interface function list is provided with a corresponding index number, and the to-be-run algorithm interface list is determined based on the target position number, the index number queue, and the algorithm interface function list, so that the type of the interference algorithm interface is randomized, the energy fluctuation and power of the hidden algorithm during the running process can be effectively concealed, the success rate of energy analysis attack is effectively reduced, and the security and reliability of the embedded security product are ensured.
[0037] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the application. BRIEF DESCRIPTION OF DRAWINGS
[0038] The above and other objects, features and advantages of the exemplary embodiments of the present application will be readily understood through reading the following detailed description and accompanying drawings. In the drawings, several embodiments of the present application are shown by way of example and not limitation, and the same or corresponding reference numerals indicate the same or corresponding parts.
[0039] Figure 1 is one of flow diagrams of the energy analysis attack mitigation method shown in the embodiments of the present application;
[0040] Figure 2 is another one of flow diagrams of the energy analysis attack mitigation method shown in the embodiments of the present application;
[0041] Figure 3 is still another one of flow diagrams of the energy analysis attack mitigation method shown in the embodiments of the present application;
[0042] Figure 4 is a structural diagram of an electronic device shown in the embodiments of the present application. DETAILED DESCRIPTION
[0043] Embodiments will now be described with reference to the accompanying drawings. It should be understood that, for the sake of brevity, the figures can not be drawn to scale and that certain specific details of the embodiments described maynot be enumerated, for the sake of clarity. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the embodiments described herein. Also, the description is not to be considered as limited to the embodiments described herein. Specific details are presented herein by way of example to provide a thorough description of the embodiments described herein. It will be apparent to those skilled in the art that numerous variations in the embodiments described herein can be practiced without departing from the spirit and scope of the embodiments described herein.
[0044] Energy analysis attack is a kind of non-intrusive attack, which generally collects the overall energy consumption of the cryptographic module from the power supply end or the circuit ground end, and then performs energy analysis to extract information corresponding to the security function operation, such as a key. The general processor chip hardware design will have the function of mitigating energy analysis attack, but in embedded security products, the processor hardware design does not have the ability to prevent energy analysis attack, at which time the processor chip and hardware design need to be replaced, which increases the cost and is cumbersome to operate. Therefore, it is urgent to provide an embedded security product with a method for mitigating energy analysis attack in non-intrusive attack to effectively reduce the success rate of energy analysis attack and ensure the security and reliability of the embedded security product.
[0045] To solve the above problems, the embodiments of the present application provide an energy analysis attack mitigation method, which can effectively reduce the success rate of energy analysis attack and ensure the security and reliability of the embedded security product.
[0046] The technical solutions of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0047] Figure 1 is one of flow diagrams of the energy analysis attack mitigation method shown in the embodiments of the present application, please refer to Figure 1 , the energy analysis attack mitigation method shown in the embodiments of the present application can include:
[0048] In step 101, the number of interference algorithm interfaces and the target position number of the target algorithm interface in the to-be-run algorithm interface list are determined based on the random number sequence and the preset list length of the to-be-run algorithm interface list.
[0049] The random number sequence is a sequence composed of random numbers. The sequence length of the random number sequence, i.e., the number of random numbers in the random number sequence, can be set to 40. It can be understood that the setting manner of the sequence length of the random number sequence is various in actual application, and needs to be set according to the actual application condition, which is not uniquely limited here. It can also be understood that the obtaining manner of the random number sequence is also various, which can be generated by the processor itself or by a third-party application, and needs to be set according to the actual application condition, which is not uniquely limited here.
[0050] The to-be-run algorithm interface list is the algorithm interface list to be run by the processor. It can be understood that the to-be-run algorithm interface list is initially an empty list. The preset list length of the to-be-run algorithm interface list can be the maximum list length of the to-be-run algorithm interface list, which can be set to 6, for example. In actual application, the setting manner of the preset list length of the to-be-run algorithm interface list is various, and needs to be set according to the actual application condition, which is not uniquely limited here.
[0051] The number of interference algorithm interfaces is the number of non-target algorithm interfaces. It can be understood that the non-target algorithm interface, i.e., the interference algorithm interface, functions to cover the target algorithm interface that is actually executed. The number of interference algorithm interfaces and the target position number of the target algorithm interface in the to-be-run algorithm interface list are determined based on the random number sequence and the preset list length, which is beneficial to hiding the target algorithm interface in multiple interference algorithm interfaces, so that the attacker cannot easily identify and determine the target algorithm interface to implement energy analysis attack.
[0052] In step 102, the index number queue is determined based on the random number sequence, the number of interference algorithm interfaces, and the pointer list length of the algorithm interface function list.
[0053] The general architecture of the embedded security product is that the upper application sends instructions to the hardware. When the hardware processes the instructions, it calls the algorithm to perform calculation, and then feeds back the instruction execution result to the upper application. The embedded software maintains an algorithm interface function list, which points to different algorithm interfaces of the processor. Each algorithm interface in the algorithm interface function list is provided with a corresponding index number.
[0054] It can be understood that in the embodiments of the present application, the number of interference algorithm interfaces is used to determine the number of index numbers stored in the index number queue, that is, the algorithm interfaces consistent with the number of interference algorithm interfaces need to be selected from the algorithm interface function list as interference algorithm interfaces. The length of the pointer list is the number of algorithm interfaces in the algorithm interface function list, which is used to limit the index number selected by the random number sequence to not exceed the number of algorithm interfaces, ensuring that the index numbers in the index number queue are all index numbers existing in the algorithm interface function list.
[0055] In step 103, a to-be-run algorithm interface list is determined based on the target position number, the index number queue, and the algorithm interface function list.
[0056] In the embodiments of the present application, the target position number determines the position of the target algorithm interface in the to-be-run algorithm interface list, and the index number queue can map the corresponding algorithm interfaces in the algorithm interface function list. These algorithm interfaces can be added to the empty to-be-run algorithm interface list together with the target algorithm interface to form the final to-be-run algorithm interface list.
[0057] By determining the number of interference algorithm interfaces and the target position number of the target algorithm interface in the to-be-run algorithm interface list based on the random number sequence and the preset list length of the to-be-run algorithm interface list, the position of the target algorithm interface in the to-be-run algorithm interface list and the number of interference algorithm interfaces are randomized. Then, the index number queue is determined based on the random number sequence, the number of interference algorithm interfaces, and the length of the pointer list of the algorithm interface function list, wherein each algorithm interface in the algorithm interface function list is provided with a corresponding index number. The to-be-run algorithm interface list is determined based on the target position number, the index number queue, and the algorithm interface function list, so that the type of interference algorithm interface is randomized, which can effectively reduce the success rate of energy analysis attack and ensure the security and reliability of embedded security products.
[0058] In some embodiments, the determination method of the number of interference algorithm interfaces and the target position number can be further designed. Figure 2 is a flowchart of the energy analysis attack mitigation method according to the embodiments of the present application, please refer to Figure 2 The energy analysis attack mitigation method according to the embodiments of the present application can include:
[0059] In step 201, a first random number is obtained from the random number sequence.
[0060] In step 202, the number of interference algorithm interfaces is determined based on the first random number and the preset list length.
[0061] In the embodiment of the present application, the first random number can be subjected to a modulo operation on the preset list length to obtain the number of interference algorithm interfaces. For example, the number of interference algorithm interfaces can be determined by the following formula one:
[0062] Formula one: SimNum = Mod (R1, ListLen)
[0063] wherein SimNum is the number of interference algorithm interfaces, R1 is the first random number, and ListLen is the preset list length.
[0064] It can be understood that the above method of determining the number of interference algorithm interfaces by modulo operation is exemplary, and in actual application, the method of determining the number of interference algorithm interfaces is various and needs to be determined according to actual application, which is not limited herein.
[0065] In step 203, a second random number is obtained in the random number sequence.
[0066] In step 204, a target position number is determined based on the second random number and the preset list length.
[0067] In the embodiment of the present application, the second random number can be subjected to a modulo operation on the sum of the preset list length plus 1 to obtain the target position number. For example, the target position number can be determined by the following formula two:
[0068] Formula two: P0 = Mod (R2, ListLen + 1)
[0069] wherein R2 is the second random number, and P0 is the target position number.
[0070] It can be understood that the above method of determining the target position number by modulo operation is exemplary, and in actual application, the method of determining the target position number is various and needs to be determined according to actual application, which is not limited herein.
[0071] In some embodiments, an index number queue can be formed based on the sequentially determined N index numbers, and then the interference algorithm interfaces are sequentially determined and added into the algorithm interface list to be run. Figure 3 is the third flowchart of the energy analysis attack mitigation method shown in the embodiment of the present application, please refer to Figure 3 The energy analysis attack mitigation method shown in the embodiment of the present application can include:
[0072] In step 301, N random numbers are sequentially obtained in the random number sequence.
[0073] In the embodiment of the present application, the number of interference algorithm interfaces is N, and N is a positive integer, that is, the number of obtained random numbers is consistent with the number of interference algorithm interfaces.
[0074] In step 302, N index numbers are determined in sequence based on N random numbers and the pointer list length.
[0075] Specifically, the N random numbers are sequentially subjected to modulo operation on the pointer list length, and N index numbers are sequentially obtained. Assuming that N is 4, the four random numbers are R3, R4, R5 and R6 in sequence, the four index numbers can be determined in sequence by executing the following formulas three to six, respectively:
[0076] Formula three: P1 = Mod(R3, AlgListLen)
[0077] Formula four: P2 = Mod(R4, AlgListLen)
[0078] Formula five: P3 = Mod(R5, AlgListLen)
[0079] Formula six: P4 = Mod(R6, AlgListLen)
[0080] Wherein, P1, P2, P3 and P4 are the four index numbers in sequence, and AlgListLen is the pointer list length.
[0081] It can be understood that the above method of determining the index number by modulo operation is exemplary, and in actual application, the method of determining the index number is various, which is determined according to the actual application, and is not limited herein.
[0082] In step 303, the index number queue is determined based on the generation order of the N index numbers and the N index numbers.
[0083] Exemplarily, assuming that N is 4, the four random numbers are R3, R4, R5 and R6 in sequence, and the four index numbers determined in sequence are P1, P2, P3 and P4 respectively, then the index number queue can be represented as {P1, P2, P3, P4}.
[0084] It can be understood that the representation form of the index number queue is various, which is determined according to the actual application, and is not limited herein.
[0085] In step 304, the to-be-run algorithm interface list is determined based on the target position number, the index number queue and the algorithm interface function list.
[0086] Specifically, the target algorithm interface is added into the to-be-run algorithm interface list according to the target position number, and then each index number in the index number queue is used to determine a corresponding algorithm interface in the algorithm interface function list as an interference algorithm interface, and each interference algorithm interface is added into the to-be-run algorithm interface list in sequence.
[0087] For example, assuming that the preset list length of the to-be-run algorithm interface list is 6, that is, the to-be-run algorithm interface list has 6 list positions. If the target position number P0=3, the target algorithm interface is first added into the third list position in the to-be-run algorithm interface list. If the four index numbers are P1, P2, P3 and P4 in sequence, P1=7, P2=3, P3=1 and P4=4, the algorithm interface with the index number 7 in the algorithm interface function list is determined as an interference algorithm interface and added into the first list position in the to-be-run algorithm interface list; the algorithm interface with the index number 3 in the algorithm interface function list is determined as an interference algorithm interface and added into the second list position in the to-be-run algorithm interface list; the algorithm interface with the index number 1 in the algorithm interface function list is determined as an interference algorithm interface and added into the fourth list position in the to-be-run algorithm interface list; and the algorithm interface with the index number 4 in the algorithm interface function list is determined as an interference algorithm interface and added into the fifth list position in the to-be-run algorithm interface list.
[0088] It can be understood that the above description of the determination manner of the to-be-run algorithm interface list is only exemplary, and in actual application, the target position number and each index number need to be determined according to actual application conditions, which is not uniquely limited herein.
[0089] In step 305, each algorithm interface in the to-be-run algorithm interface list is run in sequence. The position of the target algorithm interface in the to-be-run algorithm interface list is random, the number of interference algorithm interfaces is random, and the type of the interference algorithm interface is random, which better hides the target algorithm interface, effectively conceals the energy fluctuation and power of the hidden algorithm in the running process, so that the attacker cannot easily identify and determine the target algorithm interface to implement energy analysis attack in the running process, effectively reduces the success rate of energy analysis attack, and ensures the security and reliability of the embedded security product.
[0090] Corresponding to the foregoing application function implementation method embodiments, the present application further provides an electronic device for executing an energy analysis attack mitigation method and corresponding embodiments.
[0091] Figure 4 A block diagram showing the hardware configuration of an electronic device 800 that can implement the energy analysis attack mitigation method of the embodiments of the present application is shown. As shown in the figure, Figure 4As shown, the electronic device 800 can include a processor 810 and a memory 820. In Figure 4 In the electronic device 800, only the constituent elements related to the present embodiment are shown. Therefore, it is obvious to those skilled in the art that the electronic device 800 can further include common constituent elements different from those shown in the electronic device 800. For example, a fixed-point operator. Figure 4
[0092] The electronic device 800 can correspond to a computing device having various processing functions, for example, functions for generating a neural network, training or learning a neural network, quantizing a floating-point neural network into a fixed-point neural network, or retraining a neural network. For example, the electronic device 800 can be implemented as various types of devices, such as a personal computer (PC), a server device, a mobile device, etc.
[0093] The processor 810 controls all functions of the electronic device 800. For example, the processor 810 controls all functions of the electronic device 800 by executing a program stored in the memory 820 on the electronic device 800. The processor 810 can be implemented by a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), an artificial intelligence processor chip (IPU), etc. provided in the electronic device 800. However, the present application is not limited thereto.
[0094] In some embodiments, the processor 810 can include an input / output (I / O) unit 811 and a computing unit 812. The I / O unit 811 can be used to receive various data, such as a random number sequence. Illustratively, the computing unit 812 can be used to determine the number of interference algorithm interfaces and the target position number of the target algorithm interface in the to-be-executed algorithm interface list based on the preset list length of the to-be-executed algorithm interface list and the random number sequence received via the I / O unit 811; determine the index number queue based on the number of interference algorithm interfaces, the pointer list length of the algorithm interface function list, and the random number sequence received via the I / O unit 811; and determine the to-be-executed algorithm interface list based on the target position number, the index number queue, and the algorithm interface function list. This to-be-executed algorithm interface list can be output by the I / O unit 811, for example. The output data can be provided to the memory 820 for reading and use by the processor or other devices (not shown), or can be directly provided to the processor or other devices for use.
[0095] The memory 820 is hardware for storing various data processed in the electronic device 800. For example, the memory 820 can store processed data and data to be processed in the electronic device 800. The memory 820 can store data related to the energy analysis attack mitigation method process that the processor 810 has processed or is to process. In addition, the memory 820 can store applications, drivers, etc. to be driven by the electronic device 800. For example, the memory 820 can store various programs related to the energy analysis attack mitigation method to be executed by the processor 810. The memory 820 can be a DRAM, but the present application is not limited thereto. The memory 820 can include at least one of a volatile memory or a non-volatile memory. The non-volatile memory can include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. The volatile memory can include a dynamic RAM (DRAM), a static RAM (SRAM), a synchronous dynamic RAM (SDRAM), a PRAM, an MRAM, an RRAM, a ferroelectric RAM (FeRAM), etc. In an embodiment, the memory 820 can include at least one of a hard disk drive (HDD), a solid state drive (SSD), a compact flash (CF), a secure digital (SD) card, a micro secure digital (Micro-SD) card, a mini secure digital (Mini-SD) card, an extreme digital (xD) card, a cache, or a memory stick.
[0096] In summary, the specific functions of the memory 820 and the processor 810 of the electronic device 800 according to the embodiments of the present specification can be explained in contrast to the aforementioned embodiments of the present specification and can achieve the technical effects of the aforementioned embodiments, and thus a repeated explanation thereof will be omitted herein.
[0097] In the present embodiment, the processor 810 can be implemented in any appropriate manner. For example, the processor 810 can take the form of, for example, a microprocessor or a processor and a computer readable medium storing computer readable program codes (e.g., software or firmware) executable by the (micro)processor, a logic gate, a switch, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, etc.
[0098] It should be understood that the terms "first" or "second", etc. in the claims, specification, and drawings of the present disclosure can be used to distinguish different objects, and are not intended to describe a particular order. The terms "include" and "contain" used in the specification and claims of the present disclosure indicate the presence of described features, whole, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, whole, steps, operations, elements, components and / or sets thereof.
[0099] It should also be understood that the terms used in the specification of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used in the specification and claims of the present disclosure, unless otherwise clear from the context, the singular forms "a", "an" and "the" are intended to include plural forms. It should be further understood that the term "and / or" used in the specification and claims of the present disclosure means any combination of one or more of the associated listed terms and all possible combinations, and includes these combinations.
[0100] Although the embodiments of the present application are as described above, the above is only an example adopted for the purpose of facilitating understanding of the present application, and is not intended to limit the scope and application of the present application. Any person skilled in the art of the technology described in the present application can make any modification and change in the form and details of implementation without departing from the spirit and scope of the present application, but the patent protection scope of the present application shall be subject to the scope defined by the appended claims.
[0101] It should also be understood that any module, unit, component, server, computer, terminal or device exemplifying the execution instructions herein can include or otherwise access a computer readable medium, such as a storage medium, a computer storage medium or a data storage device (removable and / or non-removable), for example, a magnetic disk, an optical disk or a magnetic tape. The computer storage medium can include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer readable instructions, data structures, program modules or other data.
Claims
1. An energy analysis attack mitigation method, characterized by, The method comprises the following steps: determining the number of interference algorithm interfaces and the target position number of the target algorithm interface in the list of algorithm interfaces to be run based on a preset list length of a random number sequence and a list of algorithm interfaces to be run; determining an index number queue based on the random number sequence, the number of interference algorithm interfaces and a pointer list length of a list of algorithm interface functions, wherein each algorithm interface in the list of algorithm interface functions is provided with a corresponding index number; determining the list of algorithm interfaces to be run based on the target position number, the index number queue and the list of algorithm interface functions; wherein the number of interference algorithm interfaces is N, and N is a positive integer; the determination of the index number queue based on the random number sequence, the number of interference algorithm interfaces and a pointer list length of a list of algorithm interface functions comprises the following steps: obtaining N random numbers in the random number sequence in sequence; respectively performing modulo operation on the pointer list length by the N random numbers in sequence to obtain N index numbers in sequence; determining the index number queue based on the generation order of the N index numbers and the N index numbers; the determination of the list of algorithm interfaces to be run based on the target position number, the index number queue and the list of algorithm interface functions comprises the following steps: adding the target algorithm interface to the list of algorithm interfaces to be run according to the target position number; determining each algorithm interface corresponding to each index number in the index number queue in the list of algorithm interface functions as an interference algorithm interface in sequence; adding each interference algorithm interface to the list of algorithm interfaces to be run in sequence.
2. The energy analysis attack mitigation method according to claim 1, wherein the determination of the number of interference algorithm interfaces and the target position number of the target algorithm interface in the list of algorithm interfaces to be run based on a preset list length of a random number sequence and a list of algorithm interfaces to be run comprises the following steps: obtaining a first random number in the random number sequence; determining the number of interference algorithm interfaces based on the first random number and the preset list length; obtaining a second random number in the random number sequence; determining the target position number based on the second random number and the preset list length.
3. The energy analysis attack mitigation method according to claim 2, wherein the determination of the number of interference algorithm interfaces based on the first random number and the preset list length comprises the following step: performing modulo operation on the preset list length by the first random number to obtain the number of interference algorithm interfaces.
4. The energy analysis attack mitigation method according to claim 2, wherein the determination of the target position number based on the second random number and the preset list length comprises the following step: performing modulo operation on the sum of the preset list length and 1 by the second random number to obtain the target position number.
5. The energy analysis attack mitigation method according to claim 1, wherein After the target position number, the index number queue, and the algorithm interface function list are determined, the method further includes: running each algorithm interface in the to-be-run algorithm interface list in sequence.
6. An electronic device, comprising: The method comprises: a processor; and a memory having stored thereon executable code that, when executed by the processor, causes the processor to perform the method of any one of claims 1-5.
7. A non-transitory machine-readable storage medium having stored thereon executable code that, when executed by a processor of an electronic device, causes the processor to perform the method of any one of claims 1-5.
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