Magnetic disk device and method for compensating higher harmonics corresponding to harmonic interference

Abstract

A magnetic disk device capable of improving reliability and a method for compensating higher harmonics corresponding to harmonic interference are provided. The magnetic disk device involved in this embodiment comprises: a disk; a head that writes data to the disk and reads data from the disk; an actuator that performs rotational driving to control the movement of the head mounted on the disk; and a controller that estimates the fundamental frequency of a position error signal generated in the positioning control of the head corresponding to interference with harmonics, determines the fundamental frequency, determines the number of delayed sampling based on the fundamental frequency, and suppresses the multiple frequencies of the higher harmonics of the fundamental frequency corresponding to the number of delayed sampling.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2021-146119 (filing date: September 8, 2021), and this application incorporates all the contents of the basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to a magnetic disk device and a method for compensating for higher harmonics corresponding to harmonic interference. Background Art

[0003] The magnetic disk device controls the positioning of the head in the radial direction of the disk by an actuator so that the head is arranged on a track extending along the circumferential direction of the magnetic disk (hereinafter referred to as the disk). When a disturbance such as vibration or shock is applied from the outside to a base having an actuator and a disk on which the head is mounted, the magnetic disk device detects the error between the position of the head on the disk and the target track of the disk as a position error signal (or positioning error signal). The magnetic disk device performs positioning control by a feedback loop that makes the position error signal zero.

[0004] In recent years, large-scale storage systems equipped with dozens to hundreds of disk devices have been constructed. In addition to the CPU and peripheral circuits for system control, large-scale storage systems are also equipped with system fans (fans) for cooling multiple disk devices. The system fan rotates at a higher speed to obtain the air flow required to efficiently replace the air in the system cabinet. The system fan generates vibration sound and wind noise from the bearings, and thus, the base of the disk device vibrates due to its sound pressure, which may deteriorate the PES (Position Error Signal) equivalent to the position error signal of the head. The system fan often monitors the internal temperature on the system side and autonomously controls the air flow rate, that is, the FAN rotation speed. Therefore, the frequency of the PES deteriorated by the FAN rotation speed control (or change) will change. In addition, the PES deteriorated by the rotation of the system FAN may contain many higher harmonics (harmonics) of its fundamental frequency. In order to suppress the higher harmonics of the fundamental frequency of the PES deteriorated by the rotation of the system FAN, it is necessary to construct a multi-stage loop shaping filter. When the number of stages of loop shaping filters increases, in order to realize these loop shaping filters by firmware, the pressure on memory capacity increases, and there is a possibility that a lot of filter calculation time is required. Summary of the invention

[0005] Technical problem to be solved by the invention

[0006] An object of the embodiments of the present invention is to provide a magnetic disk device capable of improving reliability and a method of compensating for harmonics corresponding to harmonic interference.

[0007] The magnetic disk device involved in this embodiment comprises: a disk; a head that writes data to the disk and reads data from the disk; an actuator that performs rotational driving to control the movement of the head mounted on the disk; and a controller that estimates the fundamental frequency of a position error signal generated in the positioning control of the head corresponding to interference with harmonics, determines the fundamental frequency, determines the number of delayed sampling based on the fundamental frequency, and suppresses the multiple frequencies of the higher harmonics of the fundamental frequency corresponding to the number of delayed sampling. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a block diagram showing the structure of the magnetic disk device according to the first embodiment.

[0009] Figure 2 This is a schematic diagram showing an example of a disk according to the first embodiment.

[0010] Figure 3 This is a block diagram showing an example of a head positioning control system during access processing according to the first embodiment.

[0011] Figure 4 Yes means Figure 3 A block diagram of an example of a variable delay memory unit of a repetitive control system RC is shown.

[0012] Figure 5 This is a block diagram showing an example of a head positioning control system during access processing according to the first embodiment.

[0013] Figure 6 This is a block diagram showing an example of a head positioning control system during access processing according to the first embodiment.

[0014] Figure 7 This is a block diagram showing an example of a head positioning control system during access processing according to the first embodiment.

[0015] Figure 8 Yes means Figure 7 A block diagram of an example of a variable delay memory cell of a repetitive control system is shown.

[0016] Fig. 9 It means Figure 6 A diagram of an example of the input-output characteristics of a corresponding repetitive control system.

[0017] Fig.10This is a diagram showing an example of changes in the sensitivity characteristics of the filter and the positioning control system for the harmonics of the estimated value of the fundamental frequency of the harmonic interference.

[0018] Fig.11 1 is a diagram showing an example of a spectrum of a PES in an environment with harmonic interference and a cumulative sum of squares of the spectrum of the PES.

[0019] Fig.12 This is when no low-pass filter is applied. Figure 8 A diagram showing an example of changes in the sensitivity characteristics of a harmonic filter and a positioning control system.

[0020] Fig.13 1 is a diagram showing an example of a spectrum of a PES in an environment with harmonic interference to which no low-pass filter is applied and a cumulative sum of squares of the spectrum of the PES.

[0021] Fig.14 This is a flowchart showing an example of a method for compensating harmonics corresponding to harmonic interference according to the first embodiment.

[0022] Fig.15 This is a flowchart showing an example of a method for compensating harmonics corresponding to interference according to the first embodiment.

[0023] Fig.16 This is a block diagram showing an example of a variable delay memory cell according to the second embodiment.

[0024] Fig.17 This is a block diagram showing an example of a variable delay memory cell according to the second embodiment.

[0025] Fig.18 This is a diagram showing an example of changes in the sensitivity characteristics of the positioning control system according to the second embodiment.

[0026] Fig.19 Yes Fig.18 This is an enlarged view obtained by enlarging the waveform of the frequency near the target suppression fundamental frequency.

[0027] Fig. 20 is to be used as Fig.18 This is an enlarged diagram obtained by enlarging a waveform of a frequency near the 15th harmonic frequency of the target suppressed fundamental frequency.

[0028] Fig.21 It means in Fig.18 , Fig.19 as well as Fig. 20 The sensitivity characteristics shown are graphs showing the suppression frequency error between the frequency of the suppressed harmonics and the target suppression frequency in the variation of the two frequencies.

[0029] Fig. 22 This is a flowchart showing an example of a method for compensating harmonics corresponding to harmonic interference according to the second embodiment.

[0030] Description of symbols

[0031] 1 magnetic disk device, 10 magnetic disk, 10a user data area, 10b system area, 12 spindle motor (SPM), 13 arm, 14 voice coil motor (VCM), 15 head, 15 W write head, 15 R read head, 20 driver IC, 30 head amplifier IC, 40 read / write (R / W) channel, 50 hard disk controller (HDC), 60 microprocessor (MPU), 70 volatile memory, 80 non-volatile memory, 90 buffer memory, 100 host system (host), 130 system controller. DETAILED DESCRIPTION

[0032] Hereinafter, the embodiments will be described with reference to the drawings. Note that the drawings are examples and do not limit the scope of the invention.

[0033] (First embodiment)

[0034] Figure 1 It is a block diagram showing the structure of the magnetic disk device 1 according to the first embodiment.

[0035] The magnetic disk device 1 includes a head disk assembly (HDA) described later, a driver IC 20, a head amplifier integrated circuit (hereinafter referred to as a head amplifier IC or a pre-amplifier) ​​30, a volatile memory 70, a nonvolatile memory 80, a buffer memory (cache) 90, and a system controller 130 which is an integrated circuit of one chip. In addition, the magnetic disk device 1 is connected to a host system (hereinafter referred to as a host) 100.

[0036] The HAD includes a magnetic disk (hereinafter referred to as a disk) 10, a spindle motor (hereinafter referred to as an SPM) 12, an arm 13 carrying a head 15, and a voice coil motor (hereinafter referred to as a VCM) 14. The disk 10 is mounted on the SPM 12 and rotated by the drive of the SPM 12. The arm 13 and the VCM 14 constitute an actuator. The actuator controls the movement of the head 15 mounted on the arm 13 to a predetermined position of the disk 10 by the drive of the VCM 14. The disk 10 and the head 15 may be provided in more than two numbers.

[0037] The disk 10 allocates a user data area 10a that can be used by the user and a system area 10b for writing information required for system management to the area where data can be written. Hereinafter, the direction from the inner periphery to the outer periphery of the disk 10 or the direction from the outer periphery to the inner periphery of the disk 10 is referred to as the radial direction. In the radial direction, the direction from the inner periphery to the outer periphery is referred to as the outer direction (or the outer side), and the direction from the inner periphery to the outer periphery is referred to as the inner direction (or the inner side). The circumferential direction is equivalent to the direction along the circumference of the disk 10. The radial direction and the circumferential direction are orthogonal to each other. In addition, sometimes a predetermined position in the radial direction of the disk 10 is referred to as a radial position, and a predetermined position in the circumferential direction of the disk 10 is referred to as a circumferential position. Sometimes the radial position and the circumferential position are also referred to as positions together. The user data area 10a of the disk 10 can be divided into a plurality of areas. For example, in the radial direction, the user data area 10a can be divided into areas (hereinafter sometimes referred to as zones) containing a predetermined number of tracks. The zones can be divided into tracks in the radial direction.

[0038] In addition, a “track” refers to a recording area among a plurality of recording areas obtained by dividing the disk 10 in the radial direction, a recording area of ​​one circumference of a predetermined radial position of the disk 10, a predetermined recording area at a predetermined radial position of the disk 10, a recording area extended in the circumferential direction of the disk 10, a recording area corresponding to the path of the head 15 positioned at the predetermined radial position of the disk 10, the path of the head 15 positioned at the predetermined radial position of the disk 10, data written in a recording area among a plurality of recording areas obtained by dividing the disk 10 in the radial direction, data written in a recording area of ​​one circumference of a predetermined radial position of the disk 10, or data written in a recording area of ​​one circumference of a predetermined radial position of the disk 10. The term "data written" may be used to refer to data written in a predetermined recording area at a predetermined radial position of the disk 10, data written in a recording area extended in a circumferential direction of the disk 10, data written in a recording area corresponding to the path of the head 15 positioned at a predetermined radial position of the disk 10, data written along the path of the head 15 positioned at a predetermined radial position of the disk 10, data extended in a circumferential direction in the disk 10, data written in a predetermined track of the disk 10, one circle of data written in a predetermined track of the disk 10, a portion of data written in a predetermined track of the disk 10, or other various meanings. The term "sector" is used to refer to one of a plurality of recording areas obtained by dividing a predetermined track of the disk 10 in the circumferential direction, one of a plurality of recording areas obtained by dividing a recording area extending in the circumferential direction at a predetermined radial position of the disk 10, a predetermined recording area of ​​a predetermined track of the disk 10, a predetermined circumferential position of a predetermined track of the disk 10, a predetermined circumferential position (predetermined position) at a predetermined radial position of the disk 10, data written in one of a plurality of recording areas obtained by dividing a predetermined track of the disk 10 in the circumferential direction, data written in one of a plurality of recording areas obtained by dividing a recording area extending in the circumferential direction at a predetermined radial position of the disk 10, data written in a predetermined recording area of ​​a predetermined track of the disk 10, data written in a predetermined circumferential position of a predetermined track of the disk 10, data written in a predetermined circumferential position (predetermined position) at a predetermined radial position of the disk 10, data written in a predetermined sector, and other various meanings. The "radial width of a track" may also be referred to as "track width". “A path passing through the center position of the track width in a predetermined track” may be referred to as “track center.” Data that can be used by a user and written in the user data area 10 a may be referred to as user data.

[0039] The head 15 has a slider as a main body, and includes a write head 15W and a read head 15R mounted on the slider. The write head 15W writes data to the disk 10. The read head 15R reads the data recorded on the disk 10. In addition, sometimes the "write head 15W" is simply referred to as the "head 15", sometimes the "read head 15R" is simply referred to as the "head 15", and sometimes the "write head 15W and the read head 15R" are simply referred to as the "head 15". Sometimes the "center of the head 15" is referred to as the "head 15", the "center of the write head 15W" is referred to as the "write head 15W", and the "center of the read head 15R" is referred to as the "read head 15R". Sometimes the "center of the write head 15W" is simply referred to as the "head 15", and sometimes the "center of the read head 15R" is simply referred to as the "head 15". “Positioning the center of the head 15 at the center of the predetermined track” may be expressed as “positioning the head 15 at the predetermined track”, “arranging the head 15 at the predetermined track” or “locating the head 15 at the predetermined track”.

[0040] Figure 2 Schematic diagram showing an example of the disk 10 involved in this embodiment. Figure 2 As shown, in the circumferential direction, the direction in which the disk 10 rotates is referred to as the rotation direction. Figure 2 In the example shown, the direction of rotation is indicated by counterclockwise, but the opposite direction (clockwise) is also possible. Figure 2 In the embodiment, the disk 10 is divided into an inner peripheral region IR located inwardly, an outer peripheral region OR located in outwardly, and a middle peripheral region MR located between the inner peripheral region IR and the outer peripheral region OR.

[0041] exist Figure 2 In the example shown, the disc 10 includes a user data area 10a and a system area 10b. Figure 2 In the example, the user data area 10a and the system area 10b are adjacent in the radial direction. Here, "adjacent" includes data, objects, areas, and spaces that are arranged in contact, but also includes being arranged with a predetermined interval. Figure 2 In the embodiment, the system area 10b is adjacent to the user data area 10a in the outer direction of the user data area 10a. In addition, the system area 10b may be adjacent to the user data area 10a in the inner direction of the user data area 10a. In addition, the system area 10b may be arranged in the middle of the user data area 10a in the radial direction.

[0042] exist Figure 2In the example shown, the user data area 10a is arranged from the inner area IR to the outer area OR. The system area 10b is arranged in the outer area OR. In addition, the system area 10b may be arranged in the inner area IR or the middle area MR. The system area 10b may also be arranged in the outer area OR, the middle area MR or the inner area IR in a dispersed manner.

[0043] like Figure 2 As shown, the head 15 is driven by the VCM 14 to rotate about the rotation axis and move from the inner direction to the outer direction and be arranged at a predetermined position relative to the disk 10, or move from the outer direction to the inner direction and be arranged at a predetermined position.

[0044] The driver IC 20 controls the driving of the SPM 12 and the VCM 14 according to the control of the system controller 130 (specifically, the MPU 60 described later).

[0045] The head amplifier IC (preamplifier) ​​30 includes a read amplifier and a write driver. The read amplifier amplifies the read signal read from the disk 10 and outputs it to the system controller 130 (more specifically, the read / write (R / W) channel 40 described later). The write driver outputs a write current corresponding to the write data output from the R / W channel 40 to the head 15.

[0046] The volatile memory 70 is a semiconductor memory that loses the stored data when the power supply is disconnected. The volatile memory 70 stores data required for processing in each part of the magnetic disk device 1. The volatile memory 70 is, for example, a DRAM (Dynamic Random Access Memory) or an SDRAM (Synchronous Dynamic Random Access Memory).

[0047] The nonvolatile memory 80 is a semiconductor memory that records stored data even when power supply is turned off. The nonvolatile memory 80 is, for example, a NOR-type or NAND-type flash ROM (Flash Read Only Memory: FROM).

[0048] The buffer memory 90 is a semiconductor memory that temporarily records data transmitted and received between the magnetic disk device 1 and the host 100. In addition, the buffer memory 90 may be formed integrally with the volatile memory 70. The buffer memory 90 is, for example, a DRAM, an SRAM (Static Random Access Memory), an SDRAM, a FeRAM (Ferroelectric Random Access Memory), or an MRAM (Magnetoresistive Random Access Memory).

[0049] The system controller (controller) 130 is implemented, for example, using a large-scale integrated circuit (LSI) called a system-on-a-Chip (SoC) in which multiple components are integrated into a single chip. The system controller 130 includes a read / write (R / W) channel 40, a hard disk controller (HDC) 50, and a microprocessor (MPU) 60. The R / W channel 40, the HDC 50, and the MPU 60 are electrically connected to each other. The system controller 130 is electrically connected to, for example, a driver IC 20, a head amplifier IC 30, a volatile memory 70, a non-volatile memory 80, a buffer memory 90, and a host 100.

[0050] The R / W channel 40 performs signal processing of data transmitted from the disk 10 to the host 100, such as read data, and data transmitted from the host 100, such as write data, according to instructions from the MPU 60 described later. The R / W channel 40 has a circuit or function for measuring the signal quality of the read data. The R / W channel 40 is electrically connected to, for example, the head amplifier IC 30, the HDC 50, and the MPU 60.

[0051] The HDC 50 controls data transmission. For example, the HDC 50 controls data transmission between the host 100 and the R / W channel 40 according to instructions from the MPU 60 described later. The HDC 50 is electrically connected to the R / W channel 40, the MPU 60, the volatile memory 70, the nonvolatile memory 80, and the buffer memory 90, for example.

[0052] The MPU 60 is a main controller that controls each part of the magnetic disk device 1. The MPU 60 controls the VCM 14 via the driver IC 20 and performs servo control for positioning the head 15. The MPU 60 controls the SPM 12 via the driver IC 20 to rotate the disk 10. The MPU 60 controls the write operation of writing data to the disk 10 and selects the storage destination of data transmitted from the host 100, such as write data. The MPU 60 controls the read operation of reading data from the disk 10 and controls the processing of data transmitted from the disk 10 to the host 100, such as read data. In addition, the MPU 60 manages the area for recording data. The MPU 60 is connected to each part of the magnetic disk device 1. The MPU 60 is electrically connected to, for example, the driver IC 20, the R / W channel 40, and the HDC 50.

[0053] The MPU 60 controls the read process of reading data from the disk 10 and the write process of writing data to the disk 10 according to the command from the host 100. The MPU 60 controls the VCM 14 via the driver IC 20 to position the head 15 at a predetermined position of the disk 10 and perform the read process or the write process. Hereinafter, the term "access" may also be used to include recording or writing data to a predetermined area (or writing process), reading or reading data from a predetermined area (or reading process), and moving the head 15 to a predetermined area.

[0054] The MPU 60 performs positioning control of the radial position of the head 15 through the actuator so that the head 15 tracks the target track (hereinafter sometimes referred to as the target track) of the disk 10. Hereinafter, the system that performs this positioning control may also be referred to as a positioning control system.

[0055] The MPU 60 has a positioning control system. For example, the MPU 60 has the following positioning control system: when the base of the magnetic disk device 1 equipped with the actuator and the disk 10 is subjected to disturbances such as vibration and impact from the outside of the magnetic disk device 1, the MPU 60 detects a position error signal corresponding to the error of the position target track of the head 15, and forms a feedback loop to make the detected position error signal zero.

[0056] The MPU 60 has a filter that suppresses the frequency of a PES (position error signal) that is generated by interference. For example, the MPU 60 has a filter that suppresses (suppresses or compensates) the fundamental frequency (estimated value) of the PES and the higher harmonics (hereinafter sometimes referred to as harmonics) of the fundamental frequency (estimated value) of the PES, and can change (make the number of delayed samplings variable) the number of delayed samplings of the repetitive control system according to the fundamental frequency (estimated value) of the PES generated in the positioning control corresponding to the harmonic interference generated by the rotation of the system FAN, and the servo sampling (sampling) frequency, wherein the PES is generated in the positioning control corresponding to the following interference (hereinafter sometimes referred to as harmonic interference), which has harmonics generated by the vibration sound of the bearing generated from the system FAN that cools many, for example, tens to hundreds of magnetic disk devices mounted in the large-scale storage system, the vibration and impact caused by the sound pressure of the wind noise, etc., are applied to the base, etc. The repetitive control system sequentially outputs an internal model of a signal that repeats periodically. The internal model is updated, for example, by the sum of the output one cycle ago (or currently) and the latest input value. The internal model includes, for example, a fundamental component of the fundamental frequency of the PES generated in the positioning control corresponding to harmonic interference and a harmonic component of the fundamental frequency.

[0057] Hereinafter, "suppressing the fundamental frequency (estimated value) of PES generated in positioning control corresponding to harmonic interference and higher harmonics of the fundamental frequency (estimated value)" is sometimes referred to as "compensating for harmonic interference". "Suppressing the higher harmonics of the fundamental frequency (estimated value) of PES generated in positioning control corresponding to harmonic interference" is sometimes referred to as "compensating for harmonic interference".

[0058] Sometimes, "(the estimated value) of the fundamental frequency of PES generated in positioning control corresponding to harmonic interference" is also referred to as "(the estimated value) of the fundamental frequency corresponding to harmonic interference". Sometimes, "(the estimated value) of the higher harmonics of (the estimated value) of the fundamental frequency of PES generated in positioning control corresponding to harmonic interference" is also referred to as "(the estimated value) of the higher harmonics of (the estimated value) of (the estimated value) of the fundamental frequency corresponding to harmonic interference".

[0059] In addition, “suppressing the fundamental frequency (estimated value) of PES generated in positioning control corresponding to harmonic interference and higher harmonics of the fundamental frequency (estimated value)” is sometimes referred to as “suppressing the fundamental frequency (estimated value) corresponding to harmonic interference”. “Suppressing the fundamental frequency (estimated value) of PES generated in positioning control corresponding to harmonic interference and higher harmonics of the fundamental frequency (estimated value)” is sometimes referred to as “suppressing the higher harmonics of the fundamental frequency (estimated value) corresponding to harmonic interference”.

[0060] The MPU 60 estimates the harmonic interference (the corresponding fundamental frequency) and detects the harmonic interference when compensation of the harmonic interference is not performed. When it is determined that the harmonic interference is detected, the fundamental frequency corresponding to the detected harmonic interference is determined, and the number of delayed sampling is determined based on the fundamental frequency corresponding to the harmonic interference. The MPU 60 clears the sampling value stored (or recorded) in the recording area of ​​the repetitive controller, for example, sets it to 0 (zero), and starts the output of the sampling value corresponding to the number of delayed sampling (hereinafter sometimes also referred to as the delayed sampling value) from the repetitive controller. The MPU 60 updates the sampling value stored (or recorded) in the recording area of ​​the repetitive controller.

[0061] When the number of delayed samples has been determined and compensation of harmonic interference is being executed, the MPU 60 outputs delayed sample values ​​from the iterative controller and updates the sample values ​​stored (or recorded) in the recording area of ​​the iterative controller.

[0062] In addition, when the number of delayed samplings has been determined and compensation for harmonic interference is being performed, MPU60 determines whether the harmonic interference being compensated has changed. When it is determined that the harmonic interference being compensated has changed, MPU60 estimates the harmonic interference after the change (the corresponding fundamental frequency), compares the fundamental frequency corresponding to the estimated harmonic interference with the fundamental frequency corresponding to the harmonic interference in the current compensation, and determines whether the fundamental frequency corresponding to the changed harmonic interference has changed. When it is determined that the fundamental frequency has changed, MPU60 estimates the harmonic interference (the corresponding fundamental frequency) again, determines the fundamental frequency corresponding to the changed harmonic interference again, and determines the number of delayed sampling again based on the fundamental frequency corresponding to the harmonic interference that has been determined again.

[0063] Figure 3 1 is a block diagram showing an example of the positioning control system SY of the head 15 during access processing according to the present embodiment.

[0064] The magnetic disk device 1 has a positioning control system SY of the head 15 during access processing. The positioning control system SY has a converter A0, a controller A1, an actuator A2, a repetitive control system RC, and operators CL0 and CL1. The repetitive control system RC has a variable delay memory unit A3 and an operator CL2. The converter A0, the controller A1, the actuator A2, the repetitive control system RC, the operator CL0 and the operator CL1 are included in, for example, a system controller 130, a driver IC 20, a head amplifier IC 30, a disk 10, a volatile memory 70, a non-volatile memory 80, and a buffer memory 90. The actuator A2 is composed of, for example, an arm 13 and a VCM 14. The positioning control system SY constitutes a feedback system. The actuator A2 can use a plurality of actuators having more than two degrees of freedom, or a plurality of controllers corresponding to each actuator.

[0065] exist Figure 3 In the embodiment, a sector (C, H, S) as an object where the head 15 is configured in a predetermined track (cylinder) of the disk 10 (hereinafter sometimes referred to as an object sector), a position error signal (or PES) e0 corresponding to the difference between the target radial position (hereinafter sometimes referred to as the target radial position) r of the head 15 and the actual position (hereinafter sometimes referred to as the actual position) Y of the head 15, a repetition control signal (hereinafter sometimes referred to as a delay memory output signal) e1 corresponding to the internal state z ^(-L) × e2 after being delayed by the delay sampling number L, and the position error signal e The repetitive control signal (hereinafter sometimes referred to as the delay memory input signal or the internal state signal) e2 obtained by adding the position error signal e0 and the delay memory output signal e1, the position error signal e obtained by adding the position error signal e0 and the delay memory output signal e1, the driving amount U of the actuator A2 in the target sector, and the actual position Y of the head 15 are processed as signals (or information) in the positioning control system SY, respectively. The delayed sampling number L is equivalent to the ratio of the servo sampling frequency fs to the (estimated value) of the fundamental frequency f1 of the estimated harmonic interference. The delayed sampling number L is an integer value corresponding to the ratio of the servo sampling frequency fs to the (estimated value) of the fundamental frequency f1. The delayed sampling number L is calculated as a round value by rounding off the ratio of the servo sampling frequency fs to the (estimated value) of the fundamental frequency f1. The delayed sampling number L can be calculated as a rounded value by rounding off the ratio of the servo sampling frequency fs to the (estimated value) of the fundamental frequency f1, or can be calculated as a rounded value by rounding off the ratio of the servo sampling frequency fs to the (estimated value) of the fundamental frequency f1.

[0066] The converter A0 converts a physical position (hereinafter referred to as a physical position) corresponding to a logical position (hereinafter referred to as a logical position) of the disk 10 specified by a host device, such as the host 100, into a radial position (target radial position) of the disk 10. The logical position may be, for example, a logical block address (LBA). The physical position may be, for example, a servo information array indicating the physical position of the disk 10. For example, when the converter A0 receives an access command to the target sector (C, H, S) from the host 100 or the like, it converts the target sector (C, H, S) into a target radial position r of the head 15. The converter A0 is connected to the operator CL0. The operator CL0 is connected to the repetitive control system RC, such as the operator CL2 and the operator CL1.

[0067] The controller A1 controls the actuator A2. The controller A1 generates a driving amount U of the head 15 of the actuator A2 based on, for example, the position error signal e. The controller A1 is connected to the calculation unit CL1 and the actuator A2.

[0068] The actuator A2 is driven based on the output of the controller A1. The actuator A2 is driven based on, for example, the driving amount U to move the head 15 to the actual position Y. The actuator A2 is connected to the controller A1 and the computing unit CL0.

[0069] The repetitive control system RC sequentially outputs an internal model of a periodically repeated signal. The repetitive control system RC stores a delay memory input signal e2 obtained by adding the delay memory output signal e1 to the position error signal e0. The repetitive control system RC obtains the delay memory output signal e1 based on the delay sampling number L and the delay memory input signal e2, where the delay sampling number L is calculated by rounding off the ratio of the fundamental frequency f1 (estimated value) corresponding to the estimated harmonic interference and the servo sampling frequency fs. The repetitive control system RC outputs the obtained delay memory output signal e1. The operator CL2 is connected to the operator CL0 and the variable delay memory unit A3. The variable delay memory unit A3 is connected to the operator CL2 and the operator CL1. The operator CL1 is connected to the variable delay memory unit A3, the operator CL0, and the controller A1.

[0070] When the logical position of the disk 10 to be accessed, such as LBA, is specified by the host device, such as the host 100, the positioning control system SY converts the LBA into a physical position (C, H, S) in advance, and outputs the radial position (C, H, S) of the head 15 to the converter A0. The converter A0 receives the physical position (C, H, S) of the head 15. The converter A0 converts the physical position (C, H, S) of the head 15 into a target radial position r of the head 15. The converter A0 outputs the target radial position r of the head 15 to the operator CL0. The operator CL0 receives the target radial position r of the head 15 and the actual position Y of the head 15. The operator CL0 calculates a position error signal e0 corresponding to the difference between the target radial position r of the head 15 and the actual position Y of the head 15. The operator CL0 outputs the position error signal e0 to the repetitive control system RC and the operator CL1. In other words, the operator CL0 outputs the position error signal e0 to the operator CL2 and the operator CL1.

[0071] The position error signal e0 and the delay memory output signal e1 are input to the operator CL2. The operator CL2 calculates a delay memory input signal e2 obtained by adding the position error signal e0 and the delay memory output signal e1. The operator CL2 outputs the delay memory input signal e2 to the variable delay memory unit A3.

[0072] The variable delay memory unit A3 receives the delay sampling number L and the delay memory input signal e2. The variable delay memory unit A3 obtains the delay memory output signal e1 based on the delay sampling number L and the delay memory input signal e2. The variable delay memory unit A3 outputs the delay memory output signal e1 to the operators CL1 and CL2.

[0073] The position error signal e0 and the delay memory output signal e1 are input to the calculation unit CL1. The calculation unit CL1 calculates the position error signal e obtained by adding the position error signal e0 and the delay memory output signal e1. The calculation unit CL1 outputs the position error signal e to the controller A1.

[0074] The position error signal e is input to the controller A1. The controller A1 generates a drive amount U based on the position error signal e. The controller A1 outputs the drive amount U to the actuator A2.

[0075] The actuator A2 receives the drive amount U. The actuator A2 is driven according to the drive amount U, and moves the head 15 to the actual position Y corresponding to the drive amount U. The actuator A2 outputs the actual position Y to the operator CL0.

[0076] Figure 4 Yes means Figure 3 FIG. 1 is a block diagram of an example of a variable delay memory unit A3 of a repetitive control system RC. Figure 4 The variable delay memory cell A3 is shown with Figure 3 The variable delay memory unit A3 shown corresponds.

[0077] The variable delay memory unit A3 has a plurality of delay memories DM(k-1), DM(k-2), DM(k-3), ..., DM(kL), ..., DM(kN), and a delay selector SW. Hereinafter, the plurality of delay memories DM(k-1) to DM(kN) are sometimes referred to as memory units. k is equivalent to, for example, the total number of samples so far. L is equivalent to the number of delayed samples. N is equivalent to the upper limit of the number of samples that can be stored (or recorded) in the memory unit. N is, for example, greater than L (N>L).

[0078] The memory units DM(k-1) to DM(kN) store (or record) sampling values ​​corresponding to the input signals of the delay memories. For example, the plurality of delay memories DM(k-1) to DM(kN) respectively store (or record) the sampling values ​​of the previous sampling of the input signals. The plurality of delay memories DM(k-1) to DM(kN) are respectively connected to the previous delay memories. For example, the delay memory DM(k-1) is connected to DM(k-2), the delay memory DM(k-2) is connected to DM(k-3), ..., the delay memory DM(kL) is connected to DM(k-(L+1)), and the delay memory DM(k-(N-1)) is connected to DM(kN). The memory units DM(k-1) to DM(kN) are connected to the delay selector SW. The plurality of delay memories DM(k-1) to DM(kN) are respectively connected to the plurality of input terminals I1 to IN of the delay selector SW. For example, the memory units DM(k-1) to DM(kN) set an upper limit value N of the number of samples that can be stored (or recorded). For example, the memory units DM(k-1) to DM(kN) sequentially store the sample values ​​(hereinafter sometimes referred to as past sample values ​​or past memory values) e2[k-1], e2[k-2], ..., e2[kN] before (or in the past) of the delay memory input signal e2[k] of the kth sample. For example, the delay memory DM(k-1) receives the delay memory input signal e2[k] of the kth sample as input, and stores (or records) the delay memory input signal e2[k] as the past sample value before the kth sample. At this time, the delay memory DM(k-2) receives the delay memory input signal e2[k-1] of the k-1th sample from the delay memory DM(k-1), and stores (or records) the past sample value e2[k-1] of the k-1th sample as the past sample value e2[k-2] of the k-2th sample. Similar to delay memories DM(k-1) and DM(k-2), multiple delay memories DM(k-3) to DM(kN) are respectively input with the past sampling value of the previous sample from the previous delay memory, and sequentially update and save (or record) the input past sampling value as a new past sampling value.

[0079] The delay selector SW selects a predetermined past sample value from the past sample values ​​e2[k-1] to e2[kN] respectively recorded in the memory units DM(k-1) to DM(kN). The delay selector SW outputs the selected predetermined past sample value. For example, the delay selector SW selects a delayed sample value e2[kL] corresponding to the past sample value corresponding to the delayed sample number L from the past sample values ​​e2[k-1] to e2[kN] respectively recorded in the memory units DM(k-1) to DM(kN), according to the delayed sample number L input to the terminal V. For example, the delay selector SW outputs the delayed sample value (delay memory output signal) e1=e2[kL] via the output terminal O.

[0080] Figure 5 1 is a block diagram showing an example of the positioning control system SY of the head 15 during access processing according to the present embodiment. Figure 5 The positioning control system SY shown is Figure 3 The positioning control system SY shown is substantially the same, but has a low-pass filter A4. Figure 3 The positioning control systems shown are different. Figure 5 In, with Figure 3 The same parts of the positioning control system SY are given the same reference numerals, and their detailed description is omitted.

[0081] The repetitive control system RC includes a variable delay memory unit A3, a low-pass filter A4, and an operator CL2.

[0082] exist Figure 5 In the positioning control system SY, the delay memory input signal e3 (hereinafter sometimes referred to as the cutoff delay memory input signal) obtained by cutting off the signal (or waveform) of the cutoff frequency fc corresponding to the delayed sampling number L from the delay memory input signal e2 by the low-pass filter A4, and the delay memory output signal e1 equivalent to the internal state z^(-L)×e3 after being delayed by the delayed sampling number L are processed as signals (or information).

[0083] The repetitive control system RC stores (or records) a cut-off delay memory input signal e3 obtained by cutting off a signal (or waveform) of a cut-off frequency fc corresponding to the number of delayed samples L from the delay memory input signal e2 through the low-pass filter A4, and obtains a delay memory output signal e1 based on the cut-off delay memory input signal e3. The repetitive control system RC outputs the obtained delay memory output signal e1. The operator CL2 is connected to the operator CL0 and the low-pass filter A4. The variable delay memory unit A3 is connected to the low-pass filter A4 and the operator CL1. The low-pass filter A4 is connected to the operator CL2 and the variable delay memory unit A3.

[0084] In the positioning control system SY, the position error signal e0 and the delay memory output signal e1 are input to the operator CL2. The operator CL2 calculates the delay memory input signal e2 obtained by adding the position error signal e0 and the delay memory output signal e1. The operator CL2 outputs the delay memory input signal e2 to the low pass filter A4.

[0085] The low-pass filter A4 is input with the delay sampling number L and the delay memory input signal e2. The low-pass filter A4 sets the cut-off frequency fc according to the delay sampling number L, and generates a cut-off delay memory input signal e3 obtained by cutting off the signal (or waveform) of the cut-off frequency fc of the delay memory input signal e2. In addition, the low-pass filter A4 can also set the cut-off frequency fc according to the base frequency f1 (the estimated value), and generate a cut-off delay memory input signal e3 obtained by cutting off the signal (or waveform) of the cut-off frequency fc of the delay memory input signal e2. In addition, the cut-off frequency fc of the low-pass filter A4 can also be set to a fixed value that does not depend on the input delay sampling number L. The low-pass filter A4 outputs the cut-off delay memory input signal e3 to the variable delay memory unit A3. Thereby, it is possible to prevent the repetitive control system RC from becoming unstable due to higher harmonics.

[0086] The variable delay memory unit A3 receives the delay sampling number L and the delay memory input signal e2. The variable delay memory unit A3 obtains the delay memory output signal e1 based on the delay sampling number L and the delay memory input signal e2. The variable delay memory unit A3 outputs the delay memory output signal e1 to the operators CL1 and CL2.

[0087] Figure 6 1 is a block diagram showing an example of the positioning control system SY of the head 15 during access processing according to the present embodiment. Figure 6 The positioning control system SY shown is Figure 5 The positioning control system SY shown is substantially the same, but has a phase compensator A5. Figure 5 The positioning control system SY shown is different. Figure 6 In, with Figure 5 The same parts of the positioning control system SY are given the same reference numerals, and their detailed description is omitted.

[0088] The positioning control system SY includes a converter A0, a controller A1, an actuator A2, a repetitive control system RC, a phase compensator A5, and operators CL0 and CL1. The repetitive control system RC includes a variable delay memory unit A3, a low-pass filter A4, and an operator CL2. The converter A0, the controller A1, the actuator A2, the repetitive control system RC, the phase compensator A5, the operator CL0, and the operator CL1 are included in, for example, a system controller 130, a driver IC 20, a head amplifier IC 30, a disk 10, a volatile memory 70, a nonvolatile memory 80, and a buffer memory 90.

[0089] exist Figure 6 In the positioning control system SY, the cutoff delay memory input signal e4 obtained by cutting off the signal (or waveform) of the cutoff frequency fc from the delay memory input signal e2 by the low-pass filter A4, the delay memory output signal e1 equivalent to the internal state z^(-L)×e4 after being delayed by the delay sampling number L, and the output signal e5 (hereinafter sometimes also referred to as the phase compensated output signal) obtained by performing phase compensation on the delay memory output signal e1 are processed as signals (or information).

[0090] The repetitive control system RC holds the cut-off delay memory input signal e4 obtained by cutting off the signal (or waveform) of the cut-off frequency fc from the delay memory input signal e2 through the low-pass filter A4, and obtains the delay memory output signal e1 based on the cut-off delay memory input signal e4. The repetitive control system RC outputs the obtained delay memory output signal e1. The operator CL2 is connected to the operator CL0 and the low-pass filter A4. The variable delay memory unit A3 is connected to the low-pass filter A4 and the phase compensator A5. The operator CL1 is connected to the phase compensator A5, the operator CL0 and the controller A1.

[0091] The phase compensator A5 performs phase compensation. For example, the phase compensator A5 can compensate for the phase delay amount having closed-loop characteristics of the positioning control system SY. The phase compensator A5 performs phase compensation by outputting a phase compensation output signal e5 corresponding to a sampling value after (in the future) d sampling numbers corresponding to the delayed sampling number L with respect to the past sampling value recorded in the variable delay memory unit A3, for example, the delay memory output signal e1. In addition, the phase characteristic of the phase compensator A5 can also be changed according to the phase characteristic of the low-pass filter A4. The phase compensator A5 is connected to the variable delay memory unit A3 and the operator CL1.

[0092] In the positioning control system SY, the position error signal e0 and the delay memory output signal e1 are input to the operator CL2. The operator CL2 calculates the delay memory input signal e2 obtained by adding the position error signal e0 and the delay memory output signal e1. The operator CL2 outputs the delay memory input signal e2 to the low-pass filter A4.

[0093] The delay memory input signal e2 is input to the low-pass filter A4. The low-pass filter A4 sets a cutoff frequency fc and generates a cutoff delay memory input signal e4 obtained by cutting off the signal (or waveform) of the cutoff frequency fc of the delay memory input signal e2. The low-pass filter A4 outputs the cutoff delay memory input signal e4 to the variable delay memory unit A3.

[0094] The variable delay memory unit A3 receives the delay sampling number L and the off-delay memory input signal e4. The variable delay memory unit A3 obtains the delay memory output signal e1 based on the delay sampling number L and the off-delay memory input signal e4. The variable delay memory unit A3 outputs the delay memory output signal e1 to the operator CL2 and the phase compensator A5.

[0095] The phase compensator A5 receives the delayed sampling number L and the delay memory output signal e1 as inputs. The phase compensator A5 obtains the phase-compensated output signal e5 based on the delayed sampling number L and the delay memory output signal e1. The phase compensator A5 outputs the phase-compensated output signal e5 to the operator CL1.

[0096] The position error signal e0 and the phase compensation output signal e5 are input to the calculation unit CL1. The calculation unit CL1 calculates the position error signal e obtained by adding the position error signal e0 and the phase compensation output signal e5. The calculation unit CL1 outputs the position error signal e to the controller A1.

[0097] Figure 7 1 is a block diagram showing an example of the positioning control system SY of the head 15 during access processing according to the present embodiment. Figure 7 The positioning control system SY shown is Figure 6 The positioning control system SY shown corresponds to the following. Figure 7 In, with Figure 6 The same parts of the positioning control system SY are given the same reference numerals, and their detailed description is omitted.

[0098] The positioning control system SY includes a converter A0, a controller A1, an actuator A2, a repetitive control system RC, and operators CL0 and CL1. The repetitive control system RC includes a variable delay memory unit A6, a low-pass filter A4, and an operator CL2. The converter A0, the controller A1, the actuator A2, the repetitive control system RC, the operator CL0, and the operator CL1 are included in, for example, a system controller 130, a driver IC 20, a head amplifier IC 30, a disk 10, a volatile memory 70, a nonvolatile memory 80, and a buffer memory 90.

[0099] The operator CL2 is connected to the operator CL0, the low-pass filter A4, and the variable memory unit A6. The low-pass filter A4 is connected to the operator CL2 and the variable delay memory unit A6.

[0100] The variable delay memory unit A6 is equivalent to a memory unit in which the functions of the variable delay memory unit A3 and the phase compensator A5 are integrated. The low-pass filter A4 is connected to the operator CL2 and the variable delay memory unit A6. The variable delay memory unit A6 is connected to the low-pass filter A4, the operator CL1, and the operator CL2.

[0101] The low-pass filter A4 outputs the off-delay memory input signal e4 to the variable delay memory unit A6.

[0102] The variable delay memory unit A6 receives the delay sampling number L and the off-delay memory input signal e4. The variable delay memory unit A6 obtains the delay memory output signal e1 and the phase compensation output signal e5 based on the delay sampling number L and the off-delay memory input signal e4. The variable delay memory unit A6 outputs the delay memory output signal e1 to the operator CL2 and outputs the phase compensation output signal e5 to the operator CL1.

[0103] Figure 8 Yes means Figure 7 FIG. 1 is a block diagram of an example of a variable delay memory unit A6 of a repetitive control system RC. Figure 8 The variable delay memory cell A6 is shown with Figure 7 The variable delay memory unit A6 shown corresponds.

[0104] The variable delay memory unit A6 has memory cells DM(k-1), DM(k-2), DM(k-3), ..., DM(k-L+d), ..., DM(kL), ..., DM(kN) and a delay selector SW.

[0105] For example, the memory units DM(k-1) to DM(kN) sequentially store past sample values ​​(hereinafter sometimes referred to as cut-off past sample values ​​or cut-off past memory values) e4[k-1], e4[k-2], ..., e4[k-L+d], ..., e4[kL], ..., e2[kN] before (or in the past) the cut-off delay memory input signal e4[k] of the kth sample. For example, the delay memory DM(k-1) receives the cut-off delay memory input signal e4[k] of the kth sample, and stores (or records) the cut-off delay memory input signal e4[k] as the cut-off past sample value before the kth sample. At this time, the delay memory DM(k-2) receives the cut-off delay memory input signal e4[k-1] of the k-1th sample from the delay memory DM(k-1), and stores (or records) the cut-off past sample value e2[k-1] of the k-1th sample as the cut-off past sample value e2[k-2] of the k-2th sample. Similar to delay memories DM(k-1) and DM(k-2), multiple delay memories DM(k-3) to DM(kN) are respectively input with the cutoff past sampling value of the previous sample from the previous delay memory, and sequentially update and save (or record) the input cutoff past sampling value as a new cutoff past sampling value.

[0106] The delay selector SW selects a predetermined cut-off past sample value from the cut-off past sample values ​​e4[k-1] to e2[kN] recorded in the memory units DM(k-1) to DM(kN), respectively. The delay selector SW outputs the selected predetermined cut-off past sample value. For example, the delay selector SW selects the delay memory output signal e1=e4[kL] corresponding to the cut-off past sample value corresponding to the delay sample number L from the cut-off past sample values ​​e2[k-1] to e2[kN] recorded in the memory units DM(k-1) to DM(kN), respectively, according to the delay sample number L input to the terminal V. For example, the delay selector SW obtains a phase compensation output signal e5=e4[k-L+d] corresponding to a sample value after (in the future) d samples corresponding to the delay sample number L with respect to the selected delay memory output signal e1. For example, the delay selector SW outputs the off-delay sampled value (phase compensation output signal) e5=e4[k-L+d] via the output terminal Q simultaneously with the output of the off-delay sampled value (delay memory output signal) e1=e4[kL] via the output terminal O.

[0107] Fig. 9 It means Figure 6 An example of the input-output characteristic e5 / e0 of the corresponding repetitive control system RC is shown in FIG. Fig. 9 In, the servo sampling frequency fs = 62.4kHz. Fig. 9In the above figure, the horizontal axis represents frequency (Freq.Hz) and the vertical axis represents gain (Gain dB). Fig. 9 The above figure shows the change IOGL1 of the gain of the input-output characteristic e5 / e0 relative to the frequency of the repetitive control system RC when the fundamental frequency (estimated value) f1=367Hz (delayed sampling number L=170) corresponding to the harmonic interference generated by the rotation of the FAN, and the change IOGL2 of the gain of the input-output characteristic e5 / e0 relative to the frequency of the repetitive control system RC when the fundamental frequency (estimated value) f1=472Hz (delayed sampling number L=132) corresponding to the harmonic interference generated by the rotation of the FAN. Fig. 9 In the above figure, the change in gain IOGL1 is represented by a solid line, and the change in gain IOGL2 is represented by a dotted line. Fig. 9 In the following figure, the horizontal axis represents frequency (Freq.Hz) and the vertical axis represents phase (Phase). Fig. 9 The following figure shows the change in phase IOPL1 of the input-output characteristic e5 / e0 relative to the frequency of the repetitive control system RC when the fundamental frequency (estimated value) f1=367Hz (delayed sampling number L=170) corresponding to the harmonic interference generated by the rotation of the FAN, and the change in phase IOPL2 of the input-output characteristic e5 / e0 relative to the frequency of the repetitive control system RC when the fundamental frequency (estimated value) f1=472Hz (delayed sampling number L=132) corresponding to the harmonic interference generated by the rotation of the FAN. Fig. 9 In the following figure, the change in phase IOPL1 is represented by a solid line, and the change in phase IOPL2 is represented by a dotted line.

[0108] exist Fig. 9 In the example shown, when the servo sampling frequency fs=62.4kHz and the estimated value of the fundamental frequency f1=367Hz, the delayed sampling number L=62400 / 367=170, and therefore the repetitive control system RC operates with the delayed sampling number 170. Fig. 9 As indicated by the solid lines IOGL1 and IOPL1 (f1=367 Hz) in FIG. 1 , the repetitive control system RC also extracts the harmonics of the estimated value f1=367 Hz of the fundamental frequency at the same time.

[0109] exist Fig. 9 In the example shown, when the servo sampling frequency fs=62.4kHz and the estimated value of the fundamental frequency f1=472Hz, the delayed sampling number L=62400 / 472=132, and therefore the repetitive control system RC operates with the delayed sampling number 132. Fig. 9As indicated by the dotted lines IOGL2 and IOPL2 (f1=472 Hz) in FIG. 1 , the repetitive control system RC also extracts the harmonic multiples of the estimated value f1=472 Hz of the fundamental frequency.

[0110] From the above, it can be seen that the input-output characteristic of the repetitive control system RC corresponds to a harmonic filter of the estimated value f1 of the fundamental frequency. Fig.10 1 is a diagram showing an example of changes in the sensitivity characteristics of the filter HFL1 for harmonics of the estimated value f1 of the fundamental frequency of the harmonic interference and the positioning control system SY. Fig.10 The above picture and Fig. 9 The above figure corresponds to. Fig.10 In the above figure, the horizontal axis represents frequency (Hz) and the vertical axis represents gain (dB). Fig.10 The above figure shows the change in gain relative to frequency of the input-output characteristic e5 / e0 of the repetitive control system RC corresponding to the harmonic interference corresponding to the base frequency (estimated value) f1 = 472Hz (hereinafter sometimes referred to as the harmonic filter) HFL1. The harmonic filter HFL1 corresponds to the change in gain IOGL2, for example. Fig.10 In the following figure, the horizontal axis represents frequency (Hz), and the vertical axis represents the sensitivity characteristics of the positioning control system SY (hereinafter sometimes referred to as sensitivity characteristics). Fig.10 The following figure shows a repetitive control system RC to which this embodiment is not applied, for example Figure 6 The sensitivity characteristic SCL1 of the repetitive control system RC shown in FIG. 1 is changed with respect to the frequency, and the repetitive control system RC of this embodiment is applied with the fundamental frequency f1=472 Hz corresponding to the harmonic interference generated by the rotation of the FAN. Figure 6 The sensitivity characteristics of the repetitive control system RC with respect to the frequency change SCL2 are shown. Fig.10 In the figure below, the change SCL1 of the sensitivity characteristic is represented by a single-dot chain line, and the change SCL2 of the sensitivity characteristic is represented by a double-dot chain line.

[0111] exist Fig.10 In the example shown, the suppression sensitivity of the positioning control system SY increases at a frequency that is a multiple of the fundamental frequency (estimated value) f1 = 472 Hz.

[0112] Fig.11 1 is a diagram showing an example of a spectrum of a PES in an environment with harmonic interference and a cumulative sum of squares of the spectrum of the PES. Fig.11 For example, with Fig.10 Corresponding. Fig.11In the above figure, the horizontal axis represents frequency (Hz), and the vertical axis represents PES (dBum (4.0Hz)) of the rotational asynchronous component (NRPE: Non-Repeatable Positioning Error) in an environment with harmonic interference. Fig.11 The above figure shows a repetitive control system RC to which this embodiment is not applied, for example Figure 6 The repetitive control system RC shown in the figure shows the change NSL1 of the PES of the rotational asynchronous component in an environment with harmonic interference, and the repetitive control system RC of this embodiment is applied with the fundamental frequency f1=472Hz corresponding to the harmonic interference generated by the rotation of the FAN, for example Figure 6 The PES of the rotating non-synchronous component in the case of the repetitive control system RC with harmonic interference relative to the frequency change NSL2 is shown. Fig.11 In the above figure, the change NSL1 of the PES of the rotating asynchronous component in the environment with harmonic interference is represented by a solid line, and the change NSL2 of the PES of the rotating asynchronous component in the environment with harmonic interference is represented by a dotted line. Fig.11 In the figure below, the horizontal axis represents frequency (Hz), and the vertical axis represents the cumulative 3σ (3 times the standard deviation) value (nm) of the rotational asynchronous component in an environment with harmonic interference. Fig.11 The following figure shows a repetitive control system RC to which this embodiment is not applied, for example Figure 6 The cumulative 3σ value of the rotational asynchronous component in an environment with harmonic interference in the case of the repetitive control system RC shown in FIG. 1 is a change N3σL1 relative to the frequency, and the repetitive control system RC of this embodiment is applied with the fundamental frequency f1=472 corresponding to the harmonic interference generated by the rotation of the FAN, for example Figure 6 The cumulative 3σ value of the rotational non-synchronous component in an environment with harmonic interference in the case of the repetitive control system RC shown relative to the change in frequency N3σL2. Fig.11 In the figure below, the change in the cumulative 3σ value of the rotating asynchronous component in an environment with harmonic interference relative to the frequency N3σL1 is represented by the solid line, and the change in the cumulative 3σ value of the rotating asynchronous component in an environment with harmonic interference relative to the frequency N3σL2 is represented by the dotted line.

[0113] like Fig.11 As shown in the change of PES of the rotational asynchronous component NSL1, in an environment with harmonic interference, when the repetitive control system RC of this embodiment is not applied, since harmonic interference is applied to the base station, etc., PES deteriorates at the multiple frequency of the estimated value f1=472Hz of the fundamental frequency corresponding to the harmonic interference. Fig.11As shown in the change N3σL1 of the cumulative 3σ value of the rotational asynchronous component, in an environment with harmonic interference, when the repetitive control system RC of this embodiment is applied, the cumulative 3σ value becomes 6.63 nm.

[0114] like Fig.11 As shown in the change of PES of the rotational asynchronous component NSL2, in an environment with harmonic interference, when the repetitive control system RC of this embodiment is applied, PES is suppressed (repressed or compensated) at the 1st, 2nd, 3rd, 4th and 5th times of the estimated value of the fundamental frequency of the interference f1=472Hz. Fig.11 As shown in the change N3σL2 of the cumulative 3σ value of the rotational asynchronous component, in an environment with harmonic interference, when the repetitive control system RC of this embodiment is applied, the 3σ value becomes 6.02nm. That is, in an environment with harmonic interference, the cumulative 3σ value when the repetitive control system RC of this embodiment is applied is greatly improved compared with the cumulative 3σ value when the repetitive control system RC of this embodiment is not applied.

[0115] Fig.12 This is the case when the low-pass filter A4 is not applied. Fig.10 FIG. 1 is a diagram showing an example of changes in the sensitivity characteristics of the harmonic filter HFL1 and the positioning control system SY. Fig.12 and Fig.10 Corresponding. Fig.12 In the above figure, the horizontal axis represents frequency (Hz) and the vertical axis represents gain (dB). Fig.12 The above figure shows that the low pass filter A4 is not applied. Fig.10 The high harmonic filter HFL1 is shown. Fig.12 In the figure below, the horizontal axis represents frequency (Hz) and the vertical axis represents the sensitivity characteristics of the positioning control system SY. Fig.12 The following figure shows the low pass filter A4 and Figure 6 The repetitive control system RC shown Fig.10 The sensitivity characteristics shown in FIG. 1 are the changes in the frequency SCL1 and the low-pass filter A4 is not applied and the Figure 6 The repetitive control system RC shown Fig.10 The sensitivity characteristics shown are SCL2 with respect to the frequency variation. Fig.12 In the figure below, the change SCL1 of the sensitivity characteristic is represented by a single-dot chain line, and the change SCL2 of the sensitivity characteristic is represented by a double-dot chain line.

[0116] and Fig.10 The sensitivity characteristics shown are changed as compared to SCL2. Fig.12 The sensitivity characteristic SCL2 shown in the figure changes greatly. Fig.10 The sensitivity characteristics shown are changed as compared to SCL2. Fig.12 The change SCL2 of the sensitivity characteristic shown shows a characteristic of greatly amplifying interference particularly in the frequency band of 2 kHz to 5 kHz.

[0117] Fig.13 1 is a diagram showing an example of a spectrum of a PES in an environment with harmonic interference to which the low-pass filter A4 is not applied and a cumulative sum of squares of the spectrum of the PES. Fig.13 For example, with Fig.12 Corresponding. Fig.13 In the above figure, the horizontal axis represents frequency (Hz), and the vertical axis represents PES (dBum (4.0Hz)) of the rotational asynchronous component in an environment with harmonic interference. Fig.13 The figure above shows the unapplied Figure 6 The repetitive control system RC shown Fig.11 The PES of the rotation asynchronous component shown in FIG. 1 shows the change NSL1 with respect to the frequency, and the low pass filter A4 is not applied and the low pass filter A4 is applied. Figure 6 The repetitive control system RC shown Fig.11 The PES of the rotating asynchronous component is shown with respect to the frequency variation NSL2. Fig.13 In the above figure, the change NSL1 of the PES of the rotating asynchronous component in the environment with harmonic interference is represented by a solid line, and the change NSL2 of the PES of the rotating asynchronous component in the environment with harmonic interference is represented by a dotted line. Fig.13 In the figure below, the horizontal axis represents frequency (Hz) and the vertical axis represents the cumulative 3σ value (nm) of the rotational asynchronous component in an environment with harmonic interference. Fig.13 The following figure shows the unapplied Figure 6 The repetitive control system RC is shown in the case of Fig.11 The cumulative 3σ value of the rotation asynchronous component shown in FIG. 1 is a change N3σL1 with respect to the frequency, and the low-pass filter A4 is not applied and the low-pass filter A4 is applied. Figure 6 The repetitive control system RC is shown in the case of Fig.11 The cumulative 3σ value of the rotating asynchronous component is shown as the change in frequency N3σL2. Fig.13 In the figure below, the change in the cumulative 3σ value of the rotating asynchronous component in an environment with harmonic interference relative to the frequency N3σL1 is represented by the solid line, and the change in the cumulative 3σ value of the rotating asynchronous component in an environment with harmonic interference relative to the frequency N3σL2 is represented by the dotted line.

[0118] like Fig.13As shown in the variation of PES of the rotating asynchronous component with respect to frequency NSL2, in an environment with harmonic interference, without applying the low-pass filter A4 and the repetitive control system RC of the present embodiment, PES is suppressed (suppressed or compensated) at the 1st, 2nd, 3rd, and 4th times of the estimated value f1=472Hz of the fundamental frequency of the interference. However, at frequencies after the 5th times of the estimated value 472Hz of the fundamental frequency of the interference, the PES deterioration between times is higher than the PES suppression (suppression or compensation) at the times. Therefore, as Fig.11 As shown in the change N3σL2 of the cumulative 3σ value of the rotational asynchronous component, in an environment with harmonic interference, when the low-pass filter A4 is not applied and the repetitive control system RC of this embodiment is applied, the 3σ value becomes 6.71nm. That is, in an environment with harmonic interference, the cumulative 3σ value when the low-pass filter A4 is not applied and the repetitive control system RC of this embodiment is applied is substantially the same as or slightly worse than the cumulative 3σ value when the low-pass filter A4 and the repetitive control system RC of this embodiment are not applied.

[0119] Fig.14 This is a flowchart showing an example of a method for compensating harmonics corresponding to harmonic interference according to the present embodiment.

[0120] The MPU 60 determines whether the harmonic interference is being compensated (B1401). If it is determined that the harmonic interference is not being compensated (B1401: No), the MPU 60 estimates the harmonic interference (corresponding fundamental frequency) (B1402) and determines whether the harmonic interference is detected (B1403). If it is determined that the harmonic interference is not detected (B1403: No), the MPU 60 ends the processing.

[0121] When it is determined that harmonic interference is detected (B1403: Yes), the MPU 60 determines the fundamental frequency f1 corresponding to the harmonic interference (B1404), and determines the number of delayed samples L (B1405) based on the determined fundamental frequency f1. The MPU 60 clears the past sampling values ​​e2[k-1] to e2[kL] stored in the delay memories DM(k-1) to DM(kN), for example, to zero, and proceeds to the processing of B1407.

[0122] When it is determined that the number of delayed samples L has been determined and the harmonic interference is being compensated (B1401: Yes), the MPU 60 outputs the delayed sample value e2[kL] from the repetitive controller RC (B1407). The MPU 60 updates the past sample values ​​e2[k-1] to e2[kL] in sequence, and updates the delay memory input signal e2[k] based on the new position error signal e0[k] and the current delay memory output signal e2[kL] (B1408), and ends the processing.

[0123] Fig.15 This is a flowchart showing an example of a method for compensating harmonics corresponding to interference according to the present embodiment.

[0124] When it is determined that the harmonic interference is being compensated because the delay sampling number L has been determined (B1401: Yes), the MPU 60 determines whether the harmonic interference being compensated has changed (B1501). When it is determined that the harmonic interference being compensated has not changed (B1501: No), the MPU 60 proceeds to the process of B1407.

[0125] When it is determined that the harmonic interference being compensated has changed (B1501: Yes), MPU60 estimates the harmonic interference (the corresponding fundamental frequency) again (B1502), and determines whether the fundamental frequency f1 corresponding to the re-estimated harmonic interference has changed (B1503). For example, when MPU60 confirms an increase in the 3σ value of the PES corresponding to the harmonic interference, it determines that the harmonic interference (frequency) to be compensated has changed. When it is determined that the harmonic interference being compensated has changed, MPU60 estimates the fundamental frequency corresponding to the changed harmonic interference again, compares the re-estimated fundamental frequency corresponding to the harmonic interference with the fundamental frequency corresponding to the harmonic interference currently being compensated, and determines whether the fundamental frequency f1 has changed.

[0126] When it is determined that the fundamental frequency f1 has not changed (B1503: No), the MPU 60 proceeds to the process of B1407. When it is determined that the fundamental frequency f1 has changed (B1503: Yes), the MPU 60 proceeds to the process of B1404.

[0127] According to the present embodiment, when the magnetic disk device 1 determines that the harmonic interference is being compensated because the delayed sampling number L has been determined, the delayed sampling value e2[kL] is output from the repetitive controller RC, the past sampling values ​​e2[k-1] to e2[kL] are updated in sequence, and the delay memory input signal e2[k] is updated based on the new position error signal e0[k] and the current delay memory output signal e2[kL]. In addition, when the magnetic disk device 1 determines that the harmonic interference is not being compensated, the fundamental frequency f1 corresponding to the harmonic interference is estimated to detect the harmonic interference. When the harmonic interference is detected, the magnetic disk device 1 determines the fundamental frequency f1 of the harmonic interference, determines the delayed sampling number L based on the fundamental frequency f1, and clears the past sampling values ​​e2[k-1] to e2[kL] stored in the delay memories DM(k-1) to DM(kN), for example, to 0.

[0128] Furthermore, when the disk device 1 determines that the harmonic interference is being compensated for because the delayed sampling number L has been determined, it determines whether the harmonic interference being compensated has changed. For example, when the disk device 1 confirms an increase in the 3σ value of the PES corresponding to the harmonic interference being compensated, it determines that the frequency of the harmonic interference to be compensated has changed. When it is determined that the harmonic interference has changed, the disk device 1 again estimates the fundamental frequency corresponding to the changed harmonic interference. When it is determined that the fundamental frequency estimated again has changed relative to the fundamental frequency corresponding to the harmonic interference currently being compensated, the disk device 1 again determines a new fundamental frequency f1, and based on the re-determined new fundamental frequency f1, determines a new delayed sampling again.

[0129] Therefore, the magnetic disk device 1 can prevent the degradation of the PES caused by the harmonic interference that may vary due to the variation of the rotation speed of the FAN. Therefore, the magnetic disk device 1 can improve the reliability.

[0130] Next, a magnetic disk device according to another embodiment of the first embodiment will be described. In the other embodiments, the same reference numerals are given to the same parts as those of the first embodiment, and detailed description thereof will be omitted.

[0131] (Second embodiment)

[0132] The configuration of the variable delay memory unit A3 of the magnetic disk device 1 according to the second embodiment is different from that of the magnetic disk device 1 according to the first embodiment described above.

[0133] Fig.16 This is a block diagram showing an example of a variable delay memory cell A3 according to the second embodiment.

[0134] The variable delay memory unit A3 has memory units DM(k-1), DM(k-2), DM(k-3), ..., DM(kL), ..., DM(kN), a delay selector SW, and an interpolator ITP. Fig.16 The variable delay memory cell A3 shown is Figure 3 , Figure 5 as well as Figure 6 The variable delay memory unit A3 shown corresponds.

[0135] For example, the delay memory DM(k-1) receives the k-th sampled delay memory input signal e2[k]=e2(kTs) and stores (or records) the k-th sampled delay memory input signal e2[k]=e2(kTs) as the past sampled value e2[k-1] of the previous sample. Here, Ts is the sampling period. Similar to the delay memory DM(k-1), the multiple delay memories DM(k-2) to DM(kN) receive the past sampled values ​​of the previous sample from the previous delay memory, and sequentially update and store (or record) the input past sampled values ​​as new past sampled values.

[0136] The delay selector SW selects a predetermined past sample value from the past sample values ​​e2[k-1] to e2[kN] recorded in the memory units DM(k-1) to DM(kN), respectively. The delay selector SW outputs the selected predetermined past sample value. For example, the delay selector SW selects, from the delayed sample values ​​e2[k-1] to e2[kN] recorded in the memory units DM(k-1) to DM(kN), respectively, the delayed sample values ​​e2[kL] and e2[k-(L+1)] corresponding to the delayed sample numbers L and L+1 calculated by dividing the delay time T1 by the sampling period Ts and discarding the decimal point, respectively, according to the delay time T1 corresponding to the inverse of the fundamental frequency f1 corresponding to the harmonic interference currently being compensated input to the terminal V. For example, L≤T1 / Ts<L+1. For example, the delay selector SW outputs the selected delayed sample values ​​(delay memory output signals) e2[kL] and e2[k-(L+1)] to the interpolator ITP.

[0137] The interpolator ITP performs interpolation operations. The interpolator ITP receives the delay memory output signal e2[kL] via the input terminal II1 connected to the output terminal O1 of the delay selector SW, and receives the delay memory output signal e2[k-(L+1)] via the input terminal II2 connected to the output terminal O2 of the delay selector SW. The interpolator ITP uses the delay memory output signal e2[kL](=e2((kL)Ts)) and the delay memory output signal e2[k-(L+1)](=e2((k-(L+1))Ts) to perform interpolation operations, such as interpolation operations, according to the following formula (1) to estimate the output signal (hereinafter sometimes referred to as the interpolated delay memory output signal) e2(kTs-T1) at the delayed sampling number T1 / Ts as a real value.

[0138] e2(kTs-T1)=e2[kL]+(e2[k-(L+1)]-e2[kL])×(T1 / Ts-L) (Formula 1)

[0139] The interpolator ITP outputs the interpolated delay memory output signal e1=e2(kTs-T1) via the output terminal OI.

[0140] Fig.17 This is a block diagram showing an example of a variable delay memory cell A3 according to the second embodiment.

[0141] The variable delay memory unit A3 has a delay memory DM((k-1)Ts), memory units DM(k-1), DM(k-2), DM(k-3), ..., DM(kL), ..., DM(kN), a delay selector SW and an interpolator ITP. Fig.17 The variable delay memory cell A3 shown is Figure 3 , Figure 5 as well as Figure 6 The variable delay memory unit A3 shown corresponds.

[0142] The delay memory DM((k-1)Ts) corresponds to the sampling period Ts. The delay memory DM((k-1)Ts) is input with the delay memory input signal e2[k]=e2(kTs) of the kth sample, and stores (or records) the delay memory input signal e2[k]=e2(kTs) as the sampling value of the previous sample (hereinafter sometimes referred to as the delay memory input signal) e2((k-1)Ts). The delay memory DM((k-1)Ts) is connected to the input terminal II2 of the interpolator ITP.

[0143] The interpolator ITP receives the delay memory input signal e2[k]=e2(kTs) via the input terminal II1, and receives the sample value e2((k-1)Ts) via the input terminal II2 connected to the delay memory DM((k-1)Ts). Since the number of delayed samples L is determined based on the delay time T1, the interpolator ITP uses the delay memory input signal e2[k]=e2(kTs) and the delay memory input signal e2((k-1)Ts) to perform an interpolation operation, such as an interpolation operation, using the following formula (2) to estimate a past input signal (hereinafter sometimes referred to as an interpolated delay memory input signal) e2[k]=e2((k-(T1 / Ts-L))Ts) corresponding to the number of terminals of the delay memory input signal e2[k]=e2(kTs). In other words, since the number of delayed samples L is determined based on the delay time T1, the interpolator ITP uses the delay memory input signal e2[k]=e2(kTs) and the delay memory input signal e2((k-1)Ts) to perform an interpolation operation, such as an interpolation operation, using the following formula (2) to estimate the delay memory input signal e2[k]=e2(kTs) and the interpolated delay memory input signal that is delayed accordingly to the decimal point (T1 / Ts-L) of the value obtained by dividing the delay memory input signal e2[k]=e2(kTs) and the delay time by the sampling period.

[0144] e2(k-(T1 / Ts-L)Ts)=e2(kTs)+((e2(k-1)Ts)-e2(kTs))×(T1 / Ts-L) (Equation 2)

[0145] Here, L≤T1 / Ts<L+1.

[0146] The interpolator ITP outputs the interpolated delay memory input signal e2[k]=e2((k-(T1 / Ts-L))Ts) to the delay memory DM(k-1) (or the memory cell) via the output terminal OI connected to the delay memory DM(k-1).

[0147] For example, the delay memory DM(k-1) receives the interpolation delay memory input signal e2[k]=e2((k-(T1 / Ts-L))Ts) of the kth sample, and stores (or records) the interpolation delay memory input signal e2[k]=e2((k-(T1 / Ts-L))Ts) of the kth sample as the past sample value e2[k-1] of the previous sample. Similarly to the delay memory DM(k-1), the multiple delay memories DM(k-2) to DM(kN) receive the past sample value of the previous sample from the previous delay memory, and sequentially update and store (or record) the input past sample values ​​as new past sample values.

[0148] For example, the delay selector SW selects a delayed sampling value e2[kL] corresponding to the delayed sampling number L from the past sampling values ​​e2[k-1] to e2[kN] recorded in the memory units DM(k-1) to DM(kN) according to the delay time T1 input to the terminal V. For example, the delay selector SW outputs the selected delayed sampling value (delay memory output signal) e2[kL]=e2(kTs-T1). That is, the delay selector SW outputs the delay memory output signal e2(kTs-T1) delayed by the delay time T1 relative to the delay memory input signal e2(kTs).

[0149] Fig.18 This is a diagram showing an example of changes in the sensitivity characteristics of the positioning control system SY according to the second embodiment. Fig.18 and Fig.16 or Fig.17 Corresponding. Fig.18 In the figure, the horizontal axis represents frequency (Freq.Hz) and the vertical axis represents gain (GaindB). Fig.18 Shown in the figure are changes SCL3 in sensitivity characteristics (or gain) with respect to frequency when a repetitive control system RC including a variable delay memory unit A3 having an interpolator ITP is applied to the higher harmonics of the target suppression fundamental frequency (estimated value) f1=470 Hz corresponding to the harmonic interference (hereinafter sometimes referred to as the target suppression fundamental frequency) and changes SCL4 in sensitivity characteristics (or gain) with respect to frequency when a repetitive control system RC including a variable delay memory unit A3 without an interpolator ITP is applied to the higher harmonics of the target suppression fundamental frequency (estimated value) f1=470 Hz corresponding to the harmonic interference. Fig.18 In the example shown, a change SCL3 of the sensitivity characteristic (or gain) with respect to frequency is indicated by a solid line. A change SCL4 of the sensitivity characteristic (or gain) with respect to frequency is indicated by a dotted line. The change SCL3 of the sensitivity characteristic (or gain) with respect to frequency is applied to the repetitive control system RC of the second embodiment. The change SCL4 of the sensitivity characteristic (or gain) with respect to frequency is applied to the repetitive control system RC of the first embodiment.

[0150] exist Fig.18 In the example shown, in both the case of the change SCL3 of the sensitivity characteristic with respect to frequency and the change SCL4 of the sensitivity characteristic with respect to frequency, the higher harmonics of the frequency near the target suppression fundamental frequency (= estimated value) f1 = 470 Hz corresponding to the harmonic interference are suppressed (or compensated).

[0151] Fig.19 Yes Fig.18This is an enlarged diagram obtained by enlarging the waveform of the target suppression base frequency f1=470 Hz. Fig.19 and Fig.18 Corresponding. Fig.19 In the figure, the horizontal axis represents frequency (Hz) and the vertical axis represents gain (dB). Fig.19 In the example, the servo sampling frequency fs = 62.4kHz.

[0152] exist Fig.19 In the example shown, in the change SCL4 of the sensitivity characteristic (or gain) with respect to the frequency, the number of delayed samples is fs / f1=132.76, which is rounded to an integer value of L=133. In the case of the delayed sample number L=133, the repetitive control system suppresses (or compensates for) the frequency f1'=fs / L=469.2 Hz. In other words, in the example shown in the change SCL4 of the sensitivity characteristic (or gain) with respect to the frequency, the repetitive control system suppresses (or compensates for) the frequency f1'=fs / L=469.2 Hz. An error occurs between the frequency f1'=469.2 Hz and the target suppression base frequency f1=470 Hz. On the other hand, in the example shown in the change SCL3 of the sensitivity characteristic (or gain) with respect to the frequency, the repetitive control system RC is able to suppress (or compensate for) a frequency that is substantially consistent with the target suppression base frequency f1=470 Hz.

[0153] Fig. 20 is to be used as Fig.18 This is an enlarged diagram obtained by enlarging a waveform of a frequency near 7050 Hz, which is the 15th harmonic of the fundamental frequency f1 that is targeted for suppression. Fig. 20 and Fig.18 Corresponding. Fig. 20 In FIG. 1 , the horizontal axis represents frequency (Hz) and the vertical axis represents gain (dB).

[0154] exist Fig. 20 In the example shown, in the change SCL4 of the sensitivity characteristic (or gain) with respect to the frequency, the repetitive control system suppresses (or compensates) the frequency 15×f1'=7038Hz corresponding to the 15th harmonic. There is an error between the frequency 15×f1'=7038Hz corresponding to the 15th harmonic and the frequency of the higher harmonic to be suppressed as the target corresponding to the 15th harmonic (hereinafter sometimes referred to as the target suppression frequency) 15×f1=7050Hz. On the other hand, in the example shown in the change SCL3 of the sensitivity characteristic (or gain) with respect to the frequency, the repetitive control system RC can suppress (or compensate) the frequency that is substantially consistent with the target suppression frequency 15×f1=7050Hz corresponding to the 15th harmonic. The target suppression frequency includes the target suppression fundamental frequency.

[0155] Fig.21 It means in Fig.18 , Fig.19 as well as Fig. 20 The sensitivity characteristics shown are graphs showing the suppression frequency error between the frequency of the suppressed harmonics and the target suppression frequency in the variation of the two frequencies. Fig.21 and Fig.18 , Fig.19 as well as Fig. 20 Corresponding. Fig.21 In the figure, the horizontal axis represents the frequency (Freq.Hz), and the vertical axis represents the error (ΔFreq.Hz hereinafter sometimes referred to as the suppression frequency error) of the frequency after the actual suppression relative to the target suppression frequency. Fig.21 It is shown in Figure 18 to Figure 20 The sensitivity characteristic SCL3 shown in FIG. 1 shows the frequency variation with respect to the frequency, and the suppressed frequency errors SCE3 at each frequency and each target frequency, and the suppressed frequency errors SCE3 at each frequency. Figure 18 to Figure 20 The sensitivity characteristic with respect to the change SCL4 shown is each suppressed frequency error SCE4 at each frequency between each suppressed frequency and each target frequency. Fig.21 In FIG. 1 , each suppressed frequency error SCE3 at each frequency is represented by a circle, and each suppressed frequency error SCE4 at each frequency is represented by a triangle.

[0156] like Fig.21 As shown, each suppression frequency error SCE4 at each frequency is close to the target suppression frequency at a low frequency corresponding to low-order harmonics, but is greatly different from the target suppression frequency at a high frequency corresponding to high-order harmonics. Each suppression frequency error SCE3 at each frequency is close to the target suppression frequency at a low frequency corresponding to low-order harmonics, and is close to the target suppression frequency at a high frequency corresponding to high-order harmonics. Therefore, it can be seen that the effect of applying the repetitive control system RC of the second embodiment is particularly shown at a high frequency corresponding to high-order harmonics.

[0157] Fig. 22 This is a flowchart showing an example of a method for compensating harmonics corresponding to harmonic interference according to the second embodiment. Fig. 22 and Fig.16 correspond.

[0158] When it is determined that the compensation of harmonic interference is in progress because the number of delayed sampling L has been determined (B1401: Yes), MPU60 outputs delayed sampling values ​​e2[kL] and e2[k-(L+1)] from the selector SW in the repetitive controller RC (B2201). MPU60 outputs an interpolation delay memory output signal e2(kTs-T1) estimated by performing an interpolation operation, such as an interpolation operation, based on the delayed sampling values ​​e2[kL] and e2[k-(L+1)] (B2202). MPU60 updates the past sampling values ​​e2[k-1] to e2[kL] in sequence, and updates the delay memory input signal e2[k] based on the new position error signal e0[k] and the current delay memory output signal e2[kL] (B1408), and ends the processing.

[0159] According to the second embodiment, when the magnetic disk device 1 determines that the harmonic interference is being compensated because the delayed sampling number L has been determined, the selector SW in the repetitive controller RC outputs the delayed sampling values ​​e2[kL] and e2[k-(L+1)], and outputs the interpolation delay memory output signal e2(kTs-T1) estimated by performing an interpolation operation, such as interpolation, based on the delayed sampling values ​​e2[kL] and e2[k-(L+1)]. The magnetic disk device 1 sequentially updates the past sampling values ​​e2[k-1] to e2[kL], and updates the delay memory input signal e2[k] based on the new position error signal e0[k] and the current delay memory output signal e2[kL]. Therefore, the magnetic disk device 1 can improve reliability.

[0160] Several embodiments have been described above, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and can be omitted, replaced, and changed in various ways without departing from the scope of the invention. These embodiments and their variations are included in the scope and purpose of the invention, and are included in the invention described in the claims and their equivalents.

[0161] An example of a magnetic disk device obtained according to the configuration disclosed in this specification is described below. (1)

[0163] A magnetic disk device comprising:

[0164] plate;

[0165] a head that writes data to and reads data from the disk;

[0166] an actuator that performs rotational driving to control movement of the head mounted on the disk; and

[0167] A controller estimates the fundamental frequency of a position error signal generated in the positioning control of the head corresponding to interference with harmonics, determines the fundamental frequency, determines the number of delayed sampling based on the fundamental frequency, and suppresses the multiple frequencies of the higher harmonics of the fundamental frequency corresponding to the number of delayed sampling. (2)

[0169] The magnetic disk device according to (1),

[0170] The controller calculates the number of delayed samples as a ratio of a servo sampling frequency to the fundamental frequency. (3)

[0172] The magnetic disk device according to (1) or (2),

[0173] The controller calculates the number of delayed samples as a rounded value or a rounded value of a ratio of a servo sampling frequency to the base frequency. (4)

[0175] The magnetic disk device according to any one of (1) to (3),

[0176] The controller estimates the fundamental frequency again and determines the fundamental frequency again when the interference changes, and determines the number of delayed samples again based on the fundamental frequency determined again. (5)

[0178] According to the magnetic disk device described in (4),

[0179] When the controller detects deterioration of the position error signal, it determines that the interference has changed and estimates the fundamental frequency again. (6)

[0181] The magnetic disk device according to any one of (1) to (5),

[0182] The controller has a repetitive control system, which has an operator and a memory unit. The operator outputs an internal state signal obtained by adding an output signal corresponding to the delayed sampling number to the position error signal. The memory unit sequentially records the internal state signal input, is input with the delayed sampling number, and outputs the output signal corresponding to the delayed sampling number. (7)

[0184] According to the magnetic disk device described in (6),

[0185] The controller has a low-pass filter connected to the operator and the memory unit.

[0186] The operator outputs the internal state signal to the low-pass filter.

[0187] The low-pass filter outputs the internal state signal obtained by cutting or attenuating frequencies higher than a first frequency to the memory unit. (8)

[0189] According to the magnetic disk device described in (7),

[0190] The controller has a phase compensator connected to the memory unit,

[0191] The memory unit outputs the output signal to the phase compensator,

[0192] The phase compensator outputs the output signal after performing phase compensation to the operator. (9)

[0194] The magnetic disk device according to (1),

[0195] The controller outputs an interpolation output signal obtained by performing an interpolation operation based on the output signal corresponding to the base frequency, and performs positioning control based on the interpolation output signal. (10)

[0197] According to the magnetic disk device described in (9),

[0198] The controller calculates the delayed sampling number as an integer value obtained by rounding off a value obtained by dividing a delay time by a sampling period, wherein the delay time is the reciprocal of the fundamental frequency. (11)

[0200] The magnetic disk device according to (9) or (10),

[0201] The controller performs linear interpolation operation on a first output signal among the output signals corresponding to a first delayed sampling number among the delayed sampling numbers and a second output signal among the output signals corresponding to a second delayed sampling number after one sampling period of the first delayed sampling number among the delayed sampling numbers to calculate the interpolated output signal. (12)

[0203] A method for compensating high-order harmonics corresponding to harmonic interference is applied to a magnetic disk device, the magnetic disk device comprising a disk, a head, and an actuator, the head writing data to the disk and reading data from the disk, the actuator performing rotational driving and controlling the movement of the head mounted on the disk, the compensation method comprising:

[0204] estimating a fundamental frequency of a position error signal generated in positioning control of the head corresponding to a disturbance having harmonics;

[0205] determining the fundamental frequency;

[0206] Based on the base frequency, determining the number of delayed samples; and

[0207] The frequency multiples which are harmonics of the fundamental frequency corresponding to the number of delayed samples are suppressed. (13)

[0209] A magnetic disk device comprising:

[0210] plate;

[0211] a head that writes data to and reads data from the disk;

[0212] an actuator that performs rotational driving to control movement of the head mounted on the disk; and

[0213] A controller estimates the fundamental frequency of a position error signal generated in the positioning control of the head corresponding to interference with harmonics, determines the fundamental frequency, determines the number of delayed sampling based on the fundamental frequency, outputs an interpolated output signal obtained by interpolating an output signal corresponding to the fundamental frequency, and performs positioning control based on the interpolated output signal. (14)

[0215] According to the magnetic disk device described in (13),

[0216] The controller calculates the number of delayed samples as an integer value obtained by rounding off a value obtained by dividing a delay time by a sampling period, wherein the delay time is the reciprocal of the fundamental frequency. (15)

[0218] According to the magnetic disk device described in (14),

[0219] The controller performs linear interpolation operation on a first output signal among the output signals corresponding to a first delayed sampling number among the delayed sampling numbers and a second output signal among the output signals corresponding to a second delayed sampling number after one sampling period of the first delayed sampling number among the delayed sampling numbers to calculate the interpolated output signal. (16)

[0221] According to the magnetic disk device described in (14),

[0222] The controller calculates the output signal based on the first internal state signal that is delayed by a corresponding amount below the decimal point of a value obtained by dividing the position error signal and the delay time by the sampling period. (17)

[0224] According to the magnetic disk device described in (16),

[0225] The controller has a repetitive control system, which has: an operator, which outputs a second internal state signal obtained by adding an output signal corresponding to the delayed sampling number to the position error signal; an interpolator, which outputs the first internal state signal obtained by interpolating the second internal state signal and the third internal state signal after one sampling period of the second internal state signal; and a memory unit, which sequentially records the first internal state signal input, is input with the delayed sampling number, and outputs the output signal corresponding to the delayed sampling number.

Claims

1. A magnetic disk device comprising: plate; a head that writes data to and reads data from the disk; an actuator that performs rotational driving to control movement of the head mounted on the disk; and A controller estimates the fundamental frequency of a position error signal generated in the positioning control of the head corresponding to interference with harmonics, determines the fundamental frequency, determines the number of delayed sampling based on the fundamental frequency, and suppresses the multiple frequencies of the higher harmonics of the fundamental frequency corresponding to the number of delayed sampling.

2. The magnetic disk device according to claim 1, The controller calculates the delayed sampling number as a ratio of a servo sampling frequency to the base frequency.

3. The magnetic disk device according to claim 1 or 2, The controller calculates the delayed sampling number as a rounded value or a rounded value of a ratio of a servo sampling frequency to the base frequency.

4. The magnetic disk device according to claim 1 or 2, The controller estimates the fundamental frequency again and determines the fundamental frequency again when the interference changes, and determines the number of delayed samples again based on the fundamental frequency determined again.

5. The magnetic disk device according to claim 4, When the controller detects deterioration of the position error signal, it determines that the interference has changed and estimates the fundamental frequency again.

6. The magnetic disk device according to claim 1 or 2, The controller has a repetitive control system, which has an operator and a memory unit. The operator outputs an internal state signal obtained by adding an output signal corresponding to the delayed sampling number to the position error signal. The memory unit sequentially records the input internal state signal, is input with the delayed sampling number, and outputs the output signal corresponding to the delayed sampling number.

7. The magnetic disk device according to claim 6, The controller has a low-pass filter connected to the operator and the memory unit. The operator outputs the internal state signal to the low-pass filter. The low-pass filter outputs the internal state signal obtained by cutting or attenuating frequencies higher than a first frequency to the memory unit.

8. The magnetic disk device according to claim 7, The controller has a phase compensator connected to the memory unit, The memory unit outputs the output signal to the phase compensator, The phase compensator outputs the output signal after performing phase compensation to the operator.

9. The magnetic disk device according to claim 1, The controller outputs an interpolation output signal obtained by performing an interpolation operation based on the output signal corresponding to the base frequency, and performs positioning control based on the interpolation output signal.

10. The magnetic disk device according to claim 9, The controller calculates the delayed sampling number as an integer value obtained by rounding off a value obtained by dividing a delay time by a sampling period, wherein the delay time is the reciprocal of the fundamental frequency.

11. The magnetic disk device according to claim 9 or 10, The controller performs linear interpolation operation on a first output signal among the output signals corresponding to a first delayed sampling number among the delayed sampling numbers and a second output signal among the output signals corresponding to a second delayed sampling number after one sampling period of the first delayed sampling number among the delayed sampling numbers to calculate the interpolated output signal.

12. A method for compensating higher harmonics corresponding to harmonic interference, applied to a magnetic disk device, the magnetic disk device comprising a disk, a head and an actuator, the head writing data to the disk and reading data from the disk, the actuator performing rotational driving and controlling the movement of the head mounted on the disk, the compensation method comprising: estimating a fundamental frequency of a position error signal generated in positioning control of the head corresponding to a disturbance having harmonics; determining the fundamental frequency; Based on the base frequency, determining the number of delayed samples; as well as The higher harmonics, ie, the doubled frequencies, of the fundamental frequency corresponding to the number of delayed samples are suppressed.

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