Apparatus and method for accessing a word line

Abstract

An apparatus includes control circuitry configured to be connected to a first word line of a first vertical sub-block and a second word line of a second vertical sub-block. The first vertical sub-block and the second vertical sub-block include memory cells connected in series in NAND strings, each NAND string including a memory cell coupled to the first word line in series with a memory cell connected to the second word line. The control circuitry is configured to program or sense memory cells along a selected first word line of the first vertical sub-block while applying a first voltage to the second word line connected to programmed memory cells and a second voltage to the second word line connected to unprogrammed memory cells.

Description

Background Technology

[0001] Semiconductor memories are widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery).

[0002] One type of non-volatile memory has strings of non-volatile memory cells, each with a selection transistor at each end of the string. Typically, such strings are called NAND strings. A NAND string may have a drain-side selection transistor at one end, connecting the string to a bit line. A NAND string may also have a source-side selection transistor at one end, connecting the string to a source line. The non-volatile memory cells can also be called non-volatile memory cell transistors, and the channels of these transistors are collectively referred to as NAND string channels. Attached Figure Description

[0003] Components with similar numbers refer to common parts in different drawings.

[0004] Figure 1 This is a functional block diagram of a memory device.

[0005] Figures 2A to 2B It is a block diagram depicting an implementation scheme for a memory system.

[0006] Figure 3 This is a perspective view of one implementation of a monolithic three-dimensional memory architecture.

[0007] Figure 4A It is a block diagram of a memory structure with two planes.

[0008] Figure 4B A top view depicting a portion of a block of memory cells.

[0009] Figure 4C An implementation scheme for stacking is described, showing along... Figure 4B A sectional view of line AA.

[0010] Figure 4D Depicting Figure 4C Alternative view of the selected gate layer and word line layer of the stacked 435.

[0011] Figure 4E Depicting Figure 4C The view of area 445.

[0012] Figure 4F This is a schematic diagram of multiple NAND strings, showing multiple horizontal sub-blocks.

[0013] Figure 4G This is a schematic diagram of multiple NAND strings, showing a horizontal sub-block.

[0014] Figure 4H This is a schematic diagram of a NAND string that extends through multiple vertical sub-blocks.

[0015] Figure 5 An exemplary threshold voltage distribution for a memory array is shown when each memory cell stores three bits of data.

[0016] Figures 6A to 6B An example of connected sub-blocks and their corresponding bias schemes is shown.

[0017] Figures 7A to 7D The method of applying different voltages to different word lines of an unselected sub-block is shown.

[0018] Figures 8A to 8C A method is shown for finding the boundary between the programmed and unprogrammed portions of an open subblock.

[0019] Figure 9 This is an exemplary timing diagram for programming memory cells along selected word lines.

[0020] Figure 10 This is an exemplary timing diagram for sensing memory cells along a selected word line. Detailed Implementation

[0021] A technique is provided for accessing word lines in a selected vertical subblock connected to one or more unselected subblocks, such that the word lines of the unselected subblocks receive different voltages depending on whether they are connected to programmed or unprogrammed memory cells. The voltage applied to the word lines of the unselected subblocks connected to unprogrammed (erased) memory cells may be lower than the voltage applied to the programmed memory cells of the unselected subblocks, and the voltage applied to the programmed memory cells of the unselected subblocks may be lower than the voltage applied to the unselected memory cells of the selected subblocks. Before biasing the word lines of the unselected subblocks, the boundary between the programmed and unprogrammed portions of the subblock can be located (e.g., from control information or by searching the word lines of the unselected subblocks). Word lines on either side of this boundary are biased with different voltages (e.g., a lower voltage is applied to the word lines on the unprogrammed side, and a higher voltage is applied to the word lines on the programmed side).

[0022] In some memory structures, NAND strings reside in blocks divided into vertical sub-blocks. In one embodiment, the NAND strings pass vertically through a stack of alternating horizontal conductive and dielectric layers. In one embodiment, the stack comprises hierarchies (also referred to as vertical sub-blocks). Thus, each NAND string in the block resides in multiple vertical sub-blocks. In one embodiment, there are two such connected vertical sub-blocks. In one embodiment, there are at least three vertical sub-blocks.

[0023] In one implementation, different vertical sub-blocks can be treated as separate units for erase / programming purposes. For example, data in different vertical sub-blocks can be logically independent, allowing connected sub-blocks (sub-blocks connected by a shared NAND string) to be programmed and erased at different times. Memory cells in one vertical sub-block can be erased independently, while valid data remains in other connected vertical sub-blocks. The memory cells in the erased vertical sub-block can then be programmed, while valid data remains in other vertical sub-blocks. Therefore, different connected sub-blocks can have different numbers of write-erase cycles. Data in a vertical sub-block can remain for a period of time, during which connected vertical sub-blocks are repeatedly written to and erased, which can severely interfere with that data. Programming memory cells in selected vertical sub-blocks presents technical challenges because valid data resides in other vertical sub-blocks. This can be particularly challenging in certain memory systems (e.g., more challenging in memory cells that store more than one bit of data per cell).

[0024] In one embodiment, while accessing selected word lines in a selected vertical subblock, an overdrive voltage is applied to some memory cells, and a bypass voltage is applied to other memory cells connected to one or more unselected vertical subblocks connected to the selected vertical subblock. The overdrive voltage is defined herein as a voltage of magnitude such that when the overdrive voltage is applied to the control gate of a memory cell, the memory cell will operate as if it were in a through-gate state (e.g., conducting current or "on"), regardless of whether the memory cell is in a programming or erasing state. The bypass voltage is defined herein as a voltage of magnitude such that when the bypass voltage is applied to the control gate of a memory cell, if the memory cell is in an erasing state, the memory cell will operate as if it were in a through-gate state (e.g., conducting current or "on"), but for at least one programming state, the memory cell will not operate as if it were in a through-gate state. The overdrive voltage applied to memory cells in unselected vertical subblocks may be different from (e.g., less than) the overdrive voltage applied to memory cells in selected vertical subblocks. The bypass voltage applied to memory cells in unselected vertical subblocks may be different from (e.g., less than) the bypass voltage applied to memory cells in selected vertical subblocks.

[0025] Figures 1 to 4H Examples of memory systems that can be used to implement the techniques proposed in this paper are described. Figure 1 This is a functional block diagram of an exemplary memory system 100. Figure 1 The components depicted are circuits. The memory system 100 includes one or more memory dies 108. The one or more memory dies 108 may be complete memory dies or partial memory dies. In one embodiment, each memory die 108 includes a memory structure 126, control circuitry 110, and read / write circuitry 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write / erase circuitry 128 includes a plurality of sensing blocks 150 and allows memory cell pages to be read or programmed in parallel; these sensing blocks include SB1, SB2, ..., SBp (sensing circuitry). Furthermore, many strings of memory cells can be erased in parallel.

[0026] In some systems, controller 122 is included in the same package (e.g., a removable memory card) as one or more memory dies 108. However, in other systems, the controller may be separate from memory die 108. In some embodiments, the controller will reside on a die different from memory die 108. In some embodiments, one controller 122 will communicate with multiple memory dies 108. In other embodiments, each memory die 108 has its own controller. Commands and data are transmitted between host 140 and controller 122 via data bus 120, and between controller 122 and one or more memory dies 108 via line 118. In one embodiment, memory die 108 includes a set of input and / or output (I / O) pins connected to line 118.

[0027] Control circuitry 110 works in conjunction with read / write circuitry 128 to perform memory operations (e.g., write, read, erase, etc.) on memory structure 126, and includes state machine 112, on-chip address decoder 114, and power control circuitry 116. In one embodiment, control circuitry 110 includes buffers such as registers, ROM fuses, and other storage devices for storing default values ​​(such as base voltage and other parameters).

[0028] On-chip address decoder 114 provides an address interface between addresses used by host 140 or controller 122 and hardware addresses used by decoder 124 and decoder 132. Power control circuitry 116 controls the power and voltage supplied to word lines, bit lines, and select lines during memory operations. In one embodiment, power control circuitry 116 includes voltage circuitry. Power control circuitry 116 may include a charge pump for generating voltage. Sensing block includes bit line drivers. In one embodiment, power control circuitry 116 operates under the control of state machine 112.

[0029] State machine 112 and / or controller 122 (or equivalent functional circuit) and Figure 1 The combination of all or a subset of the other circuits depicted herein can be considered as control circuitry performing the various functions described herein. Control circuitry may consist solely of hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of control circuitry. Control circuitry may include processors, PGAs (Programmable Gate Arrays), FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), integrated circuits, or other types of circuitry.

[0030] The (on-chip or off-chip) controller 122 (circuit in one embodiment) may include one or more processors 122c, ROM 122a, RAM 122b, memory interface (MI) 122d, and host interface (HI) 122e, all of which are interconnected. The storage devices (ROM 122a, RAM 122b) store code (software), such as a set of instructions (including firmware), and one or more processors 122c are operable to execute that set of instructions to provide the functionality described herein. Alternatively or otherwise, one or more processors 122c may access the code from storage devices in a memory structure, such as reserved areas of memory cells connected to one or more word lines. RAM 122b may be used to store data for the controller 122, including cached program data (discussed below). The memory interface 122d, which communicates with the ROM 122a, RAM 122b, and processor 122c, is circuitry that provides an electrical interface between the controller 122 and one or more memory dies 108. For example, memory interface 122d can change the format or timing of signals, provide buffers, provide surge isolation, latch I / O, etc. One or more processors 122c can issue commands to control circuitry 110 (or another component of memory die 108) through memory interface 122d. Host interface 122e provides an electrical interface to host 140 data bus 120 to receive commands, addresses, and / or data from host 140 to provide data and / or status to host 140.

[0031] In one embodiment, memory structure 126 includes a three-dimensional memory array of non-volatile memory cells, wherein multiple memory stages are formed over a single substrate such as a wafer. The memory structure can include any type of non-volatile memory monolithically formed in one or more physical layers of the memory cell array, having an active region disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge-trapping material.

[0032] In another embodiment, memory structure 126 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR flash memory) may also be used. The exact type of memory array architecture or memory cells included in memory structure 126 is not limited to the examples described above.

[0033] Figure 2A This is a block diagram of an exemplary memory system 100, depicting further details of one embodiment of the controller 122. Figure 2A The controller described herein is a flash memory controller, but it should be noted that the non-volatile memory die 108 is not limited to flash memory. Therefore, the controller 122 is not limited to examples of flash memory controllers. As used herein, a flash memory controller is a device that manages data stored on flash memory and communicates with a host such as a computer or electronic device. In addition to the specific functions described herein, a flash memory controller can have a variety of functions. For example, a flash memory controller can format the flash memory to ensure proper operation, map out bad flash memory cells, and allocate spare memory cells to replace future faulty cells. A portion of the spare cells can be used to house firmware to operate the flash memory controller and implement other features. In operation, when the host needs to read data from or write data to the flash memory, it communicates with the flash memory controller. If the host provides a logical address to read / write data, the flash memory controller can translate the logical address received from the host into a physical address in the flash memory. (Alternatively, the host can provide a physical address.) The flash memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (allocating writes to specific memory blocks to avoid wear that would otherwise be repeatedly written to) and garbage collection (moving only valid data pages to a new block after a block is full, so that the entire block can be erased and reused).

[0034] The interface between the controller 122 and the non-volatile memory die 108 can be any suitable flash memory interface, such as switching modes 200, 400, or 800. In one embodiment, the memory system 100 can be a card-based system, such as a Secure Digital (SD) or Micro-Secure Digital (micro-SD) card. In another embodiment, the memory system 100 can be part of an embedded memory system. For example, flash memory can be embedded within the host computer. In other examples, the memory system 100 can be in the form of a solid-state drive (SSD).

[0035] In some embodiments, the non-volatile memory system 100 includes a single channel between the controller 122 and the non-volatile memory die 108, but the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, there are two, four, eight, or more channels between the controller and the memory die, depending on the controller's capabilities. In any embodiment described herein, even if a single channel is shown in the figures, there may be more than one single channel between the controller and the memory die.

[0036] like Figure 2A As depicted, controller 122 includes a front-end module 208 that interacts with a host, a back-end module 210 that interacts with one or more non-volatile memory dies 108, and various other modules that perform functions that will now be described in detail.

[0037] Figure 2A The components of the controller 122 depicted herein may take the form of, for example, a packaged functional hardware unit (e.g., circuitry) designed for use with other components, a portion of program code (e.g., software or firmware) executable by a specific (micro)processor or processing circuitry that typically performs related functions, or a separate hardware or software component that interacts with a larger system. For example, each module may include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), circuitry, digital logic circuitry, analog circuitry, discrete circuitry, gates, or any other type of hardware, or a combination thereof. Alternatively or additionally, each module may include software stored in a processor-readable device (e.g., memory) to program the processor to cause the controller 122 to perform the functions described herein. Figure 2A The architecture described in the text is (or may not) be usable. Figure 1 An exemplary specific implementation of the components (i.e., RAM, ROM, processor, interface) of the controller 122 depicted herein.

[0038] Referring again to the module of controller 122, the buffer manager / bus controller 214 manages the buffers in random access memory (RAM) 216 and controls the internal bus arbitration of controller 122. Read-only memory (ROM) 218 ​​stores the system boot code. Although Figure 2A The RAM 216 and ROM 218 are shown positioned separately from the controller 122, but in other embodiments, one or both of them may be located within the controller. In still other embodiments, portions of the RAM and ROM may be located both inside and outside the controller 122. Furthermore, in some specific embodiments, the controller 122, RAM 216, and ROM 218 may be located on separate semiconductor dies.

[0039] The front-end module 208 includes a host interface 220 and a physical layer interface (PHY) 222 that provides an electrical interface to the host or a next-level storage controller. The type of host interface 220 can be selected depending on the type of memory used. Examples of host interfaces 220 include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 220 is typically used for transmitting data, control signals, and timing signals.

[0040] Backend module 210 includes an error correction code (ECC) engine 224 that encodes data bytes received from the host and decodes and error-corrects data bytes read from the non-volatile memory. Command sequencer 226 generates command sequences, such as programming and erasing command sequences, to be transmitted to the non-volatile memory die 108. RAID (Redundant Array of Independent Dies) module 228 manages the generation of RAID parity and the recovery of faulty data. RAID parity can be used as an additional level of integrity protection for data written to the non-volatile memory system 100. In some cases, RAID module 228 may be part of ECC engine 224. It should be noted that RAID parity can be added as one or more additional dies, as implied by the common name, but can also be added within an existing die, for example, as an additional plane, or an additional block, or an additional write-level (WL) within a block. Memory interface 230 provides command sequences to and receives status information from the non-volatile memory die 108. In one implementation, the memory interface 230 may be a Double Data Rate (DDR) interface, such as a switching mode 200, 400, or 800 interface. The flash memory control layer 232 controls the overall operation of the back-end module 210.

[0041] Figure 2AAdditional components of the illustrated system 100 include a media management layer 238 that performs wear leveling of the memory cells of the non-volatile memory die 108. System 100 also includes other discrete components 240, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with the controller 122. In an alternative embodiment, one or more of the physical layer interface 222, RAID module 228, media management layer 238, and buffer management / bus controller 214 are optional components not required in the controller 122.

[0042] The Flash Translation Layer (FTL) or Media Management Layer (MML) 238 may be integrated as part of flash management that handles flash errors and communicates with the host. Specifically, the MML may be a module within flash management and may be responsible for internal NAND management. Specifically, the MML 238 may include algorithms in the memory device firmware that translate writes from the host into writes to the memory 126 of the memory die 108. The MML 238 may be necessary because: 1) the memory may have limited endurance; 2) the memory 126 may only have multiple pages written to; and / or 3) the memory may not be written to unless it is erased as a block (or as a layer within a block in some embodiments). The MML 238 understands these potential limitations of the memory 126, which may not be visible to the host. Therefore, the MML 238 attempts to translate writes from the host into writes to the memory 126.

[0043] The controller 122 can interface with one or more memory dies 108. In one embodiment, the controller 122 and the multiple memory dies (together comprising the non-volatile storage system 100) implement a solid-state drive (SSD), which can emulate, replace, or substitute for hard disk drives in host devices (such as NAS devices), laptops, tablets, servers, etc. Additionally, the SSD does not need to function as a hard disk drive.

[0044] Some embodiments of a non-volatile memory system will include a memory die 108 connected to a controller 122. However, other embodiments may include multiple memory dies 108 communicating with one or more controllers 122. In one example, the multiple memory dies may be grouped into a set of memory packages. Each memory package includes one or more memory dies communicating with the controller 122. In one embodiment, the memory package includes a printed circuit board (or similar structure) on which one or more memory dies are mounted. In some embodiments, the memory package may include molding material to encapsulate the memory dies of the memory package. In some embodiments, the controller 122 is physically separate from any memory package.

[0045] In one embodiment, control circuitry (e.g., control circuitry 110) is formed on a first die called a control die, and a memory array (e.g., memory structure 126) is formed on a second die called a memory die. For example, some or all of the control circuitry associated with the memory (e.g., control circuitry 110, row decoder 124, column decoder 132, and read / write circuitry 128) may be formed on the same control die. The control die may be bonded to one or more corresponding memory dies to form an integrated memory assembly. The control die and memory die may have bonding pads arranged for electrical connection to each other. The bonding pads of the control die and memory die can be aligned and bonded together using any of a variety of bonding techniques, depending in part on the bonding pad size and bonding pad spacing (i.e., bonding pad pitch). In some embodiments, in a so-called Cu-Cu bonding process, the bonding pads are bonded directly to each other without solder or other additional material. In some examples, the dies are bonded in a one-to-one arrangement (e.g., one control die to one memory die). In some examples, more than one control die and / or more than one memory die may be present in the integrated memory assembly. In some embodiments, the integrated memory assembly includes a stack of multiple control dies and / or multiple memory dies. In some embodiments, the control die is connected to or otherwise communicates with a memory controller. For example, the memory controller may receive data to be programmed into a memory array. The memory controller forwards the data to the control die, allowing the control die to program the data into the memory array on the memory die.

[0046] Figure 2B It shows Figure 2A An alternative arrangement of the arrangement, which can be implemented using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B A functional block diagram of one embodiment of an integrated memory component 307 is depicted. One or more integrated memory components 307 may be used in a memory package in a memory system 100. The integrated memory component 307 includes two types of semiconductor dies (or more simply, "dies"). Memory die 301 includes a memory array 326 (memory structure 326, which may be any suitable memory as described with respect to memory structure 126). Memory array 326 may contain non-volatile memory cells.

[0047] The control die 311 includes column control circuitry 364, row control circuitry 320, and system control logic components 360 (including a state machine 312, a power control module 316, a storage device 366, and a memory interface 368). In some embodiments, the control die 311 is configured to connect to a memory array 326 in a memory die 301. Figure 2B An example of peripheral circuitry is shown, including control circuitry formed in the peripheral circuitry or control die 311, which is coupled to a memory array 326 formed in the memory die 301. System control logic unit 360, row control circuitry 320, and column control circuitry 364 are located in the control die 311. In some embodiments, all or a portion of the column control circuitry 364 and all or a portion of the row control circuitry 320 are located on the memory die 301. In some embodiments, some circuitry in the system control logic unit 360 is located on the memory die 301.

[0048] System control logic unit 360, row control circuitry 320, and column control circuitry 364 can be formed using conventional processes (e.g., CMOS processes), making it possible to add components and functions more commonly found on memory controller 102, such as ECC, with few or no additional process steps (i.e., the same process steps used to manufacture controller 102 can also be used to manufacture system control logic unit 360, row control circuitry 320, and column control circuitry 364). Therefore, while removing such circuitry from a die (e.g., memory die 301) reduces the number of steps required to manufacture such a die, adding such circuitry to a die (e.g., control die 311) may not require many additional process steps.

[0049] Figure 2B A column control circuit 364, including a sensing block 350, is shown on a control die 311. This column control circuit is coupled to a memory array 326 on a memory die 301 via an electrical path 370. For example, the electrical path 370 may provide electrical connections between the column decoder 332, the driver circuit 372, the block selector 373, and the bit lines of the memory array (or memory structure) 326. The electrical path may extend from the column control circuit 364 in the control die 311 through pads on the control die 311 that bond to corresponding pads on the memory die 301 that connect to the bit lines of the memory structure 326. Each bit line of the memory structure 326 may have a corresponding electrical path in the electrical path 370, including a pair of bonded pads connected to the column control circuit 364. Similarly, a row control circuit 320 (including a row decoder 324, an array driver 374, and a block selector 376) is coupled to the memory array 326 via an electrical path 308. Each electrical path in electrical path 308 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 311 and the memory die 301.

[0050] In some embodiments, the integrated memory assembly 307 contains more than one control die 311 and / or more than one memory die 301. In some embodiments, the integrated memory assembly 307 includes a stack of multiple control dies 311 and multiple memory dies 301. In some embodiments, each control die 311 is attached (e.g., bonded) to at least one memory die among the memory dies 301.

[0051] The exact type of memory array architecture or memory cell included in memory structure 326 is not limited to the examples described above. Many different types of memory array architecture or memory cell technologies can be used to form memory structure 326. Implementing the new embodiments claimed herein does not require a specific non-volatile memory technology. Other examples of technologies suitable for memory cells in memory structure 326 include ReRAM memory, magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), phase-change memory (e.g., PCM), etc. Examples of suitable technologies for the architecture of memory structure 326 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bitline arrays, etc.

[0052] An example of ReRAM, or PCMRAM, or crosspoint memory includes reversible resistive switching elements arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. Based on the physical repositioning of ions within a solid electrolyte, the conductive bridge memory element can be used as a state-changing element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, ion mobility also increases, leading to a decrease in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element can have a wide range of programming thresholds across the entire temperature range.

[0053] Magnetoresistive RAM (MRAM) stores data using magnetic storage elements. Each element consists of two ferromagnetic plates, each of which remains magnetized, separated by a thin insulating layer. One of these plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of an external magnetic field to store memory. The memory device is constructed from a grid of such memory cells. In one implementation for programming, each memory cell is located between a pair of write lines arranged perpendicular to each other, parallel to the cell, one above and one below. When current passes through them, an induced magnetic field is generated.

[0054] Phase-change memory (PCM) utilizes the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb₂Te₃ superlattice, achieving a non-thermal phase transition by simply changing the coordination state of germanium atoms with a laser pulse (or a light pulse from another source). Therefore, the programming dose is the laser pulse. Memory cells can be suppressed by preventing them from receiving light. It should be noted that the use of "pulse" in this document does not require a square pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage, light, or other waves.

[0055] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, but encompass many related memory structures within the technical essence and scope described herein and as understood by those skilled in the art.

[0056] Figure 3 This is a perspective view as part of an exemplary embodiment of a monolithic three-dimensional memory array that may include memory structures 126 or 326, the memory structure comprising a plurality of non-volatile memory cells. For example, Figure 3 A portion of a block of memory is shown. The depicted structure includes a set of bit lines BL, which sit above a stack of alternating dielectric and conductive layers. For example, one dielectric layer is labeled D, and one conductive layer (also referred to as a word line layer) is labeled W. The number of alternating dielectric and conductive layers can vary based on specific implementation requirements. One set of embodiments includes between 108 and 300 alternating dielectric and conductive layers. An example embodiment includes 96 data word line layers, 8 select layers, 6 dummy word line layers, and 110 dielectric layers. More or fewer than 108 to 300 layers may also be used. Data word line layers have data memory cells. Dummy word line layers have dummy memory cells. As will be explained below, the alternating dielectric and conductive layers are divided into four “finger” sections by local interconnects LI. Figure 3 Two finger-like portions and two local interconnects LI are shown. The source line layer SL lies beneath alternating dielectric and word line layers. Memory vias are formed within the stack of alternating dielectric and conductive layers. For example, one of these memory vias is labeled MH. It should be noted that in... Figure 3 In the diagram, the dielectric layers are depicted as a perspective view, allowing the reader to see the memory holes positioned within the stack of alternating dielectric and conductive layers. In one embodiment, NAND strings are formed by filling the memory holes with a material including a charge-trapping material to form vertical columns of memory cells. Each memory cell can store one or more data bits. The following is about... Figures 4A to 4H More details are provided for three-dimensional monolithic memory arrays, including memory structures of 126 or 326.

[0057] A local interconnect LI divides a block into two horizontal sub-blocks, HSB0 and HSB1. The block includes multiple vertical sub-blocks, VSB0, VSB1, and VSB2. The vertical sub-blocks VSB0, VSB1, and VSB2 may also be referred to as "hierarchies." In one embodiment, each vertical sub-block extends across the block. Each horizontal sub-block, HSB0 or ​​HSB1 in the block is a part of a vertical sub-block, VSB0. Similarly, each horizontal sub-block, HSB0 or ​​HSB1 in the block is a part of a vertical sub-block, VSB1. Likewise, each horizontal sub-block, HSB0 or ​​HSB1 in the block is a part of a vertical sub-block, VSB2. For discussion purposes, vertical sub-block VSB0 will be referred to as the lower vertical sub-block, vertical sub-block VSB1 will be referred to as the middle vertical sub-block, and VSB2 will be referred to as the upper vertical sub-block. In one embodiment, there are two vertical sub-blocks in the block. There may be four or more vertical sub-blocks in the block.

[0058] Memory operations for vertical sub-blocks can be performed on memory cells in one or more horizontal sub-blocks. For example, programming operations for memory cells in vertical sub-block VSB0 may include: programming memory cells in horizontal sub-block HSB0 but not in horizontal sub-block HSB1; programming memory cells in horizontal sub-block HSB1 but not in horizontal sub-block HSB0; or programming memory cells in both horizontal sub-blocks HSB0 and HSB1.

[0059] In one implementation, different vertical sub-blocks VSB0, VSB1, and VSB2 are treated as individual units for erasure / programming purposes. For example, memory cells in one vertical sub-block can be erased while valid data is retained in the other vertical sub-blocks. The memory cells in the erased vertical sub-block can then be programmed, while valid data is retained in the other vertical sub-blocks. In some cases, memory cells in the middle vertical sub-block VSB1 are programmed when valid data exists in the lower vertical sub-block VSB0 and / or the upper vertical sub-block VSB2.

[0060] Figure 4A This is a block diagram illustrating an exemplary organization of memory structure 126 or 326, which is divided into two planes 302 and 304. Each plane is then divided into M blocks. In one example, each plane has approximately 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, a block of memory cells is an erase unit. That is, all memory cells in a block are erased together. In other embodiments, memory cells may be grouped into blocks for other reasons, such as to organize memory structure 126 to enable signaling and selection circuitry. In some embodiments, a block represents a group of connected memory cells because the memory cells in a block share a common set of word lines.

[0061] Figures 4B to 4F An exemplary three-dimensional (“3D”) NAND structure is depicted, which corresponds to Figure 3 The structure, and can be used to implement Figure 2A memory structure 126 or Figure 2B The memory structure is 326. Figure 4B It is a block diagram depicting a top view of a portion of a block from memory structure 126. Figure 4B The part of the block depicted in the middle corresponds to Figure 4A Part 306 in block 2. From Figure 4B It can be seen from this that Figure 4B The block depicted extends along direction 332. In one embodiment, the memory array has multiple layers; however, Figure 4B Only the top layer is shown.

[0062] Figure 4B Multiple circles representing vertical columns are depicted. Each of these vertical columns includes multiple selection transistors (also called select gates or select cells) and multiple memory cells. In one implementation, each vertical column implements a NAND string. For example, Figure 4B Vertical columns 422, 432, 442, and 452 are depicted. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. More details about these vertical columns are provided below. Due to... Figure 4B The block depicted extends in the direction of arrow 333, therefore the block includes more than Figure 4B More vertical columns are depicted in the text.

[0063] Figure 4B A set of bit lines 415 is also depicted, including bit lines 411, 412, 413, 414, ..., 419. Figure 4B Twenty-four bit lines are shown because only a portion of the block is depicted. It is envisioned that more than twenty-four bit lines connect to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate its connection to a bit line. For example, bit line 414 connects to vertical columns 422, 432, 442, and 452.

[0064] Figure 4B The block depicted includes a set of local interconnects 402, 404, 406, 408, and 410 that connect the various layers to source lines below the vertical columns. Local interconnects 402, 404, 406, 408, and 410 also serve to divide each layer of the block into four regions; for example, Figure 4BThe top layer depicted is divided into regions 420, 430, 440, and 450, which are referred to as fingers. In the layer of the blocks implementing memory cells, these four regions are referred to as word line fingers, and these regions are separated by local interconnects. In one embodiment, word line fingers on the common level of the block are connected together to form a single word line. In another embodiment, word line fingers on the same level are not connected together. In one exemplary embodiment, the bit line is connected to only one vertical column in each of regions 420, 430, 440, and 450. In this embodiment, each block has sixteen active columns, and each bit line is connected to four rows in each block. In one embodiment, all four rows connected to the common bit line are connected to the same word line (via different word line fingers connected together on the same level); therefore, the system uses source-side select lines and drain-side select lines to select one (or a subset of another) of the four to be used for memory operations (programming, verification, reading, and / or erasing).

[0065] although Figure 4B The illustration shows four vertical columns per region within a block, four regions, and sixteen vertical columns, but these exact numbers are exemplary implementations. Other implementations may include more or fewer regions per block, more or fewer vertical columns per region, and more or fewer vertical columns per block.

[0066] Figure 4B It is also shown that the vertical columns are staggered. In other embodiments, different staggering patterns may be used. In some embodiments, the vertical columns are not staggered.

[0067] Figure 4C An implementation of stack 435 is depicted, showing along... Figure 4B A cross-sectional view of line AA. In addition to data word line layers WLL0 to WLL95, two SGD layers (SGD0, SDG1), two SGS layers (SGS0, SGS1), and six dummy word line layers DWLD0, DWLD1, DWLM1, DWLM0, DWLS0, and DWLS1 are provided. Each NAND string has a drain-side selected transistor at the SGD0 layer and a drain-side selected transistor at the SGD1 layer. In operation, the same voltage can be applied to each layer (SGD0, SGD1) such that the control terminal of each transistor receives the same voltage. Each NAND string has a source-side selected transistor at the SGS0 layer and a drain-side selected transistor at the SGS1 layer. In operation, the same voltage can be applied to each layer (SGS0, SGS1) such that the control terminal of each transistor receives the same voltage. Dielectric layers DL0–DL106 are also depicted.

[0068] Columns 432 and 434 of memory cells are depicted in a multilayer stack. The stack includes a substrate 303, an insulating film 250 on the substrate, and a portion of the source line SL. A portion of bit line 414 is also depicted. Note that NAND string 484 is connected to bit line 414. NAND string 484 has a source terminal 439 at the bottom of the stack and a drain terminal 438 at the top of the stack. Source terminal 439 is connected to source line SL. Conductive via 441 connects the drain terminal 438 of NAND string 484 to bit line 414. Also depicted is... Figure 4B Local interconnects 404 and 406.

[0069] Stack 435 is divided into three vertical sub-blocks (VSB0, VSB1, VSB2). Vertical sub-block VSB0 includes WLL0 to WLL31. The following layers can also be considered as part of vertical sub-block VSB0 (SGS0, SGS1, DWLS0, DWLS1). Vertical sub-block VSB1 includes WLL32 to WLL63. Vertical sub-block VSB2 includes WLL64 to WLL95. The following layers can also be considered as part of vertical sub-block VSB2 (SGD0, SGD1, DWLD0, DWLD1). Each NAND string has a set of data memory cells in each vertical sub-block. The dummy word line layer DMLM0 is located between vertical sub-block VSB0 and vertical sub-block VSB1. The dummy word line layer DMLM1 is located between vertical sub-block VSB1 and vertical sub-block VSB2. The dummy word line layer has dummy memory cells that can be used to electrically isolate the first set of memory cell transistors (e.g., corresponding to word lines WLL0 to WLL31 of vertical subblock VSB0) from the second set of memory cell transistors (e.g., corresponding to word lines WLL32 to WLL63 of vertical subblock VSB1) within the memory string during memory operations (e.g., erase operations or programming operations).

[0070] In another embodiment, stack 435 is divided into vertical sub-blocks using one or more intermediate bonding transistor layers. An intermediate bonding transistor layer containing bonding transistors does not necessarily contain a charge storage region. Therefore, bonding transistors are not typically considered dummy memory cells. Both bonding transistors and dummy memory cells may be referred to herein as “non-data transistors.” As used herein, a non-data transistor is a transistor on a NAND string that is configured not to store user data or system data, or operates in a manner that prevents the transistor from being used to store user data or system data. Word lines connected to non-data transistors are referred to herein as non-data word lines. Examples of non-data word lines include, but are not limited to, dummy word lines and select lines in intermediate bonding transistor layers.

[0071] Stack 435 may have more than three vertical sub-blocks. For example, stack 435 may be divided into four, five, or more vertical sub-blocks. Each vertical sub-block contains at least one data memory unit. Additional layers, such as intermediate dummy word line layers (DWLMs), may exist to divide stack 435 into additional vertical sub-blocks. In one embodiment, the stack has two vertical sub-blocks.

[0072] Figure 4D Depicting Figure 4C An alternative view of the SG layer and word line layer of the stack 435. SGD layers SGD0 and SGD0 (drain-side SG layer) each include rows of parallel SG lines associated with the drain side of a set of NAND strings. For example, SGD0 includes rows of parallel SG lines associated with the drain side of a set of NAND strings. Figure 4B Consistent drain-side SG regions 420, 430, 440, and 450.

[0073] Below the SGD layer is a drain-side dummy word line layer. In one approach, each dummy word line layer represents a word line and connects to a set of dummy memory cells at a given height in the stack. For example, DWLD0 includes word line layer regions 451, 453, 455, and 457. Dummy memory cells (also called non-data memory cells) do not store data and are unable to store data, while data memory cells are eligible to store data. Furthermore, the Vth of dummy memory cells is typically fixed at manufacturing time or can be periodically adjusted, while the Vth of data memory cells changes more frequently, for example, during erase and program operations of the data memory cells.

[0074] Below the dummy word line layer is the data word line layer. For example, WLL95 includes word line layer regions 471, 472, 473, and 474.

[0075] Below the data word line layer is the source-side dummy word line layer.

[0076] Below the source-side dummy word line layer is the SGS layer. SGS layers SGS0 and SGS1 (source-side SG layers) each include parallel rows of SG lines associated with the source side of a set of NAND strings. For example, SGS0 includes source-side SG lines 475, 476, 477, and 478. In one approach, each SG line can be controlled independently. Alternatively, these SG lines can be connected and controlled collectively.

[0077] Figure 4E Depicting Figure 4CA view of region 445. Data memory cell transistors 520 and 521 are located above dummy memory cell transistor 522. Data memory cell transistors 523 and 524 are located below dummy memory cell transistor 522. Multiple layers may be deposited, for example, along the sidewalls (SW) of memory via 444 and / or within each word line layer using atomic layer deposition. For example, each column (e.g., a pillar formed by material within the memory via) may include a blocking oxide / bulk high-k material 470, a charge trapping layer or film 463 (such as SiN or other nitrides), a tunnel layer 464, a polysilicon bulk or channel 465, and a dielectric core 466. The word line layer may include a conductive metal 462 (such as tungsten) serving as a control gate. For example, control gates 490, 491, 492, 493, and 494 are provided. In this example, all layers except the metal are provided within the memory via. In other methods, some of the layers may be within the control gate layer. Additional pillars are similarly formed in different memory vias. Pillars can form the columnar active regions (AA) of a NAND string.

[0078] When a data memory cell transistor is programmed, electrons are stored in a portion of the charge-trapping layer associated with the transistor. These electrons are attracted from the channel into the charge-trapping layer and then pass through the tunnel layer. The voltage (Vth) of the data memory cell transistor increases proportionally to the amount of stored charge. During an erase operation, the electrons return to the channel.

[0079] Non-data transistors (e.g., select transistors, dummy memory cell transistors) may also include a charge trapping layer 463. Figure 4E In this configuration, the dummy memory cell transistor 522 includes a charge trapping layer 463. Therefore, the threshold voltage of at least some non-data transistors can be adjusted by storing or removing electrons from the charge trapping layer 463. Not all non-data transistors need to have an adjustable Vth. For example, the charge trapping layer 463 does not need to be present in every select transistor.

[0080] Each memory via in the memory via may be filled with multiple annular layers, including a barrier oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. The core region of each memory via in the memory via is filled with the host material, and the multiple annular layers are located between the core region and the WLL in each memory via.

[0081] In some cases, tunnel layer 464 may include multiple layers, such as in an oxide-nitride-oxide configuration.

[0082] Figure 4F yes Figures 3 to 4E A schematic diagram depicting a portion of the memory. Figure 4FThe physical word lines WL0 to WL95, which extend across the entire block, are shown. Figure 4F The structure corresponds to Figures 4A to 4E Section 306 of block 2 includes bit lines 411, 412, 413, 414, ..., 419. Within this block, each bit line is connected to four NAND strings. Drain-side select lines SGD0, SGD1, SGD2, and SGD3 are used to determine which of the four NAND strings is connected to the associated bit line. Source-side select lines SGS0, SGS1, SGS2, and SGS3 are used to determine which of the four NAND strings is connected to the common source line. It is also possible to divide this block into four horizontal sub-blocks: HSB0, HSB1, HSB2, and HSB3. Horizontal sub-block HSB0 corresponds to the vertical NAND strings controlled by SGD0 and SGS0, horizontal sub-block HSB1 corresponds to the vertical NAND strings controlled by SGD1 and SGS1, horizontal sub-block HSB2 corresponds to the vertical NAND strings controlled by SGD2 and SGS2, and horizontal sub-block HSB3 corresponds to the vertical NAND strings controlled by SGD3 and SGS3.

[0083] Figure 4G This is a schematic diagram of the horizontal sub-block HSB0. Horizontal sub-blocks HSB1, HSB2, and HSB3 have similar structures. Figure 4G The physical word lines WL0 to WL95, extending across the entire sub-block S0, are shown. All NAND strings in sub-block S0 are connected to SGD0 and SGS0. Figure 4G Only six NAND strings, 501, 502, 503, 504, 505, and 506, are depicted; however, the horizontal sub-block HSB0 will have thousands of NAND strings (e.g., 15,000 or more).

[0084] Figure 4G This concept is used to explain the selection of memory cells. Memory operations are operations designed for the purpose of using memory and include one or more of the following: reading data, writing / programming data, erasing memory cells, and refreshing data in memory cells. During any given memory operation, a subset of memory cells will be identified as undergoing one or more memory operations. These memory cells identified as undergoing memory operations are called selected memory cells. These memory cells not identified as undergoing memory operations are called unselected memory cells. Depending on the memory architecture, memory type, and memory operation, unselected memory cells may be actively or passively excluded from undergoing memory operations.

[0085] As an example of selected and unselected memory cells, during programming, the set of memory cells intended to adopt new electrical characteristics (or other characteristics) to reflect the changed programming state are called selected memory cells, while memory cells not intended to adopt new electrical characteristics (or other characteristics) to reflect the changed programming state are called unselected memory cells. In some cases, unselected memory cells may be connected to the same word line as selected memory cells. Unselected memory cells may also be connected to different word lines than selected memory cells. Similarly, during reading, the set of memory cells to be read is called selected memory cells, while memory cells not intended to be read are called unselected memory cells.

[0086] To better understand the concepts of selected and unselected memory cells, assume that a programming operation is to be performed, and for illustrative purposes only, word line WL94 and horizontal subblock HSB0 are selected for programming (see [link to documentation]). Figure 4G This means that all memory cells connected to WL94 in horizontal subblocks HSB1, HSB2, and HSB3 (other horizontal subblocks) are unselected memory cells. Some memory cells connected to WL94 in horizontal subblock HSB0 are selected memory cells, and some memory cells connected to WL94 in horizontal subblock HSB0 are unselected memory cells, depending on how the programming operation is performed and how the data pattern is programmed. For example, those memory cells used to remain in the erase state S0 will be unselected memory cells because their programming state will not change in order to store the desired data pattern, while those memory cells designed to adopt new electrical characteristics (or other characteristics) to reflect the changed programming state (e.g., programmed to states S1 through S7) are selected memory cells. See also Figure 4G Assuming that, for illustrative purposes, memory cells 511 and 514 (which are connected to word line WL94) remain in an erased state; therefore, memory cells 511 and 514 are unselected memory cells. Figure 4G (marked as unsel). Additionally, it is assumed that, for illustrative purposes, memory cells 510, 512, 513, and 515 (these memory cells are connected to word line WL94) will be programmed to any of the data states S1 through S7; therefore, memory cells 510, 512, 513, and 515 are selected memory cells ( Figure 4G (marked as sel). Although some memory cells along WL94 can be considered unselected memory cells because these memory cells are used to remain in an erased state, in this case, WL94 can be considered a “selected word line” because selected memory cells 510, 512, 513 and 515 are connected to WL94 and accessed via WL94.

[0087] Figure 4H This is a schematic diagram of a NAND string. A NAND string of 600 is similar to... Figure 4C The NAND string 484 has intermediate junction transistors to separate vertical sub-blocks. The NAND string 600 includes: a first portion of the NAND string (e.g., corresponding to vertical sub-block VSB0), a second portion of the NAND string (e.g., corresponding to vertical sub-block VSB1), a third portion of the NAND string (corresponding to vertical sub-block VSB2), an intermediate junction transistor (MJT1) 614 disposed between the first portion of the NAND string and the second portion of the NAND string, and an intermediate junction transistor (MJT2) 620 disposed between the second portion of the NAND string and the third portion of the NAND string.

[0088] The first portion of the NAND string has memory cells 610 to 612 connected to word lines WLL0 to WLL31. The second portion of the NAND string has memory cells 616 to 618 connected to word lines WLL32 to WLL63. The third portion of the NAND string has memory cells 622 to 624 connected to word lines WLL64 to WLL96. Figure 4H This does not depict all memory cells of the NAND string 600. The NAND string 600 also includes: a first source-side select-gate transistor 602 connected to SGS0; a second source-side select-gate transistor 604 connected to SGS1; two dummy memory cell transistors 606 and 608 connected to DWLS0 and DWLS1 respectively; two dummy memory cell transistors 626 and 628 connected to DWLD0 and DWLD1 respectively; a drain-side select-gate transistor 630 connected to SGD1; and a drain-side select-gate transistor 632 connected to SGD0. The drain-side select-gate transistor 632 is connected to the bit line (BL). The first source-side select-gate transistor 602 is connected to the source line (SL). In one embodiment, a dummy memory cell transistor is present on each side of each intermediate junction transistor 614, 618.

[0089] Depending on the implementation, each intermediate junction transistor 614, 618 may be a programmable transistor (such as a floating gate transistor or a charge-trapping transistor) or a non-programmable transistor (such as an NMOS transistor or a PMOS transistor). Each intermediate junction transistor 614, 618 may include an NMOS transistor without a charge-trapping layer between the channel and the gate of the NMOS transistor. In some implementations, one intermediate junction transistor 614, 618 may include a programmable transistor, and the other intermediate junction transistor 614, 618 may include a non-programmable transistor. Each intermediate junction transistor 614, 618 may have a transistor channel length different from the transistor channel length used for the memory cell transistor. This channel length may be greater than any transistor channel length used for the memory cell transistor. For example, the channel length may be twice as large as the transistor channel length used for the memory cell transistor. When the intermediate junction transistor is set to a non-conductive state, each intermediate junction transistor 614, 618 may electrically isolate memory cell transistors in different vertical subblocks.

[0090] Although Figures 3 to 4H An exemplary memory system is a three-dimensional memory structure comprising vertical NAND strings with charge-trapping material, but other (2D and 3D) memory structures can also be used with the techniques described herein. The various operations (e.g., read, program, program verification) described below for accessing data in non-volatile memory cells can be applied to the above-described... Figures 1 to 4H One or more of the example memory systems described.

[0091] Typically, during programming operations (via a selected word line), the programming voltage applied to the control gate is a series of programming pulses. Between the programming pulses is a set of verification pulses to perform verification. In many implementations, the amplitude of the programming pulses increases by a predetermined step size with each successive pulse.

[0092] In one implementation, a set of memory cells selected for programming (referred to herein as the selected memory cells) are programmed simultaneously and all connected to the same word line (the selected word line). Other memory cells not selected for programming (unselected memory cells) may also be connected to the selected word line. That is, the selected word line will also be connected to memory cells that should be disabled for programming. For example, when data is written to a set of memory cells, some memory cells will need to store data associated with an erase state, making these memory cells unprogrammable. Furthermore, when memory cells reach their intended target data state, they will be disabled for further programming. These NAND strings (e.g., unselected NAND strings) boost their channels to disable programming; these strings include the memory cells to be disabled for programming connected to the selected word line. When the channel has a boosted voltage, the voltage difference between the channel and the word line is insufficient to induce programming.

[0093] Figure 5 The threshold voltage distribution for eight data states S0 to S7 is shown, corresponding to three bits of data for each cell (three-level cells or TLC). Seven read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 for reading data from the memory cell are also shown. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is higher or lower than the seven read reference voltages, the system can determine the data state (i.e., S0, S1, S2, S3, ...) of the memory cell.

[0094] Figure 5The diagram also illustrates the seven verification reference voltages Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 used in the read verification step during the programming operation. When a memory cell is programmed to data state S1, the system tests whether these memory cells have a threshold voltage greater than or equal to Vv1. When a memory cell is programmed to data state S2, the system tests whether the memory cell has a threshold voltage greater than or equal to Vv2. When a memory cell is programmed to data state S3, the system determines whether the memory cell has a threshold voltage greater than or equal to Vv3. When a memory cell is programmed to data state S4, the system tests whether these memory cells have a threshold voltage greater than or equal to Vv4. When a memory cell is programmed to data state S5, the system tests whether these memory cells have a threshold voltage greater than or equal to Vv5. When a memory cell is programmed to data state S6, the system tests whether these memory cells have a threshold voltage greater than or equal to Vv6. When a memory cell is programmed to data state S7, the system tests whether these memory cells have a threshold voltage greater than or equal to Vv7. Figure 6 also shows Vev, which is the voltage level used to test whether a memory cell has been correctly erased (e.g., whether the memory cell is in data state S0).

[0095] In one implementation known as full-sequence programming, memory cells can be directly programmed from an erased data state S0 to any of the programmed data states S1 through S7. For example, a group of memory cells to be programmed can be erased first, leaving all memory cells in the group in an erased data state S0. Then, a programming process is used to directly program the memory cells into data states S1, S2, S3, S4, S5, S6, and / or S7. For example, while some memory cells are being programmed from data state S0 to data state S1, other memory cells are being programmed from data state S0 to data state S2 and / or from data state S0 to data state S3, and so on. Figure 5 The arrow indicates full-sequence programming. In some implementations, data states S1 through S7 may overlap, where controller 122 relies on error correction to identify the correct data being stored.

[0096] In addition to full-sequence programming, the techniques described herein can also be used with other types of programming, including but not limited to multi-level programming / multi-phase programming. In one implementation of multi-level programming / multi-phase programming, in the first stage, all memory cells ending in any of data states S4 through S7 are programmed to an intermediate state no higher than S4. In the first stage, memory cells ending in any of data states S0 through S3 are not programmed. In the second stage, memory cells ending in any of data states S2 or S3 are programmed to a state no higher than S2; memory cells ending in any of data states S6 or S7 are programmed to a state no higher than S6. In the third stage, these memory cells are programmed to their final state. In one implementation, a first page is programmed in the first stage, a second page is programmed in the second stage, and a third page is programmed in the third stage. As described herein, once a page has been programmed into a set of memory cells, the memory cells can be retrieved by reading the memory cells. Therefore, intermediate states associated with multi-phase programming are considered programming states herein.

[0097] Generally, during the sensing phase of both the verification and read operations, the selected word line is connected to a voltage (an example of a reference signal), the level of which is specified for each read operation (see, for example, [reference]). Figure 5 The read comparison levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7) or the verification operation (e.g., see [link to relevant documentation]). Figure 5 The verification target levels (Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7) are specified to determine whether the threshold voltage of the relevant memory cell has been reached. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, then it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verification process, unselected memory cells are provided with one or more read pass voltages (also known as bypass voltages) at their control gate, causing these memory cells to conduct current as if they were being operated through the gate (e.g., conducting current regardless of whether these memory cells are being programmed or erased).

[0098] Numerous methods exist for measuring the conduction current of a memory cell during sensing in a read or verification operation. In one example, the conduction current of the memory cell is measured as the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or disallows) the NAND string of the memory cell to discharge to the corresponding bit line. The voltage on the bit line is measured after a certain period to see if it has discharged. It should be noted that the techniques described herein can be used in conjunction with various methods known in the art for sensing during a verification or read operation. Other read and verification techniques known in the art may also be used.

[0099] Figure 5 Two examples of overdrive voltages V_OD1 and V_OD2 are also shown, which can be applied to the control gate of a data memory cell. Both overdrive voltages are higher than all data states S0 through S7. Therefore, these overdrive voltages will be higher than the threshold voltage of the data memory cell in any of the data states S0 through S7. During memory access (e.g., during the programming or program verification step of a programming operation, or during the read step of a read operation), when overdrive voltages are applied to the control gate of a data memory cell, these overdrive voltages are sufficient to make the memory cell operate as if it were in a gate-through state (e.g., conducting current or "on"), regardless of whether the memory cell is in a programming state (e.g., S1 through S7) or an erase state (e.g., S0). In some examples, two different overdrive voltages (e.g., V_OD1 and V_OD2) are applied to different word lines connected to the same NAND string during programming or sensing (read or verification) operations. For example, when accessing a memory cell connected to a selected word line in a selected sub-block, a first overdrive voltage V_OD1 may be applied to an unselected word line in the selected sub-block connected to the memory cell, while a second (e.g., lower) overdrive voltage V_OD2 may be applied to an unselected word line in one or more unselected sub-blocks connected to the programmable memory cell.

[0100] In one embodiment, the system uses one or more "bypass voltages" during memory access. In one embodiment, the bypass voltage is at least VeV, but no greater than Vv7. For example, these bypass voltages could be Vr1, Vv1, Vv2, etc. Therefore, during the precharge phase of a programming operation, when the bypass voltage is applied to the control gate of a data memory cell, if the memory cell is in an erase state, these bypass voltages will cause the memory cell to operate as a pass-through (e.g., become conductive or "on"), but for at least one programming state, the memory cell will not operate as a pass-through.

[0101] Figure 6AAn example of a portion of a memory structure (e.g., a portion of memory structure 126 or 326) is shown, comprising two vertical sub-blocks, VSB0 and VSB1, each containing non-volatile memory cells connected in series within NAND strings 811, 815, 817, and 819. The first vertical sub-block, VSB0, includes first word lines WL0 to WL5. The second vertical sub-block, VSB1, includes second word lines WL6 to WL11. The first word lines WL0 to WL5 and the second word lines WL6 to WL11 are data word lines, separated by a non-data word line (dummy word line DWL1) coupled to a non-data transistor. NAND strings 811, 815, 817, and 819 are connected to a bit line (BL) at the top and a source line (SL) at the bottom.

[0102] exist Figure 6A In the example, the first vertical subblock VSB0 includes a selected word line WL3 and may therefore be referred to as a selected subblock. VSB0 includes unselected word lines WL4 and WL5 connected to programmable memory cells, and unselected word lines WL0 to WL2 connected to unprogrammed memory cells (memory cells along the selected word line WL3 may be programmed, unprogrammed, or partially programmed; for example, WL3 may be undergoing a programming operation that may include programming steps and verification steps).

[0103] In this example, the second vertical sub-block VSB1 is an unselected sub-block. Because NAND strings 811, 815, 817, and 819 extend through the first sub-block VSB0 and the second sub-block VSB1, these sub-blocks are connected, and when accessing a selected sub-block, both sub-blocks (not just the selected sub-block) can be appropriately biased. For example, when accessing the selected word line WL3 in VSB0, appropriate voltages can be applied to the second word lines WL6 through WL11 of VSB1 to ensure that NAND strings 811, 815, 817, and 819 are fully conductive. Similarly, when accessing word lines in VSB1, appropriate voltages can be applied to the first word lines WL0 through WL5 to ensure that NAND strings 811, 815, 817, and 819 are fully conductive.

[0104] Accessing (e.g., reading or programming) a memory cell along a NAND string can affect other memory cells along that NAND string. In structures comprising NAND strings extending between two or more sub-blocks, accessing a memory cell in one sub-block can affect memory cells in connected sub-blocks. For example, repeated reads (read interference) or repeated writes (write interference) can cause data storage to be disturbed. These effects can be particularly problematic when sub-blocks are managed individually (e.g., containing logically unrelated data and being written to and erased independently). In this case, a sub-block can be repeatedly written to, read from, and erased while connected sub-blocks continue to store the same data, which can be disturbed by repeated access to adjacent sub-blocks of that connected sub-block. Disturbance can have a greater impact on memory structures where each cell stores more than one bit (e.g., because the threshold voltage range for different data states is narrower). Therefore, reducing the impact of interference can be particularly beneficial for structures arranged in sub-blocks and in memory structures where each cell stores more than one bit (e.g., Figure 5 (TLC arrangement shown in the figure).

[0105] Figure 6A An example of voltages that can be applied to both the selected subblock (VSB0) and the unselected subblock (VSB1) to mitigate interactions between subblocks is shown. For example, a biasing scheme according to the example shown herein can address the technical problem of interference in a memory structure with multiple subblocks. The voltages applied to the different lines are shown to the left of the corresponding lines. In the selected subblock, all unselected word lines (WL0 to WL2 and WL4 to WL5) receive an applied first overdrive voltage V_OD1, such that all memory cells along these unselected word lines are turned on (regardless of whether the memory cells are programmed). V_OD1 can be a relatively high voltage that raises the channel voltage along either side of the selected word line WL3 in the selected subblock.

[0106] In the unselected subblock VSB1, a second overdrive voltage V_OD2 is applied to all word lines (WL6 to WL8) connected to the programmable memory cell. The second overdrive voltage V_OD2 can be a lower voltage than the first overdrive voltage V_OD1 (e.g., as shown in the image). Figure 5(As shown). The word lines (WL9 to WL11) connected to the unprogrammed memory cells receive a bypass voltage (Vbypass) sufficient to turn on the unprogrammed memory cells located along WL9 to WL11. As shown, using relatively low voltages (V_OD2 less than V_OD1, and Vbypass less than both V_OD2 and V_OD1) in the unselected subblock VSB1 generally reduces unwanted interactions between subblocks and results in less interference, thus providing a lower error rate (especially in memory structures where more than one bit is stored per cell).

[0107] Although Figure 6A Examples of two linker subblocks, VSB0 and VSB1, are shown, programmed with an intermediate output sequence (programmed from DWL1). However, aspects of this technique can be applied to any suitable memory, such as any number of linker subblocks, any number of word lines per subblock, any number of bits stored per cell, and any suitable programming sequence.

[0108] Figure 6B An example of a portion of a memory structure (e.g., a portion of memory structure 126 or 326) is shown, comprising NAND strings 811, 815, 817, and 819 extending through three vertical sub-blocks VSB0, VSB1, and VSB2. The first vertical sub-block VSB0 includes first word lines WL0 to WL5. The second vertical sub-block VSB1 includes second word lines WL6 to WL11. The third vertical sub-block VSB2 includes third word lines WL12 to WL17. The first word lines WL0 to WL5 and the second word lines WL6 to WL11 are data word lines, and the first and second word lines are separated by a non-data word line (dummy word line DWL1) coupled to a non-data transistor. The third word lines WL12 to WL17 are data word lines and are separated from the second word lines WL6 to WL11 by a non-data word line (dummy word line DWL2), which is coupled to a non-data transistor. NAND strings 811, 815, 817, and 819 are connected to the bit line (BL) at the top and to the source line (SL) at the bottom.

[0109] exist Figure 6BIn the example shown, the selected word line WL7 (e.g., for the purpose of reading or writing) is located in VSB1, making VSB1 the selected subblock, and VSB0 and VSB2 are unselected subblocks. The control circuit applies a first overdrive voltage V_OD1 to the unselected word lines (WL6 and WL8 to WL11 of VSB1) of the selected subblock to turn on the corresponding memory cells and boost the channels in the selected subblock VSB1. In both the unselected subblocks VSB0 and VSB2, the word lines connected to the programmable memory cells receive a second overdrive voltage V_OD2, and the word lines connected to the unprogrammable memory cells receive a bypass voltage Vbypass. For example, in VSB0, WL0 to WL3 receive V_OD2, while WL4 to WL5 receive Vbypass. In VSB2, WL12 to WL14 receive V_OD2, while WL15 to WL17 receive Vbypass. Therefore, in this example, the same biasing scheme is applied to all unselected sub-blocks (with different voltages for programmed and unprogrammed memory cells). In other examples, different biases can be applied to the word lines of different sub-blocks. Such biasing schemes can be extended to any number of sub-blocks, each containing any number of word lines, NAND strings, and other components, and this technique is not limited to the example shown.

[0110] Figure 7A An example is shown of accessing a selected word line in a selected vertical sub-block of any suitable memory structure (e.g., memory structure 126 or 326), which accesses word lines in one or more unselected vertical sub-blocks (e.g., such as...). Figures 6A to 6B (As shown) At least two different voltages are applied. The steps shown in this method and other methods described below can be performed by one or more suitable control circuits (e.g., control circuit 110 and / or read / write circuit 128; system control logic unit 360, row control circuit 320 and / or column control circuit 364; or other suitable control circuits that may be located on the same die as the memory structure being accessed, may be located on different dies, or some combination thereof). The method includes the steps of: identifying a selected word line 7002 in a selected subblock (e.g., a word line connected to a memory cell to be programmed or read), and identifying an unselected subblock 7004 connected to the selected subblock (e.g., as shown). Figures 6A to 6B(As shown). The method further includes: locating the boundary 7006 between the write portion and the unwrite portion of the unselected subblock; applying a first voltage 7008 to the word lines of the write portion of the unselected subblock; and applying a second voltage 7010 to the word lines of the unwrite portion of the unselected subblock. The boundary can be located by any suitable method, and examples are described below. In some cases, the subblock may be completely written or completely unwriteable, in which case a single voltage (either the first voltage or the second voltage, depending on the situation) may be applied to all word lines of the subblock. The method further includes: accessing the selected word lines in the selected subblock 7012 while applying the first voltage and the second voltage to the word lines of the unselected block (although steps 7008, 7010, and 7012 are shown sequentially, the first voltage and the second voltage are maintained for a period of time including accessing the selected subblock). Access can mean, for example, programming a memory cell along a selected word line (e.g., by applying one or more programming pulses to the selected word line), or sensing a memory cell along a selected word line (e.g., as a programming verification step during a programming operation, or as part of a read operation to obtain data requested by a read command). During such access operations, appropriate voltages may be applied to other components (e.g., unselected word lines, dummy word lines, select lines, bit lines, and select lines of the selected subblock).

[0111] Figure 7B This illustrates a method for programming memory cells connected to selected word lines. Figure 7A An example of the method. Step 7002 includes identifying selected word lines in the selected subblock for programming (e.g., in response to a programming command that designates a specific word line in a memory structure as a data storage destination). The method includes: identifying unselected subblocks connected to the selected subblock 7004; locating the boundary between the write portion and the unwrite portion of the unselected subblock 7006; applying a first voltage 7008 to the word lines of the write portion of the unselected subblock; and applying a second voltage 7010 to the word lines of the unwrite portion of the unselected subblock as described above. The method also includes: applying a series of programming pulses 7014 on the selected word lines while applying the first and second voltages to the word lines of the unselected subblock. For example, applying V_OD2 and Vbypass (as described above) Figures 6A to 6B While (as shown), one or more programming pulses are applied to raise the threshold voltage of the memory cell (e.g., ...). Figure 5 (As shown).

[0112] Figure 7C This illustrates a method for verifying or reading memory cells connected to selected word lines. Figure 7A An example of a method. Step 7002 includes identifying selected word lines within a selected sub-block for verification or reading. For example, in a... Figure 7BFollowing the programming steps shown, a verification step may occur during programming of the memory cell connected to the selected word line, such that the selected word line is indicated by a programming command. Such programming and verification steps may be performed alternately until the programming operation is complete. The selected word line for reading may be indicated by a read command (e.g., a command for reading and returning data stored in the memory cell along a specific word line). The method includes: identifying an unselected sub-block 7004 connected to the selected sub-block; locating the boundary 7006 between the write portion and the unwrite portion of the unselected sub-block; applying a first voltage 7008 to the word line of the write portion of the unselected sub-block; and applying a second voltage 7010 to the word line of the unwrite portion of the unselected sub-block as described above. The method also includes: sensing the memory cell connected to the selected word line while applying the first and second voltages to the word line of the unselected sub-block. For example, in... Figures 6A to 6B As shown, while applying V_OD2 and Vbypass, by applying [the following] to the selected word lines... Figure 5 One or more verification voltages Vv1 to Vv7 are applied to the selected word line, while current through NAND strings 811, 815, 817, and 819 is sensed during the verification step, or memory cells are sensed along the selected word line by applying one or more read voltages Vr1 to Vr7 to the selected word line, while current through NAND strings 811, 815, 817, and 819 is sensed during the read step.

[0113] Figure 7D It shows in such as Figures 6A to 6B Examples of methods using this technology in structures shown in the examples are provided. The method includes: identifying one or more unselected vertical sub-blocks 7020 connected to selected vertical sub-blocks in a non-volatile memory array comprising NAND strings extending through two or more vertical sub-blocks; locating a boundary 7022 between programmed and unprogrammed portions of the one or more unselected vertical sub-blocks; and applying a first voltage to word lines of the unselected vertical sub-blocks connected to programmed non-volatile memory cells during programming or sensing of non-volatile memory cells in the selected vertical sub-blocks, and applying a second voltage 7024 to word lines of the unselected vertical sub-blocks connected to unprogrammed non-volatile memory cells.

[0114] Figure 7DThe steps shown can be performed by any suitable control circuitry, including, for example, control circuitry 110 and / or read / write circuitry 128; system control logic unit 360, row control circuitry 320, and / or column control circuitry 364. Such control circuitry can be considered as a means to: apply a read voltage or programming pulse to selected word lines of a first set of data word lines for reading or programming memory cells along the selected word lines, while simultaneously applying an overdrive voltage to all programmed data word lines in a second set of data word lines, and applying a bypass voltage to all unprogrammed data word lines in the second set of data word lines.

[0115] The boundary between the written and unwritten portions of an unselected subblock can be located using any suitable method. In some memory systems, control information can be maintained to indicate specific information about the subblock. For example, the control information may indicate whether the block is fully programmed (closed), partially programmed (open), or completely unprogrammed (erased). In the case of closing or erasing an unselected subblock, all word lines can be processed similarly, and the same voltage can be applied to all such word lines (e.g., a suitable overdrive voltage (such as V_OD2) can be applied to all word lines of a closed block, and a suitable bypass voltage (such as Vbypass) can be applied to all word lines of an erased block). In the case of an open subblock, the control information may indicate where the boundary between the written and unwritten portions is located. In this case, finding the boundary may include accessing the relevant control information. In other cases, such control information is unavailable or unreliable (e.g., after an unexpected power outage, when the control information may not have been saved from volatile memory to non-volatile memory before the power outage), and the unselected subblock can be searched to find the boundary.

[0116] Figure 8A This illustrates a method for searching for unselected sub-blocks that are connected to a selected sub-block (e.g., for finding...). Figures 7A to 7C The first example of the boundary method in step 7006. This method includes applying an overdrive voltage 830 to all word lines of the selected sub-block (e.g., to...). Figure 6B A first overdrive voltage V_OD1 is applied to WL6 through WL11 of VSB1. An overdrive voltage (e.g., 7 volts) can also be applied to all word lines of any other unselected sub-block besides the searched sub-block, such that all memory cells of the NAND string connected outside the searched sub-block are conductive (e.g., when in...). Figure 6AWhen searching for boundaries in the unselected subblock VSB0, word lines WL12 to WL17 of the unselected subblock VSB2 may receive overdrive voltages such as V_OD1 or V_OD2. The method includes: setting the variable “n” to zero (n=0) 832, where n indicates the word line being checked as programmed / unprogrammed; applying a bypass voltage (e.g., 0 volts) 834 to WLn of the unselected subblock; and applying an overdrive voltage (e.g., 7 volts) 836 to all other word lines of the unselected subblock. It is then determined whether the NAND string is conducting 838 (e.g., by measuring the current flowing through NAND strings 811, 815, 817, 819). Because some memory cells remain in the S0 data state even when the memory cells are being programmed, a single conducting NAND string may not be sufficient to indicate the unprogrammed state of memory cells along the word line. The results of sensing multiple NAND strings (e.g., average current, the number of NAND strings exceeding the expected current, or some other combination of results) can be used. If the NAND string is conductive when a bypass voltage is applied to WLn, then WLn is connected to an unprogrammed memory cell, and the boundary lies between WLn and WLn-1 840. If the NAND string is conductive when n=0 (the first word line of the sub-block), the block is erased when the selected word line of the selected sub-block is accessed, and a bypass voltage (e.g., Vbypass) can be applied to all word lines of the unselected sub-block. If the NAND string is not conductive, it is determined whether word line WLn is the last word line of the sub-block, n=maximum value 842. If n=maximum value, the unselected sub-block is fully programmed (closed) 844, and an overdrive voltage (e.g., V_OD2) can be applied to all word lines of the unselected sub-block while the selected word line of the selected sub-block is accessed. If WLn is not the last word line (n≠maximum value), then n is incremented to n+1 846, and the next word line is checked until a boundary is found or the last word line is reached.

[0117] The word lines are checked in the order they were programmed. Therefore, for example, in... Figure 6B In the unselected subblock VSB0, the first word line checked can be WL0, followed by WL1, WL2, etc., such that the indicated numbering indicates the order of checks. The bypass voltage applied to any of WL0 through WL3 is insufficient to conduct NAND strings 811, 815, 817, and 819 (at least on average) because these NAND strings are programmed and have high threshold voltages (e.g., corresponding to...). Figure 5 (Data states S1 to S7). The bypass voltage applied to WL4 is sufficient to conduct NAND strings 811, 815, 817, and 819, since only unprogrammed memory cells are connected to WL4. Therefore, Figure 8A The method is applied to Figure 6BVSB0 includes incrementing n up to n=4 and searching for boundaries between WL3 and WL4. When searching for boundaries in an unselected subblock VSB2, WL12 can be the first word line to be checked, followed by WL13, WL14, and so on. The value of n can be biased accordingly (e.g., n can be initialized to 12 instead of zero). In some cases (e.g., using center-output programming), word lines can be checked in a different order, with some subblocks checking from the lowest to the highest word line according to the programming order, and others checking from the highest to the lowest word line according to the programming order (e.g., in some subblocks, n can be biased and can be decremented instead of incremented).

[0118] like Figure 8A As shown, while searching for boundaries one word line at a time sequentially is one method, another method uses a binary search tree, which reduces the number of steps required to find boundaries. According to this method, the word line at the center of the sub-block is first examined to determine which half of the sub-block contains the boundary. Then, the word line at the center of that half of the sub-block is examined to determine which quarter contains the boundary. These successive steps reduce the search area by half until the boundary is found.

[0119] Figure 8B A sub-block with 34 word lines is shown, comprising 7 word lines (0 to 6) connected to programmable memory cells and 25 word lines (7 to 33) connected to unprogrammable memory cells. Using a sequential search might require seven sensing operations corresponding to word lines 0 to 7 (in the programming order from word line 0). If the boundary is higher, more steps would be needed (e.g., if the boundary location is random, then on average, the boundary would be between word lines 16 and 17, requiring 18 sequential steps to find). Conversely, using a binary search method involves a first check at the center of the sub-block, i.e., at word line 16, where the sub-block is unprogrammed, indicating the boundary is in the lower half of the sub-block (between 0 and 16). A second check at the center of the lower half, i.e., at word line 8, indicates the boundary is in the lower quarter of the sub-block (between 0 and 8). A third check at the center of the lower quarter, i.e., at word line 4, indicates the boundary is in the upper part of the lower quarter (between 4 and 8). The fourth check, performed at the center of the upper portion of the lower quarter, i.e. at word line 6, indicates that the boundary is above word line 6 (between 6 and 8). The fifth check, performed at word line 7, indicates that the boundary is below word line 7, such that the boundary is determined to be between word lines 6 and 7 (e.g., word lines 0 to 6 are connected to programmed memory cells, and word lines 7 to 33 are connected to unprogrammed memory cells).

[0120] Figure 8C This illustrates a method for implementing binary search operations (e.g., using...). Figure 8B The binary search operation shown in is applied to Figure 6A or Figure 6B the unselected sub-block). The method includes: applying an over-drive voltage 850 to all word lines of the selected sub-block (e.g., the sub-block containing the selected word lines for programming or sensing); and setting a first variable L to 0 and a second variable H to N: setting L = 0 and setting H = N, 852. These variables respectively correspond to the lowest word line (WLL) within the search range to be searched and the highest word line (WLH) within the search range to be searched. These variables can be initialized to the lowest word line (WL0) in the sub-block and the highest word line (WLN in the sub-block, where there are N + ¹ word lines in the sub-block, e.g., in Figure 8B the example of N = 33). Thus, the initial range to be searched includes all word lines of the sub-block. Determine whether L + 1 is less than H, 854, and if so (e.g., at initialization L + 1 = 1, 1 < 34), then set the variable n (corresponding to the word line to be checked) to (L + H) / 2, 856 (e.g., WL16, which is Figure 8A the target of the first check in). The method includes: applying a bypass voltage (e.g., 0 volts) to WLn, 858; applying an over-drive voltage (e.g., 7 volts) to all other word lines of the unselected sub-block, 860; and determining whether the NAND string is conductive, 862 (e.g., by sensing the current passing through the NAND string). If the NAND string is conductive, then WLn is connected to an unprogrammed memory cell, such that the boundary is below WLn, and the upper boundary of the next search region is set at WLn by setting H = n, 864. If the NAND string is not conductive, then WLn is connected to a programmed memory cell, such that the boundary is above WLn, and the lower boundary of the next search region is set at WLn by setting L = n, 866. Then determine whether L + 1 < H, with the new value of H or L, 854. If L + 1 remains less than H (e.g., after the first check in Figure 8B 1 < 16), then set n to (L + H) / 2 with the new value (e.g., for Figure 8B the second check in, n = 8), and sense WLn by applying a bypass voltage to WLn, 858, applying an over-drive voltage to all other word lines of the unselected sub-block, 860, and determining whether the NAND string is conductive, 862. If the NAND string is conductive, then set H to n, 846 (e.g., after the second check in Figure 8B set n to 8, such that the range is from WL0 to WL8), and if the NAND string is not conductive, then set L to n, 866 (e.g., after Figure 8AAfter the third check of WL4, set L to 4, such that the range is from WL4 to WL8). The method continues until it is determined in step 854 that L+1<H is not true (for example, when H is set to 7 after the fifth check and L is set to 6 after the fourth check, then L+1 = H), and then it is determined that the boundary is between WLL and WLH 868 (for example, between Figure 8B WL6 and WL7 of

[0121] In some embodiments, the result of the boundary search can be stored so that the search does not have to be repeated (for example, as Figures 8A to 8C shown). For example, in a programming operation that includes multiple programming steps and verification steps, once the boundary is found in a sub-block, the boundary can be used throughout the programming operation (for example, the position of the boundary can be stored by the control circuit and retrieved as needed). The control circuit (such as control circuit 110 and / or read / write circuit 128) can be configured to store such position information and apply the word line voltage according to the stored position information.

[0122] Figure 9 is an exemplary timing diagram showing the specific voltages that can be applied by a control circuit (e.g., by control circuit 110 and / or read / write circuit 128; system control logic 360, row control circuit 320, and / or column control circuit 364; or other suitable control circuits, which may be on the same die as the memory structure being accessed, may be on different dies, or some combination) to program memory cells in a memory structure. The voltages shown include: the voltage applied to the word lines of the selected vertical sub-block, and the voltage applied to the word lines of one or more unselected vertical sub-blocks connected to the selected vertical sub-block (for example, as Figures 6A to 6B shown). Initially, at time T0, all the illustrated voltages are 0 volts. Subsequently, at time T1, the bit line voltage (BL or Vbl) increases to VDDSA (e.g., about 2 volts to 2.5 volts), the drain select gate voltage (SGD or Vsgd) increases to VSGD (e.g., 2.5 volts), the source select gate voltage SGS remains at 0 volts, and the source line voltage (CELSRC or Vcsrc) increases to VDDSA (e.g., about 2 volts to 2.5 volts).

[0123] In the selected vertical sub-block (e.g., Figure 6AIn VSB0, the voltage on the selected word line (e.g., WL3) is increased to VPGM (e.g., a programming pulse), the voltage on the programming word lines (e.g., word lines WL4 to WL5 connected to the programmable memory cell) is increased to a first overdrive voltage V_OD1 (e.g., between 8 volts and 10 volts or about 9 volts), and the voltage on the unprogrammed word lines (e.g., word lines WL0 to WL2 connected to the unprogrammable memory cell) is also increased to V_OD1. In other examples, different voltages may be applied to the word lines connected to the programmable memory cell and the word lines connected to the unprogrammable memory cell in the selected subblock.

[0124] In the absence of a selected vertical sub-block (e.g., Figure 6A In VSB1, word lines connected to programmed memory cells (e.g., WL6 to WL8) and word lines connected to unprogrammed memory cells (e.g., WL9 to WL11) receive different voltages. The programmed and unprogrammed portions of such unselected subblocks can be identified by any suitable method, including methods such as those described above. Figures 8A to 8C The search is described as follows: An overdrive voltage V_OD2 (e.g., a voltage less than the first overdrive voltage V_OD1, such as between 6 and 8 volts, or about 7 volts) is applied to the programming word line. A bypass voltage (e.g., between 4 and 6 volts, or about 5 volts) is applied to the unprogrammed word line. All illustrated voltages return to 0 volts at time t2 and remain at 0 volts until at least time t3 is reached, at which point subsequent steps can be performed (e.g., a verification step to determine whether the programming steps are sufficient or whether another programming step is needed).

[0125] Figure 10 This is an exemplary timing diagram illustrating specific voltages that can be applied by control circuitry (e.g., control circuitry 110 and / or read / write circuitry 128; system control logic unit 360, row control circuitry 320 and / or column control circuitry 364; or other suitable control circuitry, which may be located on the same die as the memory structure being accessed, or on different dies, or in some combination thereof) to sense memory cells in a memory structure (e.g., during a read or verification). The voltages shown include: voltages applied to word lines of a selected sub-block, and voltages applied to word lines connected to one or more unselected sub-blocks connected to the selected sub-block (e.g., such as...). Figures 6A to 6B (As shown). Initially, at time T0, all voltages shown are 0 volts. Subsequently, at time T1, the bit line voltage (BL or Vbl) increases to VBL (e.g., about 3 volts), the drain-select gate voltage (SGD or Vsgd) increases to VSG (e.g., 8 volts), the source-select gate voltage SGS also increases to VSG, and the source line voltage (CELSRC or Vcsrc) remains at 0 volts.

[0126] In the selected vertical sub-block (e.g., Figure 6A In VSB0, the voltage on the selected word line (e.g., WL3) is increased to VCG (e.g., read voltages Vr1 to Vr7 or verification voltages Vv1 to Vv7, which is 1 volt in this example), the voltage on the programming word lines (e.g., word lines WL4 to WL5 connected to the programming memory cell) is increased to the overdrive voltage V_OD2 (e.g., between 6 volts and 8 volts or about 7 volts), and the voltage on the unprogrammed word lines (e.g., word lines WL0 to WL2 connected to the unprogrammed memory cell) is also increased to V_OD2. In other examples, different voltages may be applied to the word lines connected to the programming memory cell and the word lines connected to the unprogrammed memory cell in the selected subblock.

[0127] In the absence of a selected vertical sub-block (e.g., Figure 6A In VSB1, word lines connected to programmed memory cells (e.g., WL6 to WL8) and word lines connected to unprogrammed memory cells (e.g., WL9 to WL11) receive different voltages. The programmed and unprogrammed portions of such unselected subblocks can be identified by any suitable method, including methods such as those described above. Figures 8A to 8C The search is described above. A drive voltage V_OD2 (e.g., between 6 and 8 volts, or about 7 volts) is applied to the programming word line. A bypass voltage (e.g., between 2 and 4 volts, or about 3 volts) is applied to the unprogrammed word line. All illustrated voltages return to 0 volts at time t2 and remain at 0 volts until at least time t3, at which point subsequent steps can be performed (e.g., if verification indicates further programming is required, a subsequent programming step is performed; or a subsequent read step is performed using a VCG at a different level).

[0128] One embodiment includes an apparatus comprising control circuitry configured to connect to a first word line of a first vertical sub-block and a second word line of a second vertical sub-block, the first and second vertical sub-blocks including memory cells connected in series in NAND strings, each NAND string including memory cells coupled to the first word line in series with the memory cells connected to the second word line, the control circuitry being configured to: program or sense memory cells along selected first word lines of the first vertical sub-block, while simultaneously applying a first voltage to one or more second word lines in the second vertical sub-block connected to programmed memory cells, and applying a second voltage to one or more second word lines in the second vertical sub-block connected to unprogrammed memory cells.

[0129] The control circuit can be further configured to identify the boundary between second word lines connected to programmed memory cells and second word lines connected to unprogrammed memory cells located in the second vertical sub-block. The control circuit can be further configured to identify the boundary by sensing the second word lines of the second vertical sub-block in a binary search of these second word lines. The control circuit can be further configured to identify the boundary by sensing the second word lines of the second vertical sub-block in a sequential search of these second word lines. The first voltage can be an overdrive voltage sufficient to turn on memory cells programmed to all data states, and the second voltage can be a bypass voltage sufficient to turn on unprogrammed memory cells but insufficient to turn on memory cells programmed to one or more data states. The control circuit can be further configured to apply a third voltage to an unselected first word line of the first vertical sub-block, the third voltage being an overdrive voltage sufficient to turn on memory cells programmed to all data states, and the third voltage being greater than the first voltage. The control circuit can be further configured to program memory cells along a selected first word line of the first vertical sub-block while applying a first voltage of approximately 6 to 8 volts, a second voltage of approximately 4 to 6 volts, and a third voltage of approximately 8 to 10 volts. The control circuit can be further configured to sense memory cells along the selected first word line of the first vertical sub-block while applying a first voltage of approximately 6 to 8 volts, a second voltage of approximately 2 to 4 volts, and a third voltage of approximately 6 to 8 volts. The control circuit can be further configured to independently erase the first and second vertical sub-blocks and to assign logically unrelated data to the first and second vertical sub-blocks, such that the write-erase cycle counts of the first and second vertical sub-blocks are independent of each other.

[0130] An exemplary method includes: in a non-volatile memory array comprising a NAND string extending through two or more vertical sub-blocks, identifying one or more unselected vertical sub-blocks connected to selected vertical sub-blocks; locating a boundary between a programmed portion and an unprogrammed portion of the one or more unselected vertical sub-blocks; and, during programming or sensing of non-volatile memory cells in the selected vertical sub-blocks, applying a first voltage to word lines in the programmed portion of the unselected vertical sub-blocks and applying a second voltage to word lines in the unprogrammed portion of the unselected vertical sub-blocks.

[0131] The first voltage may be higher than the second voltage. The method may further include applying one or more programming pulses to selected word lines of a selected vertical subblock during programming of a non-volatile memory cell, while simultaneously applying a third voltage to unselected word lines of the selected vertical subblock, the third voltage being higher than the first and second voltages. The method may further include applying a third voltage equal to or greater than the first voltage to unselected word lines of the selected vertical subblock when sensing a non-volatile memory cell. The method may further include applying a first voltage to word lines connected to programmed non-volatile memory cells and applying a second voltage to word lines connected to unprogrammed non-volatile memory cells in one or more additional vertical subblocks that share a NAND string with the selected vertical subblock during programming or sensing. Lookup boundaries may include performing a binary search on word lines of unselected vertical subblocks. Lookup boundaries may include performing a sequential search on word lines of unselected vertical subblocks.

[0132] An exemplary non-volatile memory device includes: a plurality of NAND strings of memory cells, each NAND string having a first set of data memory cells, a second set of data memory cells, and a first non-data transistor located between the first set of data memory cells and the second set of data memory cells; a plurality of word lines connected to the data memory cells, the word lines including a first set of data word lines connected to the first set of data memory cells and a second set of data word lines connected to the second set of data memory cells; and means for: applying a read voltage or programming pulse to selected word lines of the first set of data word lines to read or program memory cells along the selected word lines, while applying an overdrive voltage to all programmed data word lines of the second set of data word lines, and applying a bypass voltage to all unprogrammed data word lines of the second set of data word lines.

[0133] The non-volatile memory device may further include means for identifying programmed and unprogrammed data word lines in the second set of data word lines by searching the second set of data word lines in a serial or binary search mode. Each of the plurality of NAND strings may further include at least a third set of data memory cells and a second non-data transistor located between the second set of data memory cells and the third set of data memory cells; the plurality of word lines may further include a third set of data word lines connected to the third set of data memory cells. The overdrive voltage may be about 7 volts, and the bypass voltage may be in the range of about 3 volts to about 5 volts.

[0134] For the purposes of this document, the terms “implementation scheme,” “one implementation scheme,” “some implementation schemes,” or “another implementation scheme” used in the specification may be used to describe different implementation schemes or the same implementation scheme.

[0135] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is mentioned as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is mentioned as being directly connected to another element, there is no intermediary element between the two elements. If two devices are directly or indirectly connected, the two devices are “communicating”, enabling them to communicate electronic signals between them.

[0136] For the purposes of this document, the term “based on” may be understood as “at least partially based on”.

[0137] For the purposes of this document, the use of numerical terms such as “first” object, “second” object, and “third” object without additional context may not imply an ordering of objects, but may be used for identification purposes to distinguish different objects.

[0138] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0139] The detailed description above has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the precise forms disclosed in the invention. Many modifications and variations are possible based on the teachings above. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and various modifications suitable for the specific intended use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. An apparatus, the apparatus comprising: A control circuit configured to be connected to a plurality of first word lines of a first vertical sub-block and a plurality of second word lines of a second vertical sub-block, the first and second vertical sub-blocks including memory cells connected in series in NAND strings, each NAND string including memory cells coupled to the plurality of first word lines in series with the memory cells connected to the plurality of second word lines, the control circuit being configured to: Programming or sensing memory cells along selected first word lines of the first vertical sub-block, while simultaneously applying a first voltage to one or more second word lines of the second vertical sub-block connected to the programmed memory cells, and applying a second voltage to one or more second word lines of the second vertical sub-block connected to the unprogrammed memory cells.

2. The apparatus according to claim 1, wherein: The control circuit is further configured to identify the boundary between the second word line connected to the programmable memory cell and the second word line connected to the unprogrammable memory cell located in the second vertical sub-block.

3. The apparatus according to claim 2, wherein: The control circuit is further configured to identify the boundary by sensing the second word line of the second vertical sub-block in a binary search of the plurality of second word lines.

4. The apparatus according to claim 2, wherein: The control circuit is further configured to identify the boundary by sensing the second character line of the second vertical sub-block during the sequential search of the plurality of second character lines.

5. The apparatus according to claim 1, wherein: The first voltage is an overdrive voltage sufficient to turn on memory cells programmed to all data states, and the second voltage is a bypass voltage sufficient to turn on unprogrammed memory cells, but insufficient to turn on memory cells programmed to one or more data states.

6. The apparatus according to claim 5, wherein: The control circuit is further configured to apply a third voltage to an unselected first word line of the first vertical sub-block, the third voltage being an overdrive voltage sufficient to turn on memory cells programmed to all data states, and the third voltage being greater than the first voltage.

7. The apparatus according to claim 6, wherein: The control circuit is further configured to program the memory cell along a selected first word line of the first vertical sub-block while applying a first voltage of about 6 to 8 volts, a second voltage of about 4 to 6 volts, and a third voltage of about 8 to 10 volts.

8. The apparatus according to claim 6, wherein: The control circuit is further configured to sense the memory cell along a selected first word line of the first vertical sub-block while applying a first voltage of about 6 to 8 volts, a second voltage of about 2 to 4 volts, and a third voltage of about 6 to 8 volts.

9. The apparatus according to claim 1, wherein: The control circuit is further configured to independently erase the first vertical sub-block and the second vertical sub-block, and is configured to assign logically unrelated data to the first vertical sub-block and the second vertical sub-block, such that the write erase cycle counts of the first vertical sub-block and the second vertical sub-block are independent of each other.

10. A method, the method comprising: In a non-volatile memory array comprising NAND strings extending through two or more vertical sub-blocks, identify one or more unselected vertical sub-blocks connected to a selected vertical sub-block; Locate the boundary between the programmed and unprogrammed portions of the one or more unselected vertical sub-blocks; as well as During programming or sensing of non-volatile memory cells in the selected vertical sub-block, a first voltage is applied to the word lines of the unselected vertical sub-block in the programmed portion, and a second voltage is applied to the word lines of the unprogrammed portion of the unselected vertical sub-block.

11. The method of claim 10, wherein the first voltage is higher than the second voltage.

12. The method of claim 11, further comprising: During programming of the non-volatile memory cell, one or more programming pulses are applied to the selected word line of the selected vertical sub-block, while a third voltage, higher than the first voltage and the second voltage, is applied to the unselected word line of the selected vertical sub-block.

13. The method of claim 11, further comprising: When sensing the non-volatile memory cell, a third voltage is applied to the unselected word line of the selected vertical sub-block, the third voltage being equal to or greater than the first voltage.

14. The method of claim 10, further comprising: During programming or sensing, the first voltage is applied to word lines connected to programmed nonvolatile memory cells in one or more additional vertical sub-blocks, and the second voltage is applied to word lines connected to unprogrammed nonvolatile memory cells, the one or more additional vertical sub-blocks sharing the NAND string with the selected vertical sub-block.

15. The method of claim 10, wherein finding the boundary comprises performing a binary search on the word lines of the unselected vertical sub-block.

16. The method of claim 10, wherein finding the boundary comprises performing a sequential search on the word lines of the unselected vertical sub-block.

17. A non-volatile storage device, the non-volatile storage device comprising: Multiple NAND strings of memory cells, each NAND string having a first group of data memory cells, a second group of data memory cells, and a first non-data transistor located between the first group of data memory cells and the second group of data memory cells; Multiple word lines are connected to the data memory units, and the word lines include a first set of data word lines connected to the first set of data memory units and a second set of data word lines connected to the second set of data memory units; and The apparatus is used to: apply a read voltage or programming pulse to selected word lines of the first set of data word lines to read or program memory cells along the selected word lines, while applying an overdrive voltage to all programmed data word lines of the second set of data word lines, and applying a bypass voltage to all unprogrammed data word lines of the second set of data word lines.

18. The non-volatile storage device of claim 17, further comprising means for identifying the boundary between programmed and unprogrammed data word lines in the second set of data word lines by searching the second set of data word lines in a serial or binary search mode.

19. The non-volatile storage device according to claim 17, wherein: Each of the plurality of NAND strings further includes at least a third set of data memory cells and a second non-data transistor located between the second set of data memory cells and the third set of data memory cells; and The plurality of word lines also includes a third set of data word lines connected to the third set of data memory units.

20. The non-volatile storage device according to claim 17, wherein: The overdrive voltage is about 7 volts, and the bypass voltage is in the range of about 3 volts to about 5 volts.

Images