semiconductor structure

Abstract

The embodiments of the present application relate to a semiconductor structure, comprising: a first wafer, wherein the first wafer has a plurality of memory chips therein; a second wafer, wherein the second wafer has a plurality of logic chips therein, wherein the first surface of the second wafer is connected to the first surface of the first wafer, and the memory chips and the logic chips are electrically connected; a substrate, wherein a liquid conduit is provided therein, the substrate is in contact with the second surface of the first wafer, and the substrate is used to pass a heating solution into the liquid conduit before the memory chips are put into operation to heat the memory chips to a preset temperature; wherein the second surface of the first wafer is arranged opposite to the first surface of the first wafer. Before the memory chips are put into operation, the memory chips are heated to a preset temperature by passing a heating solution into the liquid conduit, thereby increasing the rate at which data is transmitted and stored in the memory chips at the start of operation, allowing data to be completely written to the memory chips within the memory write recovery time, thereby eliminating the impact on the overall performance of the semiconductor structure caused by the inability of the memory chips to write complete data at the start of operation.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor structure. Background Art

[0002] With the advent of the 5G communication and artificial intelligence (AI) era, the chips in semiconductor devices used in such related fields need to transmit, store and interactively process large amounts of data at high speed, which requires the semiconductor devices to have a relatively high operating speed. In actual applications, it is found that the overall performance of the semiconductor device is low at the beginning of operation, and the data cannot be completely written into the storage chip. As the operating time increases, the overall performance of the semiconductor device gradually improves, and the data begins to be completely written into the storage chip. How to improve the overall performance of the semiconductor device at the beginning of operation has become an urgent problem to be solved. Summary of the Invention

[0003] The embodiments of the present application provide a semiconductor structure that can optimize the overall performance of a semiconductor device when it starts working, so that data can be completely written into a memory chip when the semiconductor device starts working.

[0004] A semiconductor structure comprising:

[0005] A first wafer, wherein the first wafer has a plurality of memory chips;

[0006] A second wafer having a plurality of logic chips therein, wherein a first surface of the second wafer is connected to a first surface of the first wafer, and the memory chips and the logic chips are electrically connected;

[0007] a substrate having a liquid conduit disposed therein, the substrate being in contact with the second surface of the first wafer, and being used to pass a heating solution into the liquid conduit before the memory chip operates, so as to heat the memory chip to a preset temperature;

[0008] The second surface of the first wafer is arranged opposite to the first surface of the first wafer.

[0009] In one embodiment, the substrate is further used to pass a cooling solution into the liquid conduit when the memory chip is operating, so as to reduce the temperature of the semiconductor structure.

[0010] In one embodiment, the heating solution and the cooling solution are made of the same material.

[0011] In one embodiment, the materials of the heating solution and the cooling solution are both water.

[0012] In one embodiment, the semiconductor structure further comprises:

[0013] The first cooling pump is connected to the liquid pipeline and is used to drive the flow of the heating solution.

[0014] In one embodiment, the first cooling pump is also used to drive the flow of the cooling solution.

[0015] In one embodiment, the semiconductor structure further comprises:

[0016] A metal plate is provided with a heat dissipation pipe, the metal plate is in contact with the second surface of the second wafer, and the second surface of the second wafer is arranged opposite to the first surface of the second wafer.

[0017] In one embodiment, a heat dissipation solution is provided in the heat dissipation pipe, and the heat dissipation solution is used to reduce the temperature of the semiconductor structure.

[0018] In one embodiment, the heat dissipation solution includes water or a silicate-based coolant.

[0019] In one embodiment, the semiconductor structure further comprises:

[0020] The second cooling pump is connected to the heat dissipation pipeline and is used to drive the flow of the heat dissipation solution.

[0021] In one embodiment, a receiving groove is provided in the metal plate; and the semiconductor structure further comprises:

[0022] The connecting device is located on the second surface of the second wafer, is located in the receiving groove, and is electrically connected to the logic chip.

[0023] In one embodiment, the semiconductor structure further comprises:

[0024] The fixing piece passes through the metal plate and contacts the base plate, and is used to fix the metal plate and the base plate together.

[0025] In one embodiment, the fixing member is further used to transfer heat generated by the logic chip to the substrate.

[0026] In one embodiment, the functional surface of the memory chip is located on the first surface of the first wafer, and the functional surface of the logic chip is located on the second surface of the second wafer.

[0027] In one embodiment, a conductive structure is formed in the second wafer, and the conductive structure is used to lead the logic chip to the first surface of the second wafer.

[0028] In one embodiment, the functional surface of the memory chip is located on the first surface of the first wafer, and the functional surface of the logic chip is located on the first surface of the second wafer.

[0029] In one embodiment, the first side of the first wafer and the first side of the second wafer are bonded together using a micro-bump bonding process or a fusion bonding process.

[0030] The above-mentioned semiconductor structure includes: a first wafer, wherein the first wafer has a plurality of memory chips; a second wafer, wherein the second wafer has a plurality of logic chips, wherein the first surface of the second wafer is connected to the first surface of the first wafer, and the memory chips and the logic chips are electrically connected; a substrate, wherein a liquid pipeline is provided in the substrate, the substrate is in contact with the second surface of the first wafer, and the substrate is used to pass a heating solution into the liquid pipeline before the memory chips are put into operation to heat the memory chips to a preset temperature; wherein the second surface of the first wafer is arranged opposite to the first surface of the first wafer. In the present application, before the memory chips are put into operation, the memory chips are heated to a preset temperature by passing a heating solution into the liquid pipeline, thereby increasing the rate at which data is transmitted and stored in the memory chips at the start of operation, so that data can be completely written into the memory chips within the memory write recovery time, eliminating the impact on the overall performance of the semiconductor structure caused by the inability of the memory chips to write complete data at the start of operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 is a schematic structural diagram of the semiconductor structure in the first embodiment;

[0033] Figure 2 is a schematic structural diagram of a semiconductor structure in a second embodiment;

[0034] Figure 3 is a schematic structural diagram of a semiconductor structure in a third embodiment;

[0035] Figure 4 is a schematic structural diagram of a semiconductor structure in a fourth embodiment;

[0036] Figure 5 is a schematic top view of a substrate in one embodiment;

[0037] Figure 6 is a schematic structural diagram of a semiconductor structure in a fifth embodiment;

[0038] Figure 7 FIG. 4 is a schematic structural diagram of the semiconductor structure in the sixth embodiment.

[0039] Description of reference numerals:

[0040] 100, first wafer; 102, memory chip; 200, second wafer; 202, logic chip; 204, conductive structure; 206, connecting device; 300, substrate; 302, liquid pipeline; 304, first input terminal; 306, first output terminal; 308, groove; 310, vacuum adsorption hole; 402, conductive bump; 404, fixing member; 406, container; 408, third input terminal; 410, third output terminal; 500, metal plate; 502, heat dissipation pipeline; 504, second input terminal; 506, second output terminal. DETAILED DESCRIPTION

[0041] To facilitate understanding of the embodiments of the present application, a more comprehensive description of the embodiments of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings provide preferred embodiments of the embodiments of the present application. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the embodiments of the present application.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present application. The terms used herein in the description of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0043] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0044] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first wafer may be referred to as a second wafer, and similarly, a second wafer may be referred to as a first wafer, without departing from the scope of this application. The first wafer and the second wafer are both wafers, but they are not the same wafer.

[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of this application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0046] Figure 1 FIG. 1 is a schematic diagram of the semiconductor structure in the first embodiment. Figure 1As shown, in this embodiment, the semiconductor structure includes: a first wafer 100, a second wafer 200 and a substrate 300; the first wafer 100 has a plurality of memory chips 102, that is, a plurality of memory chips 102 are formed in the first wafer 100; the second wafer 200 has a plurality of logic chips 202, that is, a plurality of logic chips 202 are formed in the second wafer 200; the first surface of the second wafer 200 is connected to the first surface of the first wafer 100, and the memory chips 102 and the logic chips 202 are electrically connected; the substrate 300 is provided with a liquid pipeline 302, The substrate 300 is in contact with the second surface of the first wafer 100. The substrate 300 is used to pass a heating solution into the liquid pipe 302 before the memory chip 102 works to heat the memory chip 102 to a preset temperature. The heating solution is a solution with a large thermal conductivity coefficient. The larger the thermal conductivity coefficient of the heating solution, the shorter the time required to heat the memory chip 102 to the preset temperature. The second surface of the first wafer 100 is arranged opposite to the first surface of the first wafer 100, that is, the second surface of the first wafer 100 is a surface of the first wafer 100 away from the second wafer 200. The DRAM Write Recovery Time (Twr) refers to the time interval between sending a write command to the memory chip (calculated from the start of writing) and the next precharge of the memory chip. If the DRAM Write Recovery Time is too short or the data transmission rate is too slow, the next precharge may begin before the previous write is completely written to the memory chip, resulting in incomplete data written to the memory chip and data loss. Because the substrate 300 is in contact with the second surface of the first wafer 100, the heated solution in the liquid pipe 302 can heat the memory chip 102 in the first wafer 100. The preset temperature refers to the actual temperature of the memory chip 102 when the operating rate of the memory chip 102 for processing data reaches a stable speed. In other words, the preset temperature refers to the actual temperature of the memory chip 102 when data can be completely written to the memory chip 102 within the DRAM Write Recovery Time of the memory chip 102. Through the above setting, the rate of data transmission and storage in the memory chip 102 at the start of operation is increased, so that data can be completely written to the memory chip 102 within the DRAM Write Recovery Time, eliminating the impact of the inability of the memory chip 102 to write complete data at the start of operation on the overall performance of the semiconductor structure.

[0047] The above-mentioned semiconductor structure includes: a first wafer 100, which has a plurality of memory chips 102 therein; a second wafer 200, which has a plurality of logic chips 202 therein, and the first surface of the second wafer 200 is connected to the first surface of the first wafer 100, and the memory chips 102 and the logic chips 202 are electrically connected; a substrate 300, in which a liquid pipeline 302 is provided, and the substrate 300 contacts the second surface of the first wafer 100. The substrate 300 is used to pass a heating solution into the liquid pipeline 302 before the memory chips 102 work, so as to heat the memory chips 102 to a preset temperature; wherein, the second surface of the first wafer 100 is arranged opposite to the first surface of the first wafer 100. Before the memory chip 102 works, the present application heats the memory chip 102 to a preset temperature by introducing a heating solution into the liquid pipe 302, thereby increasing the rate at which data is transmitted and stored in the memory chip 102 when the work starts, so that data can be completely written into the memory chip 102 within the memory write recovery time, thereby eliminating the impact of the inability of the memory chip 102 to write complete data at the start of the work on the overall performance of the semiconductor structure.

[0048] In one embodiment, the substrate 300 is further configured to introduce a cooling solution into the liquid conduit 302 when the memory chip 102 is operating to reduce the temperature of the semiconductor structure. Specifically, during the operation of the memory chip 102, a cooling solution is introduced into the liquid conduit 302 to reduce the temperature of the semiconductor structure. Since the heat generated by the logic chip 202 during operation is greater than that generated by the memory chip 102, a cooling solution may be introduced into the liquid conduit 302 during the operation of the logic chip 202 to reduce the temperature of the semiconductor structure. The heat generated during the operation of the memory chip 102 and the logic chip 202 can be conducted to the surface of the substrate 300 in contact with the first wafer 100, and then dissipated through the cooling solution in the liquid conduit 302, thereby reducing the overall temperature of the semiconductor structure and increasing the service life of the semiconductor structure. The cooling solution is a solution with a large thermal conductivity coefficient. The greater the thermal conductivity of the cooling solution, the faster the heat conducted to the surface of the substrate 300 in contact with the first wafer 100 will be dissipated, making it easier to stabilize the temperature of the memory chip 102 at a preset temperature.

[0049] In one embodiment, the heating solution and the cooling solution are made of the same material.

[0050] In one embodiment, the materials of the heating solution and the cooling solution are both water or silicate-type coolant.

[0051] In other embodiments, the heating solution and the cooling solution are made of different materials.

[0052] Continue to refer Figure 1In one embodiment, one end of the liquid pipe 302 is a first input end 304 of a heating solution or a cooling solution, and the other end of the liquid pipe 302 is a first output end 306 of a heating solution or a cooling solution. The storage chip 102 is heated by the flow of the heating solution in the liquid pipe 302, and the heat is dissipated by the flow of the cooling solution in the liquid pipe 302.

[0053] Continue to refer Figure 1 In one embodiment, the functional surface of the memory chip 102 is located on the first surface of the first wafer 100, and the functional surface of the logic chip 202 is located on the second surface of the second wafer 200. Specifically, the first wafer 100 includes a substrate and a functional structure of a memory device located on the substrate (the functional surface of the memory chip 102), wherein the surface where the functional structure of the memory device is located is the first surface of the first wafer 100, and the surface where the functional structure of the substrate is not formed is the second surface of the first wafer 100. Similarly, the second wafer 200 includes a substrate and a functional structure of a logic device located on the substrate (the functional surface of the second chip), wherein the surface where the functional structure of the logic device is located is the first surface of the second wafer 200, and the surface where the functional structure of the substrate is not formed is the second surface of the second wafer 200.

[0054] Continue to refer Figure 1 In one embodiment, a conductive structure 204 is formed in the second wafer 200. The conductive structure 204 is used to lead the logic chip 202 to the first surface of the second wafer 200. That is, one end of the conductive structure 204 is electrically connected to the logic chip 202, and the other end of the conductive structure 204 extends to the first surface of the second wafer 200. The conductive structure 204 leads the pads of the logic chip 202 (the functional end of the logic chip 202) to the first surface of the second wafer 200. The memory chip 102 is connected to at least one of the conductive structures 204. That is, the functional end of the memory chip 102 is electrically connected to the corresponding pad on the logic chip 202. In this way, the electrical connection between the memory chip 102 and the logic chip 202 is achieved. The number of conductive structures 204 can be set according to actual needs.

[0055] Continue to refer Figure 1 In one embodiment, the first surface of the first wafer 100 and the first surface of the second wafer 200 are bonded using a micro-bump bonding process, that is, the first surface of the first wafer 100 and the first surface of the second wafer 200 are connected together through a conductive bump 402 bonding process, and there is a conductive bump 402 between the first surface of the first wafer 100 and the first surface of the second wafer 200. Exemplarily, the material of the conductive bump 402 includes metal nickel, metal tin, metal copper, metal gold, etc.

[0056] like Figure 1As shown, in one embodiment, the conductive bumps 402 include main conductive bumps 402 for electrically connecting the logic chip 202 and the memory chip 102 and secondary conductive bumps 402 for auxiliary support, that is, the two ends of the conductive bumps 402 are respectively electrically connected to the logic chip 202 and the memory chip 102 and connect and transmit the signals in the logic chip 202 and the memory chip 102. The remaining conductive bumps 402 are secondary conductive bumps 402. While reducing the deformation between the first wafer 100 and the second wafer 200 due to suspension, the secondary conductive bumps 402 play a role in heat conduction between the second wafer 200 and the first wafer 100, that is, the secondary conductive bumps 402 conduct heat from the second wafer 200 to the first wafer 100, and then dissipate the heat through the liquid pipe 302, thereby achieving the effect of further reducing the overall temperature of the semiconductor structure. It is understood that the size of the primary conductive bump 402 may be different from the size of the secondary conductive bump 402 , or the size of at least part of the primary conductive bump 402 may be the same as the size of the secondary conductive bump 402 .

[0057] In one embodiment, the semiconductor structure further includes a first cooling pump connected to the liquid conduit 302 for driving the flow of the heated solution. Specifically, the first cooling pump is connected to the liquid conduit 302. Before the memory chip 102 operates, the first cooling pump drives the heated solution to flow in the liquid conduit 302, thereby heating the memory chip 102 to a preset temperature through the heated solution. It will be appreciated that the semiconductor structure further includes a first storage tank for storing the heated solution, and the first cooling pump is used to drive the heated solution in the first storage tank to flow in the liquid conduit 302.

[0058] In one embodiment, the first cooling pump is also used to drive the flow of the cooling solution. Specifically, after the memory chip 102 or the logic chip 202 starts working, the first cooling pump drives the cooling solution to flow in the liquid pipe 302, so as to achieve the purpose of lowering the overall temperature of the semiconductor structure by the cooling solution. It is understandable that the semiconductor structure also includes a second storage tank for storing the cooling solution, and the first cooling pump is also used to drive the cooling solution in the second storage tank to flow in the liquid pipe 302302. At this time, the semiconductor structure also includes: a detection device connected to the first cooling pump, the first cooling pump is connected to the liquid pipe 302, and under normal conditions, is used to drive the flow of the heated solution in the liquid pipe 302. When the detection device detects that the temperature of the memory chip 102 is greater than the preset temperature, the memory chip 102 is working, or the logic chip 202 is working, it controls the first cooling pump to drive the cooling solution to flow in the liquid pipe 302.

[0059] Figure 2 FIG. 1 is a schematic diagram of the semiconductor structure in the second embodiment. Figure 2As shown, in one embodiment, the semiconductor structure further includes a connector 206, which is located on the second surface of the second wafer 200 and electrically connected to the logic chip 202. Specifically, the connector 206 is electrically connected to at least one logic chip 202, that is, the connection end of the connector 206 is correspondingly connected to the functional end of the logic chip 202. In this way, the connector 206, the logic chip 202, and the memory chip 102 are electrically connected, and different signals are sent to the logic chip 202 and the memory chip 102 through the connector 206. At this time, the heat generated by the connector 206 can be conducted to the first wafer 100 through the second wafer 200, and then dissipated through the liquid pipe 302.

[0060] Figure 3 FIG. 1 is a schematic diagram of the structure of the semiconductor structure in the third embodiment. Figure 3 As shown, in one embodiment, the semiconductor structure further includes: a metal plate 500, in which a heat dissipation pipe 502 is disposed. The metal plate 500 contacts the second surface of the second wafer 200, and the second surface of the second wafer 200 is arranged opposite to the first surface of the second wafer 200. That is, the second surface of the second wafer 200 is a surface of the second wafer 200 that is away from the first wafer 100. The heat generated during the operation of the logic chip 202 and the memory chip 102 can be transferred to the surface of the heat dissipation device in contact with the second wafer 200, and then dissipated through the heat dissipation pipe, thereby increasing the speed of heat dissipation and further reducing the overall temperature of the semiconductor structure. At this time, the secondary conductive bumps 402 can also transfer heat from the first wafer 100 to the second wafer 200, and then dissipate the heat through the heat dissipation pipe 502. Exemplary materials of the metal plate 500 include metal materials such as titanium, nickel, copper, tungsten, polysilicon, silver, and aluminum.

[0061] In one embodiment, a heat dissipation solution is provided in the heat dissipation pipe 502 , and the heat dissipation solution is used to reduce the temperature of the semiconductor structure. Specifically, the temperature of the semiconductor structure is reduced by the flow of the heat dissipation solution in the heat dissipation pipe 502 .

[0062] In one embodiment, the heat dissipation pipe 302 is made of a thermally conductive material, which can quickly transfer heat to the coolant.

[0063] In one embodiment, the heat dissipation solution includes water or a silicate coolant. The silicate coolant has good cooling performance and will not corrode the heat dissipation pipes.

[0064] In one embodiment, one end of the heat dissipation pipe is the second input end 504 of the heat dissipation solution, and the other end of the heat dissipation pipe is the second output end 506 of the heat dissipation solution. Heat is dissipated by the heat dissipation solution flowing in the heat dissipation pipe.

[0065] In one embodiment, the semiconductor structure further comprises:

[0066] A second cooling pump is connected to the heat dissipation pipe 502 and is used to drive the flow of the heat dissipation solution. It is understood that the semiconductor structure also includes a third storage tank for storing the heat dissipation solution, and the second cooling pump is used to drive the heat dissipation solution in the third storage tank to flow in the heat dissipation pipe. It is understood that when the heat dissipation solution and the coolant are the same solution, the second storage tank storing the cooling solution can be used as the third storage tank. In this case, the second cooling pump is set to another cooling pump different from the first cooling pump according to the test needs, and the first cooling pump can also be used as the second cooling pump at the same time.

[0067] Continue to refer Figure 3 In one embodiment, a receiving groove is provided in the metal plate 500 , and the connector is located in the receiving groove and is electrically connected to the logic chip 202 .

[0068] Figure 4 FIG. 4 is a schematic diagram of the structure of the semiconductor structure in the fourth embodiment. Figure 4 As shown, in one embodiment, the semiconductor structure further includes a fixing member 404. The fixing member 404 extends through the metal plate 500 and contacts the substrate 300, thereby securing the metal plate 500 to the substrate 300. The provision of the fixing member 404 can avoid the problem of the metal plate 500 being partially suspended above the second wafer 200 and easily moving. It is understood that the material of the fixing member 404 can be any material as long as it satisfies the requirement for securing the metal plate 500 to the substrate 300.

[0069] In one embodiment, the fixing member 404 is also used to transfer heat generated by the logic chip 202 to the substrate 300. In this case, the fixing member 404 can transfer heat (heat generated by the logic chip 202 and / or heat generated by the connecting device 206) directly from the metal plate 500 to the substrate 300, or directly from the substrate 300 to the metal plate 500, thereby maximizing heat dissipation between the metal plate 500 and the substrate 300. It is understood that the material selected for the fixing member and the material of the heat conducting device 406 include metal silver, metal copper, metal aluminum, aluminum oxide, aluminum alloy, thermal conductive tape, graphite, diamond, silicon, etc.

[0070] Figure 5 FIG. 3 is a schematic top view of a substrate 300 in one embodiment. Figure 5As shown, in one embodiment, a groove 308 is provided on the surface of the substrate 300 in contact with the first wafer 100, and the liquid pipe 302 is located in the groove 308, and the liquid pipe 302 is in contact with the second surface of the first wafer 100. Through this arrangement, the memory chip 102 can be quickly heated, and the heat conducted to the second surface of the first wafer 100 can also be quickly dissipated through the liquid pipe 302, so as to further reduce the overall temperature of the semiconductor structure.

[0071] In one embodiment, after the liquid conduit 302 passes through the substrate 300 , a portion of the liquid conduit 302 is located in the groove 308 . In another embodiment, the liquid conduit 302 is entirely located in the groove 308 .

[0072] Continue to refer Figure 5 In one embodiment, a surface of the liquid pipe 302 in contact with the first wafer 100 is provided with a plurality of vacuum adsorption holes 310 spaced apart from the liquid pipe 302. The liquid pipe 302 is in adsorption contact with the second surface of the second wafer 200 through the vacuum adsorption holes 310. By providing the vacuum adsorption holes 310, the second surface of the first wafer 100 is adsorbed on the surface of the substrate 300, thereby eliminating the influence of the preparation error on the contact between the second surface of the first wafer 100 and the substrate 300, and being more conducive to heat conduction.

[0073] Continue to refer Figure 5 In one embodiment, the liquid pipe 302 is arranged around the vacuum adsorption hole 310.

[0074] In one embodiment, the substrate 300 is made of a heat conductive material. Exemplarily, the material of the substrate 300 includes metallic silver, metallic copper, metallic aluminum, aluminum oxide, aluminum alloy, thermal conductive tape, graphite, diamond, silicon, etc.

[0075] Figure 6 FIG. 1 is a schematic diagram of the structure of the semiconductor structure in the fifth embodiment. Figure 6 As shown, in one embodiment, the functional surface of the memory chip 102 is located on the first surface of the first wafer 100 , and the functional surface of the logic chip 202 is located on the first surface of the second wafer 200 .

[0076] In one embodiment, the first side of the first wafer 100 and the first side of the second wafer 200 are bonded together using a fusion bonding process or a hybrid bonding process.

[0077] Figure 7 FIG. 1 is a schematic diagram of the structure of the semiconductor structure in the sixth embodiment. Figure 7As shown, in one embodiment, the semiconductor structure further includes a container 406 disposed outside the first wafer 100, the second wafer 200, the substrate 300, the metal plate 500, and the fixture 404. The container 406 contains a coolant for reducing the temperature of the semiconductor structure. In one embodiment, the container 406 further includes a third coolant input port 408 and a third coolant output port 410. The coolant dissipates heat through the flow of the coolant in the container 406.

[0078] In one embodiment, at least one of the cooling solution and the heat dissipation solution is a coolant in the container 406 .

[0079] In one embodiment, the semiconductor structure further includes a third cooling pump, which is used to drive the flow of coolant in the container 406 to quickly dissipate heat.

[0080] In one embodiment, the semiconductor structure further includes a fourth storage tank for storing coolant. The third cooling pump is configured to drive the coolant in the fourth storage tank to flow through the container 406, thereby rapidly dissipating heat. Exemplarily, the coolant includes water or a silicate-based coolant.

[0081] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-described embodiments merely represent several implementation methods of the embodiments of the present application. The descriptions thereof are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that, for those skilled in the art, several variations and improvements can be made without departing from the concept of the embodiments of the present application, and these all fall within the scope of protection of the embodiments of the present application. Therefore, the scope of protection of the patent of the embodiments of the present application shall be based on the appended claims.

Claims

1. A semiconductor structure, characterized in that include: a first wafer, wherein the first wafer has a plurality of memory chips therein; a second wafer, wherein the second wafer has a plurality of logic chips therein, wherein a first surface of the second wafer is connected to a first surface of the first wafer, and the memory chips and the logic chips are electrically connected; a substrate having a liquid conduit disposed therein, the substrate being in contact with the second surface of the first wafer, the substrate being configured to pass a heating solution into the liquid conduit before the memory chip operates to heat the memory chip to a preset temperature, and the substrate being configured to pass a cooling solution into the liquid conduit when the memory chip operates to lower the temperature of the semiconductor structure; The second surface of the first wafer is arranged opposite to the first surface of the first wafer.

2. The semiconductor structure according to claim 1, wherein: The heating solution and the cooling solution are made of the same material.

3. The semiconductor structure according to claim 2, wherein: The materials of the heating solution and the cooling solution are both water.

4. The semiconductor structure according to claim 1, wherein: Also includes: A first cooling pump is connected to the liquid pipeline and is used to drive the flow of the heating solution.

5. The semiconductor structure according to claim 4, wherein: The first cooling pump is also used to drive the flow of the cooling solution. The semiconductor structure according to claim 1 , wherein: Also includes: A metal plate is provided with a heat dissipation pipe, the metal plate is in contact with the second surface of the second wafer, and the second surface of the second wafer is arranged opposite to the first surface of the second wafer.

7. The semiconductor structure according to claim 6, wherein: A heat dissipation solution is provided in the heat dissipation pipe, and the heat dissipation solution is used to reduce the temperature of the semiconductor structure.

8. The semiconductor structure according to claim 7, wherein: The heat dissipation solution includes water or silicate type coolant.

9. The semiconductor structure according to claim 7, wherein: Also includes: A second cooling pump is connected to the heat dissipation pipeline and is used to drive the flow of the heat dissipation solution.

10. The semiconductor structure according to claim 6, wherein: The metal plate is provided with a receiving groove; the semiconductor structure further comprises: A connecting device is located on the second surface of the second wafer, is located in the receiving groove, and is electrically connected to the logic chip.

11. The semiconductor structure according to claim 6, wherein: Also includes: A fixing member passes through the metal plate and contacts the base plate, and is used for fixing the metal plate to the base plate.

12. The semiconductor structure according to claim 11, wherein: The fixing member is further used to transfer heat generated by the logic chip to the substrate.

13. The semiconductor structure according to claim 1, wherein: The functional surface of the memory chip is located on the first surface of the first wafer, and the functional surface of the logic chip is located on the second surface of the second wafer.

14. The semiconductor structure according to claim 13, wherein: A conductive structure is formed in the second wafer, and the conductive structure is used to lead the logic chip to the first surface of the second wafer.

15. The semiconductor structure according to claim 1, wherein: The functional surface of the memory chip is located on the first surface of the first wafer, and the functional surface of the logic chip is located on the first surface of the second wafer.

16. The semiconductor structure according to claim 13 or 15, characterized in that: The first surface of the first wafer and the first surface of the second wafer are bonded together using a micro-bump bonding process or a fusion bonding process.

Images