Silicon wafer defect detection method

Abstract

The present invention relates to a method for detecting silicon wafer defects, comprising the following steps: cutting a silicon wafer to be detected into two sub-silicon wafers to be detected; performing metal contamination treatment on the two sub-silicon wafers to be detected; performing different heat treatments on the two sub-silicon wafers to be detected, and judging the defects of the silicon wafer to be detected according to whether the two sub-silicon wafers to be detected show copper contamination patterns. Cutting the silicon wafer to be detected into two sub-silicon wafers to be detected, and performing different heat treatments on the two sub-silicon wafers to be detected, according to the characteristics of the PV area and the PI area, so that the two sub-silicon wafers to be detected have different results, the PV area and the PI area can be accurately judged.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for detecting silicon wafer defects. Background Art

[0002] In the process of single crystal growth by MCZ method, various crystal native defects are usually generated. For example, crystal native defect (COP), flow pattern defect (FPD), oxidation induced stacking fault (OiSF), direct surface oxidation defect (DSOD), etc. According to the type and aggregation mode of defects, we divide the quality of crystal rod into vacancy defect aggregation area v-rich, direct surface oxidation defect (DSOD), boundary p-band, vacancy point defect area pv, interstitial point defect area pi, b-band and interstitial defect aggregation area i-rich area. The aggregation of these defects will not only cause poor withstand voltage of silicon substrate oxide film, but also cause PN junction leakage, slot capacitor short circuit or insulation failure, reducing the yield of integrated circuits. Therefore, it is necessary to control the crystal quality in the point defect area by the temperature in the crystal pulling furnace and the crystal growth rate. Furthermore, it is also very important to quickly and accurately evaluate and judge the crystal area. The v-rich area and i-rich area can be quickly judged by the method of preferential corrosion, but the judgment of other areas is limited. Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides a method for detecting silicon wafer defects to solve the problem that PV and PI cannot be accurately judged.

[0004] In order to achieve the above object, the technical solution adopted in the embodiment of the present invention is: a method for detecting silicon wafer defects, comprising the following steps:

[0005] Cutting the silicon wafer to be tested into two sub-silicon wafers to be tested;

[0006] The two silicon wafers to be tested are subjected to metal contamination treatment;

[0007] The two silicon wafers to be tested are subjected to different heat treatments, and the defects of the silicon wafers to be tested are determined based on whether the two silicon wafers to be tested show copper contamination patterns.

[0008] Optionally, the two sub-silicon wafers to be detected include a first sub-silicon wafer and a second sub-silicon wafer, the two sub-silicon wafers to be detected are subjected to different heat treatments, and the defects of the silicon wafer to be detected are judged according to whether the two sub-silicon wafers to be detected show copper contamination patterns, specifically including:

[0009] The first silicon wafer is subjected to two consecutive heat treatments to make the vacancy point defects form cluster defects to adsorb copper complexes, so that no copper contamination pattern is formed on the surface of the first silicon wafer;

[0010] The second silicon wafer is subjected to a heat treatment so that a copper contamination pattern can be formed on an area of ​​the second silicon wafer without cluster defects.

[0011] Optionally, two silicon wafers to be tested are subjected to different heat treatments, and the defects of the silicon wafers to be tested are judged according to whether the copper contamination patterns appear on the two silicon wafers to be tested, which specifically includes:

[0012] If no copper contamination pattern appears on the first sub-silicon wafer and the second sub-silicon wafer, then determining that the area corresponding to the silicon wafer to be tested is a v-rich area and an i-rich area;

[0013] If the copper contamination pattern does not appear on the first sub-silicon wafer, and the copper contamination pattern appears on the second sub-silicon wafer, then the corresponding area on the silicon wafer to be tested is determined to be the pv area;

[0014] If copper contamination patterns appear on both the first sub-silicon wafer and the second sub-silicon wafer, then the area corresponding to the silicon wafer to be tested is determined to be the pi area;

[0015] When the copper contamination patterns on the two sub-silicon wafers to be inspected are dispersedly arranged, the DSOD method is used to determine whether the silicon wafer to be inspected has a COP defect.

[0016] Optionally, the conditions for performing two consecutive heat treatments on the first sub-silicon wafer include: the temperature is 800-950 degrees, and the heating time is 50-250 minutes; and the temperature is 950-1050 degrees, and the heating time is 50-200 minutes; the conditions for performing one heat treatment on the second sub-silicon wafer include: 950-1050 degrees, and the heating time is 50-200 minutes.

[0017] Optionally, when the oxygen concentration on the silicon wafer to be tested is greater than 11.5, the conditions for the first sub-silicon wafer to be heat-treated twice in succession include: a temperature of 870 degrees and a heating time of 220 minutes; and a temperature of 1000 degrees and a heating time of 120 minutes; the conditions for the second sub-silicon wafer to be heat-treated once include: a temperature of 980 degrees and a heating time of 190 minutes;

[0018] When the oxygen concentration on the silicon wafer to be tested is between 10.5 and 11.5, the conditions for the first silicon wafer to be heat-treated twice in succession include: a temperature of 870 degrees and a heating time of 120 minutes; and a temperature of 1000 degrees and a heating time of 120 minutes; the conditions for the second silicon wafer to be heat-treated once include: a temperature of 1000 degrees and a heating time of 120 minutes;

[0019] When the oxygen concentration on the silicon wafer to be tested is between 9.5 and 10.5, the conditions for the first silicon wafer to be heat-treated twice in succession include: a temperature of 870 degrees and a heating time of 85 minutes; and a temperature of 1000 degrees and a heating time of 120 minutes; the conditions for the second silicon wafer to be heat-treated once include: a temperature of 1000 degrees and a heating time of 55 minutes;

[0020] When the oxygen concentration on the silicon wafer to be tested is less than 9.5, the conditions for the first sub-silicon wafer to undergo two consecutive heat treatments include: a temperature of 870 degrees and a heating time of 85 minutes; and a temperature of 1000 degrees and a heating time of 120 minutes; the conditions for the second sub-silicon wafer to undergo one heat treatment include: a temperature of 940 degrees and a heating time of 50 minutes.

[0021] Optionally, the steps of subjecting the two silicon wafers to be tested to different heat treatments and judging the defects of the silicon wafers to be tested based on whether the two silicon wafers to be tested show copper contamination patterns include:

[0022] Acquire an image of the sub-silicon wafer to be detected, perform binarization processing on the image, and obtain the width of the region of the copper contamination pattern on the surface of the sub-silicon wafer to be detected in the radial direction of the sub-silicon wafer to be detected according to the binarized image;

[0023] If the width of the region of the copper contamination pattern in the radial direction of the sub-silicon wafer to be detected is greater than a preset value, the region of the copper contamination pattern is determined to be a COP free region.

[0024] Optionally, two silicon wafers to be tested are subjected to metal contamination treatment, specifically including:

[0025] The two silicon wafers to be detected are immersed in a buffered oxidant solution containing copper nitrate, wherein the concentration of copper ions is 3-8 ppmw.

[0026] Optionally, before the step of subjecting the two to-be-detected silicon wafers to metal contamination treatment, the following steps are also included:

[0027] The two silicon wafers to be detected are cleaned with HF.

[0028] The beneficial effect of the present invention is: the silicon wafer to be tested is cut into two sub-silicon wafers to be tested, and the two sub-silicon wafers to be tested are subjected to different heat treatments. According to the characteristics of the pv area and the pi area, different results are produced on the two sub-silicon wafers to be tested, so that the pv area and the pi area can be accurately judged. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram showing a flow chart of a method for detecting silicon wafer defects in an embodiment of the present invention;

[0030] Figure 2 Schematic diagram of the surface of the silicon wafer to be detected after different heat treatments in the embodiment of the present invention Figure 1 ;

[0031] Figure 3 Schematic diagram of the surface of the silicon wafer to be detected after different heat treatments in the embodiment of the present invention Figure 2 ;

[0032] Figure 4 Schematic diagram of the surface of the silicon wafer to be detected after different heat treatments in the embodiment of the present invention Figure 3 ;

[0033] Figure 5 Schematic diagram of the surface of the silicon wafer to be detected after different heat treatments in the embodiment of the present invention Figure 4 ;

[0034] Figure 6 Schematic diagram of the surface of the silicon wafer to be detected after different heat treatments in the embodiment of the present invention Figure 5 ;

[0035] Figure 7 Schematic diagram of the surface of the silicon wafer to be detected after different heat treatments in the embodiment of the present invention Figure 6 ;

[0036] Figure 8 Schematic diagram of the surface of the silicon wafer to be detected after different heat treatments in the embodiment of the present invention Figure 7 ;

[0037] Fig. 9 Schematic diagram of the surface of the silicon wafer to be detected after different heat treatments in the embodiment of the present invention Figure 8 ;

[0038] Fig.10 Schematic diagram of the surface of the silicon wafer to be detected after different heat treatments in the embodiment of the present invention Figure 9 ;

[0039] Fig.11 Representation Identification Fig.10 Schematic diagram obtained after the image is taken;

[0040] Fig.12 Indicates that Fig.11 Schematic diagram of the figure after binarization. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0042] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0043] Various grown-in defects will occur in the grown single crystal silicon ingot, and these grown-in defects will become problems in the device manufacturing process. Its representative grown-in defects include: dislocation clusters that occur in the region where intercrystalline silicon is dominant (hereinafter referred to as "I region") due to growth under low-speed pulling conditions, and crystal origin particles (COP: Crystal Originated Particle) that occur in the region where vacancies are dominant (hereinafter referred to as "V region") due to growth under high-speed pulling conditions. In addition, there are ring-shaped defects called oxidation-induced stacking faults (OSF: Oxidation induced Stacking Fault) near the boundary between the I region and the V region.

[0044] The distribution of these crystal defects in the grown single crystal silicon ingot depends on the crystal pulling speed V and the temperature gradient G at the solid-liquid interface. When the pulling speed V is large, the single crystal silicon ingot is controlled by the COP generation area as the crystal area where the COP is detected, and when V is reduced, an OSF potential nucleus area is formed, and the OSF potential nucleus area is manifested (surfaced) in the form of a ring-shaped OSF area when a specific oxidation heat treatment is performed.

[0045] If the pulling speed V is further reduced, a crystal region where oxygen precipitates exist and COP is undetectable, namely an oxygen precipitation promotion region (hereinafter also referred to as the "Pv region"), is formed, followed by a crystal region where oxygen precipitation is not easily caused and COP is undetectable, namely an oxygen precipitation inhibition region (hereinafter also referred to as the "Pi region"), and then a dislocation cluster region is formed as a crystal region where dislocation clusters are detected.

[0046] In silicon wafers taken from single crystal silicon ingots showing such defect distribution according to V / G, the OSF region, Pv region, and Pi region, except for the COP occurrence region and the dislocation cluster region, are all defect-free regions (COP-free regions) with very few native defects. In addition, there is a region called DSOD region where direct surface oxidation defects (DSOD) may occur just above the defect-free region. DSOD refers to a tiny COP with a diameter of about 10 to 20 nm detected by Cu decoration treatment.

[0047] Since the production method of silicon wafers mostly adopts the Czochralski method, the growth process is to pull while rotating, so the defect distribution of silicon wafers is basically the same along the radial direction. Therefore, when performing defect detection on silicon wafers, the silicon wafer to be detected can be cut into multiple sub-silicon wafers to be detected along its diameter direction, and then the sub-silicon wafers to be detected can be subjected to defect detection.

[0048] Figure 1 : is a flow chart of the silicon wafer defect detection method in this embodiment. The silicon wafer defect detection method in this embodiment includes the following steps:

[0049] Cutting the silicon wafer to be tested into two sub-silicon wafers to be tested;

[0050] The two silicon wafers to be tested are subjected to metal contamination treatment;

[0051] The two silicon wafers to be tested are subjected to different heat treatments, and the defects of the silicon wafers to be tested are determined based on whether the two silicon wafers to be tested show copper contamination patterns.

[0052] The Pv and Pi zones have the following characteristics:

[0053] Pv zone: There are a large number of vacancy type point defects in the Pv zone, so it will show the following performance under different heat treatments: after the first step of heat treatment, the vacancies are enlarged and oxygen nuclei are formed at the vacancy positions; after the second step of heat treatment, the oxygen nuclei grow to form cluster defects, and adsorb copper complexes, so that they will not diffuse to the surface, that is, no copper pollution pattern will be formed; and if the first step of heat treatment (i.e. the step of oxygen nucleus formation) is omitted, no oxygen nuclei will be enlarged, that is, no cluster defects will be formed, and the copper complex will not be adsorbed, so it can diffuse to the surface, forming a copper pollution pattern.

[0054] Pi region: There are a large number of interstitial point defects in the Pi region. Different from vacancy point defects, even after the first step of heat treatment, oxygen nuclei cannot be formed because there is no location for oxygen nuclei to be generated (i.e., vacancies). Therefore, in the Pi region, no matter which heat treatment method is used, the copper complex will not be adsorbed and will diffuse smoothly to the surface of the silicon wafer, forming a copper contamination pattern.

[0055] According to the above characteristics, two silicon wafers to be tested are subjected to different heat treatments, the two silicon wafers to be tested include a first silicon wafer and a second silicon wafer, if no copper contamination pattern appears on the first silicon wafer and a copper contamination pattern appears on the second silicon wafer, then the corresponding area on the silicon wafer to be tested is determined to be a pv area;

[0056] If copper contamination patterns appear on both the first sub-silicon wafer and the second sub-silicon wafer, the area corresponding to the silicon wafer to be inspected is determined to be the pi area.

[0057] In an exemplary embodiment, two sub-silicon wafers to be detected include a first sub-silicon wafer and a second sub-silicon wafer. The two sub-silicon wafers to be detected are subjected to different heat treatments, and the defects of the silicon wafers to be detected are judged according to whether the two sub-silicon wafers to be detected show copper contamination patterns, specifically including:

[0058] The first silicon wafer is subjected to two consecutive heat treatments to make the vacancy point defects form cluster defects to adsorb copper complexes, so that no copper contamination pattern is formed on the surface of the first silicon wafer;

[0059] The second silicon wafer is subjected to a heat treatment so that a copper contamination pattern can be formed on an area of ​​the second silicon wafer without cluster defects.

[0060] It should be noted that the first sub-silicon wafer is subjected to two consecutive heat treatments, wherein the temperature is increased during the first heat treatment and then the second heat treatment is performed without interruption, and the temperature of the first heat treatment is lower than the temperature of the second heat treatment.

[0061] It should be noted that, in the step of subjecting the second sub-silicon wafer to a heat treatment, relative to subjecting the first sub-silicon wafer to a heat treatment twice in a row, it is equivalent to omitting the first heat treatment of the first sub-silicon wafer in the two consecutive heat treatments and directly subjecting the second heat treatment to the first sub-silicon wafer, but the temperature and time of the second heat treatment of the first sub-silicon wafer in the two consecutive heat treatments may be the same as or different from the temperature and time of subjecting the second sub-silicon wafer to a heat treatment once, and the temperature of the first heat treatment of the first sub-silicon wafer in the two consecutive heat treatments is lower than the temperature of subjecting the second sub-silicon wafer to a heat treatment once.

[0062] In an exemplary implementation, the defect detection method of the silicon wafer in this embodiment can be used to determine not only the pv area and the pi area, but also other areas.

[0063] v-rich area: Since there are a large number of clustered vacancy defects in the v-rich area, as long as the above heat treatment is performed, whether it is continuous heat treatment on both sides or only one heat treatment, the copper complex will be easily adsorbed by the internal defects and will not diffuse to the surface; therefore, when observed under a high light, it can be found that there is no copper contamination pattern on the surface;

[0064] i-rich area: Since there are a large number of clustered interstitial defects in the i-rich area, the copper complex will be easily adsorbed by the internal defects after the above-mentioned heat treatment, whether it is continuous heat treatment on both sides or only one heat treatment; and since the point defects in this area have been clustered, sporadic copper pollution patterns can still be seen spreading to the surface. Therefore, even in the case of copper complex adsorption, there is no copper pollution pattern phenomenon on the surface, among which the density of the i-rich area is slightly higher than that of the Pv area.

[0065] In summary, in this embodiment, two silicon wafers to be tested are subjected to different heat treatments, and the defects of the silicon wafers to be tested are judged according to whether the two silicon wafers to be tested show copper contamination patterns, which specifically includes:

[0066] If no copper contamination pattern appears on the first sub-silicon wafer and the second sub-silicon wafer, it is determined that the defects of the silicon wafer to be tested are v-rich and i-rich;

[0067] If the copper contamination pattern does not appear on the first sub-silicon wafer, and the copper contamination pattern appears on the second sub-silicon wafer, then the corresponding area on the silicon wafer to be tested is determined to be the pv area;

[0068] If copper contamination patterns appear on both the first sub-silicon wafer and the second sub-silicon wafer, the corresponding area on the silicon wafer to be inspected is determined to be the pi area.

[0069] Figure 2-Figure 9 They are schematic diagrams of sub-silicon wafers to be tested after different heat treatments, wherein the sub-silicon wafer on the left is the first sub-silicon wafer after two consecutive heat treatments, and the sub-silicon wafer on the right is the second sub-silicon wafer after one heat treatment.

[0070] It should be noted that, in the two consecutive heat treatments performed on the left sub-silicon wafer, the first one is a low-temperature heat treatment and the second one is a high-temperature heat treatment, and the right sub-silicon wafer performs one heat treatment. Compared with the left sub-silicon wafer performing two consecutive heat treatments, it is equivalent to the right sub-silicon wafer omitting the first heat treatment of the two consecutive heat treatments performed on the left sub-silicon wafer and directly performing the second heat treatment, that is, the right sub-silicon wafer directly performs high-temperature heat treatment.

[0071] Exemplarily, the conditions for the first sub-silicon wafer to undergo two consecutive heat treatments include: the temperature is 800-950 degrees, the heating time is 50-250 minutes, and the temperature is 950-1050 degrees, and the heating time is 50-200 minutes; the conditions for the second sub-silicon wafer to undergo one heat treatment include: 950-1050 degrees, and the heating time is 50-200 minutes.

[0072] It should be noted that, according to the different oxygen concentrations of the silicon wafer to be detected, the temperature and time of the heat treatment of the sub-silicon wafer to be detected are set differently. Several setting methods in this embodiment are introduced below.

[0073] In an exemplary embodiment, when the oxygen concentration on the silicon wafer to be tested is greater than 11.5, the conditions for the first sub-silicon wafer to undergo two consecutive heat treatments include: a temperature of 870 degrees, a heating time of 220 minutes and a temperature of 1000 degrees, and a heating time of 120 minutes; the conditions for the second sub-silicon wafer to undergo one heat treatment include: a temperature of 980 degrees, and a heating time of 190 minutes.

[0074] In an exemplary embodiment, when the oxygen concentration on the silicon wafer to be tested is between 10.5-11.5, the conditions for the first sub-silicon wafer to undergo two consecutive heat treatments include: a temperature of 870 degrees and a heating time of 120 minutes; and a temperature of 1000 degrees and a heating time of 120 minutes; the conditions for the second sub-silicon wafer to undergo one heat treatment include: a temperature of 1000 degrees and a heating time of 120 minutes.

[0075] In an exemplary embodiment, when the oxygen concentration on the silicon wafer to be tested is between 9.5-10.5, the conditions for performing two consecutive heat treatments on the first sub-silicon wafer include: a temperature of 870 degrees and a heating time of 85 minutes; and a temperature of 1000 degrees and a heating time of 120 minutes; the conditions for performing one heat treatment on the second sub-silicon wafer include: a temperature of 1000 degrees and a heating time of 55 minutes.

[0076] In an exemplary embodiment, when the oxygen concentration on the silicon wafer to be tested is less than 9.5, the conditions for the first sub-silicon wafer to undergo two consecutive heat treatments include: a temperature of 870 degrees and a heating time of 85 minutes; and a temperature of 1000 degrees and a heating time of 120 minutes; the conditions for the second sub-silicon wafer to undergo one heat treatment include: a temperature of 940 degrees and a heating time of 50 minutes.

[0077] It should be noted that the Band area is a junction area, and different situations may occur depending on the size of the COP. It is possible that a small amount of copper contamination pattern appears or no copper contamination pattern appears. In order to accurately identify this area, in this embodiment, two silicon wafers to be tested are subjected to different heat treatments, and the defects of the silicon wafer to be tested are judged based on whether the copper contamination pattern appears on the two silicon wafers to be tested, which also includes:

[0078] When the copper contamination patterns on the two sub-silicon wafers to be inspected are relatively dispersed or there is no copper contamination pattern, the DSOD method is used to determine whether there is a COP area on the silicon wafer to be inspected.

[0079] The DSOD test method is a method for testing the distribution of small-sized COP (crystal native defects). The specific operation of the DSOD detection method is: high-temperature thermal oxidation of the prepared polished silicon wafer to grow an oxide film of a specific thickness; HF acid (hydrofluoric acid) is used to etch the local oxide film on the back of the silicon wafer to achieve the purpose of conductivity; the etched silicon wafer is cleaned and blown dry; Dummy silicon wafers are used to make the electrolyte solution have enough copper ions; copper is precipitated on the oxide film on the front of the silicon wafer to be evaluated; finally, the defects of the silicon wafer are evaluated by the number and distribution of copper deposits on the defective parts of the silicon wafer. Therefore, for small-sized native defects, the accuracy of the DSOD test results is of great significance to the evaluation of silicon wafer quality.

[0080] Through the above judgment method, we can find that no matter in the Pv area or the Pi area, the heat-treated sub-silicon wafers to be tested all show copper contamination patterns. No other areas have this feature. Based on this phenomenon, we can optimize the qualitative judgment method of surface copper contamination pattern into a quantitative detection method and use it for mass production. That is: by scanning the density of the copper contamination pattern on the surface of the silicon wafer for calculation and measuring the width of the copper contamination pattern, we can determine whether the silicon wafer is in the Pv area or the Pi area (i.e., the COP Free area).

[0081] Since the point defects in the i-rich area have been clustered, sporadic copper contamination patterns can still be seen spreading to the surface. In order to eliminate interference, in this embodiment, the two silicon wafers to be tested are subjected to different heat treatments, and the defects of the silicon wafer to be tested are judged based on whether the copper contamination patterns appear on the two silicon wafers to be tested. The steps include:

[0082] An image of the sub-silicon wafer to be detected is acquired, and the image is binarized, and the width of the area of ​​the copper contamination pattern on the surface of the sub-silicon wafer to be detected in the radial direction of the sub-silicon wafer to be detected is obtained according to the binarized image; for example, a result with a density lower than a fixed value is regarded as having no copper contamination pattern, and the image is displayed as black; a result with a density higher than the value is regarded as having a copper contamination pattern on the surface, and the image is displayed as white.

[0083] If the width of the region of the copper contamination pattern in the radial direction of the sub-silicon wafer to be detected is greater than a preset value, the region of the copper contamination pattern is determined to be a COP free region.

[0084] Fig.10 Displays the original scanned image. Fig.11 This is a schematic diagram of the original scanned image after recognition. Fig.12 This is a schematic diagram after binarization processing. It can be seen that each defect area can be more clearly distinguished.

[0085] Exemplarily, this embodiment further provides a copper contamination pattern analysis device, including a closed and dark chamber, and a high-brightness light source for scanning images, specifically including an image scanning unit, an image recognition unit, and a binarization processing unit.

[0086] In an exemplary embodiment, two silicon wafers to be tested are subjected to metal contamination treatment, specifically including:

[0087] The two silicon wafers to be detected are immersed in a buffered oxidant (BOE) solution containing copper nitrate, wherein the concentration of copper ions is 3-8 ppmw.

[0088] In an exemplary embodiment, before the step of subjecting the two to-be-detected silicon wafers to metal contamination treatment, the following steps are also included:

[0089] The two silicon wafers to be tested are cleaned with HF (hydrofluoric acid) (hydrofluoric acid can react with oxides on the surface of the silicon wafers) to remove contamination on the surface of the silicon wafers to be tested.

[0090] In an exemplary embodiment, after the step of subjecting two to-be-detected silicon wafers to metal contamination treatment, the method further includes:

[0091] The two silicon wafers to be detected are rinsed with ultrapure water to remove the copper ions remaining on the surfaces of the two silicon wafers to be detected, and then completely dried.

[0092] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A method for detecting silicon wafer defects, characterized in that: The following steps are involved: Cutting the silicon wafer to be tested into two sub-silicon wafers to be tested; The two silicon wafers to be tested are subjected to metal contamination treatment; The two silicon wafers to be tested are subjected to different heat treatments, and the defects of the silicon wafers to be tested are determined according to whether the two silicon wafers to be tested show copper contamination patterns; The two sub-silicon wafers to be tested include a first sub-silicon wafer and a second sub-silicon wafer. The two sub-silicon wafers to be tested are subjected to different heat treatments, and the defects of the silicon wafers to be tested are judged according to whether the copper contamination patterns appear on the two sub-silicon wafers to be tested, specifically including: The first silicon wafer is subjected to two consecutive heat treatments to make the vacancy point defects form cluster defects to adsorb copper complexes, so that no copper contamination pattern is formed on the surface of the first silicon wafer; The second silicon wafer is subjected to a heat treatment so that a copper contamination pattern can be formed on an area of ​​the second silicon wafer without cluster defects; The first silicon wafer is subjected to two consecutive heat treatments, including a first heat treatment and a second heat treatment, wherein the second heat treatment is directly heated from the first heat treatment, there is no interruption between the first heat treatment and the second heat treatment, and the temperature of the first heat treatment is lower than the temperature of the second heat treatment; The temperature of the first treatment is lower than the temperature of the first heat treatment of the second silicon wafer; The two silicon wafers to be tested are subjected to different heat treatments, and the defects of the silicon wafers to be tested are judged according to whether the copper contamination patterns appear on the two silicon wafers to be tested, specifically including: If no copper contamination pattern appears on the first sub-silicon wafer and the second sub-silicon wafer, then determining that the area corresponding to the silicon wafer to be tested is a v-rich area and an i-rich area; If the copper contamination pattern does not appear on the first sub-silicon wafer, and the copper contamination pattern appears on the second sub-silicon wafer, then the corresponding area on the silicon wafer to be tested is determined to be a pv area; If copper contamination patterns appear on both the first sub-silicon wafer and the second sub-silicon wafer, then the area corresponding to the silicon wafer to be tested is determined to be the pi area; When the copper contamination patterns on the two sub-silicon wafers to be inspected are dispersedly arranged, the DSOD method is used to determine whether the silicon wafer to be inspected has a COP defect.

2. The method for detecting silicon wafer defects according to claim 1, characterized in that: The conditions for the first sub-silicon wafer to be heat-treated twice continuously include: temperature of 800-950 degrees, heating time of 50-250 minutes; and temperature of 950-1050 degrees, heating time of 50-200 minutes; the conditions for the second sub-silicon wafer to be heat-treated once include: 950-1050 degrees, heating time of 50-200 minutes.

3. The method for detecting silicon wafer defects according to claim 1, characterized in that: The conditions for the first silicon wafer to be heat-treated twice in succession include: a temperature of 870 degrees and a heating time of 220 minutes; and a temperature of 1000 degrees and a heating time of 120 minutes; the conditions for the second silicon wafer to be heat-treated once include: a temperature of 980 degrees and a heating time of 190 minutes; When the oxygen concentration on the silicon wafer to be tested is greater than 11.5, the conditions for the first silicon wafer to be heat-treated twice in succession include: a temperature of 870 degrees and a heating time of 220 minutes; and a temperature of 1000 degrees and a heating time of 120 minutes; the conditions for the second silicon wafer to be heat-treated once include: a temperature of 980 degrees and a heating time of 190 minutes; When the oxygen concentration on the silicon wafer to be tested is between 10.5 and 11.5, the conditions for the first silicon wafer to be heat-treated twice in succession include: a temperature of 870 degrees and a heating time of 120 minutes; and a temperature of 1000 degrees and a heating time of 120 minutes; the conditions for the second silicon wafer to be heat-treated once include: a temperature of 1000 degrees and a heating time of 120 minutes; When the oxygen concentration on the silicon wafer to be tested is between 9.5 and 10.5, the conditions for the first silicon wafer to be heat-treated twice in succession include: a temperature of 870 degrees and a heating time of 85 minutes; and a temperature of 1000 degrees and a heating time of 120 minutes; the conditions for the second silicon wafer to be heat-treated once include: a temperature of 1000 degrees and a heating time of 55 minutes; When the oxygen concentration on the silicon wafer to be tested is less than 9.5, the conditions for the first sub-silicon wafer to undergo two consecutive heat treatments include: a temperature of 870 degrees and a heating time of 85 minutes; and a temperature of 1000 degrees and a heating time of 120 minutes; the conditions for the second sub-silicon wafer to undergo one heat treatment include: a temperature of 940 degrees and a heating time of 50 minutes.

4. The method for detecting silicon wafer defects according to claim 1, characterized in that: The step of determining the defects of the silicon wafer to be inspected comprises: Acquire an image of the sub-silicon wafer to be detected, perform binarization processing on the image, and obtain the width of the region of the copper contamination pattern on the surface of the sub-silicon wafer to be detected in the radial direction of the sub-silicon wafer to be detected according to the binarized image; If the width of the region of the copper contamination pattern in the radial direction of the sub-silicon wafer to be detected is greater than a preset value, the region of the copper contamination pattern is determined to be a COP free region.

5. The method for detecting silicon wafer defects according to claim 1, characterized in that: The two silicon wafers to be tested are subjected to metal contamination treatment, specifically including: The two silicon wafers to be detected are immersed in a buffered oxidant solution containing copper nitrate, wherein the copper ion concentration is 3-8 ppmw.

6. The method for detecting silicon wafer defects according to claim 1, characterized in that: Before the two silicon wafers to be tested are subjected to metal contamination treatment, the following steps are also included: The two silicon wafers to be detected are cleaned by using HF.

Images