Scanning speed determination method and device, electronic device and storage medium

Abstract

The present disclosure relates to a method and device for determining a scanning speed, an electronic device, and a computer-readable storage medium, and relates to the field of semiconductor production and manufacturing technology, and can be applied to scenarios for determining the TVS scanning speed of semiconductors. The method includes: obtaining a semiconductor to be tested, applying an initial voltage to the semiconductor to be tested, triggering the semiconductor to be tested to generate a potential step, and stepping to a constant potential state; applying the initial voltage based on a specific scanning speed; applying a disturbance voltage to the semiconductor to be tested in a constant potential state to obtain the charge state of the semiconductor to be tested in a constant potential state; in response to the charge state being in a charge activity equilibrium state, using the scanning speed in the charge activity equilibrium state as the target scanning speed of the semiconductor to be tested. The present disclosure can determine whether a semiconductor satisfies a quasi-static distribution based on the current scanning speed of the semiconductor, without the need for an additional experiment.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor production and manufacturing technology, and in particular to a scanning speed determination method, a scanning speed determination device, an electronic device, and a computer-readable storage medium. Background Art

[0002] Gate oxide charge density is commonly measured using a triangular voltage sweep (TVS) technique. TVS measurement relies on ensuring that the mobile ion charge distribution achieves a quasi-static distribution—a state in which the mobile ion charge distribution remains constant over time. To achieve this, the TVS scan speed is crucial. If the scan speed is too fast, quasi-static conditions are not met; if it is too slow, the test time is prolonged.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a scanning speed determination method, a scanning speed determination device, an electronic device, and a computer-readable storage medium, thereby overcoming, at least to a certain extent, the problem that the current determination of the scanning speed required for TVS measurement requires an additional experiment to determine whether the charge reaches a quasi-static state, resulting in low speed determination efficiency.

[0005] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0006] According to a first aspect of the present disclosure, a method for determining a scan speed is provided, comprising: obtaining a semiconductor to be tested, applying an initial voltage to the semiconductor to be tested, triggering the semiconductor to be tested to generate a potential step, and stepping to a constant potential state; applying the initial voltage is performed based on a specific scan speed;

[0007] A disturbance voltage is applied to the semiconductor to be tested in a constant potential state to obtain a charge state of the semiconductor to be tested in the constant potential state; in response to the charge state being in a charge activity equilibrium state, a scanning speed in the charge activity equilibrium state is used as a target scanning speed of the semiconductor to be tested.

[0008] In an exemplary embodiment of the present disclosure, applying an initial voltage to the semiconductor to be tested to trigger the semiconductor to be tested to generate a potential step includes: determining a scan start time point for performing a voltage scan on the semiconductor to be tested; and performing a voltage scan on the gate oxide layer of the semiconductor to be tested based on the scan start time point and the initial voltage to trigger the semiconductor to be tested to generate a potential step.

[0009] In an exemplary embodiment of the present disclosure, performing a voltage scan on the gate oxide layer of the semiconductor to be tested according to the scan starting time point and the initial voltage includes: determining an initial scan speed for performing a voltage scan on the semiconductor to be tested; and performing a voltage scan on the gate oxide layer starting from the scan starting time point based on the initial scan speed and the initial voltage.

[0010] In an exemplary embodiment of the present disclosure, performing a voltage scan on the gate oxide layer starting from the scan start time point includes: determining a scan duration for performing a voltage scan on the gate oxide layer; the scan duration is the continuous time for scanning the gate oxide layer using the initial voltage; starting from the scan start time point, performing a continuous voltage scan on the gate oxide layer based on the scan duration to trigger the semiconductor to be tested to generate a potential step.

[0011] In an exemplary embodiment of the present disclosure, determining the scan duration of the voltage scan on the gate oxide layer includes: determining the characteristic frequency of the mobile ionic charge in the semiconductor to be tested; and determining the scan duration of the voltage scan on the semiconductor to be tested based on the characteristic frequency.

[0012] In an exemplary embodiment of the present disclosure, applying a disturbance voltage to a semiconductor to be tested that is in a constant potential state to obtain a charge state of the semiconductor to be tested in the constant potential state includes: applying the disturbance voltage to the semiconductor to be tested in response to detecting that the semiconductor to be tested is in a constant potential state; receiving state response information of the semiconductor to be tested after applying the disturbance voltage; and determining the charge state of the semiconductor to be tested in the constant potential state based on the state response information.

[0013] In an exemplary embodiment of the present disclosure, determining the charge state of the semiconductor to be tested in a constant potential state based on the state response information includes: determining the real part of the impedance and the imaginary part of the impedance of the mobile ion charge in the semiconductor to be tested based on the state response information; determining the real-imaginary correlation relationship between the real part of the impedance and the imaginary part of the impedance; and determining the charge state of the semiconductor to be tested in a constant potential state based on the imaginary-real correlation relationship.

[0014] In an exemplary embodiment of the present disclosure, determining the charge state of the semiconductor to be tested in a constant potential state based on the virtual-real correlation relationship includes: obtaining a pre-configured complex semi-analytical function; determining a matching result between the virtual-real correlation relationship and the complex semi-analytical function; and determining the charge state based on the matching result.

[0015] In an exemplary embodiment of the present disclosure, determining the charge state according to the matching result includes: if the imaginary-real association relationship matches the complex semi-analyzable function, determining the charge state as the charge activity equilibrium state.

[0016] In an exemplary embodiment of the present disclosure, determining the charge state according to the matching result includes: if the imaginary-real correlation relationship does not match the complex semi-analyzable function, adjusting a scanning speed for the semiconductor to be tested.

[0017] In an exemplary embodiment of the present disclosure, if the imaginary-real correlation relationship does not match the complex semi-analytical function, adjusting the scanning speed for the semiconductor to be tested includes: if the imaginary-real correlation relationship does not match the complex semi-analytical function, increasing the scanning duration of the voltage scan for the semiconductor to be tested.

[0018] In an exemplary embodiment of the present disclosure, if the imaginary-real correlation relationship does not match the complex semi-analytical function, adjusting the scanning speed for the semiconductor to be tested includes: if the imaginary-real correlation relationship does not match the complex semi-analytical function, adjusting the disturbance voltage applied to the semiconductor to be tested to obtain an updated disturbance voltage; applying the updated disturbance voltage to the semiconductor to be tested in a constant potential state, and determining the target scanning speed of the semiconductor to be tested according to the updated disturbance voltage.

[0019] According to a second aspect of the present disclosure, a scanning speed determination device is provided, comprising: a potential step triggering module, configured to obtain a semiconductor to be tested, apply an initial voltage to the semiconductor to be tested, trigger the semiconductor to be tested to generate a potential step, and step to a constant potential state; the applying of the initial voltage is performed based on a specific scanning speed;

[0020] A charge state determination module is used to apply a disturbance voltage to the semiconductor to be tested in a constant potential state to obtain the charge state of the semiconductor to be tested in the constant potential state; a target speed determination module is used to respond to the charge state being in a charge activity equilibrium state and use the scanning speed in the charge activity equilibrium state as the target scanning speed of the semiconductor to be tested.

[0021] In an exemplary embodiment of the present disclosure, the potential step trigger module includes a potential step trigger unit, which is used to determine a scanning starting time point for performing a voltage scan on the semiconductor to be tested; based on the scanning starting time point and the initial voltage, a voltage scan is performed on the gate oxide layer of the semiconductor to be tested to trigger the semiconductor to be tested to generate a potential step.

[0022] In an exemplary embodiment of the present disclosure, the potential step trigger unit includes a voltage scanning unit for determining an initial scanning speed for performing voltage scanning on the semiconductor to be tested; based on the initial scanning speed and the initial voltage, the gate oxide layer is voltage scanned starting from the scanning start time point.

[0023] In an exemplary embodiment of the present disclosure, the voltage scanning unit includes a voltage scanning sub-unit for determining a scanning duration for performing a voltage scan on the gate oxide layer; the scanning duration is the continuous time for scanning the gate oxide layer using the initial voltage; starting from the scanning start time point, the gate oxide layer is continuously voltage scanned based on the scanning duration to trigger the semiconductor to be tested to generate a potential step.

[0024] In an exemplary embodiment of the present disclosure, the voltage scanning unit includes a scanning duration determining unit for determining a characteristic frequency of mobile ionic charges in the semiconductor to be tested; and determining a scanning duration for performing a voltage scan on the semiconductor to be tested based on the characteristic frequency.

[0025] In an exemplary embodiment of the present disclosure, the charge state determination module includes a charge state determination unit for applying the disturbance voltage to the semiconductor to be tested in response to detecting that the semiconductor to be tested is in a constant potential state; receiving state response information of the semiconductor to be tested after the disturbance voltage is applied; and determining the charge state of the semiconductor to be tested in the constant potential state based on the state response information.

[0026] In an exemplary embodiment of the present disclosure, the charge state determination unit includes a charge state determination sub-unit, which is used to determine the real part of the impedance and the imaginary part of the impedance of the mobile ion charge in the semiconductor to be tested based on the state response information; determine the real-imaginary correlation relationship between the real part of the impedance and the imaginary part of the impedance; and determine the charge state of the semiconductor to be tested in a constant potential state based on the imaginary-real correlation relationship.

[0027] In an exemplary embodiment of the present disclosure, the charge state determination subunit includes a matching result determination subunit, which is used to obtain a pre-configured complex semi-analyzable function; determine the matching result between the virtual-real association relationship and the complex semi-analyzable function; and determine the charge state based on the matching result.

[0028] In an exemplary embodiment of the present disclosure, the matching result determination subunit includes a first result determination subunit for determining the charge state as the charge activity equilibrium state if the imaginary-real association relationship matches the complex semi-analyzable function.

[0029] In an exemplary embodiment of the present disclosure, the matching result determining subunit includes a second result determining subunit configured to adjust a scanning speed for the semiconductor to be tested if the imaginary-real association relationship does not match the complex semi-analytical function.

[0030] In an exemplary embodiment of the present disclosure, the scanning speed determining apparatus includes a first speed adjusting unit for increasing a scanning duration of a voltage scan for the semiconductor to be tested if the imaginary-real correlation relationship does not match the complex semi-analytical function.

[0031] In an exemplary embodiment of the present disclosure, the scanning speed determination device includes a second speed adjustment unit, which is used to adjust the disturbance voltage applied to the semiconductor to be tested to obtain an updated disturbance voltage if the imaginary-real correlation relationship does not match the complex semi-analyzable function; apply the updated disturbance voltage to the semiconductor to be tested in a constant potential state, and determine the target scanning speed of the semiconductor to be tested according to the updated disturbance voltage.

[0032] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the scanning speed determination method according to any one of the above items is implemented.

[0033] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the scanning speed determination method according to any one of the above items is implemented.

[0034] The technical solution provided by the present disclosure may have the following beneficial effects:

[0035] The scanning speed determination method in the exemplary embodiment of the present disclosure can determine whether the current scanning speed meets the conditions of quasi-static distribution through the experimental data of the current voltage scanning of the semiconductor to be tested, thereby avoiding adding an additional scanning experiment and improving experimental efficiency.

[0036] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0038] Figure 1 Schematically illustrates a schematic diagram of scanning a semiconductor using a triangle wave voltage scanning method according to an exemplary embodiment of the present disclosure;

[0039] Figure 2 Schematically illustrates a relationship between a scan voltage and a current charge state during a triangle wave voltage scanning method according to an exemplary embodiment of the present disclosure;

[0040] Figure 3 Schematically shows a flow chart of a method for determining a scanning speed according to an exemplary embodiment of the present disclosure;

[0041] Figure 4 Schematically shows a schematic diagram of applying a disturbance voltage to a semiconductor to be tested according to an exemplary embodiment of the present disclosure;

[0042] Figure 5 Schematically shows a schematic diagram of a matching result between a virtual-real association relationship and a complex semi-analytical function according to an exemplary embodiment of the present disclosure;

[0043] Figure 6 Schematically shows a block diagram of a scanning speed determination apparatus according to an exemplary embodiment of the present disclosure;

[0044] Figure 7 A block diagram schematically illustrates an electronic device according to an exemplary embodiment of the present disclosure;

[0045] Figure 8 A schematic diagram schematically illustrates a computer-readable storage medium according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the drawings represent like or similar parts, and thus repetitive description thereof will be omitted.

[0047] In addition, the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known structures, methods, devices, implementations, materials or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0048] The blocks shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. Specifically, these functional entities may be implemented in software, or in one or more software-hardened modules, or in different networks and / or processor devices and / or microcontroller devices.

[0049] The commonly used method for determining the required sweep speed for TVS measurement is based on the fact that as the sweep speed is further slowed down, the TVS curves overlap. Figure 1 , Figure 1 Schematic diagram of scanning a semiconductor using a triangle wave voltage scanning method according to an exemplary embodiment of the present disclosure is shown. Figure 1 It can be seen that during the semiconductor voltage scanning process, the scanning speed must be continuously adjusted to make the scanning speed meet the point where the mobile ion charge current in the semiconductor is stable, that is, the point corresponding to quasi-static. At this time, the semiconductor itself reaches a quasi-static state.

[0050] In order to achieve a quasi-static distribution of charge in the semiconductor gate oxide layer, the selection of TVS scanning speed is extremely important. If the scanning speed is too fast, the quasi-static state is not satisfied. If the scanning speed is too slow, the test time will be extended. Figure 2 , Figure 2 A diagram schematically illustrates the relationship between the scan voltage and the current state of charge during the triangular wave voltage scanning method according to an exemplary embodiment of the present disclosure. Therefore, determining the scan speed required for TVS measurement requires at least one additional experiment to determine whether a quasi-static state has been achieved, resulting in low speed determination efficiency.

[0051] Based on this, in this example embodiment, a scanning speed determination method is first provided. The scanning speed determination method of the present disclosure can be implemented using a server, or the method described in the present disclosure can be implemented using a terminal device. The terminals described in the present disclosure may include mobile terminals such as mobile phones, tablet computers, laptops, PDAs, personal digital assistants (PDAs), and fixed terminals such as desktop computers. Figure 3 The following schematically illustrates a flow chart of a method for determining a scanning speed according to some embodiments of the present disclosure. Figure 3 , the scanning speed determination method may include the following steps:

[0052] Step S310 , obtaining a semiconductor to be tested, applying an initial voltage to the semiconductor to be tested, triggering the semiconductor to be tested to generate a potential step, and stepping to a constant potential state; applying the initial voltage is performed based on a specific scanning speed.

[0053] According to some exemplary embodiments of the present disclosure, the semiconductor under test may be a semiconductor subjected to measurement using a voltage sweep method. The initial voltage may be the voltage applied to the semiconductor under test to generate a potential step in the semiconductor under test. A potential step may refer to a change in the state of the semiconductor under test from a first point to a second point. A constant potential state refers to a state in which the energized point of the semiconductor remains at a set control point. The specific sweep speed may be the sweep speed used when performing a voltage sweep on the semiconductor under test.

[0054] When determining the charge density of a semiconductor gate oxide layer, a voltage sweep method is typically used. After acquiring the semiconductor to be tested, an initial voltage can be applied to the semiconductor to be tested. Based on the initial voltage and a specific sweep speed, a voltage sweep is performed on the semiconductor to be tested. The initial voltage triggers a potential step in the semiconductor to be tested, causing the semiconductor to step to a constant potential state. During the voltage sweep of the semiconductor to be tested, the specific sweep speed can be adjusted based on the scanning requirements to ultimately determine a target sweep speed that meets the requirements.

[0055] Step S320 , applying a disturbance voltage to the semiconductor to be tested in a constant potential state to obtain a charge state of the semiconductor to be tested in the constant potential state.

[0056] According to some exemplary embodiments of the present disclosure, a perturbation voltage may refer to a voltage applied to cause instability and fluctuation in the semiconductor under test. A charge state may refer to the state of mobile ionic charges in the semiconductor under test. Mobile ionic charges may refer to mobile ionized positive ionic charges in silicon dioxide. Most of these charges are metal ions and positive hydrogen ions.

[0057] When the semiconductor to be tested is in a constant potential state, a disturbance voltage can be applied to the semiconductor to be tested, causing the semiconductor to be tested to be unstable or fluctuating. When the disturbance voltage is applied to the semiconductor to be tested in a constant potential state, a voltage scan can be performed on the semiconductor to be tested at a certain scanning speed, and the charge state of the semiconductor to be tested at a certain scanning speed can be obtained.

[0058] In step S330 , in response to the charge state being in the charge activity equilibrium state, a scan speed corresponding to the current charge state is used as a target scan speed of the semiconductor to be tested.

[0059] According to some exemplary embodiments of the present disclosure, the charge activity equilibrium state may be a state in which mobile ionic charges in the semiconductor under test are in a quasi-static state. The current charge state may be the charge state of the semiconductor under test at the current moment. The scan speed may be the speed currently used to perform a voltage sweep on the semiconductor under test. The target scan speed may be the scan speed corresponding to a quasi-static charge state of the semiconductor under test.

[0060] By continuously acquiring the charge state of the semiconductor to be tested, the current state of the semiconductor to be tested can be continuously analyzed. If it is detected that the charge state of the semiconductor to be tested currently acquired is in a charge activity equilibrium state, that is, the semiconductor to be tested is in a quasi-static charge state, therefore, the current charge state corresponding to the semiconductor to be tested is determined, and the scanning speed of the voltage scanning for the semiconductor to be tested under the current charge state is obtained. The current scanning speed is used as the target scanning speed of the semiconductor to be tested.

[0061] According to the scanning speed determination method in this example embodiment, the experimental data of the current voltage scan of the semiconductor to be tested can be used to determine whether the current scanning speed meets the conditions of quasi-static distribution, avoiding an additional scanning experiment and improving experimental efficiency.

[0062] Next, the scanning speed determination method in this exemplary embodiment will be further described.

[0063] In an exemplary embodiment of the present disclosure, an initial voltage is applied to a semiconductor to be tested to trigger the semiconductor to be tested to generate a potential step, including: determining a scan start time point for performing a voltage scan on the semiconductor to be tested; and performing a voltage scan on the gate oxide layer of the semiconductor to be tested according to the scan start time point and the initial voltage to trigger the semiconductor to be tested to generate a potential step.

[0064] The scanning start time point may be a start time point for performing a voltage scan on the semiconductor to be tested.

[0065] Before applying an initial voltage to the semiconductor under test, a scan start time point for performing a voltage scan on the semiconductor under test can be determined. That is, the voltage scan can be performed on the semiconductor under test starting from the scan start time point. During the voltage scan, a voltage scan can be performed on the gate oxide layer of the semiconductor under test based on the scan start time point and the initial voltage to trigger a potential step in the semiconductor under test. After the potential step is generated in the semiconductor under test, a subsequent scan speed determination operation is performed on the semiconductor under test.

[0066] In an exemplary embodiment of the present disclosure, a voltage scan is performed on the gate oxide layer of the semiconductor to be tested according to the scan start time point and the initial voltage, including: determining an initial scan speed for the voltage scan of the semiconductor to be tested; and based on the initial scan speed and the initial voltage, starting from the scan start time point, performing a voltage scan on the gate oxide layer.

[0067] The initial scanning speed may be a scanning speed used to scan the semiconductor to be tested using an initial voltage.

[0068] Before performing a voltage scan on the semiconductor under test based on the initial voltage, a corresponding initial scan speed may be determined. That is, the initial scan speed will be used during the voltage scan of the semiconductor under test using the initial voltage. After the initial scan speed is determined, a voltage scan is performed on the gate oxide layer starting from the scan start time based on the initial scan speed and the initial voltage to generate a potential step in the semiconductor under test.

[0069] In an exemplary embodiment of the present disclosure, starting from a scan start time point, a voltage scan is performed on the gate oxide layer, including: determining a scan duration for the voltage scan of the gate oxide layer; the scan duration is the continuous time for scanning the gate oxide layer using an initial voltage; starting from the scan start time point, a continuous voltage scan is performed on the gate oxide layer based on the scan duration to trigger a potential step in the semiconductor to be tested.

[0070] The scanning duration may be the duration of scanning the gate oxide layer of the semiconductor to be tested using the initial voltage.

[0071] The process of applying an initial voltage to the semiconductor under test needs to last for a certain period of time. Therefore, before performing the voltage scan, the scan duration can be determined. After determining the scan start time, an initial voltage corresponding to the scan duration can be applied to the semiconductor under test starting at the scan start time, and a continuous voltage scan can be performed on the gate oxide layer to trigger a potential step in the semiconductor under test.

[0072] In an exemplary embodiment of the present disclosure, determining a scan duration for performing a voltage scan on a gate oxide layer includes: determining a characteristic frequency of mobile ionic charges in a semiconductor to be tested; and determining a scan duration for performing a voltage scan on the semiconductor to be tested based on the characteristic frequency.

[0073] The characteristic frequency may refer to a cutoff frequency at which the main function of the mobile ion charges in the semiconductor to be tested is reduced to a level that is difficult to use.

[0074] According to the inherent characteristics of the mobile ion charge in the semiconductor to be tested, the scanning duration (Potentiostatic time) can usually be determined according to the characteristic frequency of the mobile ion charge. Since the constant potential time is actually the relaxation time of the mobile ion charge, based on the relevant content of testing the characteristic frequency of the mobile ion charge, it can be known that the reciprocal of the characteristic frequency of the mobile ion charge is the time constant. The characteristic frequency of the mobile ion charge can be used to roughly know the range of the constant potential time.

[0075] Therefore, the duration of a voltage sweep performed on the semiconductor under test can be determined based on the characteristic frequency of the mobile ion charge. For example, the duration of the sweep, i.e., the initial potentiostatic time, can be determined based on the measured characteristic frequency f1 of the mobile ion charge. The initial potentiostatic time can be the inverse of the characteristic frequency.

[0076] In an exemplary embodiment of the present disclosure, a disturbance voltage is applied to a semiconductor to be tested that is in a constant potential state to obtain a charge state of the semiconductor to be tested in the constant potential state, including: in response to detecting that the semiconductor to be tested is in a constant potential state, applying a disturbance voltage to the semiconductor to be tested; receiving state response information of the semiconductor to be tested after the disturbance voltage is applied; and determining the charge state of the semiconductor to be tested in the constant potential state according to the state response information.

[0077] The state response information can be the response information of the charge state of the semiconductor to be tested under the disturbance voltage after the disturbance voltage is applied to the semiconductor to be tested, which can be expressed as ΔI sub express.

[0078] When the voltage of the semiconductor to be tested is scanned, the current state of the mobile ion charge in the semiconductor to be tested can be continuously detected. When it is detected that the semiconductor to be tested is in a constant potential state, a disturbance voltage ΔV can be applied to the semiconductor to be tested. GS (f1). Reference Figure 4 , Figure 4 A schematic diagram illustrating the application of a perturbation voltage to a semiconductor under test according to an exemplary embodiment of the present disclosure is shown. Under the influence of the perturbation voltage, the semiconductor under test may experience changes in its charge state, which can be derived from state response information. Therefore, after applying the perturbation voltage to the semiconductor under test, state response information of the semiconductor under test after the application of the perturbation voltage can be received. By analyzing the received state response information, the charge state of the semiconductor under test in a constant potential state can be determined based on the state response information.

[0079] In an exemplary embodiment of the present disclosure, the charge state of the semiconductor to be tested in a constant potential state is determined according to the state response information, including: determining the real part of the impedance and the imaginary part of the impedance of the mobile ion charge in the semiconductor to be tested based on the state response information; determining the real-imaginary correlation relationship between the real part of the impedance and the imaginary part of the impedance; and determining the charge state of the semiconductor to be tested in a constant potential state according to the imaginary-real correlation relationship.

[0080] Impedance can be the portion of mobile ionic charge that opposes current flow in a circuit. Impedance is often represented by Z, a complex number. The real part of impedance can be resistance, represented by Re(Z); the imaginary part can be reactance, represented by Im(Z). The real-imaginary-real relationship can be the relationship between the real and imaginary parts of impedance.

[0081] After obtaining the state response information corresponding to the semiconductor under test, the real and imaginary impedance components of the mobile ionic charges in the semiconductor under test can be determined based on the state response information. Furthermore, the real-imaginary correlation between the real and imaginary impedance components can be determined. This correlation can reflect the charge state of the mobile ionic charges in the semiconductor under test. Therefore, the charge state of the semiconductor under test can be determined based on the real-imaginary correlation between the real and imaginary impedance components.

[0082] In an exemplary embodiment of the present disclosure, the charge state of a semiconductor to be tested in a constant potential state is determined based on a virtual-real correlation relationship, including: obtaining a pre-configured complex semi-analytical function; determining a matching result between the virtual-real correlation relationship and the complex semi-analytical function; and determining the charge state based on the matching result.

[0083] The Kramers–Kronig relations are mathematical formulas that relate the real and imaginary parts of complex semianalytical functions. Complex semianalytical functions can be constructed based on the Kramers–Kronig formula to express the relationship between the real and imaginary parts of impedance.

[0084] The Kramers-Kroning relationship between the real impedance (Re(Z)) and the imaginary impedance (Im(Z)) of the mobile ion charge is satisfied only when the metal-oxide-semiconductor system is in a steady state. Furthermore, compared to other processes, mobile ions achieve quasi-statics the slowest. Therefore, achieving quasi-statics based on mobile ion charges is equivalent to achieving quasi-statics with semiconductors.

[0085] To determine whether a semiconductor's mobile ion charge has achieved a quasi-static distribution, single-frequency AC impedance (SFA) testing can be used to measure the mobile ion charge response impedance. If the real and imaginary parts of the impedance satisfy the Kramers-Kroning relationship, this indicates that the mobile ions have achieved a quasi-static distribution within the current potentiostatic time and that the current scan speed can ensure this distribution. Single-frequency testing is used to shorten evaluation time, and the single frequency can be the characteristic frequency of the mobile ion charge or a lower frequency.

[0086] In an exemplary embodiment of the present disclosure, if the imaginary-real association relationship matches the complex semi-analyzable function, the charge state is determined to be a charge activity equilibrium state.

[0087] When the real-imaginary correlation between the real part and the imaginary part of the impedance of the mobile ion charge is obtained, the matching relationship between the real-imaginary correlation and the complex semi-analyzable function can be determined. Figure 5 , Figure 5 A schematic diagram illustrating the matching results between the virtual-real correlation relationship and the complex semi-analytical function according to an exemplary embodiment of the present disclosure is shown. In step S510, if the virtual-real correlation relationship matches the complex semi-analytical function, it indicates that the current real and imaginary impedance parts of the mobile ion charge satisfy the Kramers-Kroning relationship. Therefore, the charge state can be determined to be a charge activity equilibrium state, i.e., a quasi-static state.

[0088] In an exemplary embodiment of the present disclosure, if the imaginary-real correlation relationship does not match the complex semi-analytical function, the scanning speed for the semiconductor to be tested is adjusted.

[0089] If the imaginary-real relationship does not match the complex semianalyzable function, it indicates that the current real and imaginary impedance components of the mobile ion charge do not satisfy the Kramers-Kroning relationship. Therefore, the scan speed for the voltage sweep across the semiconductor under test needs to be adjusted. By adjusting the scan speed, the mobile ion charge in the semiconductor under test satisfies the Kramers-Kroning relationship, and ultimately the target scan speed is determined.

[0090] In an exemplary embodiment of the present disclosure, if the imaginary-real correlation relationship does not match the complex semi-analytical function, adjusting the scanning speed for the semiconductor to be tested includes: if the imaginary-real correlation relationship does not match the complex semi-analytical function, increasing the scanning duration of the voltage scan for the semiconductor to be tested.

[0091] Continue to refer Figure 5 In step S520, when the imaginary-real correlation between the real and imaginary impedance parts does not match the complex semi-analyzable function, the mobile ionic charge of the semiconductor under test is not in a quasi-static state. In this case, the scanning speed of the semiconductor under test needs to be adjusted so that the adjusted scanning speed can place the semiconductor under test in a quasi-static state. Specifically, this can be achieved by increasing the duration of the voltage scan performed on the semiconductor under test, which is equivalent to reducing the initial scanning speed for the semiconductor under test.

[0092] After readjusting the scan speed, the tester can obtain the real-to-virtual relationship between the real and imaginary impedance components of the movable ion charge in real time and determine whether this relationship satisfies the Kramers-Kroning relationship. The tester automatically verifies the Kramers-Kroning relationship and adjusts the Potentiostatic time based on the result, such as increasing the Potentiostatic time. If the charge state still does not satisfy the Kramers-Kroning relationship after the scan speed adjustment, the Potentiostatic time is further adjusted until the real-to-virtual relationship of the movable ion charge satisfies the Kramers-Kroning relationship.

[0093] In an exemplary embodiment of the present disclosure, if the virtual-real correlation relationship does not match the complex semi-analyzable function, the scanning speed for the semiconductor to be tested is adjusted, including: if the virtual-real correlation relationship does not match the complex semi-analyzable function, adjusting the disturbance voltage applied to the semiconductor to be tested to obtain an updated disturbance voltage; applying the updated disturbance voltage to the semiconductor to be tested in a constant potential state, and determining the target scanning speed of the semiconductor to be tested according to the updated disturbance voltage.

[0094] If the virtual-real relationship does not match the complex semianalyzable function, the step of applying a perturbation voltage to the semiconductor under test can be re-executed. Thus, the perturbation voltage applied to the semiconductor under test can be updated to obtain an updated perturbation voltage. The updated perturbation voltage is applied to the semiconductor under test in a constant potential state, and a target scanning speed for the semiconductor under test is determined based on the updated perturbation voltage. The process of determining the target scanning speed based on the updated perturbation voltage is similar to the aforementioned process of applying a perturbation voltage to the semiconductor under test and determining the target scanning speed based on the perturbation voltage, and this disclosure will not further elaborate on this process.

[0095] In addition, in this embodiment, the test mode used for the semiconductor to be tested is CV test (C-V measurement). Therefore, during the test process, there is no need to add new functions to the tester, which can further simplify the test process and improve test efficiency.

[0096] In summary, the scanning speed determination method disclosed herein obtains a semiconductor to be tested, applies an initial voltage to the semiconductor to be tested, triggers the semiconductor to be tested to generate a potential step, and then steps to a constant potential state; applies the initial voltage based on a specific scanning speed; applies a perturbation voltage to the semiconductor to be tested in the constant potential state to obtain the charge state of the semiconductor to be tested in the constant potential state; in response to the charge state being in a charge activity equilibrium state, obtains the current charge state corresponding to the semiconductor to be tested; and uses the scanning speed corresponding to the current charge state as the target scanning speed for the semiconductor to be tested. Using the experimental data of the current voltage scan on the semiconductor to be tested, it is possible to determine whether the current scanning speed meets the conditions of quasi-static distribution, avoiding the need for an additional scanning experiment and improving experimental efficiency.

[0097] It should be noted that although the steps of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0098] In addition, in this exemplary embodiment, a scanning speed determination device is also provided. Figure 6 The scanning speed determination device 600 may include: a potential step trigger module 610 , a charge state determination module 620 and a target speed determination module 630 .

[0099] Specifically, the potential step trigger module 610 is used to obtain the semiconductor to be tested, apply an initial voltage to the semiconductor to be tested, trigger the semiconductor to be tested to generate a potential step, and step to a constant potential state; the application of the initial voltage is based on a specific scanning speed; the charge state determination module 620 is used to apply a disturbance voltage to the semiconductor to be tested in a constant potential state to obtain the charge state of the semiconductor to be tested in a constant potential state; the target speed determination module 630 is used to respond to the charge state being in a charge activity equilibrium state, and use the scanning speed in the charge activity equilibrium state as the target scanning speed of the semiconductor to be tested.

[0100] In an exemplary embodiment of the present disclosure, the potential step trigger module 610 includes a potential step trigger unit for determining a scan start time point for performing a voltage scan on the semiconductor to be tested; based on the scan start time point and the initial voltage, a voltage scan is performed on the gate oxide layer of the semiconductor to be tested to trigger the semiconductor to be tested to generate a potential step.

[0101] In an exemplary embodiment of the present disclosure, the potential step trigger unit includes a voltage scanning unit for determining an initial scanning speed for performing a voltage scan on the semiconductor to be tested; based on the initial scanning speed and the initial voltage, a voltage scan is performed on the gate oxide layer starting from the scanning start time point.

[0102] In an exemplary embodiment of the present disclosure, the voltage scanning unit includes a voltage scanning sub-unit for determining a scanning duration for performing a voltage scan on a gate oxide layer; the scanning duration is the continuous time for scanning the gate oxide layer using an initial voltage; starting from the scanning start time point, the gate oxide layer is continuously voltage scanned based on the scanning duration to trigger a potential step in the semiconductor to be tested.

[0103] In an exemplary embodiment of the present disclosure, the voltage scanning unit includes a scanning duration determining unit for determining a characteristic frequency of mobile ionic charges in the semiconductor to be tested; and determining a scanning duration for performing a voltage scan on the semiconductor to be tested according to the characteristic frequency.

[0104] In an exemplary embodiment of the present disclosure, the charge state determination module 620 includes a charge state determination unit for applying a disturbance voltage to the semiconductor to be tested in response to detecting that the semiconductor to be tested is in a constant potential state; receiving state response information of the semiconductor to be tested after the disturbance voltage is applied; and determining the charge state of the semiconductor to be tested in the constant potential state based on the state response information.

[0105] In an exemplary embodiment of the present disclosure, the charge state determination unit includes a charge state determination sub-unit, which is used to determine the real part of the impedance and the imaginary part of the impedance of the mobile ion charge in the semiconductor to be tested based on the state response information; determine the real-imaginary correlation relationship between the real part of the impedance and the imaginary part of the impedance; and determine the charge state of the semiconductor to be tested in a constant potential state based on the imaginary-real correlation relationship.

[0106] In an exemplary embodiment of the present disclosure, the charge state determination subunit includes a matching result determination subunit, which is used to obtain a pre-configured complex semi-analytical function; determine the matching result between the virtual-real association relationship and the complex semi-analytical function; and determine the charge state according to the matching result.

[0107] In an exemplary embodiment of the present disclosure, the matching result determination subunit includes a first result determination subunit for determining the charge state as a charge activity equilibrium state if the imaginary-real association relationship matches the complex semi-analyzable function.

[0108] In an exemplary embodiment of the present disclosure, the matching result determining subunit includes a second result determining subunit for adjusting a scanning speed for the semiconductor to be tested if the imaginary-real correlation relationship does not match the complex semi-analytical function.

[0109] In an exemplary embodiment of the present disclosure, the scanning speed determining apparatus 600 includes a first speed adjusting unit for increasing a scanning duration of a voltage sweep for a semiconductor to be tested if the imaginary-real correlation relationship does not match the complex semi-analytical function.

[0110] In an exemplary embodiment of the present disclosure, the scanning speed determination device 600 includes a second speed adjustment unit, which is used to adjust the disturbance voltage applied to the semiconductor to be tested to obtain an updated disturbance voltage if the virtual-real correlation relationship does not match the complex semi-analyzable function; apply the updated disturbance voltage to the semiconductor to be tested in a constant potential state, and determine the target scanning speed of the semiconductor to be tested according to the updated disturbance voltage.

[0111] The specific details of the virtual modules of each of the above-mentioned scanning speed determination devices have been described in detail in the corresponding scanning speed determination methods, and thus will not be repeated here.

[0112] It should be noted that although several modules or units of the scanning speed determination device are mentioned in the detailed description above, such division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in a single module or unit. Conversely, the features and functions of a single module or unit described above can be further divided and embodied by multiple modules or units.

[0113] In addition, in an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

[0114] Those skilled in the art will appreciate that various aspects of the present invention may be implemented as systems, methods, or program products. Accordingly, various aspects of the present invention may be implemented as a complete hardware embodiment, a complete software embodiment (including firmware, microcode, etc.), or a combination of hardware and software embodiments, which may be collectively referred to herein as "circuits," "modules," or "systems."

[0115] Reference below Figure 7 7 to describe an electronic device 700 according to such an embodiment of the present disclosure. Figure 7 The electronic device 700 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0116] like Figure 7As shown, electronic device 700 is implemented as a general-purpose computing device. Components of electronic device 700 may include, but are not limited to, the aforementioned at least one processing unit 710, the aforementioned at least one storage unit 720, a bus 730 connecting various system components (including storage unit 720 and processing unit 710), and a display unit 740.

[0117] The storage unit stores program codes, which can be executed by the processing unit 710, so that the processing unit 710 performs the steps according to various exemplary embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.

[0118] The storage unit 720 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 721 and / or a cache memory unit 722 , and may further include a read-only memory unit (ROM) 723 .

[0119] The storage unit 720 may include a program / utility 724 having a set (at least one) of program modules 725, such program modules 725 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0120] Bus 730 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0121] The electronic device 700 can also communicate with one or more external devices 770 (e.g., a keyboard, a pointing device, a Bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 700, and / or any device that enables the electronic device 700 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication can occur via an input / output (I / O) interface 750. Furthermore, the electronic device 700 can also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via a network adapter 760. As shown, the network adapter 760 communicates with other modules of the electronic device 700 via a bus 730. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device 700, including but not limited to microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0122] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0123] In exemplary embodiments of the present disclosure, a computer-readable storage medium is also provided, storing a program product capable of implementing the aforementioned methods of this specification. In some possible embodiments, various aspects of the present invention may also be implemented in the form of a program product comprising program code. When the program product is executed on a terminal device, the program code is configured to cause the terminal device to perform the steps according to various exemplary embodiments of the present invention described in the "Exemplary Methods" section of this specification.

[0124] refer to Figure 8 , a program product 800 for implementing the above method according to an embodiment of the present invention is described. The program product 800 may be a portable compact disc read-only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0125] The program product may be implemented in any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0126] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0127] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0128] The program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and the like, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0129] Furthermore, the above-described figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention and are not intended to be limiting. It is readily understood that the processes illustrated in the above-described figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0130] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow from the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0131] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for determining a scanning speed, characterized in that: include: Obtaining a semiconductor to be tested, applying an initial voltage to the semiconductor to be tested, triggering the semiconductor to be tested to generate a potential step, and stepping to a constant potential state; The applying of the initial voltage is performed based on a specific scanning speed; Applying a disturbance voltage to the semiconductor to be tested in a constant potential state to obtain a charge state of the semiconductor to be tested in the constant potential state; In response to the charge state being in a charge activity equilibrium state, a scan speed in the charge activity equilibrium state is used as a target scan speed of the semiconductor to be tested.

2. The method according to claim 1, characterized in that The applying an initial voltage to the semiconductor to be tested to trigger the semiconductor to be tested to generate a potential step includes: Determining a scan start time point for performing a voltage scan on the semiconductor to be tested; A voltage scan is performed on the gate oxide layer of the semiconductor to be tested according to the scan start time point and the initial voltage, so as to trigger the semiconductor to be tested to generate a potential step.

3. The method according to claim 2, characterized in that The step of performing voltage scanning on the gate oxide layer of the semiconductor to be tested according to the scanning start time point and the initial voltage includes: determining an initial scanning speed for performing voltage scanning on the semiconductor to be tested; Based on the initial scanning speed and the initial voltage, a voltage scan is performed on the gate oxide layer starting from the scanning start time point.

4. The method according to claim 3, characterized in that The step of performing voltage scanning on the gate oxide layer starting from the scanning start time point includes: Determining a scan duration for performing a voltage scan on the gate oxide layer; the scan duration is a continuous time for scanning the gate oxide layer using the initial voltage; Starting from the scanning start time point, the gate oxide layer is continuously voltage scanned based on the scanning duration time to trigger the semiconductor to be tested to generate a potential step.

5. The method according to claim 4, characterized in that The determining of a scan duration for performing a voltage scan on the gate oxide layer comprises: determining a characteristic frequency of mobile ionic charges in the semiconductor to be tested; A sweep duration for performing a voltage sweep on the semiconductor to be tested is determined according to the characteristic frequency.

6. The method according to claim 1, characterized in that The step of applying a disturbance voltage to the semiconductor to be tested in a constant potential state to obtain a charge state of the semiconductor to be tested in the constant potential state includes: In response to detecting that the semiconductor to be tested is in a constant potential state, applying the disturbance voltage to the semiconductor to be tested; receiving state response information of the semiconductor to be tested after the disturbance voltage is applied; The charge state of the semiconductor to be tested in a constant potential state is determined according to the state response information.

7. The method according to claim 6, characterized in that Determining the charge state of the semiconductor to be tested in a constant potential state according to the state response information includes: determining a real part of impedance and an imaginary part of impedance of mobile ionic charges in the semiconductor to be tested based on the state response information; Determining a real-imaginary correlation relationship between the real part of the impedance and the imaginary part of the impedance; According to the virtual-real correlation relationship, the charge state of the semiconductor to be tested in a constant potential state is determined.

8. The method according to claim 7, characterized in that Determining the charge state of the semiconductor to be tested in a constant potential state according to the virtual-real correlation relationship includes: Get a preconfigured complex semianalyzable function; Determining a matching result between the virtual-real association relationship and the complex semi-analyzable function; The charge state is determined according to the matching result.

9. The method according to claim 8, characterized in that Determining the charge state according to the matching result includes: If the imaginary-real association relationship matches the complex semi-analyzable function, the charge state is determined to be the charge activity equilibrium state.

10. The method according to claim 8, characterized in that Determining the charge state according to the matching result includes: If the imaginary-real association relationship does not match the complex semi-analytical function, the scanning speed for the semiconductor to be tested is adjusted.

11. The method according to claim 10, characterized in that If the imaginary-real association relationship does not match the complex semi-analytical function, adjusting the scanning speed for the semiconductor to be tested includes: If the imaginary-real correlation relationship does not match the complex semi-analytical function, the scanning duration of the voltage sweep performed on the semiconductor to be tested is increased.

12. The method according to claim 10, characterized in that If the imaginary-real association relationship does not match the complex semi-analytical function, adjusting the scanning speed for the semiconductor to be tested includes: If the imaginary-real association relationship does not match the complex semi-analyzable function, adjusting the disturbance voltage applied to the semiconductor to be tested to obtain an updated disturbance voltage; An updated disturbance voltage is applied to the semiconductor to be tested in a constant potential state, and a target scanning speed of the semiconductor to be tested is determined according to the updated disturbance voltage.

13. A scanning speed determination device, characterized in that: include: A potential step trigger module is used to obtain a semiconductor to be tested, apply an initial voltage to the semiconductor to be tested, and trigger the semiconductor to be tested to generate a potential step, which steps to a constant potential state; The applying of the initial voltage is performed based on a specific scanning speed; A charge state determination module is used to apply a disturbance voltage to the semiconductor to be tested in a constant potential state to obtain the charge state of the semiconductor to be tested in the constant potential state; The target speed determining module is configured to, in response to the charge state being in a charge activity equilibrium state, use a scanning speed in the charge activity equilibrium state as a target scanning speed of the semiconductor to be tested.

14. An electronic device, characterized in that: include: processor; as well as A memory having computer-readable instructions stored thereon, wherein the computer-readable instructions are executed by the processor to implement the scanning speed determination method according to any one of claims 1 to 12. 15 . A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the scanning speed determination method according to claim 1 is implemented.

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