A bus fault detection circuit

Abstract

The present invention provides a bus fault detection circuit, comprising: a level conversion module, a decision comparison module, and a count lock module; the level conversion module connects bus input signals CANH and CANL and outputs the differential voltage between the bus and the power supply to the decision comparison module; the decision comparison module is used to compare the differential voltage with the component of the power supply voltage. If the bus voltage is within the fault decision interval, it outputs a high level to the count lock module to issue a fault alarm; the leading edge blanking module is connected to the input end of the TXD input signal and is used to control the TXD input signal to output a control signal TXDn_deglitch to the count lock module after a delay time when the TXD input signal undergoes a falling edge transition; the count lock module identifies whether a bus fault has occurred and outputs a bus fault identifier Fault if it is determined that a fault has actually occurred. The present invention can monitor the bus status in real time and can quickly and accurately report the fault when the bus is short-circuited to the power supply or ground.

Description

Technical Field

[0001] The present invention relates to the technical field of communication bus interface networks, and in particular to a bus fault detection circuit. Background Art

[0002] In industrial control and in-vehicle networks, differential bus pairs are often used to transmit signals. These buses, such as the CAN bus and RS485 bus, offer high reliability and versatility. A single bus often connects multiple nodes, each of which can independently control the bus state to send and receive data. If a node fails, it could short-circuit the bus to power or ground. This necessitates prompt system reporting and troubleshooting.

[0003] In the existing CAN bus short-circuit online monitoring method, a resistor is connected in series on the bus to detect the fault. Due to the voltage drop across the detection resistor, heat and efficiency loss will be caused, thereby affecting bus communication. Summary of the Invention

[0004] In view of this, an embodiment of the present application provides a bus fault detection circuit that monitors the status of the bus in real time without affecting bus communication, and can quickly and accurately report the fault when the bus is short-circuited to the power supply or ground.

[0005] The embodiment of the present application provides the following technical solution: a bus fault detection circuit, comprising:

[0006] A level conversion module, a judgment and comparison module, and a counting and locking module that are sequentially connected in communication;

[0007] The input end of the level conversion module is connected to the bus input signals CANH and CANL, and is used to convert the bus voltage level and output the differential voltage between the bus and the power supply to the decision comparison module; the decision comparison module is used to compare the differential voltage with the component of the power supply voltage, and if the bus voltage is in the fault decision interval, output a high level to the count lock module to issue a fault alarm;

[0008] It also includes a leading edge blanking module, wherein the input end of the leading edge blanking module is connected to the TXD input signal, and the TXD input signal is used to control the switching of the dominant and recessive states of the buses CANH and CANL. The leading edge blanking module is used to control the TXD input signal to output a control signal TXDn_deglitch to the counting lock module after a delay time when the TXD input signal has a falling edge jump;

[0009] The counting and locking module identifies whether a bus fault occurs according to the control signal TXDn_deglitch and the high-level fault alarm signal output by the decision and comparison module, and outputs a bus fault identifier Fault if it is determined that a fault actually occurs.

[0010] According to one embodiment, the process of the counting and locking module identifying whether a bus failure occurs includes:

[0011] The counting and locking module counts the effective fault detection time of the input high level. If the effective fault detection time lasts for at least two cycles, it is determined that a fault has actually occurred, and the signal is locked and then a bus fault identifier Fault is output.

[0012] According to an embodiment, after the bus fault is resolved, the counting and locking module clears the counter and the fault identifier Fault.

[0013] According to one embodiment, the level conversion module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a buffer, and an amplifier;

[0014] The first end of the first resistor is connected to the bus input signals CANH and CANL, and the second end is connected to the first end of the second resistor, and the second end of the second resistor is connected to the common mode point Vcc / 2; the intermediate node between the first and second resistors is connected to the input end of the buffer, and the output end of the buffer is connected to the first end of the third resistor, which is used to output the voltage of the intermediate node at the same level to the third resistor; the second end of the third resistor is connected to the first input end of the amplifier, and the second input end of the amplifier is connected to the reference level Vcc / 2. The output end of the amplifier is fed back to the first input end of the amplifier through the fourth resistor, and the amplifier outputs the differential voltage between the bus and the power supply to the decision comparison module.

[0015] According to an embodiment, the relationship among the resistance value R1 of the first resistor, the resistance value R2 of the second resistor, the resistance value R3 of the third resistor, and the resistance value R4 of the fourth resistor is: R2*R4 / R3*(R1+R2)=1.

[0016] According to one embodiment, the judgment and comparison module includes a comparator, a first input end of the comparator is connected to the output end of the amplifier, and a second input end is connected to the reference level Vcc / N, and is used to compare the differential voltage Vcc-CANH between the bus and the power supply with the component Vcc / N of the power supply voltage. When the bus voltage CANH enters the fault judgment interval between Vcc and (Vcc-Vcc / N), the comparator outputs a high level to issue a fault alarm.

[0017] The beneficial effects achieved by the embodiments of this specification include at least the following: The present invention provides a bus fault detection circuit that accurately monitors bus faults in real time and issues a timely fault report without affecting normal bus communication. The present invention also proposes a fault determination interval that changes with power supply Vcc, reducing the rate of false fault determinations at different power supply voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 It is a traditional transceiver structure and fault detection circuit;

[0020] Figure 2 The bus fault detection architecture proposed by the present invention;

[0021] Figure 3 The normal operation interval and fault detection interval of the bus in the embodiment of the present invention;

[0022] Figure 4 The level sampling circuit and the decision comparison circuit in the embodiment of the present invention;

[0023] Figure 5 1 is a waveform diagram of nodes at each level in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0025] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments, and the technical solutions of the present invention will be clearly and completely described. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0026] like Figure 1 As shown, Figure 1This is a traditional transceiver structure and fault detection circuit. CAN transceiver 10 drives bus lines CANH and CANL for communication, with resistor 15 serving as the bus's terminal load. A traditional bus fault detection method involves inserting a detection resistor 13 and another detection resistor 14 between the CAN transceiver 10 and the terminal load resistor 15. When a short circuit occurs on bus lines CANH and CANL, the current flowing through detection resistors 13 and 14 differs from the normal state. A first comparator 11 and a second comparator 12 connected across the detection resistors detect the fault and issue a fault alarm. This fault detection method requires the insertion of detection resistors in series on the bus, which can cause a voltage drop and power loss.

[0027] like Figure 2 As shown, the present invention provides a bus fault detection circuit, comprising:

[0028] A level conversion module 20, a decision comparison module 21 and a count lock module 22 which are sequentially connected in communication;

[0029] The input end of the level conversion module 20 is connected to the bus input signals CANH and CANL, and is used to convert the bus voltage level and output the differential voltage between the bus and the power supply to the decision comparison module 21; the decision comparison module 21 is used to compare the differential voltage with the component of the power supply voltage. If the bus voltage is in the fault decision range, it outputs a high level to the count lock module 22 to issue a fault alarm;

[0030] The system further includes a leading edge blanking module 23, wherein the input end of the leading edge blanking module 23 is connected to the TXD input signal, and the TXD input signal is used to control the switching of the dominant and recessive states of the buses CANH and CANL. The leading edge blanking module 23 is used to control the TXD input signal to output a control signal TXDn_deglitch to the counting lock module 22 after a delay time when the TXD input signal has a falling edge jump;

[0031] The counting and locking module 22 identifies whether a bus fault occurs based on the control signal TXDn_deglitch and the high-level fault alarm signal output by the decision and comparison module 21. Specifically, the counting and locking module 22 counts the effective fault detection time of the input high level. If the effective fault detection time lasts for at least two cycles, it is determined that a fault has actually occurred and a bus fault identifier Fault is output.

[0032] The present invention converts the bus voltage level, displays the differential voltage between the bus voltage and the power supply, and compares the differential voltage with a component of the power supply voltage. When the bus voltage is in the fault range, the comparator outputs a high level to alarm.

[0033] When the transceiver transitions from dominant to recessive, the bus state changes. This bus level change can cause glitches in the fault detection comparator output. Therefore, deglitching is necessary during the transceiver state transition. If a fault is still reported after deglitching and persists for several cycles, the fault is considered to have occurred and is latched, generating an alarm. Once the fault is resolved, the counter and alarm are reset, and the system re-monitors the bus state.

[0034] When the embodiment of the present invention is implemented, Figure 2 As shown, the bus input signals CANH and CANL are connected to the level conversion module 20. After level conversion, the differential voltage Vs between the bus and the power supply is output to the next stage. The decision comparison module 21 compares the converted differential voltage with the power supply voltage component. If the bus is in a fault state, an alarm is issued to the next stage. Because the bus voltage fluctuates when the bus state switches, it will cause disturbances in the fault detection output, requiring a delay time to remove burrs. The TXD signal that controls the state switching is connected to the leading edge blanking module 23. When TXD has a falling edge transition, the control signal TXDn_deglitch is sent to the next stage after a delay time. The count lock module 22 determines whether a bus fault has occurred based on the output Vout of the decision comparison module 21 and the output TXDn_deglitch of the leading edge blanking module 23. If a fault is determined, an alarm Fault is issued. After the bus fault is resolved, the counter and fault identifier Fault are cleared.

[0035] like Figure 3 As shown, Figure 3 Figure 2 shows the normal operating range and fault detection range of the bus. In the dominant state, the normal operating ranges of the bus lines CANH and CANL are shown as CANH 31 and CANL 32, respectively. If a bus fault occurs, such as a short circuit between CANL and ground via a small resistor or a short circuit between CANH and VCC via a small resistor, the bus will fall within the fault ranges CANH short 30 and CANL short 33. At this point, the fault detection circuit will identify these faults and issue an alarm. No alarm will be issued if the bus is within the normal operating range.

[0036] In the embodiment of the present invention, Figure 4 As shown, the level conversion module 20 includes a first resistor 40, a second resistor 41, a third resistor 43, a fourth resistor 44, a buffer 42 and an amplifier 45;

[0037] The first end of the first resistor 40 is connected to the bus input signals CANH and CANL, and the second end is connected to the first end of the second resistor 41, and the second end of the second resistor 41 is connected to the common mode point Vcc / 2; the intermediate node between the first resistor 40 and the second resistor 41 is connected to the input end of the buffer 42, and the output end of the buffer 42 is connected to the first end of the third resistor 43, which is used to output the voltage of the intermediate node at the same level to the third resistor 43; the second end of the third resistor 43 is connected to the first input end of the amplifier 45, and the second input end of the amplifier 45 is connected to the reference level Vcc / 2. The output end of the amplifier 45 is fed back to the first input end of the amplifier 45 through the fourth resistor 44, and the amplifier 45 outputs the differential voltage between the bus and the power supply to the decision comparison module 21.

[0038] The judgment and comparison module 21 includes a comparator 46, a first input end of which is connected to the output end of the amplifier 45, and a second input end of which is connected to the reference level Vcc / N. The comparator 46 is used to compare the differential voltage Vcc-CANH between the bus and the power supply with the component Vcc / N of the power supply voltage. When the bus voltage CANH enters the fault judgment interval between Vcc and (Vcc-Vcc / N), the comparator 46 outputs a high level to issue a fault alarm.

[0039] Specifically, bus CANH / L is connected to the common mode point Vcc / 2 through a first voltage divider resistor 40 and a second voltage divider resistor 41. In this way, the voltage level of the intermediate node between the first voltage divider resistor 40 and the second voltage divider resistor 41 is CANH*R2 / (R1+R2)+Vcc*R1 / 2*(R1+R2). The input end of buffer 42 is connected to the intermediate output node of the voltage divider resistor, which is used to output the voltage level of the intermediate node to the next level without drawing additional current from the voltage divider resistor. A third resistor 43 is connected to the output of buffer 42 and connected to one input end of amplifier 45. The other input end of amplifier 45 is connected to the reference voltage level Vcc / 2. The output end of amplifier 45 is fed back to its input end through a fourth resistor 44. In this way, the output level of amplifier 45 is Vcc / 2-(CANH-Vcc / 2)*R2*R4 / R3*(R1+R2). If the values of fourth resistor 44R4 and third resistor 43R3 are appropriately chosen so that R2*R4 / R3(R1+R2)=1, then the output level Vs of amplifier 45 is Vcc-CANH, and the circuit characterizes the difference between CANH and Vcc. One input of comparator 46 is connected to the output of preamplifier 45, and the other input is connected to the reference level Vcc / N. Thus, when the levels of the two inputs of comparator 46 are close, that is, when CANH enters the fault range between Vcc and (Vcc-Vcc / N), comparator 46 will output an alarm. The advantage of this architecture is that the fault judgment range (Vcc to (Vcc-Vcc / N)) changes with the power supply Vcc, reducing the fault misjudgment rate when the power supply voltage is different.

[0040] like Figure 5 As shown, Figure 5 The waveform diagram of each node of each level of the embodiment of the present invention is shown in FIG. Waveform 50 is the TXD input signal, which is used to control the dominant and recessive states of the CANH bus 51 and the CANL bus 52. When a bus failure occurs, such as a sudden short circuit of CANL to GND, Figure 4 The output of the comparator 46 will send out an alarm signal, as shown in the waveform Vout_L 53. When the TXD input state switches, the bus state during the short circuit is also different, and the output of the comparator 46 may have glitches. In order to prevent the subsequent stage from making a misjudgment, it is necessary to delay the judgment for a period of time after the TXD jump. Figure 2 The output signal TXDn_deglitch of the leading edge blanking module 23 is used for judgment, that is, the high level of the waveform TXDn_deglitch 54 is the effective fault detection time. Then the counter counts two cycles and outputs the fault identifier Fault after confirming that it is a valid fault, as shown by Fault 55 in the figure.

[0041] The bus fault detection circuit of the present invention can accurately monitor the occurrence of bus faults in real time and issue a fault report in a timely manner without affecting normal bus communication.

[0042] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A bus fault detection circuit, characterized in that: include: A level conversion module, a judgment and comparison module, and a counting and locking module that are sequentially connected in communication; The input end of the level conversion module is connected to the bus input signals CANH and CANL, and is used to perform level conversion on the bus voltage and output the differential voltage between the bus and the power supply to the decision comparison module; The level conversion module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a buffer, and an amplifier; a first end of the first resistor is connected to bus input signals CANH and CANL, a second end is connected to the first end of the second resistor, and a second end of the second resistor is connected to a common mode point Vcc / 2; an intermediate node between the first and second resistors is connected to the input end of the buffer, and an output end of the buffer is connected to the first end of the third resistor, for outputting a voltage of the intermediate node at the same level to the third resistor; a second end of the third resistor is connected to the first input end of the amplifier, a second input end of the amplifier is connected to a reference level Vcc / 2, and an output end of the amplifier is fed back to the first input end of the amplifier through the fourth resistor, and the amplifier outputs the differential voltage between the bus and the power supply to the decision comparison module; wherein the relationship between the resistance value R1 of the first resistor, the resistance value R2 of the second resistor, the resistance value R3 of the third resistor, and the resistance value R4 of the fourth resistor is: R2*R4 / R3*(R1+R2)=1; The judgment and comparison module is used to compare the differential voltage with the component of the power supply voltage, and if the bus voltage is in the fault judgment interval, output a high level to the counting and locking module to issue a fault alarm; The judgment and comparison module includes a comparator, a first input terminal of the comparator is connected to the output terminal of the amplifier, and a second input terminal is connected to the reference voltage Vcc / N, and is used to compare the differential voltage Vcc-CANH between the bus and the power supply with the component Vcc / N of the power supply voltage. When the bus voltage CANH enters the fault judgment interval between Vcc and (Vcc-Vcc / N), the comparator outputs a high level to issue a fault alarm; It also includes a leading edge blanking module, wherein the input end of the leading edge blanking module is connected to the TXD input signal, and the TXD input signal is used to control the switching of the dominant and recessive states of the buses CANH and CANL. The leading edge blanking module is used to control the TXD input signal to output a control signal TXDn_deglitch to the counting lock module after a delay time when the TXD input signal has a falling edge jump; The counting and locking module identifies whether a bus fault occurs according to the control signal TXDn_deglitch and the high-level fault alarm signal output by the decision and comparison module, and outputs a bus fault identifier Fault if it is determined that a fault actually occurs.

2. The bus fault detection circuit according to claim 1, wherein: The process of the counting and locking module identifying whether a bus failure occurs includes: The counting and locking module counts the effective fault detection time of the input high level. If the effective fault detection time lasts for at least two cycles, it is determined that a fault has actually occurred, and the signal is locked and then a bus fault identifier Fault is output.

3. The bus fault detection circuit according to claim 1, wherein: After the bus fault is cleared, the counting and locking module clears the counter and the fault identifier Fault.

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