A synchronous shunt regulation device for a spaceborne solar cell array

Abstract

This invention provides a synchronous current shunt adjustment device for a spaceborne solar array, comprising a current shunt and drive circuit, a first voltage divider circuit, an isolation and drive circuit, a second voltage divider circuit, a push-pull circuit, a subtractor, a first comparator, a third comparator, a fourth comparator, an OR gate, and a diode. The current shunt and drive circuit is connected to the SAS output terminal of the solar array, the first voltage divider circuit, the isolation and drive circuit, and the push-pull circuit, respectively. The first voltage divider circuit is connected to the SAS output terminal of the solar array, the isolation and drive circuit, the inverting input terminal of the third comparator, and the ground terminal, respectively. The isolation and drive circuit is also connected to the SAS output terminal of the solar array, the second voltage divider circuit, the bus voltage VBUS, the subtractor, the ground terminal, and pin 3 of the OR gate, respectively. The beneficial effects of this invention are: the synchronous current shunt adjustment device for a spaceborne solar array reduces the difficulty of thermal design, improves energy utilization, and enables rapid assembly and reduction of the solar array area.

Description

Technical Field

[0001] This invention relates to the field of satellite technology, and in particular to a synchronous shunt adjustment device for a spaceborne solar cell array. Background Technology

[0002] The shunt regulation circuit of the solar cell array is an important component of the satellite power system. Its main function is to ensure that the solar cell array can output a stable voltage when the temperature, light intensity, incident angle, and load change, so that the bus voltage can be maintained within a certain range in both the illuminator and the shadow area.

[0003] Currently, the commonly used voltage regulation method is switching shunt regulation technology, which generally includes S... 3 R and S 4 In an R-topology, to prevent the battery pack from short-circuiting to ground through the shunt tube when the solar array is in shunt mode, leading to high-current discharge and potentially burning out the components, a common practice is to use a diode to isolate the solar array shunt tube from the primary power bus. When the shunt tube is in the off state, the solar array supplies power to the primary power bus through the diode; when the shunt tube is in the on state, the solar array is short-circuited through the shunt tube, and the diode is in the reverse cutoff state, preventing the battery pack from short-circuiting.

[0004] When the solar array is in a non-shunt state, all power is supplied to the primary power bus through the diodes. Due to the large forward voltage drop of the diodes, the heat dissipation is large. In order to ensure the reliability of the device and the derating design, the diodes need to be mounted on the housing. The process is relatively complicated, which is not conducive to rapid assembly and has a high cost. Improper handling may cause the diodes to burn out, affecting the power supply of the entire satellite and directly affecting the success or failure of the satellite mission.

[0005] Meanwhile, the diodes increase power consumption, and the solar array needs to provide more energy output to meet the satellite's power requirements. This leads to a larger solar array area, longer design cycle, and higher cost.

[0006] As can be seen, in traditional solar cell array-battery bank systems, the solar cell array is connected to the primary power bus via an isolation diode. Due to the large voltage drop and heat dissipation of the isolation diode, the thermal design becomes more difficult, the energy utilization rate is low, and it is not conducive to the rapid assembly of the power control system and the reduction of the solar cell array area. Summary of the Invention

[0007] This invention provides a synchronous current shunt adjustment device for a spaceborne solar cell array, comprising a current shunt and drive circuit, a first voltage divider circuit, an isolation and drive circuit, a second voltage divider circuit, a push-pull circuit, a subtractor, a first comparator, a third comparator, a fourth comparator, an OR gate, and a diode. The current shunt and drive circuit is connected to the SAS output terminal of the solar cell array, the first voltage divider circuit, the isolation and drive circuit, and the push-pull circuit, respectively.

[0008] The first voltage divider circuit is also connected to the SAS output terminal of the solar cell array, the isolation and drive circuit, the inverting input terminal of the third comparator, and the ground terminal.

[0009] The isolation and drive circuit is also connected to the SAS output terminal of the solar cell array, the second voltage divider circuit, the bus voltage VBUS, the subtractor, the ground terminal, and the OR gate pin 3, respectively.

[0010] The second voltage divider circuit is also connected to the bus voltage VBUS, the subtractor, the ground terminal, and the non-inverting input terminal of the fourth comparator.

[0011] The push-pull circuit is also connected to the VCC terminal, the output terminal of the first comparator, the anode of the diode, and the ground terminal, respectively.

[0012] The subtractor is also connected to the inverting input of the first comparator, the second voltage divider circuit, the bus voltage VBUS, and the ground terminal.

[0013] The non-inverting input of the first comparator is connected to the second reference voltage VREF2.

[0014] The non-inverting input of the third comparator is connected to the third reference voltage VREF3, and the output of the third comparator is connected to pin 2 of the OR gate.

[0015] The inverting input of the fourth comparator is connected to the first reference voltage VREF1, and the output of the fourth comparator is connected to pin 1 of the OR gate and the cathode of the diode.

[0016] As a further improvement of the present invention, the current shunt and drive circuit includes a current shunt tube, a fifth resistor, and a sixth resistor, wherein the gate (G) of the current shunt tube is connected to one end of the fifth resistor, the drain (D) of the current shunt tube is connected to the SAS output terminal of the solar cell array, the first voltage divider circuit, and the isolation and drive circuit, and the source (S) of the current shunt tube is connected to one end of the sixth resistor and the ground terminal.

[0017] The other end of the fifth resistor is connected to the push-pull circuit and the other end of the sixth resistor, respectively;

[0018] One end of the sixth resistor is also connected to the ground terminal.

[0019] As a further improvement of the present invention, the first voltage divider circuit includes a third resistor and a fourth resistor, wherein one end of the third resistor is connected to the SAS output terminal of the solar cell array, the drain terminal of the shunt tube, and the isolation and driving circuit, respectively, and the other end of the third resistor is connected to one end of the fourth resistor and the inverting input terminal of the third comparator.

[0020] One end of the fourth resistor is also connected to the inverting input of the third comparator, and the other end of the fourth resistor is grounded.

[0021] As a further improvement of the present invention, the isolation and driving circuit includes an isolation PMOS transistor and a third transistor. The onboard solar cell array synchronous shunt adjustment device also includes a first resistor, a first capacitor, a twelfth resistor, a second resistor, a second capacitor, and a fifteenth resistor. The drain of the isolation PMOS transistor is connected to the SAS output terminal of the solar cell array, the drain of the shunt transistor, and one end of the third resistor. The gate of the isolation PMOS transistor is connected to one end of the fifteenth resistor, the subtractor, one end of the second resistor, and one end of the second capacitor. The source of the isolation PMOS transistor is connected to the other end of the second resistor, the other end of the second capacitor, the bus voltage VBUS, the second voltage divider circuit, and the subtractor.

[0022] The emitter (e) of the third transistor is connected to the other end of the fifteenth resistor. The base (b) of the third transistor is connected to one end of the first resistor, one end of the first capacitor, and one end of the twelfth resistor. The collector (c) of the third transistor is connected to the other end of the first resistor, the other end of the first capacitor, and the ground terminal.

[0023] One end of the first resistor is also connected to one end of the first capacitor and one end of the twelfth resistor, and the other end of the first resistor is also connected to the other end of the first capacitor and the ground terminal.

[0024] One end of the first capacitor is also connected to one end of the twelfth resistor, and the first capacitor is also connected to the ground terminal.

[0025] The other end of the twelfth resistor is connected to pin 3 of the OR gate.

[0026] One end of the second resistor is also connected to one end of the second capacitor, the bus voltage VBUS, the second voltage divider circuit, and the subtractor, respectively. The other end of the second resistor is also connected to the other end of the second capacitor, one end of the fifteenth resistor, and the subtractor, respectively.

[0027] One end of the second capacitor is also connected to the bus voltage VBUS, the second voltage divider circuit, and the subtractor, respectively, and the other end of the second capacitor is also connected to one end of the fifteenth resistor and the subtractor, respectively.

[0028] One end of the fifteenth resistor is also connected to the subtractor.

[0029] As a further improvement of the present invention, the second voltage divider circuit includes a thirteenth resistor and a fourteenth resistor, wherein one end of the thirteenth resistor is connected to the source of the isolation PMOS transistor, one end of the second resistor, one end of the second capacitor, the bus voltage VBUS, and the subtractor, respectively, and the other end of the thirteenth resistor is connected to one end of the fourteenth resistor and the non-inverting input of the fourth comparator.

[0030] One end of the fourteenth resistor is also connected to the non-inverting input of the fourth comparator, and the other end of the fourteenth resistor is grounded.

[0031] As a further improvement of the present invention, the on-board solar cell array synchronous shunt adjustment device further includes a seventh resistor, one end of which is connected to the push-pull circuit and the anode of the diode, and the other end of which is connected to the output of the first comparator.

[0032] As a further improvement of the present invention, the push-pull circuit includes a first transistor and a second transistor, wherein the collector (c) of the first transistor is connected to VCC, the emitter (e) of the first transistor is connected to the other end of the fifth resistor, the other end of the sixth resistor, and the emitter of the second transistor, respectively, and the base (b) of the first transistor is connected to the base of the second transistor, one end of the seventh resistor, and the anode of the diode, respectively.

[0033] The emitter of the second transistor is also connected to the other end of the fifth resistor and the other end of the sixth resistor. The base of the second transistor is also connected to one end of the seventh resistor and the anode of the diode. The collector of the second transistor is grounded.

[0034] As a further improvement of the present invention, the subtractor includes an operational amplifier, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor, wherein the output terminal of the operational amplifier is connected to one end of the eighth resistor and the inverting input terminal of the first comparator, the inverting input terminal of the operational amplifier is connected to the other end of the eighth resistor and one end of the ninth resistor, and the non-inverting input terminal of the operational amplifier is connected to one end of the tenth resistor and one end of the eleventh resistor.

[0035] One end of the eighth resistor is also connected to the inverting input of the first comparator, and the other end of the eighth resistor is also connected to one end of the ninth resistor.

[0036] The other end of the ninth resistor is connected to the gate of the isolation PMOS transistor, the other end of the second resistor, and the other end of the second capacitor.

[0037] One end of the tenth resistor is also connected to one end of the eleventh resistor, and the other end of the tenth resistor is connected to the bus voltage VBUS, one end of the thirteenth resistor, one end of the second capacitor, one end of the second resistor, and the source of the isolation PMOS transistor.

[0038] The other end of the eleventh resistor is grounded.

[0039] The beneficial effects of the present invention are: the synchronous current shunt adjustment device for spaceborne solar cell arrays provided by the present invention is stable and highly reliable, reduces the difficulty of thermal design, improves energy utilization, and can achieve the purpose of rapid assembly and reduction of solar cell array area. Attached Figure Description

[0040] Figure 1 This is a block diagram of the principle of the synchronous current shunt adjustment device for the spaceborne solar cell array. Detailed Implementation

[0041] like Figure 1 As shown, the present invention discloses a synchronous shunt adjustment device for a spaceborne solar cell array, including a shunt and drive circuit 1, a first voltage divider circuit 2, an isolation and drive circuit 3, a second voltage divider circuit 4, a push-pull circuit 5, a subtractor 6, a first comparator U1, a third comparator U3, a fourth comparator U4, an OR gate U5, and a diode D1. The shunt and drive circuit 1 is connected to the SAS output terminal of the solar cell array, the first voltage divider circuit 2, the isolation and drive circuit 3, and the push-pull circuit 5, respectively.

[0042] The first voltage divider circuit 2 is also connected to the output terminal of the solar cell array SAS, the isolation and drive circuit 3, the inverting input terminal of the third comparator U3, and the ground terminal.

[0043] The isolation and drive circuit 3 is also connected to the output terminal of the solar cell array SAS, the second voltage divider circuit, the bus voltage VBUS, the subtractor 6, the ground terminal, and the 3rd pin of the OR gate U5.

[0044] The second voltage divider circuit 4 is also connected to the bus voltage VBUS, the subtractor 6, the ground terminal, and the non-inverting input terminal of the fourth comparator U4.

[0045] The push-pull circuit 5 is also connected to the VCC terminal, the output terminal of the first comparator U1, the anode of the diode D1, and the ground terminal, respectively.

[0046] The subtractor 6 is also connected to the inverting input of the first comparator U1, the second voltage divider circuit 4, the bus voltage VBUS, and the ground terminal.

[0047] The non-inverting input of the first comparator U1 is connected to the second reference voltage VREF2.

[0048] The non-inverting input of the third comparator U3 is connected to the third reference voltage VREF3, and the output of the third comparator U3 is connected to pin 2 of the OR gate U5.

[0049] The inverting input of the fourth comparator U4 is connected to the first reference voltage VREF1, and the output of the fourth comparator U4 is connected to pin 1 of the OR gate U5 and the cathode of the diode D1.

[0050] The current shunt and drive circuit 1 includes a shunt tube V1, a fifth resistor R5, and a sixth resistor R6. The gate (G) of the shunt tube V1 is connected to one end of the fifth resistor R5. The drain (D) of the shunt tube V1 is connected to the output terminal of the solar cell array SAS, the first voltage divider circuit 2, and the isolation and drive circuit 3. The sink (S) of the shunt tube V1 is connected to one end of the sixth resistor R6 and the ground terminal.

[0051] The other end of the fifth resistor R5 is connected to the push-pull circuit 5 and the other end of the sixth resistor R6, respectively.

[0052] One end of the sixth resistor R6 is also connected to the ground terminal.

[0053] The first voltage divider circuit 2 includes a third resistor R3 and a fourth resistor R4. One end of the third resistor R3 is connected to the output terminal of the solar cell array SAS, the drain of the shunt tube V1, and the isolation and drive circuit 3, respectively. The other end of the third resistor R3 is connected to one end of the fourth resistor R4 and the inverting input terminal of the third comparator U3, respectively.

[0054] One end of the fourth resistor R4 is also connected to the inverting input of the third comparator U3, and the other end of the fourth resistor R4 is grounded.

[0055] The isolation and drive circuit 3 includes an isolation PMOS transistor V2 and a third transistor Q3. The onboard solar cell array synchronous shunt adjustment device also includes a first resistor R1, a first capacitor C1, a twelfth resistor R12, a second resistor R2, a second capacitor C2, and a fifteenth resistor R15. The drain of the isolation PMOS transistor V2 is connected to the output terminal of the solar cell array SAS, the drain of the shunt transistor V1, and one end of the third resistor R3. The gate of the isolation PMOS transistor V2 is connected to one end of the fifteenth resistor R15, the subtractor 6, one end of the second resistor R2, and one end of the second capacitor C2. The source of the isolation PMOS transistor V2 is connected to the other end of the second resistor R2, the other end of the second capacitor C2, the bus voltage VBUS, the second voltage divider circuit 4, and the subtractor 6.

[0056] The emitter of the third transistor Q3 is connected to the other end of the fifteenth resistor R15. The base of the third transistor Q3 is connected to one end of the first resistor R1, one end of the first capacitor C1, and one end of the twelfth resistor R12. The collector of the third transistor Q3 is connected to the other end of the first resistor R1, the other end of the first capacitor C1, and the ground terminal.

[0057] One end of the first resistor R1 is also connected to one end of the first capacitor C1 and one end of the twelfth resistor R12, and the other end of the first resistor R1 is also connected to the other end of the first capacitor C1 and the ground terminal.

[0058] One end of the first capacitor C1 is also connected to one end of the twelfth resistor R12, and the first capacitor C1 is also connected to the ground terminal.

[0059] The other end of the twelfth resistor R12 is connected to pin 3 of the OR gate U5.

[0060] One end of the second resistor R2 is also connected to one end of the second capacitor C2, the bus voltage VBUS, the second voltage divider circuit 4, and the subtractor 6, respectively. The other end of the second resistor R2 is also connected to the other end of the second capacitor C2, one end of the fifteenth resistor R15, and the subtractor 6, respectively.

[0061] One end of the second capacitor C2 is also connected to the bus voltage VBUS, the second voltage divider circuit 4, and the subtractor 6, respectively. The other end of the second capacitor C2 is also connected to one end of the fifteenth resistor R15 and the subtractor 6, respectively.

[0062] One end of the fifteenth resistor R15 is also connected to the subtractor 6.

[0063] The second voltage divider circuit 4 includes a thirteenth resistor R13 and a fourteenth resistor R14. One end of the thirteenth resistor R13 is connected to the source of the isolation PMOS transistor V2, one end of the second resistor R2, one end of the second capacitor C2, the bus voltage VBUS, and the subtractor 6. The other end of the thirteenth resistor R13 is connected to one end of the fourteenth resistor R14 and the non-inverting input of the fourth comparator U4.

[0064] One end of the fourteenth resistor R14 is also connected to the non-inverting input of the fourth comparator U4, and the other end of the fourteenth resistor R14 is grounded.

[0065] The onboard solar array synchronous shunt adjustment device also includes a seventh resistor R7. One end of the seventh resistor R7 is connected to the push-pull circuit 5 and the anode of the diode D1, respectively, and the other end of the seventh resistor R7 is connected to the output terminal of the first comparator U1.

[0066] The push-pull circuit 5 includes a first transistor Q1 and a second transistor Q2. The collector (c) of the first transistor Q1 is connected to VCC. The emitter (e) of the first transistor Q1 is connected to the other end of the fifth resistor R5, the other end of the sixth resistor R6, and the emitter (e) of the second transistor Q2. The base (b) of the first transistor Q1 is connected to the base (b) of the second transistor Q2, one end of the seventh resistor R7, and the anode of the diode D1.

[0067] The emitter of the second transistor Q2 is also connected to the other end of the fifth resistor R5 and the other end of the sixth resistor R6. The base of the second transistor Q2 is also connected to one end of the seventh resistor R7 and the anode of the diode D1. The collector of the second transistor Q2 is grounded.

[0068] The subtractor 6 includes an operational amplifier U2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11. The output terminal of the operational amplifier U2 is connected to one end of the eighth resistor R8 and the inverting input terminal of the first comparator U1. The inverting input terminal of the operational amplifier U2 is connected to the other end of the eighth resistor R8 and one end of the ninth resistor R9. The non-inverting input terminal of the operational amplifier U2 is connected to one end of the tenth resistor R10 and one end of the eleventh resistor R11.

[0069] One end of the eighth resistor R8 is also connected to the inverting input of the first comparator U1, and the other end of the eighth resistor R8 is also connected to one end of the ninth resistor R9.

[0070] The other end of the ninth resistor R9 is connected to the gate of the isolation PMOS transistor V2, the other end of the second resistor R2, and the other end of the second capacitor C2.

[0071] One end of the tenth resistor R10 is also connected to one end of the eleventh resistor R11, and the other end of the tenth resistor R10 is connected to the bus voltage VBUS, one end of the thirteenth resistor R13, one end of the second capacitor C2, one end of the second resistor R2, and the source of the isolation PMOS transistor V2.

[0072] The other end of the eleventh resistor R11 is grounded.

[0073] Working principle of the invention:

[0074] The spaceborne solar array synchronous shunt adjustment device disclosed in this invention includes a shunt and drive circuit 1, an isolation and drive circuit 3, and a synchronization signal generation circuit. SAS is the output voltage of a certain subarray of the solar array, VBUS is the bus voltage, VREF1 is the first reference voltage, VREF2 is the second reference voltage, and VREF3 is the third reference voltage. The output terminal of the solar array SAS is connected to ground through a shunt transistor V1 and to the primary power bus through an isolation PMOS transistor V2.

[0075] When the satellite is powered on, the isolation PMOS transistor V2 is initially turned on, and the shunt transistor V1 is initially turned off. The output voltage of the solar array is divided by the third resistor R3 and the fourth resistor R4 and compared with the third reference voltage VREF3. When the divided voltage is higher than the third reference voltage VREF3, the output of the third comparator U3 is low. The bus voltage VBUS is divided by the thirteenth resistor R13 and the fourteenth resistor R14 and compared with the first reference voltage VREF1. When the divided voltage is higher than the first reference voltage VREF1, the output of the fourth comparator U4 is high.

[0076] The outputs of the third comparator U3 and the fourth comparator U4 are connected to the two inputs of the OR gate U5, respectively. When the output of the fourth comparator U4 is high, the output of the OR gate U5 is also high, causing the third transistor Q3 to turn off. The gate voltage of the isolated PMOS transistor V2 gradually increases. The operational amplifier U2, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11 form a subtractor to subtract the voltage of the bus voltage VBUS from the gate voltage of the isolated PMOS transistor V2. The output voltage of the operational amplifier U2 is compared with the second reference voltage VREF2. When the voltage difference between the bus voltage VBUS and the gate voltage of the isolated PMOS transistor V2 is less than the second reference voltage VREF2, the first comparator U1 outputs a high level, driving the first transistor Q1 in the push-pull circuit 5 to turn on and the second transistor Q2 to turn off, thereby turning on the shunt transistor V1. The output current of the solar cell array SAS is short-circuited through the shunt transistor V1, stopping the power supply to the bus VBUS. At this point, the voltage across the solar cell array SAS, divided by the third resistor R3 and the fourth resistor R4, is less than the third reference voltage VREF3. The third comparator U3 outputs a high level, the OR gate U5 maintains a high output, and the isolation PMOS transistor V2 is off. This completes the shunt control of the solar cell array.

[0077] After the solar cell array SAS stops supplying power to the bus VBUS, the bus voltage gradually decreases. When the voltage drop across the bus VBUS via the thirteenth resistor R13 and the fourteenth resistor R14 is less than the first reference voltage VREF1, the output of the fourth comparator U4 changes from high to low. Since the output of the third comparator U3 is high, the third transistor Q3 is kept off, and the isolation PMOS transistor V2 remains off. The output of the fourth comparator U4 is low. This low level, through diode D1, pulls down the control terminal of the push-pull circuit 5, causing the upper transistor (first transistor Q1) in the push-pull circuit 5 to disconnect and the lower transistor (second transistor Q2) to turn on. The shunt transistor V1 is disconnected, and the SAS voltage of the solar array begins to rise. When the voltage division of the solar array SAS through the third resistor R3 and the fourth resistor R4 exceeds the third reference voltage VREF3, the output of the third comparator U3 changes from high to low. At this time, the output of the OR gate U5 changes from high to low, driving the third transistor Q3 to conduct, thereby controlling the isolation PMOS transistor V2 to conduct. This completes the control of the solar array supplying power to the bus.

[0078] Advantages of this invention:

[0079] 1. Using an isolation PMOS transistor V2 instead of a traditional isolation diode avoids the disadvantages of traditional diodes, such as high heat dissipation and difficult thermal design.

[0080] 2. Introduce the gate voltage signal of the isolated PMOS transistor V2 as the basis for determining whether the isolated PMOS transistor is turned on or off;

[0081] 3. Introduce the output voltage signal of the solar cell array as the basis for determining the on and off states of the shunt tube;

[0082] 4. The function of turning on the shunt transistor after the isolation PMOS transistor V2 is turned off is implemented, ensuring that there is no risk of short circuit to ground on the power bus.

[0083] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A synchronous current shunt adjustment device for a spaceborne solar cell array, characterized in that: The circuit includes a current divider and drive circuit (1), a first voltage divider circuit (2), an isolation and drive circuit (3), a second voltage divider circuit (4), a push-pull circuit (5), a subtractor (6), a first comparator (U1), a third comparator (U3), a fourth comparator (U4), an OR gate (U5), and a diode (D1). The current splitting and driving circuit (1) is connected to the SAS output terminal of the solar cell array, the first voltage divider circuit (2), the isolation and driving circuit (3), and the push-pull circuit (5), respectively. The first voltage divider circuit (2) is also connected to the output terminal of the solar cell array SAS, the isolation and drive circuit (3), the inverting input terminal of the third comparator (U3), and the ground terminal, respectively. The isolation and drive circuit (3) is also connected to the output terminal of the solar cell array SAS, the second voltage divider circuit, the bus voltage VBUS, the subtractor (6), the ground terminal, and the 3rd pin of the OR gate (U5); The second voltage divider circuit (4) is also connected to the bus voltage VBUS, the subtractor (6), the ground terminal, and the non-inverting input terminal of the fourth comparator (U4); The push-pull circuit (5) is also connected to the VCC terminal, the output terminal of the first comparator (U1), the anode of the diode (D1), and the ground terminal, respectively. The subtractor (6) is also connected to the inverting input of the first comparator (U1), the second voltage divider circuit (4), the bus voltage VBUS, and the ground terminal, respectively. The non-inverting input of the first comparator (U1) is connected to the second reference voltage VREF2; The non-inverting input of the third comparator (U3) is connected to the third reference voltage VREF3, and the output of the third comparator (U3) is connected to pin 2 of the OR gate (U5). The inverting input of the fourth comparator (U4) is connected to the first reference voltage VREF1, and the output of the fourth comparator (U4) is connected to pin 1 of the OR gate (U5) and the cathode of the diode (D1).

2. The spaceborne solar cell array synchronous shunt adjustment device according to claim 1, characterized in that: The current shunt and drive circuit (1) includes a current shunt (V1), a fifth resistor (R5), and a sixth resistor (R6), wherein, The G terminal of the shunt tube (V1) is connected to one end of the fifth resistor (R5), the D terminal of the shunt tube (V1) is connected to the SAS output terminal of the solar cell array, the first voltage divider circuit (2), and the isolation and drive circuit (3) respectively, and the S terminal of the shunt tube (V1) is connected to one end of the sixth resistor (R6) and the ground terminal respectively. The other end of the fifth resistor (R5) is connected to the push-pull circuit (5) and the other end of the sixth resistor (R6); One end of the sixth resistor (R6) is also connected to the ground terminal.

3. The spaceborne solar cell array synchronous shunt adjustment device according to claim 2, characterized in that: The first voltage divider circuit (2) includes a third resistor (R3) and a fourth resistor (R4), wherein, One end of the third resistor (R3) is connected to the output terminal of the solar cell array SAS, the drain of the shunt tube (V1), and the isolation and drive circuit (3), respectively. The other end of the third resistor (R3) is connected to one end of the fourth resistor (R4) and the inverting input terminal of the third comparator (U3), respectively. One end of the fourth resistor (R4) is also connected to the inverting input of the third comparator (U3), and the other end of the fourth resistor (R4) is grounded.

4. The spaceborne solar cell array synchronous shunt adjustment device according to claim 3, characterized in that: The isolation and drive circuit (3) includes an isolation PMOS transistor (V2) and a third transistor (Q3). The onboard solar cell array synchronous shunt adjustment device also includes a first resistor (R1), a first capacitor (C1), a twelfth resistor (R12), a second resistor (R2), a second capacitor (C2), and a fifteenth resistor (R15). The drain of the isolation PMOS transistor (V2) is connected to the output terminal of the solar cell array SAS, the drain of the shunt transistor (V1), and one end of the third resistor (R3). The gate of the isolation PMOS transistor (V2) is connected to one end of the fifteenth resistor (R15), the subtractor (6), one end of the second resistor (R2), and one end of the second capacitor (C2). The source of the isolation PMOS transistor (V2) is connected to the other end of the second resistor (R2), the other end of the second capacitor (C2), the bus voltage VBUS, the second voltage divider circuit (4), and the subtractor (6). The emitter (e) of the third transistor (Q3) is connected to the other end of the fifteenth resistor (R15). The base (b) of the third transistor (Q3) is connected to one end of the first resistor (R1), one end of the first capacitor (C1), and one end of the twelfth resistor (R12). The collector (c) of the third transistor (Q3) is connected to the other end of the first resistor (R1), the other end of the first capacitor (C1), and the ground terminal. One end of the first resistor (R1) is also connected to one end of the first capacitor (C1) and one end of the twelfth resistor (R12), and the other end of the first resistor (R1) is also connected to the other end of the first capacitor (C1) and the ground terminal. One end of the first capacitor (C1) is also connected to one end of the twelfth resistor (R12), and the first capacitor (C1) is also connected to the ground terminal; The other end of the twelfth resistor (R12) is connected to pin 3 of the OR gate (U5); One end of the second resistor (R2) is also connected to one end of the second capacitor (C2), the bus voltage VBUS, the second voltage divider circuit (4), and the subtractor (6), respectively. The other end of the second resistor (R2) is also connected to the other end of the second capacitor (C2), one end of the fifteenth resistor (R15), and the subtractor (6), respectively. One end of the second capacitor (C2) is also connected to the bus voltage VBUS, the second voltage divider circuit (4), and the subtractor (6), respectively. The other end of the second capacitor (C2) is also connected to one end of the fifteenth resistor (R15) and the subtractor (6), respectively. One end of the fifteenth resistor (R15) is also connected to the subtractor (6).

5. The spaceborne solar cell array synchronous shunt adjustment device according to claim 4, characterized in that: The second voltage divider circuit (4) includes a thirteenth resistor (R13) and a fourteenth resistor (R14), wherein, One end of the thirteenth resistor (R13) is connected to the source of the isolation PMOS transistor (V2), one end of the second resistor (R2), one end of the second capacitor (C2), the bus voltage VBUS, and the subtractor (6). The other end of the thirteenth resistor (R13) is connected to one end of the fourteenth resistor (R14) and the non-inverting input of the fourth comparator (U4). One end of the fourteenth resistor (R14) is also connected to the non-inverting input of the fourth comparator (U4), and the other end of the fourteenth resistor (R14) is grounded.

6. The spaceborne solar cell array synchronous shunt adjustment device according to claim 5, characterized in that: The onboard solar cell array synchronous shunt adjustment device also includes a seventh resistor (R7), one end of which is connected to the push-pull circuit (5) and the anode of the diode (D1), and the other end of which is connected to the output of the first comparator (U1).

7. The spaceborne solar cell array synchronous shunt adjustment device according to claim 6, characterized in that: The push-pull circuit (5) includes a first transistor (Q1) and a second transistor (Q2), wherein, The collector (c) of the first transistor (Q1) is connected to VCC. The emitter (e) of the first transistor (Q1) is connected to the other end of the fifth resistor (R5), the other end of the sixth resistor (R6), and the emitter of the second transistor (Q2). The base (b) of the first transistor (Q1) is connected to the base of the second transistor (Q2), one end of the seventh resistor (R7), and the anode of the diode (D1). The emitter of the second transistor (Q2) is also connected to the other end of the fifth resistor (R5) and the other end of the sixth resistor (R6). The base of the second transistor (Q2) is also connected to one end of the seventh resistor (R7) and the anode of the diode (D1). The collector of the second transistor (Q2) is grounded.

8. The spaceborne solar cell array synchronous shunt adjustment device according to claim 7, characterized in that: The subtractor (6) includes an operational amplifier (U2), an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), and an eleventh resistor (R11), wherein, The output terminal of the operational amplifier (U2) is connected to one end of the eighth resistor (R8) and the inverting input terminal of the first comparator (U1), respectively. The inverting input terminal of the operational amplifier (U2) is connected to the other end of the eighth resistor (R8) and one end of the ninth resistor (R9), respectively. The non-inverting input terminal of the operational amplifier (U2) is connected to one end of the tenth resistor (R10) and one end of the eleventh resistor (R11), respectively. One end of the eighth resistor (R8) is also connected to the inverting input of the first comparator (U1), and the other end of the eighth resistor (R8) is also connected to one end of the ninth resistor (R9). The other end of the ninth resistor (R9) is connected to the gate of the isolation PMOS transistor (V2), the other end of the second resistor (R2), and the other end of the second capacitor (C2); One end of the tenth resistor (R10) is also connected to one end of the eleventh resistor (R11), and the other end of the tenth resistor (R10) is connected to the bus voltage VBUS, one end of the thirteenth resistor (R13), one end of the second capacitor (C2), one end of the second resistor (R2), and the source terminal of the isolation PMOS transistor (V2). The other end of the eleventh resistor (R11) is grounded.

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