Cached data verification methods, devices, electronic equipment, and storage media

Abstract

This disclosure provides a cached data verification method, relating to the field of artificial intelligence technology, and particularly to the fields of integrated circuit technology and deep learning technology. The specific implementation scheme includes: acquiring cache line transmission information from the cache unit to be verified; determining whether the cache line transmission information includes miss information; in response to determining that the cache line transmission information includes miss information, generating verification information for the cache unit to be verified; and using the verification information to verify the cache unit to be verified to obtain a verification result. This disclosure also provides a cached data verification apparatus, electronic device, and storage medium.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence technology, and more particularly to the fields of integrated circuit technology and deep learning technology. More specifically, this disclosure provides a cached data verification method, apparatus, electronic device, and storage medium. Background Technology

[0002] With the development of integrated circuit technology, processor processing units can retrieve cached data from cache units. Cache units can reduce the average time required for processing units to access memory. Summary of the Invention

[0003] This disclosure provides a method, apparatus, device, and storage medium for verifying cached data.

[0004] According to one aspect of this disclosure, a cached data verification method is provided, the method comprising: acquiring cache line transmission information from a cache unit to be verified; determining whether the cache line transmission information includes miss information; generating verification information for the cache unit to be verified in response to determining that the cache line transmission information includes miss information; and verifying the cache unit to be verified using the verification information to obtain a verification result.

[0005] According to another aspect of this disclosure, a cache data verification apparatus is provided, the apparatus comprising: an acquisition module for acquiring cache line transmission information from a cache unit to be verified; a determination module for determining whether the cache line transmission information includes miss information; a generation module for generating verification information for the cache unit to be verified in response to determining whether the cache line transmission information includes miss information; and a verification module for verifying the cache unit to be verified using the verification information to obtain a verification result.

[0006] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a method provided according to this disclosure.

[0007] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing a computer to perform the methods provided according to this disclosure.

[0008] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the method provided according to this disclosure.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0010] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0011] Figure 1 This is an exemplary system architecture diagram of a cached data verification method and apparatus applicable according to an embodiment of the present disclosure;

[0012] Figure 2 This is a flowchart of a cached data verification method according to an embodiment of the present disclosure;

[0013] Figure 3 This is a schematic diagram of a cached data verification method according to an embodiment of the present disclosure;

[0014] Figure 4 This is a schematic diagram of a cached data verification platform according to an embodiment of the present disclosure;

[0015] Figure 5 This is a block diagram of a cached data verification apparatus according to an embodiment of the present disclosure; and

[0016] Figure 6 This is a block diagram of an electronic device to which a cached data verification method can be applied, according to an embodiment of the present disclosure. Detailed Implementation

[0017] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0018] A processor's processing unit can be called a processing core. A multi-core processor can include multiple processing units. The cache replacement strategy of a multi-core processor can affect the processor's instruction fetch and memory access performance. The processor's instruction fetch operation includes the process of retrieving the instruction to be executed from a memory location. Cache replacement algorithms can include the pseudo-least recently used (PLRU) algorithm.

[0019] For repetitive computational tasks, the results can be cached. When the task is computed again, the actual computation can be skipped, and the result can be retrieved directly from the cache, thus speeding up processing. If the cached result becomes invalid, the task can be recomputed. During computation, caching algorithms can include optimization instructions or algorithms. The structure maintained by computer programs or hardware can utilize these instructions or algorithms to manage cached information. A cache unit can store recently or frequently used data items in a faster or more convenient storage location than regular memory to improve performance. When this storage location is full, a cache replacement algorithm can be used to select data items to discard, freeing up storage space for new data items. Cache replacement algorithms include Least Recently Used (LRU), Most Recently Used (MRU), and pseudo-Least Recently Used algorithms. For example, the Least Recently Used algorithm might include adding data to a linked list, sorting it by access time, and discarding the item with the earliest access time when it needs to be discarded. The Most Recently Used algorithm might include discarding the item with the most recent access time.

[0020] For processor caches with high correlation, the implementation cost of the Least Recently Used (LRU) algorithm is too high. Discarding the least recently used item among multiple cache entries is sufficient. Compared to the LRU algorithm, the pseudo-LRU algorithm has a slightly lower hit rate, better latency, less power consumption, and lower overhead.

[0021] Figure 1 Figure 1 is an exemplary system architecture diagram illustrating a cached data verification method and apparatus applicable according to an embodiment of this disclosure. It should be noted that Figure 1 is merely an example of a system architecture applicable to embodiments of this disclosure, intended to help those skilled in the art understand the technical content of this disclosure, but does not imply that embodiments of this disclosure cannot be used in other devices, systems, environments, or scenarios.

[0022] like Figure 1 As shown, the multi-core processor may include processing unit 111 and processing unit 112. Cache unit 120 may include cache replacer 121 and buffer 122. Cache replacer 121 may be used to execute cache replacement algorithms (e.g., pseudo-least recently used algorithm).

[0023] In a system architecture comprising multiple processing units, cache unit 120 can receive cache line requests from multiple processing units. Next, the cache unit can determine whether multiple cache lines in buffer 122 can hit the cache line address information corresponding to the request. Thus, cache unit 120 can determine whether there is any missed cache line address information. If there is missed cache line address information, it can send the missed cache line address information to the main memory unit to retrieve the cache line corresponding to the missed cache line address information. The new cache line returned by main memory unit 130 can be transmitted to the processing unit via cache replacer 121. Cache replacer 121 can determine whether to replace the cache line in buffer 122.

[0024] It's understandable that if the cache replacer encounters an error, it replaces the next cache line to be accessed in the buffer with a new cache line returned by the main memory. Therefore, when there are requests for the same cache line, a cache miss will occur, leading to another sending of the cache miss address information to the main memory, causing memory access latency and impacting processor performance.

[0025] In some examples, it can be verified whether the cache lines returned by the cache unit are correct. To further improve processor performance, this disclosure validates the cache replacer, which will be described in detail below.

[0026] Figure 2 This is a flowchart of a cached data verification method according to an embodiment of the present disclosure.

[0027] like Figure 2 As shown, the method 200 may include operations S210 to S240.

[0028] In operation S2l0, cache line transmission information from the cache unit to be verified is obtained.

[0029] For example, the cache unit to be verified may include the cache unit described above. The cache unit to be verified may store multiple cache lines.

[0030] In this embodiment of the disclosure, the processor's processing unit can send a cache line request to the cache unit to be verified. The cache line request can correspond to at least one cache line address. The cache unit to be verified can determine whether multiple cache lines can hit the cache line address information based on the cache line request. For example, a first processing unit can send a first cache line request to the cache unit to be processed. The first cache line request can correspond to first cache line address information. If multiple cache lines can hit the first cache line address information, a hit message can be generated. The first cache line that hits the first cache line address information can be returned to the first processing unit. The information transmitted between the first processing unit and the cache unit to be verified can be used as cache line transmission information. As another example, a second processing unit can send a second cache line request to the cache unit to be processed. The second cache line request can correspond to second cache line address information. If multiple cache lines cannot hit the second cache line address information, a miss message can be generated. The miss message can be returned to the second processing unit. The information transmitted between the second processing unit and the cache unit to be verified can also be used as cache line transmission information. This cache line transmission information can be obtained.

[0031] In operation S220, determine whether the cache line transmission information includes miss information.

[0032] For example, the cached line transmission information can be parsed to obtain hit or miss information. If a miss is obtained, operation S230 can be executed.

[0033] In operation S230, in response to determining that the cache line transmission information includes miss information, verification information is generated for the cache unit to be verified.

[0034] For example, based on the miss information, outside the cache unit to be verified, the target cache replacement algorithm can be used to generate the address information of the cache line to be verified for the above cache line request, which can then be used as the verification information for the cache unit to be verified.

[0035] In operation S240, the verification information is used to verify the cache unit to be verified, and the verification result is obtained.

[0036] For example, in the event of a cache miss, the cache unit to be verified can send the actual cache miss address information to the main memory unit. The actual cache miss address information and the verification cache miss address information can be compared to obtain the verification result. The verification result can indicate whether the cache unit to be verified is functioning correctly.

[0037] This disclosure verifies the input (missed cache address information) to the cache replacement method, enabling effective verification of the cache replacement strategy. It comprehensively and effectively verifies the performance of cache units, helping to reduce or eliminate performance loss, and effectively reducing the additional performance overhead caused by cache replacer errors.

[0038] As can be understood, the above has described the method flow of this disclosure. The following will use the Universal Verification Methodology (UVM) platform to illustrate some ways to implement the above method.

[0039] Figure 3 This is a schematic diagram of a cached data verification method according to an embodiment of the present disclosure.

[0040] like Figure 3 As shown, the multiple processing units include processing unit 311 and processing unit 312. Cache unit 320 may include cache replacer 321 and buffer 322. Cache replacer 321 may be used to execute cache replacement algorithms (e.g., pseudo-least recently used algorithm).

[0041] The cache unit 320 can receive cache line requests from multiple processing units. Based on the cache line address information corresponding to the request and multiple cache lines in the buffer 322, it determines whether there is a cache line miss. If a cache line miss exists, the cache unit 320 can send a retrieval request corresponding to the cache line miss to the main memory unit 330. The new cache line returned by the main memory unit 330 can be transmitted to the processing unit via the cache replacer 321. The cache replacer 321 can determine whether to replace the cache line in the buffer 322. The cache unit 320 can serve as the aforementioned cache unit to be verified.

[0042] like Figure 3As shown, the information acquisition module 301 can perform the above-described operation S210. In this embodiment of the present disclosure, acquiring cache line transmission information from the cache unit to be verified may include: periodically acquiring cache line requests sent by the multi-core processor to the cache unit to be verified; and determining cache line transmission information based on the cache line requests. For example, in a processing cycle, the processing unit 311 may send the above-described first cache line request to the cache unit 320. The processing unit 312 may send the above-described second cache line request to the cache unit 320. The acquisition unit 301 may periodically acquire these cache line requests. Furthermore, the information acquisition module 301 can determine the first cache line transmission information corresponding to the first cache line request from multiple cache line transmission information. The information acquisition module 301 can also determine the second cache line transmission information corresponding to the second cache line request from multiple cache line transmission information.

[0043] like Figure 3 As shown, the hit or miss determination module 302 can perform the above-described operation 220. In this embodiment of the disclosure, determining whether the cache line transmission information includes miss information includes: parsing the cache line transmission information using a target cache replacement method to obtain at least one of hit information and miss information. The target replacement method includes one of the least recently used method and the pseudo least recently used method. For example, the target cache replacement algorithm may include a tree-based pseudo least recently used algorithm (tree-PLRU).

[0044] In this embodiment of the disclosure, the cache line transmission information includes multiple cache line address information. For example, the first cache line transmission information may include multiple first cache line address information. The second cache line transmission information may include multiple second cache line address information.

[0045] In this embodiment of the disclosure, the hit information indicates the cache line address information that the cache line currently stored in the cache unit to be verified can hit among multiple cache line address information. The cache unit 320 can determine whether the M cache lines in the buffer 322 can hit the cache line address information. In one example, if the cache unit 320 can determine that N first cache lines out of the M cache lines hit N first cache line address information, the hit or miss determination module 302 can parse the hit information from the first cache transmission information. M is an integer greater than 1. N can be an integer greater than 1 and less than M. In another example, among multiple second cache line address information, if the cache unit 320 can determine that none of the M cache lines hit the second cache line address information cache_line21, the hit or miss determination module 302 can parse the miss information from the second cache transmission information. In the case of parsing the miss information, the verification information generation module 303 can perform related operations.

[0046] like Figure 3 As shown, the verification information generation module 303 can perform the above-described operation S230. In this embodiment of the present disclosure, in response to determining that the cache line transmission information includes miss information, generating verification information for the cache unit to be verified may include: determining, based on the miss information, the address information of the cache line request that is a verification miss cache line, as the verification information. For example, in response to the existence of miss information, among multiple second cache line address information, the verification information generation module 303 may determine the second cache line address information cache line 2T that cannot be hit by M cache lines, as the verification miss cache line address information.

[0047] like Figure 3 As shown, the cache verification module 304 can perform the above-described operation S240. In this embodiment of the present disclosure, verifying the cache unit to be verified using verification information and obtaining the verification result may include: obtaining the actual cache line address information that the cache unit to be verified sent to the main storage unit. Comparing the actual cache line address information with the verified cache line address information to obtain the verification result. For example, as described above, the cache unit 320 can determine that M cache lines cannot hit the second cache line address information cache line 21. The cache unit 320 can send the second cache line address information cache line 21 to the main storage unit 330. The second cache line address information cache line 21 can be used as the actual cache line address information. For another example, the second cache line address information cache line 21 can be compared with the second cache line information cache line 2T to obtain the verification result.

[0048] In this embodiment, comparing the actual cache line miss address information with the verified cache line miss address information to obtain the verification result may include: if the actual cache line miss address information and the verified cache line miss address information are consistent, the cache unit to be verified is determined to be abnormal. For example, if the second cache line address information cacheline21 is inconsistent with the second cache line address information cacheline2T, it can be determined that cache unit 320 is abnormal. Next, an alarm message can be issued to adjust the cache replacer.

[0049] In another embodiment of this disclosure, comparing the actual cache line miss address information with the verified cache line miss address information to obtain the verification result may include: if the actual cache line miss address information and the verified cache line miss address information are consistent, it is determined that the cache unit to be verified is normal.

[0050] The performance of the cache replacement was verified through the embodiments disclosed herein, thereby enabling a comprehensive and effective verification of the performance of the cache unit. This helps to reduce or eliminate performance loss of the cache unit and effectively reduce the additional performance overhead caused by cache replacement errors.

[0051] As can be understood, the method of this disclosure has been described above, and the application scenarios of this disclosure will be described below.

[0052] Figure 4 This is a schematic diagram illustrating an application scenario of a cached data verification method according to an embodiment of the present disclosure.

[0053] like Figure 4 As shown, the cached data verification platform 400 can be configured in the UVM environment level 406 of the UVM test bench 405. The cached data verification platform 400 can, for example, implement the method 200 described above. For instance, the cached data verification platform 400 may include the aforementioned information acquisition module, hit / miss determination module, verification information generation module, and cache verification module.

[0054] The cache data verification platform 400 can obtain cache line transfer information of the cache unit 420 to be verified through the System VeriLog Virtual Interface. The cache data verification platform 400 can also be started after the general verification test platform 405 is started. Next, the cache data verification platform 400 can perform cache data verification in multiple processing cycles of the processor. Through this embodiment, a cache data verification method is implemented based on a general verification test platform, which can verify different cache units, has high repeatability, and is suitable for verifying cache replacements of multi-core processors.

[0055] Figure 5 This is a block diagram of a cached data verification apparatus according to an embodiment of the present disclosure.

[0056] like Figure 5 As shown, the device 500 may include an acquisition module 510, a determination module 520, a generation module 530, and a verification module 540.

[0057] The acquisition module 510 is used to acquire cache line transmission information from the cache unit to be verified.

[0058] The determination module 520 is used to determine whether the cache line transmission information includes miss information.

[0059] The generation module 530 is used to generate verification information for the cache unit to be verified in response to determining that the cache line transmission information includes miss information.

[0060] The verification module 540 is used to verify the cache unit to be verified using the verification information and obtain the verification result.

[0061] In some embodiments, the acquisition module includes: a first acquisition submodule, configured to periodically acquire cache line requests sent by the multi-core processor to the cache unit to be verified; and a first determination submodule, configured to determine cache line transmission information based on the cache line requests.

[0062] In some embodiments, the cache line transmission information includes multiple cache line address information; the determining module includes: a parsing submodule, used to parse the cache line transmission information using a target cache replacement method to obtain at least one of hit information and miss information, wherein the hit information indicates the hit cache line address information that can be hit by the multiple cache lines currently stored in the cache unit to be verified among the multiple cache line address information; the miss information indicates the verification miss cache line address information that cannot be hit by the multiple cache lines currently stored in the cache unit to be verified among the multiple cache line address information.

[0063] In some embodiments, the generation module includes a second determining submodule, configured to determine, based on the miss information, the address information of the cache line that was not verified for the cache line request, as verification information.

[0064] In some embodiments, the verification module includes: a second acquisition submodule, configured to acquire the actual cache line address information sent by the cache unit to be verified to the main storage unit; and a comparison submodule, configured to compare the actual cache line address information with the verification cache line address information to obtain a verification result.

[0065] In some embodiments, the comparison submodule includes: a first determining unit, configured to determine that the cache unit to be verified is normal when the actual cache miss address information is consistent with the verified cache miss address information; and a second determining unit, configured to determine that the cache unit to be verified is abnormal when the actual cache miss address information is inconsistent with the verified cache miss address information.

[0066] In some embodiments, the target cache replacement method includes one of the Least Recently Used (LRU) method and the pseudo Least Recently Used (PLRU) method.

[0067] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0068] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0069] Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0070] like Figure 6 As shown, device 600 includes a computing unit 601, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 602 or a computer program loaded from storage unit 608 into random access memory (RAM) 603. RAM 603 may also store various programs and data required for the operation of device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.

[0071] Multiple components in device 600 are connected to I / O interface 605, including: input unit 606, such as keyboard, mouse, etc.; output unit 607, such as various types of monitors, speakers, etc.; storage unit 608, such as disk, optical disk, etc.; and communication unit 609, such as network card, modem, wireless transceiver, etc. Communication unit 609 allows device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0072] The computing unit 601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as the cached data verification method. For example, in some embodiments, the cached data verification method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of the cached data verification method described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform the cached data verification method by any other suitable means (e.g., by means of firmware).

[0073] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0074] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0075] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0076] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) monitor or an LCD (liquid crystal display)) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0077] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0078] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other.

[0079] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0080] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for validating cached data, comprising: Obtain cache line transmission information from the cache unit to be verified, wherein obtaining cache line transmission information from the cache unit to be verified includes: periodically obtaining cache line requests sent by the multi-core processor to the cache unit to be verified; and determining cache line transmission information based on the cache line requests; Determine whether the cache line transmission information includes a miss information, wherein the miss information indicates that the cache line of the cache unit to be verified did not match the cache line address information corresponding to the cache line request; In response to determining that the cache line transmission information includes miss information, verification miss cache line address information for the cache unit to be verified is generated, wherein generating the verification miss cache line address information for the cache unit to be verified includes: based on the miss information, outside the cache unit to be verified, using a target cache replacement algorithm to generate verification miss cache line address information for the cache line request, as verification information for the cache unit to be verified; Obtain the actual cache line address information of the cache unit to be verified sent to the main storage unit; and The actual cache miss address information is compared with the verified cache miss address information to obtain a verification result. If the actual cache miss address information and the verified cache miss address information are consistent, the cache unit to be verified is determined to be normal.

2. The method according to claim 1, wherein, The cache line transmission information includes multiple cache line address information; determining whether the cache line transmission information includes miss information includes: The cache line transmission information is parsed using a target cache replacement method to obtain at least one of hit information and miss information. The hit information indicates the hit cache line address information that the cache line currently stored in the cache unit to be verified can hit among the multiple cache line address information; The miss information indicates that, among the multiple cache line address information, the multiple cache lines currently stored in the cache unit to be verified cannot be matched by the verification miss cache line address information.

3. The method according to claim 1, wherein, Comparing the actual cache miss address information with the verified cache miss address information to obtain the verification result further includes: If the actual cache miss address information is inconsistent with the verified cache miss address information, the cache unit to be verified is determined to be abnormal.

4. The method according to claim 2, wherein, The target cache replacement method includes one of the Least Recently Used (LRU) method and the pseudo Least Recently Used (PLRU) method.

5. A cached data verification device, comprising: An acquisition module is used to acquire cache line transmission information from a cache unit to be verified. The acquisition module includes: a first acquisition submodule, used to periodically acquire cache line requests sent by a multi-core processor to the cache unit to be verified; and a first determination submodule, used to determine cache line transmission information based on the cache line requests. The determination module is used to determine whether the cache line transmission information includes miss information, wherein the miss information indicates that the cache line of the cache unit to be verified has missed the cache line address information corresponding to the cache line request; A generation module is configured to, in response to determining that the cache line transmission information includes miss information, generate verification miss cache line address information for the cache unit to be verified, wherein generating the verification miss cache line address information for the cache unit to be verified includes: based on the miss information, generating verification miss cache line address information for the cache line request outside the cache unit to be verified using a target cache replacement algorithm, as verification information for the cache unit to be verified; and The verification module includes a second acquisition submodule and a comparison submodule. The second acquisition submodule is used to acquire the actual cache line address information sent by the cache unit to be verified to the main storage unit. The comparison submodule is used to compare the actual cache line address information with the verification cache line address information to obtain a verification result. The first determination unit of the comparison submodule determines that the cache unit to be verified is normal when the actual cache line address information and the verification cache line address information are consistent.

6. The apparatus according to claim 5, wherein, The cache line transmission information includes multiple cache line address information; The determining module includes: The parsing submodule is used to parse the cache line transmission information using the target cache replacement method to obtain at least one of hit information and miss information. The hit information indicates the hit cache line address information that the cache line currently stored in the cache unit to be verified can hit among the multiple cache line address information; The miss information indicates that, among the multiple cache line address information, the multiple cache lines currently stored in the cache unit to be verified cannot be matched by the verification miss cache line address information.

7. The apparatus according to claim 5, wherein, The comparison submodule further includes: The second determining unit determines that the cache unit to be verified is abnormal if the actual cache miss address information is inconsistent with the verified cache miss address information.

8. The apparatus according to claim 6, wherein, The target cache replacement method includes one of the Least Recently Used (LRU) method and the pseudo Least Recently Used (PLRU) method.

9. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 4.

10. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 4.

11. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 4.

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