A general multi-master parallel on-chip bus supporting x86 architecture

By designing a universal multi-master parallel on-chip bus that supports the x86 architecture, the problem that existing buses cannot support the x86 architecture and other development environments is solved. It realizes parallel data transmission and resource saving for multi-master devices, is applicable to different EDA development tools, improves work efficiency and reduces R&D costs.

CN115794712BActive Publication Date: 2026-01-09709TH RESEARCH INSTITUTE CHINA STATE SHIPBUILDING CORP LTD
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Patent Information

Application Number
CN202211392588.0
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-11-08
Publication Date
2026-01-09
Estimated Expiration
2042-11-08

AI Technical Summary

Technical Problem

The existing bus cannot support the x86 architecture and other development environments, and its arbitration mechanism is simplistic, consuming PPGA pin resources.

Method used

A general-purpose multi-master parallel on-chip bus supporting the x86 architecture is designed, including a master device interface unit, a slave device interface unit, a bus arbiter, a logic control unit, an address router, a read data router, a write data router, and a control signal router, which realizes multi-master device access, bus interface multiplexing, and multiple priority arbitration strategies.

Benefits of technology

It enables parallel data transmission between multiple master and slave devices, supports IO and memory space access, saves PPGA pin resources, is suitable for different EDA development tools and environments, improves work efficiency, and reduces R&D costs and time.

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Abstract

The application discloses a general multi-master parallel on-chip bus supporting X86 architecture and belongs to the field of data transmission buses. The general on-chip bus supports parallel data transmission between multiple master processing devices and multiple slave devices, supports IO and memory space access, multiple priority arbitration strategies, multiple waiting states, an on-chip shared address multi-path data (SAMD) topology structure and three-state multiplexing of a bus data external interface, read and write data are multiplexed, and PPGA pin resources are saved. Through testing and simulation, a general IP core is formed, can be applied in different EDA development tools and development environments, has strong generalization, can effectively avoid repeated work, improve work efficiency, and further reduce research and development cost and research and development time.
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