PCIE bus-based extended dual-port RAM communication device and implementation method

Abstract

The application provides an extended dual-port RAM communication device based on a PCIE bus and an implementation method, which communicates with a CPU through a PCIE bus, connects with external equipment through an interface, and realizes dual-port RAM communication between the PCIE bus CPU and the external equipment. The application can work independently or in parallel in a far-end mode and a near-end mode. The extended dual-port RAM communication device based on the PCIE bus supports physical connection with a dual-port RAM communication port of the external equipment through a plurality of optional types of interfaces, and matches the electrical characteristics of the dual-port RAM communication physical port of different external equipment. The extended dual-port RAM communication device based on the PCIE bus generates a square wave signal and transmits the square wave signal to the CPU and the external equipment at both ends of the dual-port RAM communication, so that the CPU and the external equipment respectively perform read and write access to the dual-port RAM in the positive half cycle and the negative half cycle of the square wave signal, and the conflict caused by simultaneous read and write of both parties to the same address unit in the dual-port RAM is avoided.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of communication technology, and more particularly relates to an extended dual-port RAM communication device based on a peripheral component interconnect express (PCIE) bus and an implementation method. BACKGROUND

[0002] In the fields of ships, aviation, and measurement and control, multiple processor systems often need to work in parallel and cooperatively, and the use of dual-port random access memory (RAM) communication is a common means of data interaction between processor systems. Dual-port RAM has two completely independent ports composed of data lines, address lines, and control lines, allowing two independent systems to simultaneously access it through the two ports for data sharing.

[0003] Dual-port RAM communication has the advantages of high flexibility, low hardware overhead, and low synchronization requirements for data caching mechanisms for both parties, and is commonly used for data interaction between computers and other devices such as radars. The existing dual-port RAM communication method between computers and other devices is generally based on CPCI bus computer design and implementation. With the development of computer technology, the Compact Peripheral Component Interconnect (CPCI) bus is gradually replaced by the PCIE bus, and PCIE bus computers are gradually becoming mainstream.

[0004] In the military and industrial fields, the state of the device on one end of the dual-port RAM communication is usually fixed, while the computer on the other end needs to be upgraded to a PCIE bus computer. There is currently no specific technical solution for PCIE bus computers to perform dual-port RAM communication, so how to effectively implement PCIE bus extended dual-port RAM communication is a necessary problem that needs to be solved in the field. SUMMARY

[0005] To overcome the defects of the prior art, the present application aims to provide an extended dual-port RAM communication device and implementation method based on a PCIE bus, which solves the problem of the lack of a specific technical solution for PCIE bus computers to perform dual-port RAM communication in the prior art.

[0006] To achieve the above-mentioned purpose, in a first aspect, the present application provides an extended dual-port RAM communication device based on a PCIE bus, comprising a programmable logic unit, a memory unit, an atomic clock unit, an interface level conversion unit, and a port allocation unit.

[0007] The programmable logic unit includes a Field Programmable Gate Array (FPGA); the FPGA builds a PCIE bus physical link through a GTX port and a connector or a gold finger, and is connected with a central processing unit (CPU) through the PCIE bus; the FPGA is internally integrated with a plurality of functional modules designed by a Verilog hardware description language, and realizes PCIE communication with the CPU and dual-port RAM communication with external devices through the PCIE bus;

[0008] The memory unit includes a group of Double Data Rate (DDR) memories; the memory unit is connected with the FPGA of the programmable logic unit, and temporarily stores data in the running process of the FPGA;

[0009] The atomic clock unit is based on a chip-level atomic clock, is connected with the FPGA of the programmable logic unit, outputs a pulse signal to the FPGA through an I / O interface, generates a reference signal for time-sharing access of the CPU and external devices to the dual-port RAM, and communicates with the FPGA through a UART interface;

[0010] The interface level conversion unit is connected with the port distribution unit at one end and is connected with external dual-port RAM communication devices through a plurality of types of interfaces at the other end, provides a signal transmission link matching different electrical characteristics, and is controlled by the FPGA of the programmable logic unit to perform half-duplex signal transmission on a transmission path.

[0011] The port distribution unit is connected with the FPGA of the programmable logic unit at one end and is connected with the interface level conversion unit at the other end, and connects I / O ports of the FPGA with signal transmission links with different electrical characteristics in a hardware configuration manner.

[0012] The plurality of types of interfaces can be an LVDS interface, an M-LVDS interface, an RS485 interface, a 5V TTL interface, a 3.3V TTL interface, and the like.

[0013] In an optional example, the functional modules inside the programmable logic unit of the FPGA are designed by a Verilog hardware description language, and include a Utility Buffer, an XDMA, an AXI Interconnect, an AXI SmartConnect, a first AXI block random memory (BRAM) controller, a second AXI BRAM controller, a remote mode BRAM, a near mode BRAM, a data interaction module, a remote mode BRAM port control module, a remote mode read module, a remote mode write module, an external device dual-port RAM port control module, a near mode control module, and a configuration module.

[0014] The Utility Buffer, the XDMA, the AXI SmartConnect, and the AXI Interconnect are used to build a mapping channel of a PCIE bus to an AXI bus and an AXI LITE bus on an FPGA chip; the mapping channel is used to realize read-write access of a CPU to functional modules and IP cores on the AXI bus and the AXI LITE bus.

[0015] The data interaction module is mounted on the AXI LITE bus, and is used to acquire instructions and parameters issued by the CPU through an AXI interface register, to control execution of the remote mode read module, the remote mode write module, and the near mode control module according to the acquired instructions and parameters, and to upload state parameters of the execution process of the remote mode read module, the remote mode write module, and the near mode control module to the CPU through the AXI interface register.

[0016] The first AXI BRAM controller and the remote mode BRAM are used to build an on-chip storage space and a CPU access entry in a remote mode; one end of the first AXI BRAM controller is mounted on the AXI bus, and the other end is connected to an A port of the remote mode BRAM; the CPU reads and writes the remote mode BRAM through the A port of the remote mode BRAM; and a B port of the remote mode BRAM is used to connect the remote mode BRAM port control module.

[0017] The remote mode read module, the remote mode write module, the remote mode BRAM port control module, and the external device dual-port RAM port control module are cooperatively matched, and under the control of the data interaction module, data is read from the remote mode BRAM through the B port of the remote mode BRAM and written into the dual-port RAM of an external device, or data is read from the dual-port RAM of the external device and written into the remote mode BRAM through the B port of the remote mode BRAM.

[0018] The second AXI BRAM controller and the near-end mode BRAM are used for constructing on-chip storage space and CPU access entry in the near-end mode; one end of the second AXI BRAM controller is mounted on the AXI bus, and the other end is connected to the A port of the near-end mode BRAM, and the CPU reads and writes the near-end mode BRAM through the A port of the near-end mode BRAM, and the B port of the near-end mode BRAM is connected to the near-end mode control module;

[0019] The near-end mode control module is connected to the external device at one end and connected to the B port of the near-end mode BRAM at the other end, and selects to write the data transmitted by the external device into the corresponding address unit of the near-end mode BRAM or to take out the data from the corresponding address unit of the near-end mode BRAM and send to the data line connected to the external device by detecting whether the control line, address line and data line connected to the external device meet the read-write timing.

[0020] In an optional example, the functional module designed by the Verilog hardware description language inside the FPGA of the programmable logic unit further comprises: an atomic clock communication module, a digital phase-locked loop and a signal generation module;

[0021] The atomic clock communication module performs UART communication with the atomic clock;

[0022] The digital phase-locked loop receives the pulse signal of the atomic clock and performs frequency multiplication, transmits the frequency-multiplied signal to the signal generation module, and generates a preset square wave signal according to actual needs; the preset square wave signal is used to notify the CPU in the form of an interrupt and is transmitted to an external dual-port RAM communication device through an external interface, so that the two parties of the dual-port RAM communication respectively access the dual-port RAM in the positive half cycle and the negative half cycle of the preset square wave signal, avoiding access conflict caused by simultaneous access of both parties to the same address unit in the dual-port RAM.

[0023] In an optional example, the functional module designed by the Verilog hardware description language inside the FPGA of the programmable logic unit further comprises: an interrupt control module;

[0024] The interrupt control module is mounted on the AXI LITE bus and is used for receiving the interrupt source transmitted by the signal generation module, triggering the XDMA to generate an MSI interrupt to notify the CPU according to the interrupt source, and the AXI interface register of the interrupt control module receives the write operation of the CPU to realize enabling and clearing the interrupt.

[0025] In a second aspect, the application provides a dual-port RAM communication implementation method based on the communication device provided in the first aspect, comprising the following steps:

[0026] The AXI interface register of the interrupt control module receives the enabling interrupt command written by the CPU;

[0027] The digital phase-locked loop receives the reference signal transmitted by the atomic clock, performs frequency multiplication on the reference signal, and transmits the frequency-multiplied reference signal to a signal generation module;

[0028] The signal generation module generates a preset square wave signal according to the frequency-multiplied reference signal, captures the rising edge of the preset square wave signal, and generates a trigger pulse at each rising edge and transmits the trigger pulse to an interrupt control module as an interrupt source;

[0029] The interrupt control module generates an interrupt trigger level when receiving the trigger pulse, and triggers the XDMA to generate an MSI interrupt to notify the CPU;

[0030] The AXI interface register of the data interaction module receives the control signal and parameters written by the CPU, wherein the control signal and parameters include a write enable signal in a remote mode, a target address range of writing the external device dual-port RAM in the remote mode, a read enable signal in the remote mode, and a target address range of reading the external device dual-port RAM in the remote mode; the remote mode BRAM receives the target data of writing the external device dual-port RAM in the remote mode written by the CPU;

[0031] The AXI interface register of the interrupt control module receives the write clear interrupt command sent by the CPU, and then receives the write enable interrupt command sent by the CPU;

[0032] The data interaction module polls the AXI interface register inside the data interaction module, and if it is detected that the write enable signal in the remote mode is valid, the remote mode write operation program is entered, the remote mode write module is started to execute, and a remote mode write process flag bit is established;

[0033] During the validity of the remote mode write process flag bit, the external device dual-port RAM port control module gives the remote mode write module control over the dual-port RAM port of the external device, and the remote mode BRAM port control module gives the remote mode write module control over the B port of the remote mode BRAM;

[0034] The remote mode write module queries the start address and the end address of the target address range of writing the external device dual-port RAM in the remote mode in the AXI interface register inside the data interaction module;

[0035] The remote mode write module enables the remote mode write action counter inside the remote mode write module, and assigns the start address of the target address range of writing the external device dual-port RAM in the remote mode, which is queried in the AXI interface register of the data interaction module, to the remote mode write action counter;

[0036] The remote mode write module judges whether the value of the remote mode write action counter is in the target address range of writing the external device dual-port RAM in the remote mode. If the value is in the target address range, the remote mode write module accesses the B port of the remote mode BRAM through the remote mode BRAM port control module to read the data in the address unit equal to the value of the remote mode write action counter in the remote mode BRAM. The remote mode write module writes the data read from the remote mode BRAM into the address unit equal to the value of the remote mode write action counter in the external device dual-port RAM through the external device dual-port RAM port control module according to the time sequence, and controls the remote mode write action counter to increase by one, and the above-mentioned judgment and subsequent operations are continued.

[0037] In an optional example, the method further comprises the following steps: the remote mode write module judges whether the value of the remote mode write action counter in the remote mode write module is in the target address range of writing the external device dual-port RAM in the remote mode. If the value is not in the target address range, after all the to-be-written data of the remote mode write operation are written into the corresponding address units of the external device dual-port RAM, the remote mode write action counter is cleared, the remote mode write module releases the control right of the FPGA accessing the external device dual-port RAM port and the access control right of the B port of the remote mode BRAM, clears the remote mode write process flag, and waits for the next operation.

[0038] In an optional example, the method further comprises the following steps:

[0039] The data interaction module polls the AXI interface register in the data interaction module. If it is detected that the read enable signal in the remote mode is valid, the remote mode read operation program is entered, the remote mode read module is executed, and the remote mode read process flag is established.

[0040] During the validity of the remote mode read process flag, the external device dual-port RAM port control module gives the remote mode read module the control right of the FPGA accessing the external device dual-port RAM port, and the remote mode BRAM port control module gives the remote mode read module the control right of accessing the B port of the remote mode BRAM.

[0041] The remote mode read module queries the start address and the end address of the target address range of reading the external device dual-port RAM in the remote mode in the AXI interface register in the data interaction module.

[0042] The remote mode read module enables the remote mode read action counter in the remote mode read module, and assigns the start address of the target address range of reading the external device dual-port RAM in the remote mode to the remote mode read action counter.

[0043] The remote mode reading module judges whether the value of the remote mode reading action counter is in the target address range of reading the external device dual-port RAM in the remote mode. If the value is in the target address range, the remote mode reading module reads the data in the address unit equal to the value of the remote mode reading action counter in the external device dual-port RAM according to the timing regulation through the external device dual-port RAM port control module, writes the data read from the external device dual-port RAM into the address unit equal to the value of the remote mode reading action counter in the remote mode BRAM through the remote mode BRAM port control module, and provides the CPU for inquiry. The remote mode reading action counter is incremented, and the above-mentioned judgment of whether the value of the remote mode reading action counter is in the target address range of reading the external device dual-port RAM and the subsequent operations are continuously executed in a loop.

[0044] In an optional example, the method further includes the following steps: the remote mode reading module judges whether the value of the remote mode reading action counter in the remote mode reading module is in the target address range of reading the external device dual-port RAM in the remote mode. If the value is not in the target address range, after all the to-be-read data of the remote mode reading operation are read out from the external dual-port device RAM and written into the corresponding address unit of the remote mode BRAM, the remote mode reading action counter is cleared, the remote mode reading module releases the control right of the FPGA to access the external device dual-port RAM port and the access control right of the B port of the remote mode BRAM, clears the remote mode reading process flag bit, and waits for the next operation.

[0045] In a third aspect, the application provides another dual-port RAM communication implementation method based on the communication device provided in the above-mentioned first aspect, which includes the following steps:

[0046] The configuration module receives a write-enabled near-end mode command;

[0047] The interrupt control module AXI interface register receives a CPU write-enabled interrupt command;

[0048] The digital phase-locked loop receives the reference signal sent by the atomic clock, performs frequency multiplication on the reference signal, and transmits the reference signal after frequency multiplication to the signal generation module;

[0049] The signal generation module generates a preset square wave signal according to the reference signal after frequency multiplication by the digital phase-locked loop, captures the rising edge of the preset square wave signal, and generates a trigger pulse at each rising edge and transmits the trigger pulse to the interrupt control module as an interrupt source;

[0050] The interrupt control module generates an interrupt trigger level when the trigger pulse is received, and triggers the XDMA to generate an MSI interrupt to notify the CPU;

[0051] The A port of the near-end mode BRAM receives data written by the CPU to the near-end mode BRAM.

[0052] The AXI interface register of the interrupt control module receives the write clear interrupt command sent by the CPU, and then receives the write enable interrupt command sent by the CPU;

[0053] The near-end mode control module cyclically detects the level and timing state of the control line of the dual-port RAM communication port connected between the FPGA and the external device, and if the state conforms to the dual-port RAM write timing, enters a near-end mode write operation program, executes near-end mode write operation logic, and establishes a near-end mode write process flag bit;

[0054] During the validity period of the near-end mode write process flag bit, the near-end mode control module gives the near-end mode write operation logic in its interior access control right of the B port of the near-end mode BRAM;

[0055] The near-end mode control module detects the address line and data line of the dual-port RAM communication port connected between the FPGA and the external device, and obtains the address and corresponding data expected to be written into the dual-port RAM by the external device under the near-end mode;

[0056] The near-end mode write operation logic in the near-end mode control module writes the obtained data into the corresponding address unit of the near-end mode BRAM through the B port of the near-end mode BRAM;

[0057] The near-end mode control module clears the near-end mode write process flag bit, and waits for the next operation.

[0058] In an optional example, the method further includes the following steps:

[0059] The near-end mode control module cyclically detects the level and timing state of the control line of the dual-port RAM communication port connected between the FPGA and the external device, and if the state conforms to the dual-port RAM read timing, enters a near-end mode read operation program, executes near-end mode read operation logic, and establishes a near-end mode read process flag bit;

[0060] During the validity period of the near-end mode read process flag bit, the near-end mode control module gives the near-end mode read operation logic in its interior access control right of the B port of the near-end mode BRAM;

[0061] The near-end mode control module detects the address line of the dual-port RAM communication port connected between the FPGA and the external device, and obtains the address expected to read out data from the dual-port RAM by the external device under the near-end mode;

[0062] The near-end mode read operation logic in the near-end mode control module reads out data from the address unit corresponding to the read-out address in the near-end mode BRAM through the B port of the near-end mode BRAM, and sends the data to the data line of the dual-port RAM communication port connected between the FPGA and the external device;

[0063] The near-end mode control module clears the near-end mode reading process flag bit and waits for the next operation.

[0064] Compared with the prior art, the above technical scheme conceived by the present application has the following beneficial effects in general:

[0065] The application provides an extended dual-port RAM communication device and implementation method based on a PCIE bus, and realizes dual-port RAM communication between a PCIE bus processor system and external equipment.

[0066] The application provides an extended dual-port RAM communication device and implementation method based on a PCIE bus, and supports independent or parallel work in a far-end mode through software setting, that is, external equipment is arranged with dual-port RAM as a communication node, and the device performs dual-port RAM communication by accessing the dual-port RAM on the external equipment.

[0067] The application provides an extended dual-port RAM communication device and implementation method based on a PCIE bus, and supports independent or parallel work in a far-end mode through software setting, that is, external equipment is arranged with dual-port RAM as a communication node, and the device performs dual-port RAM communication by accessing the dual-port RAM on the external equipment.

[0068] The application provides an extended dual-port RAM communication device and implementation method based on a PCIE bus, and supports independent or parallel work in a far-end mode through software setting, that is, external equipment is arranged with dual-port RAM as a communication node, and the device performs dual-port RAM communication by accessing the dual-port RAM on the external equipment. BRIEF DESCRIPTION OF DRAWINGS

[0069] Figure 1 is a hardware principle block diagram of the extended dual-port RAM communication device based on the PCIE bus provided by the embodiment of the application;

[0070] Figure 2 is a principle block diagram of an internal function module of the FPGA;

[0071] Figure 3 is an implementation step flow chart of the far-end mode.

[0072] Figure 4 is an implementation step flow chart of the near-end mode provided by the embodiment of the present application. DETAILED DESCRIPTION

[0073] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0074] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that when the terms "comprise" and / or "include" are used in the present specification, it means that the features, steps, operations, devices, components and / or their combinations exist.

[0075] Unless otherwise specifically stated, the relative arrangement of the components and steps, numerical expressions, and numerical values set forth in the various examples herein are not meant to limit the scope of the present application. It should also be understood that all the parts shown in the drawings are not necessarily drawn to scale. Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail, but should be considered as part of the description of the present application. In all the examples shown and discussed herein, any specific value should be interpreted as merely an example, and not as a limitation. Therefore, other examples of the example embodiments can have different values. It should be noted that similar reference numbers and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0076] In the description of the present application, it should be understood that the orientation words such as "front, back, up, down, left, right", "horizontal, vertical, perpendicular, horizontal" and "top, bottom" and the like indicate the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate and imply that the indicated device or element must have a specific orientation or be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the scope of protection of the present application: the orientation words "inner, outer" refer to the inner and outer relative to the contour of each component.

[0077] For purposes of the description hereinafter, spatial or directional terms, such as, for example, "above", "below", "upper", "lower", and the like, can be used with reference to the illustrated embodiment. Such terms are intended only to reflect relative positional relationships between the components or elements of the device, as illustrated in the drawings. It will be appreciated, however, that the spatial or directional terms are used herein for purposes of description and illustration only and do not limit the position of the device in use or operation. For example, if the device is inverted, then the components or elements described as above other components or elements would then be positioned below the other components or elements. Thus, the exemplary term "above" can encompass both a position above and a position below. The device can be otherwise positioned (rotated 90° or in another orientation), and the spatial or directional descriptions used herein interpreted accordingly.

[0078] In addition, it should be pointed out that the use of the terms "first", "second", and the like, to describe various elements is merely intended to differentiate one element from another, and the terms are not intended to signify relative importance or significance of the elements. Unless otherwise defined, the terms "comprise", "comprising", "comprises", "include", "including", "includes", "contain", "containing", "contains", "have", "having", "has", or the like, are used in this disclosure in their open-ended, conventional sense, that is, they are used to mean "including, but not limited to".

[0079] In the description of the present application, if the meaning of several is more than one, the meaning of multiple is more than two, greater than, less than, more than, etc. are understood as not including the number, above, below, within, etc. are understood as including the number. If it is described as first, second, it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the sequence of indicated technical features.

[0080] In the description of the present application, unless otherwise explicitly defined, the words "arrange", "install", "connect", etc. should be interpreted in a broad sense, and the person skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical solution.

[0081] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0082] In order to overcome the deficiencies in the prior art, the application provides an extended dual-port RAM communication device based on a PCIE bus and an implementation method, which communicates with a CPU through a PCIE bus and is connected with external equipment through an interface, so that the CPU can directly or indirectly read and write access to the dual-port RAM shared with the external equipment, and the dual-port RAM communication between the PCIE bus CPU and the external equipment is realized.

[0083] The extended dual-port RAM communication device based on the PCIE bus can be independently or in parallel operated in a far-end mode (referring to the external equipment arranging the dual-port RAM as a communication node, and the device performing dual-port RAM communication by accessing the dual-port RAM on the external equipment) and a near-end mode (referring to the external equipment not arranging the dual-port RAM as a communication node, and the external equipment performing dual-port RAM communication by accessing the dual-port RAM space of the device) through software setting.

[0084] The extended dual-port RAM communication device based on the PCIE bus supports physical connection with a dual-port RAM communication port of the external equipment through a plurality of types of interfaces (LVDS / M-LVDS / RS485 / TTL) that can be selected, and matches the electrical characteristics of the dual-port RAM communication physical port of the different external equipment.

[0085] The extended dual-port RAM communication device based on the PCIE bus can generate a square wave signal with a certain period, frequency and duty cycle through software and hardware setting and transmit the square wave signal to the CPU and the external equipment at both ends of the dual-port RAM communication, so that the CPU and the external equipment respectively perform read and write access to the dual-port RAM in the positive half cycle and the negative half cycle of the square wave signal, and the conflict caused by simultaneous read and write of the same address unit in the dual-port RAM by both sides is avoided.

[0086] The hardware architecture of the application is a PCIE bus extended dual-port RAM communication device based on FPGA, and the device hardware includes a programmable logic unit 100, a memory unit 200, an atomic clock unit 300, a port distribution unit 400, an interface level conversion unit 500, as shown in Figure 1 .

[0087] The programmable logic unit is composed of FPGA and configuration circuit, JTAG circuit, Flash circuit, clock circuit and reset circuit which are independently connected with the FPGA, wherein the FPGA is connected with a connector or a gold finger through a GTX port to build a PCIE bus physical link, is connected with a CPU through the PCIE bus, and performs bidirectional PCIE communication with the CPU.

[0088] The memory unit is composed of a group of DDR memories, and is connected with the FPGA of the programmable logic unit to perform temporary storage processing of data in the running process.

[0089] The atomic clock unit is based on a chip-level atomic clock, is connected with the FPGA of the programmable logic unit, outputs high-precision 10MHz and 1PPS pulse signals to the FPGA through an I / O interface, generates reference signals for time-sharing access of CPUs and external devices to the dual-port RAM, and communicates with the FPGA through a UART interface.

[0090] One end of the port allocation unit is connected with the FPGA of the programmable logic unit, and the other end is connected with the interface level conversion device, the I / O port of the FPGA is selectively connected with signal transmission links with different electrical characteristics through a hardware configuration mode.

[0091] One end of the interface level conversion unit is connected with the port allocation unit, and the other end is connected with external dual-port RAM communication devices through LVDS / M-LVDS / RS485 / 5V TTL / 3.3V TTL interfaces; the interface level conversion device is controlled by the FPGA to perform half-duplex signal transmission on a transmission path.

[0092] It should be noted that the CPU in the application is not an external device, but a host computer. The dual-port RAM communication device provided by the application can be simply understood as a PCIE expansion card in a computer, which can be compared with a graphics card.

[0093] It can be understood that the basis of dual-port RAM communication is that both sides of the communication parties access the dual-port RAM respectively to achieve data interaction, and the dual-port RAM can be contained in the FPGA of the device, or can not be on the device, but located in an external device. In the following, the dual-port RAM communication device provided by the application has a "remote mode" and a "near-end mode", wherein the remote mode is the working mechanism when the dual-port RAM is located in an external device, and the near-end mode is that the external device has no dual-port RAM, at this time, the dual-port RAM is constructed by the FPGA of the device, and the dual-port RAM is located in the FPGA of the device.

[0094] The FPGA of the programmable logic unit is a functional core of the application, which internally integrates various functional modules designed by the Verilog hardware description language, and mainly realizes PCIE communication with the CPU, double-port RAM communication with external devices and all logic control of the device; the functional modules designed by the Verilog hardware description language include UtilityBuffer 1, XDMA 2, AXI Interconnect 4, AXI SmartConnect 3, a first AXI BRAM controller 5, a second AXI BRAM controller 16, a remote mode BRAM 6, a near-end mode BRAM 17, a digital phase-locked loop 14, a data interaction module 7, a remote mode BRAM port control module 10, a remote mode read module 8, a remote mode write module 9, an external device double-port RAM port control module 11, an interrupt control module 12, an atomic clock communication module 15, a signal generation module 13, a near-end mode control module 18, a configuration module 19 and the like. Figure 2

[0095] It can be understood that the connection relationship shown in the accompanying drawings only represents part of the connection relationship of the modules in the FPGA, and some other possible connection relationships are not shown due to the limited space of the schematic diagram, that is, the module connection relationship in the accompanying drawings does not have any limiting effect on the data flow direction between the modules, and the application will not make special description on this. Figure 2 Figure 2 It can be understood that the connection relationship shown in the accompanying drawings only represents part of the connection relationship of the modules in the FPGA, and some other possible connection relationships are not shown due to the limited space of the schematic diagram, that is, the module connection relationship in the accompanying drawings does not have any limiting effect on the data flow direction between the modules, and the application will not make special description on this.

[0096] The Utility Buffer, XDMA, AXI SmartConnect and AXI Interconnect build a mapping channel of the PCIE bus to the AXI bus and AXI LITE bus on the FPGA chip; based on the channel, the CPU can read and write access the functional modules and IP cores on the AXI bus and AXI LITE bus through the corresponding base address and offset address, and realize data interaction.

[0097] The data interaction module is mounted on the AXI LITE bus, obtains the instructions and parameters issued by the CPU through the AXI interface register, controls the execution of the remote mode read module, the remote mode write module and the near-end mode control module according to the obtained instructions and parameters, and uploads the state parameters and other data of the execution process of the remote mode read module, the remote mode write module and the near-end mode control module to the CPU through the AXI interface register.

[0098] ​​The first AXI BRAM controller and the remote mode BRAM build on-chip storage space and CPU access entrance in the remote mode; one end of the first AXI BRAM controller is mounted on the AXI bus, and the other end is connected to the A port of the remote mode BRAM, and the CPU can read and write the remote mode BRAM through the A port of the remote mode BRAM, and the B port of the remote mode BRAM is connected to the remote mode BRAM port control module and other functional modules.

[0099] The remote mode read module, the remote mode write module, the remote mode BRAM port control module and the external device dual-port RAM port control module cooperate under the control of the data interaction module, and data is taken out from the remote mode BRAM through the B port of the remote mode BRAM and written into the dual-port RAM of the external device, or data is read out from the dual-port RAM of the external device and written into the remote mode BRAM through the B port of the remote mode BRAM.

[0100] The second AXI BRAM controller and the near-end mode BRAM build on-chip storage space and CPU access entrance in the near-end mode; one end of the second AXI BRAM controller is mounted on the AXI bus, and the other end is connected to the A port of the near-end mode BRAM, and the CPU can read and write the near-end mode BRAM through the A port of the near-end mode BRAM, and the B port of the near-end mode BRAM is connected to the near-end mode control module.

[0101] The near-end mode control module has one end connected to the external device and the other end connected to the B port of the near-end mode BRAM, and selects to write the data transmitted by the external device into the corresponding address unit of the near-end mode BRAM or to take out the data from the corresponding address unit of the near-end mode BRAM and send it to the data line connected to the external device by detecting whether the control line, address line and data line connected to the external device meet the read-write timing.

[0102] The atomic clock communication module communicates with the atomic clock through UART; the digital phase-locked loop receives the 10MHz and 1PPS pulse signals of the atomic clock and performs frequency multiplication, and the frequency-multiplied signals are transmitted to the signal generation module to generate square wave signals with certain frequency, period and duty cycle according to actual needs; the square wave signals notify the CPU in the form of interruption and are transmitted to the external dual-port RAM communication device through the external interface, and the two parties of the dual-port RAM communication respectively access the dual-port RAM in the positive half cycle and the negative half cycle of the square wave signals to avoid access conflict caused by simultaneous access to the same address unit in the dual-port RAM.

[0103] It should be noted that the dual-port RAM communication device refers to a device communicating through the dual-port RAM, and each dual-port RAM communication device accesses one side port of the dual-port RAM to realize data interaction; and the dual-port RAM refers to the dual-port RAM accessed by two end devices in dual-port RAM communication. Specifically, the two dual-port RAM communication devices perform data interaction by independently accessing one side port of the dual-port RAM, and realize dual-port RAM communication.

[0104] The interrupt control module is mounted on the AXI LITE bus, receives the interrupt source transmitted by the signal generation module, triggers the XDMA to generate an MSI interrupt to notify the CPU according to the interrupt source, and enables and clears the interrupt by writing the AXI interface register of the interrupt control module.

[0105] The application provides an implementation method of an extended dual-port RAM communication device based on a PCIE bus, which supports a far-end mode and a near-end mode. Figure 3 As shown in the figure, the method comprises the following steps:

[0106] Step 101: The CPU writes an enable interrupt command into the AXI interface register of the interrupt control module, and enters step 102.

[0107] Step 102: 10MHz and 1PPS signals transmitted by the atomic clock are received, and a square wave signal with a certain frequency, period and duty cycle is generated through a digital phase-locked loop and a signal generation module; the square wave signal is transmitted to an external device and is also transmitted to subsequent logic, and enters step 103.

[0108] Step 103: The rising edge of the square wave signal in step 2 is captured, and a trigger pulse is generated at each rising edge and is transmitted to the interrupt control module as an interrupt source, and enters step 104.

[0109] Step 104: When the trigger pulse in step 103 is received, the interrupt control module generates an interrupt trigger level, triggers the XDMA to generate an MSI interrupt to notify the CPU, and enters step 105.

[0110] Step 105: The CPU processes the interrupt, writes control signals and parameters into the AXI interface register of the data interaction module, the control signals and parameters comprising a write enable signal in the far-end mode, a target address range of writing the dual-port RAM of the external device in the far-end mode, a read enable signal in the far-end mode, a target address range of reading the dual-port RAM of the external device in the far-end mode, and writes target data of writing the dual-port RAM of the external device in the far-end mode into the far-end mode BRAM. After step 105 is completed, enter step 106.

[0111] Step 106: After the CPU finishes processing the interrupt, the AXI interface register of the interrupt control module is written with a clear interrupt command, and then the AXI interface register of the interrupt control module is written with an enable interrupt command again, and step 107 is entered.

[0112] Step 107: The AXI interface register of the data interaction module is polled, if the write enable signal in the remote mode is detected to be valid, a remote mode write operation program is entered, and step 108 is entered; if the read enable signal in the remote mode is detected to be valid, a remote mode read operation program is entered, and step 117 is entered.

[0113] Step 108: The remote mode write operation program is entered, the remote mode write module is executed, a remote mode write process flag bit is established, and step 109 is entered.

[0114] Step 109: During the validity of the remote mode write process flag bit, the remote mode write module obtains the control right of the dual-port RAM port of the FPGA accessing the external device and the access control right of the B port of the remote mode BRAM, and step 110 is entered.

[0115] Step 110: The start address and the end address of the target address range of the dual-port RAM of the external device in the remote mode are queried in the AXI interface register of the data interaction module, and step 111 is entered.

[0116] Step 111: The remote mode write action counter is enabled, and the start address of the target address range of the dual-port RAM of the external device in the remote mode is assigned to the remote mode write action counter, and step 112 is entered.

[0117] Step 112: It is judged whether the value of the remote mode write action counter is in the target address range of the dual-port RAM of the external device in the remote mode, if yes, step 113 is entered; otherwise, step 116 is entered.

[0118] Step 113: The data in the address unit of the remote mode BRAM equal to the value of the remote mode write action counter is read through the B port of the remote mode BRAM, and step 114 is entered.

[0119] Step 114: The data read from the remote mode BRAM is written into the address unit of the dual-port RAM of the external device equal to the value of the remote mode write action counter according to the time sequence, and step 115 is entered.

[0120] Step 115: The remote mode write action counter is incremented, and step 112 is entered.

[0121] Step 116: After all the data to be written in the remote mode writing operation is written into the corresponding address units of the external device dual-port RAM, the remote mode writing action counter is cleared, the remote mode writing module releases the control right of the FPGA accessing the external device dual-port RAM port and the access control right of the B port of the remote mode BRAM, clears the remote mode writing process flag bit, and enters step 107 to wait for the next execution.

[0122] Step 117: The remote mode reading operation program is entered, the remote mode reading module is executed, the remote mode reading process flag bit is established, and step 118 is entered.

[0123] Step 118: During the validity of the remote mode reading process flag bit, the remote mode reading module obtains the control right of the FPGA accessing the external device dual-port RAM port and the access control right of the B port of the remote mode BRAM, and enters step 119.

[0124] Step 119: The target address range start address and end address of reading the external device dual-port RAM in the remote mode are queried in the AXI interface register of the data interaction module, and step 120 is entered.

[0125] Step 120: The remote mode reading action counter is enabled, and the target address range start address of reading the external device dual-port RAM in the remote mode is assigned to the remote mode reading action counter, and step 121 is entered.

[0126] Step 121: It is judged whether the value of the remote mode reading action counter is in the target address range of reading the external device dual-port RAM in the remote mode, if yes, step 122 is entered, otherwise, step 125 is entered.

[0127] Step 122: The data in the address unit equal to the value of the remote mode reading action counter in the external device dual-port RAM is read according to the timing regulation, and step 123 is entered.

[0128] Step 123: The data read from the external device dual-port RAM is written into the address unit equal to the value of the remote mode reading action counter in the remote mode BRAM for the CPU to query, and step 124 is entered.

[0129] Step 124: The remote mode reading action counter is incremented, and step 121 is entered.

[0130] Step 125: After all the data to be read in the remote mode reading operation is read out from the external dual-port device RAM and written into the corresponding address units of the remote mode BRAM, the remote mode reading action counter is cleared, the remote mode reading module releases the control right of the FPGA accessing the external device dual-port RAM port and the access control right of the B port of the remote mode BRAM, clears the remote mode reading process flag bit, and enters step 107 to wait for the next execution.

[0131] The application provides an implementation method of an extended dual-port RAM communication device based on a PCIE bus, which supports a far-end mode and a near-end mode. Figure 4 As shown in the figure, the method comprises the following steps:

[0132] Step 201: write an enable near-end mode command to a configuration module, and enter step 202.

[0133] Step 202: write an enable interrupt command to an AXI interface register of an interrupt control module by a CPU, and enter step 203.

[0134] Step 203: receive 10MHz and 1PPS signals sent by an atomic clock, generate a square wave signal with certain frequency, period and duty cycle through a digital phase-locked loop and a signal generating module; the square wave signal is sent to an external device and is transmitted to subsequent logic, and the method enters step 204 and step 208.

[0135] Step 204: capture a rising edge of the square wave signal in step 203, and generate a trigger pulse at each rising edge, which is transmitted to the interrupt control module as an interrupt source, and the method enters step 205.

[0136] Step 205: when the trigger pulse in step 203 is received, the interrupt control module generates an interrupt trigger level, which triggers XDMA to generate an MSI interrupt to inform the CPU, and the method enters step 206.

[0137] Step 206: the CPU processes the interrupt, writes data to the near-end mode BRAM through an A port of the near-end mode BRAM, and the method enters step 207.

[0138] Step 207: after the CPU completes processing the interrupt, write a clear interrupt command to the AXI interface register of the interrupt control module, and then write an enable interrupt command to the AXI interface register of the interrupt control module again.

[0139] Step 208: cyclically detect the level and timing state of a dual-port RAM communication control line connected with the external device, if the state conforms to a dual-port RAM write timing, the method enters step 209; if the state conforms to a dual-port RAM read timing, the method enters step 214.

[0140] Step 209: enter a near-end mode write operation program, execute near-end mode write operation logic, and establish a near-end mode write process flag, and the method enters step 210.

[0141] Step 210: during the validity period of the near-end mode write process flag, the near-end mode write operation logic obtains access control of a B port of the near-end mode BRAM, and the method enters step 211.

[0142] Step 211: detecting the address line and data line of the dual-port RAM connected with the external device, obtaining the address and corresponding data that the external device in the near-end mode expects to write into the dual-port RAM, and entering step 212.

[0143] Step 212: writing the data obtained in step 211 into the corresponding address unit of the near-end mode BRAM through the B port of the near-end mode BRAM, and entering step 213.

[0144] Step 213: clearing the near-end mode write process flag, and entering step 208 to wait for the next operation.

[0145] Step 214: entering the near-end mode read operation program, executing the near-end mode read operation logic, establishing the near-end mode read process flag, and entering step 215.

[0146] Step 215: during the validity of the near-end mode read process flag, the near-end mode read operation logic obtains the access control right of the B port of the near-end mode BRAM, and enters step 216.

[0147] Step 216: detecting the address line of the dual-port RAM connected with the external device, obtaining the address that the external device in the near-end mode expects to read data from the dual-port RAM, and entering step 217.

[0148] Step 217: reading the data from the address unit corresponding to the address obtained in step 216 in the near-end mode BRAM through the B port of the near-end mode BRAM and sending the data to the data line of the dual-port RAM connected with the external device, and entering step 218.

[0149] Step 218: clearing the near-end mode read process flag, and entering step 208 to wait for the next operation.

[0150] It should be understood that each step of the above method embodiment can be completed by a logic circuit in the form of hardware in the processor or an instruction in the form of software.

[0151] It can be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. In addition, in some possible implementation manners, each step in the above embodiment can be selectively executed, partially executed, or fully executed according to actual conditions, which is not limited here.

[0152] It can be understood that the processor in the embodiments of the present application can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0153] The method steps in the embodiments of the present application can be realized by hardware or by the processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor, so that the processor can read information from and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC.

[0154] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in or transmitted by a computer readable storage medium. The computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through a wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)) and the like.

[0155] Those skilled in the art will readily understand that the above description is only preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A dual-port RAM communication device based on a PCIe bus, characterized in that, include: Programmable logic unit, memory unit, atomic clock unit, interface level conversion unit, and port allocation unit; The programmable logic unit includes an FPGA; the FPGA establishes a PCIe bus physical link by connecting to a connector or gold fingers through a GTX port, and connects to the CPU through the PCIe bus; the FPGA integrates multiple functional modules designed with the Verilog hardware description language to realize PCIe communication with the CPU through the PCIe bus and dual-port RAM communication with external devices. The memory unit includes a set of DDR memory; The memory unit is connected to the FPGA programmable logic unit to temporarily store data during FPGA operation; The atomic clock unit is built on a chip-level atomic clock and connected to the FPGA of the programmable logic unit. It outputs pulse signals to the FPGA through the I / O interface, generates reference signals for the CPU and external devices to access the dual-port RAM in a time-sharing manner, and communicates with the FPGA through the UART interface. The interface level conversion unit is connected to the port allocation unit at one end and to an external dual-port RAM communication device through various types of interfaces at the other end, providing signal transmission links that match different electrical characteristics; the interface level conversion unit is controlled by the FPGA of the programmable logic unit to perform half-duplex signal transmission on the transmission path; The port allocation unit is connected at one end to the FPGA of the programmable logic unit and at the other end to the interface level conversion unit. Through hardware configuration, it connects the I / O ports of the FPGA to signal transmission links with different electrical characteristics.

2. The apparatus according to claim 1, characterized in that, The functional modules designed using the Verilog hardware description language within the FPGA programmable logic unit include: Utility Buffer, XDMA, AXI Interconnect, AXI SmartConnect, first AXI BRAM controller, second AXI BRAM controller, remote mode BRAM, near-end mode BRAM, data interaction module, remote mode BRAM port control module, remote mode read module, remote mode write module, external device dual-port RAM port control module, near-end mode control module, and configuration module; The Utility Buffer, XDMA, AXI SmartConnect, and AXI Interconnect are used to construct a mapping channel from the PCIe bus to the on-chip AXI bus and AXI LITE bus of the FPGA; the mapping channel is used to enable the CPU to read and write access to the functional modules and IP cores on the AXI bus and AXI LITE bus; The data interaction module is mounted on the AXI LITE bus and is used to obtain instructions and parameters issued by the CPU through the AXI interface register. Based on the obtained instructions and parameters, it controls the execution of the remote mode read module, the remote mode write module, and the near mode control module, and uploads the status parameters of the execution process of the remote mode read module, the remote mode write module, and the near mode control module to the CPU through the AXI interface register. The first AXI BRAM controller and the remote mode BRAM are used to construct the on-chip storage space and CPU access entry in remote mode; one end of the first AXI BRAM controller is connected to the AXI bus, and the other end is connected to the A port of the remote mode BRAM. The CPU reads and writes the remote mode BRAM through the A port of the remote mode BRAM. The B port of the remote mode BRAM is used to connect to the remote mode BRAM port control module. The remote mode read module, remote mode write module, remote mode BRAM port control module, and external device dual-port RAM port control module work together to retrieve data from the remote mode BRAM and write it to the external device's dual-port RAM through the B port of the remote mode BRAM, or read data from the external device's dual-port RAM and write it to the remote mode BRAM through the B port of the remote mode BRAM, under the control of the data interaction module. The second AXI BRAM controller and the near-end mode BRAM are used to construct the on-chip storage space and CPU access entry in near-end mode; one end of the second AXI BRAM controller is connected to the AXI bus, and the other end is connected to the A port of the near-end mode BRAM. The CPU reads and writes the near-end mode BRAM through the A port of the near-end mode BRAM, and the B port of the near-end mode BRAM is connected to the near-end mode control module. The near-end mode control module is connected to an external device at one end and to the B port of the near-end mode BRAM at the other end. By detecting whether the control line, address line, and data line connected to the external device conform to the read / write timing, it selects to write the data transmitted by the external device into the corresponding address unit in the near-end mode BRAM, or to retrieve the data from the corresponding address unit in the near-end mode BRAM and send it to the data line connected to the external device.

3. The apparatus according to claim 2, characterized in that, The functional modules designed using the Verilog hardware description language within the FPGA of the programmable logic unit also include: an atomic clock communication module, a digital phase-locked loop, and a signal generation module. The atomic clock communication module communicates with the atomic clock via UART. The digital phase-locked loop receives the pulse signal from the atomic clock and multiplies it. The multiplied signal is then transmitted to the signal generation module, which generates a preset square wave signal as needed. The preset square wave signal is used to notify the CPU in the form of an interrupt and is transmitted to the external dual-port RAM communication device through an external interface. This allows both parties in the dual-port RAM communication to access the dual-port RAM during the positive and negative half-cycles of the preset square wave signal, thus avoiding access conflicts caused by both parties accessing the same address unit in the dual-port RAM simultaneously.

4. The apparatus according to claim 3, characterized in that, The functional modules designed using the Verilog hardware description language within the FPGA of the programmable logic unit also include: an interrupt control module; The interrupt control module is mounted on the AXI LITE bus and is used to receive interrupt sources transmitted by the signal generation module. Based on the interrupt source, the XDMA is triggered to generate an MSI interrupt to notify the CPU. The AXI interface register of the interrupt control module receives write operations from the CPU to enable and clear interrupts.

5. A method for implementing dual-port RAM communication based on the communication device according to any one of claims 1 to 4, characterized in that, Includes the following steps: The AXI interface register of the interrupt control module receives the interrupt enable command written by the CPU; The digital phase-locked loop receives the reference signal sent by the atomic clock, multiplies the frequency, and then transmits the multiplied reference signal to the signal generation module. The signal generation module generates a preset square wave signal based on the reference signal after frequency multiplication by the digital phase-locked loop, captures the rising edge of the preset square wave signal, and generates a trigger pulse at each rising edge, which is transmitted to the interrupt control module as an interrupt source. When the interrupt control module receives a trigger pulse, it generates an interrupt trigger level, which triggers the XDMA to generate an MSI interrupt to notify the CPU. The AXI interface register of the data interaction module receives control signals and parameters written by the CPU. The control signals and parameters include a write enable signal in remote mode, a target address range for writing to the external device dual-port RAM in remote mode, a read enable signal in remote mode, and a target address range for reading from the external device dual-port RAM in remote mode. The remote mode BRAM receives the target data written by the CPU for writing to the external device dual-port RAM in remote mode. The AXI interface register of the interrupt control module receives the write clear interrupt command sent by the CPU, and then receives the write enable interrupt command sent by the CPU. The data interaction module polls its internal AXI interface register. If it detects that the write enable signal in remote mode is valid, it enters the remote mode write operation program. The remote mode write module starts execution and establishes the remote mode write process flag bit. During the period when the remote mode write process flag is valid, the external device dual-port RAM port control module grants the remote mode write module FPGA control right to access the external device dual-port RAM port, and the remote mode BRAM port control module grants the remote mode write module control right to access the remote mode BRAM B port. The remote mode write module queries the AXI interface register inside the data interaction module to find the start and end addresses of the target address range for writing to the external device's dual-port RAM in remote mode. The remote mode write module enables its internal remote mode write action counter and assigns the starting address of the target address range for writing to the dual-port RAM of the external device in remote mode, which is queried from the AXI interface register of the data interaction module, to the remote mode write action counter. The remote mode write module determines whether the value of the remote mode write action counter is within the target address range for writing to the external device dual-port RAM in remote mode. If it is within the target address range, the remote mode write module accesses the B port of the remote mode BRAM through the remote mode BRAM port control module to read the data in the address unit in the remote mode BRAM that is equal to the value of the remote mode write action counter. The remote mode write module writes the data read from the remote mode BRAM into the address unit in the external device dual-port RAM that is equal to the value of the remote mode write action counter through the external device dual-port RAM port control module according to the timing rules. At the same time, it controls the remote mode write action counter to increment itself and continues to loop to determine whether the value of the write action counter is within the target address range for writing to the external device dual-port RAM and the subsequent operations.

6. The method according to claim 5, characterized in that, The process also includes the following steps: The remote mode write module determines whether the value of its internal remote mode write action counter is within the target address range for writing to the external device dual-port RAM in remote mode. If it is not within the target address range, after all the data to be written in the remote mode write operation is written to the corresponding address unit of the external device dual-port RAM, the remote mode write action counter is cleared to zero. The remote mode write module releases the FPGA's control over accessing the external device dual-port RAM port and the access control over the B port of the remote mode BRAM, clears the remote mode write process flag, and waits for the next operation.

7. The method according to claim 5, characterized in that, It also includes the following steps: The data interaction module polls its internal AXI interface register. If it detects that the read enable signal in remote mode is valid, it enters the remote mode read operation program, executes the remote mode read module, and establishes the remote mode read process flag bit. During the period when the remote mode read process flag is valid, the external device dual-port RAM port control module grants the remote mode read module FPGA control right to access the external device dual-port RAM port, and the remote mode BRAM port control module grants the remote mode read module control right to access the B port of the remote mode BRAM. The remote mode read module queries the AXI interface register inside the data interaction module to read the target address range, starting and ending addresses, of the external device dual-port RAM in remote mode. The remote mode read module enables its internal remote mode read action counter and assigns the starting address of the target address range for reading the external device dual-port RAM in remote mode, which is queried from the AXI interface register of the data interaction module, to the remote mode read action counter. The remote mode read module determines whether the value of the remote mode read action counter is within the target address range for reading the external device dual-port RAM in remote mode. If it is within the target address range, the remote mode read module reads data from the external device dual-port RAM at the address unit that matches the value of the remote mode read action counter according to the timing rules through the external device dual-port RAM port control module. The remote mode read module then writes the data read from the external device dual-port RAM into the address unit in the remote mode BRAM that matches the value of the remote mode read action counter through the remote mode BRAM port control module. This data is then queried by the CPU, which controls the remote mode read action counter to increment and continues to loop through the above process of determining whether the value of the remote mode read action counter is within the target address range for reading the external device dual-port RAM and performing subsequent operations.

8. The method according to claim 7, characterized in that, The process also includes the following steps: The remote mode read module determines whether the value of its internal remote mode read action counter is within the target address range for reading the external device dual-port RAM in remote mode. If it is not within the target address range, all the data to be read in the remote mode read operation is read from the external dual-port RAM and written to the corresponding address unit of the remote mode BRAM. After this is completed, the remote mode read action counter is cleared to zero, the remote mode read module releases the FPGA's control over accessing the external device dual-port RAM port and the access control over the B port of the remote mode BRAM, clears the remote mode read process flag, and waits for the next operation.

9. A method for implementing dual-port RAM communication based on the communication device according to any one of claims 1 to 4, characterized in that, Includes the following steps: The configuration module receives the command to enable near-end mode. The interrupt control module's AXI interface register receives the interrupt enable command written by the CPU. The digital phase-locked loop receives the reference signal sent by the atomic clock, multiplies the frequency, and then transmits the multiplied reference signal to the signal generation module. The signal generation module generates a preset square wave signal based on the reference signal after frequency multiplication by the digital phase-locked loop, captures the rising edge of the preset square wave signal, and generates a trigger pulse at each rising edge, which is transmitted to the interrupt control module as an interrupt source. When the interrupt control module receives a trigger pulse, it generates an interrupt trigger level, which triggers the XDMA to generate an MSI interrupt to notify the CPU. Port A of the near-end mode BRAM receives data written by the CPU to the near-end mode BRAM; The AXI interface register of the interrupt control module receives the write clear interrupt command sent by the CPU, and then receives the write enable interrupt command sent by the CPU. The near-end mode control module continuously detects the level and timing status of the control line of the dual-port RAM communication port connecting the FPGA and the external device. If the status matches the dual-port RAM write timing, it enters the near-end mode write operation program, executes the near-end mode write operation logic, and establishes the near-end mode write process flag bit. During the period when the near-end mode write process flag is valid, the near-end mode control module grants access control rights to the B port of the near-end mode BRAM to its internal near-end mode write operation logic. The near-end mode control module detects the address and data lines of the dual-port RAM communication port connecting the FPGA and the external device, and obtains the address and corresponding data that the external device expects to write to the dual-port RAM in near-end mode; The near-end mode write operation logic inside the near-end mode control module writes the acquired data into the corresponding address unit in the near-end mode BRAM through the B port of the near-end mode BRAM. The near-end mode control module clears the near-end mode write process flag and waits for the next operation.

10. The method according to claim 9, characterized in that, It also includes the following steps: The near-end mode control module continuously detects the level and timing status of the dual-port RAM communication control line connecting the FPGA and the external device. If the status matches the dual-port RAM read timing, it enters the near-end mode read operation program, executes the near-end mode read operation logic, and establishes the near-end mode read process flag bit. During the period when the near-end mode read process flag is valid, the near-end mode control module grants its internal near-end mode read operation logic access control to the B port of the near-end mode BRAM. The near-end mode control module detects the address lines of the dual-port RAM communication port connecting the FPGA and the external device, and obtains the address at which the external device expects to read data from the dual-port RAM in near-end mode; The near-end mode read operation logic inside the near-end mode control module reads data from the address unit corresponding to the read address in the near-end mode BRAM through the B port of the near-end mode BRAM and sends it to the data line of the dual-port RAM communication port connecting the FPGA and the external device. The near-end mode control module clears the near-end mode read process flag and waits for the next operation.

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