A voltage distribution method for dual-rail standard cell library

Abstract

This invention proposes a voltage allocation method for a dual-track standard cell library, comprising: a sensitivity-based coarse cell replacement, which calculates the replacement sensitivity of each cell based on its delay and power consumption, and replaces some high-voltage cells in the circuit with low-voltage cells in descending order of replacement sensitivity, resulting in a target chip where the estimated delay margin value for each path is the minimum positive value; and a path-based fine cell adjustment, which classifies each path and the cells in each path in the target chip, and then performs cell replacement adjustment, eliminating timing violations while further reducing the occurrence of low-voltage cells driving high-voltage cells, resulting in a target chip where the accurate delay margin value for each path is the minimum positive value, while minimizing circuit power consumption.

Description

Technical Field

[0001] This invention relates to the field of application-specific integrated circuit (ASIC) design, specifically to a voltage allocation method for a dual-track standard cell library. Background Technology

[0002] As process dimensions shrink and chip integration increases, the power consumption of a single transistor decreases, but the number of transistors per unit area increases dramatically. This causes the power consumption per unit area and the overall power consumption of integrated circuits to rise at an alarming rate. Higher power consumption per unit area means that chips will operate under higher temperatures, leading to a series of problems such as increased signal noise, mechanical cracking, enhanced chemical corrosion, and increased leakage current. Furthermore, the increased chip power consumption poses a serious challenge to the battery life of products. In recent years, with the rapid development of portable smart devices, such as smartphones, tablets, and smartwatches, these devices have become integrated into all aspects of people's lives. These products often use chips with advanced manufacturing processes, whose performance improves rapidly year by year. They are thin and light, and often powered by batteries. This places extremely high demands on device heat dissipation and battery life. Therefore, one way to improve device battery life and enhance market competitiveness is to reduce device power consumption.

[0003] In the past, all circuits used the same power supply voltage. However, with continuous advancements in technology, power supply voltages have decreased, and the emergence of multi-power supply voltage technology has provided designers with the possibility of reducing circuit power consumption. Multi-power supply voltage technology plays an increasingly important role in low-power design.

[0004] The principle of the dual-supply voltage method is that power is proportional to the square of voltage. Therefore, reducing the voltage can effectively reduce dynamic power consumption. However, since reducing the supply voltage increases delay and degrades circuit performance, low-voltage units must be used while ensuring timing convergence and meeting performance requirements. A typical dual-supply voltage method uses two standard units with different supply voltages: a high-voltage unit and a low-voltage unit. When a low-voltage unit drives a high-voltage unit, the high-voltage unit will generate leakage current. Therefore, when allocating units, the scenario of the low-voltage unit driving the high-voltage unit needs to be considered. Existing technologies such as CVS and ECVS allocate appropriate power to gates through a circuit with reverse topology level sequence from primary output to primary input, but they do not consider the impact of the increase in gate delay and the decrease in gate power consumption on the total delay and total power consumption after power allocation. In fact, for gates on different paths, the change in gate delay after power allocation is different, which affects the accuracy of power consumption optimization. Therefore, a low-power voltage allocation method that can improve the accuracy of power consumption optimization is needed to minimize circuit power consumption. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing low-power technologies by proposing a voltage allocation method for dual-track standard cell libraries.

[0006] To achieve this objective, the present invention proposes the following technical solution: A voltage allocation method for a dual-track standard cell library includes: firstly, performing a sensitivity-based coarse cell replacement on each dual-track standard cell in each path of the target chip to obtain a target chip where the estimated delay margin value for each path is the minimum positive value; then, performing a fine-tuning of the target chip based on path cell classification to eliminate the error caused by the coarse estimation of delay margin during the coarse replacement, thereby obtaining a target chip where the accurate delay margin value for each path is the minimum positive value, while simultaneously minimizing circuit power consumption.

[0007] Furthermore, the dual-track standard cell library consists of high-voltage (VDDH) standard cells and low-voltage (VDDL) standard cells. The VDDH standard cells and VDDL standard cells are connected to the same set of high and low voltage power lines. The PMOS source terminal and substrate terminal inside the VDDH standard cell are connected to the high-voltage power line for power supply, while the low-voltage power line is left floating. The PMOS source terminal inside the VDDL standard cell is connected to the low-voltage power line for power supply, while the substrate terminal is connected to the high-voltage power line for power supply.

[0008] Furthermore, the sensitivity-based coarse cell replacement includes the following steps:

[0009] S1: Use VDDH standard cells for logic synthesis to obtain a target chip with all VDDH cells, and generate a gate-level netlist of all VDDH cells, and then perform back-end placement and routing on the target chip.

[0010] S2: Perform static timing analysis on the target chip with all VDDH units to obtain the delay margin slack of all paths in the target chip, as well as the delay (VDDH) and power (VDDH) of each VDDH unit.

[0011] S3: Calculate the delay (VDDL) and power (VDDL) after each VDDH unit is replaced with the corresponding VDDL unit, and then calculate the replacement delay difference Δdelay, replacement power difference Δpower, and replacement sensitivity for each unit.

[0012] S4: Based on the target chip with all VDDH cells, arbitrarily select a path. First, sort all VDDH cells on the path in descending order of their corresponding replacement sensitivity. Then, replace the VDDH cells on the path with VDDL cells in sequence. After each cell replacement, obtain the path delay margin slack and the replacement delay difference Δdelay of the cell based on static timing analysis. Estimate and update the path delay margin slack. If the estimated value of the path delay margin slack is positive after the update, continue to replace the next VDDH cell. If the estimated value of the path delay margin slack is negative after the update, cancel the current VDDH cell replacement and end the coarse replacement of the path. After the coarse replacement of the path ends, mark all cells in the path as fixed.

[0013] S5: Switch to the next path that has not been coarsely replaced. First, based on the path delay margin slack obtained from the static timing analysis and the replacement delay difference Δdelay of the existing fixed state units in the path, estimate and update the path delay margin slack. Then, sort all non-fixed state VDDH units on the path in descending order of their corresponding replacement sensitivity.

[0014] S6: Replace the non-fixed VDDH cells in the path with VDDL cells in descending order of replacement sensitivity. After each cell replacement, continue to estimate and update the path delay margin slack based on the replacement delay difference Δdelay of the cell. If the estimated value of the path delay margin slack is positive, continue to replace the next VDDH cell. If the estimated value of the path delay margin slack is negative, cancel the current VDDH cell replacement and end the coarse replacement of the path. After completing the coarse replacement of the path, mark all non-fixed cells in the path as fixed.

[0015] S7: Based on whether there are still paths that have not been coarsely replaced, if yes, proceed to step S6; if no, the coarse replacement of the target chip's cells is completed, a coarse gate-level netlist is output, and all cells in the target chip are restored to a non-fixed state.

[0016] Furthermore, the calculation formulas for the delay (VDDL), power (VDDL), replacement delay difference Δdelay, replacement power difference Δpower, and replacement sensitivity in the sensitivity-based unit coarse replacement step S3 are as follows:

[0017] ;

[0018] ;

[0019] ;

[0020] ;

[0021] ;

[0022] Where α is the scaling factor, obtained from simulation fitting; VDDH is the high voltage power supply voltage value; VDDL is the low voltage power supply voltage value; and VTH is the threshold voltage of the transistor in the dual-rail standard cell library, obtained from the transistor simulation model or simulation provided by the process manufacturer.

[0023] Furthermore, the fine-tuning of the units based on path unit classification includes the following steps:

[0024] Step 1: Select any path that has not been fine-tuned, and use a static timing analysis tool to perform timing analysis on the path to obtain the accurate value of the delay margin of the path;

[0025] Step 2: If the exact value of the delay margin of the path is less than 0, it is a timing violation path and a type A replacement strategy is executed for it; if the exact value of the delay margin of the path is greater than 0, it is a timing compliant path and a type B replacement strategy is executed for it.

[0026] Step 3: After completing the fine-tuning of the path, mark all the units in the path as fixed, and no further replacement operations will be performed on the fixed units;

[0027] Step 4: Determine if there are any paths that have not been fine-tuned. If so, return to step 1; otherwise, the fine-tuning of the target chip's cells is complete, and the final gate-level netlist is output.

[0028] Furthermore, the execution of strategy type A includes the following steps:

[0029] Step 1: Divide the non-fixed state VDDL units in the A-class path into three categories: A1, A2, and A3. Among them, A1 is an isolated VDDL unit, that is, a VDDL unit whose preceding and following units are both VDDH units; A2 is a boundary VDDL unit, that is, a VDDL unit in which only one of the preceding or following units is a VDDH unit; and A3 is an intermediate VDDL unit, that is, a VDDL unit in which both the preceding and following units are VDDL units.

[0030] Step 2: Sort the non-fixed state VDDL units in the path in the order of A1, A2, A3, and sort them from low to high according to the power consumption difference Δpower of each unit replacement within each category.

[0031] Step 3: Replace the non-fixed-state VDDL units in the path with VDDH units in the order described in Step 2. After each replacement, perform static timing analysis again and update the delay margin accuracy value of the path. If the delay margin accuracy value is negative, continue to replace the next non-fixed-state VDDL; if the delay margin accuracy value is positive, end the fine-tuning of the path.

[0032] Furthermore, the B-type strategy includes the following steps:

[0033] Step 1: Divide the non-fixed state VDDH units in the B-class path into three categories: B1, B2, and B3. Among them, B1 is an isolated VDDH unit, that is, a VDDH unit whose preceding and following units are both VDDL units; B2 is a boundary VDDH unit, that is, a VDDH unit whose preceding or following unit is only one VDDL unit; and B3 is an intermediate VDDH unit, that is, a VDDH unit whose preceding and following units are both VDDH units.

[0034] Step 2: Sort the non-fixed state VDDH units in the path in the order of B1, B2, B3, and sort them from low to high within each category according to the replacement delay difference Δdelay.

[0035] Step 3: Replace the non-fixed-state VDDH units in the path with VDDL units in the order described in Step 2. After each replacement, perform static timing analysis again to update the accurate value of the delay margin of the path. If the accurate value of the delay margin is positive, continue to replace the next non-fixed-state VDDH unit; if the accurate value of the delay margin is negative, cancel the replacement of the VDDH unit and end the fine-tuning of the path.

[0036] The voltage allocation method for dual-track standard cell libraries proposed in this invention has the following advantages compared with existing technologies:

[0037] 1. The sensitivity-based coarse cell replacement method achieves rapid replacement by roughly calculating sensitivity, avoiding a large number of iterative iterations of time series analysis tools and saving time;

[0038] 2. The fine-tuning method of the cell based on path cell classification reduces the occurrence of low-voltage cells driving high-voltage cells, thereby reducing the additional leakage power consumption. Attached Figure Description

[0039] Figure 1 This invention presents a voltage allocation method for a dual-track standard cell library.

[0040] Figure 2 This paper compares the circuit structures of the dual-track standard unit proposed in this invention with those of the conventional standard unit. Detailed Implementation

[0041] The present invention will be further described in detail below with reference to the embodiments.

[0042] In this embodiment, as Figure 1 As shown, a comparison of the circuit structures of the dual-track standard unit proposed in this invention with those of conventional standard units reveals that the dual-track standard unit library consists of VDDH standard units and VDDL standard units. The VDDH standard units and VDDL standard units are connected to the same set of high and low voltage power lines. The PMOS source terminal and substrate terminal inside the VDDH standard unit are connected to the high voltage power line for power supply, while the low voltage power line is left floating. The PMOS source terminal inside the VDDL standard unit is connected to the low voltage power line for power supply, while the substrate terminal is connected to the high voltage power line for power supply.

[0043] In this embodiment, as Figure 2 As shown in the flowchart of the voltage allocation method for a dual-track standard cell library proposed in this invention, it can be seen that the voltage allocation method for a dual-track standard cell library proposed in this invention is carried out in two main steps: coarse cell replacement based on sensitivity and fine cell adjustment based on path cell classification.

[0044] In this embodiment, the sensitivity-based coarse cell replacement method calculates the replacement sensitivity of each cell based on its delay and power consumption. Then, it replaces some high-voltage cells with low-voltage cells in descending order of replacement sensitivity, completing the initial coarse allocation of cells of both high and low voltage types. The specific operation steps are as follows:

[0045] S1: Use VDDH standard cells for logic synthesis, select ASIC synthesis mode to obtain a target chip with all VDDH cells, and generate a gate-level netlist of all VDDH cells, and then perform back-end placement and routing on the target chip.

[0046] S2: Perform static timing analysis on the target chip with all VDDH units to obtain the delay margin slack of all paths in the target chip, as well as the delay (VDDH) and power (VDDH) of each VDDH unit.

[0047] S3: Calculate the delay (VDDL) and power (VDDL) after replacing each VDDH unit with the corresponding VDDL unit, and then calculate the replacement delay difference Δdelay, replacement power difference Δpower, and replacement sensitivity for each unit. The calculation formulas are as follows:

[0048] ;

[0049] ;

[0050] ;

[0051] ;

[0052] ;

[0053] Where α is the scaling factor, obtained from simulation fitting; VDDH is the high voltage power supply voltage value; VDDL is the low voltage power supply voltage value; VTH is the threshold voltage of the transistor in the dual-rail standard cell library, obtained from the transistor simulation model or simulation provided by the process manufacturer;

[0054] S4: For a target chip with all VDDH cells, arbitrarily select a path. First, sort all VDDH cells on that path in descending order of their corresponding replacement sensitivity. Then, replace the VDDH cells on that path with VDDL cells sequentially. After each cell replacement, obtain the path delay margin slack and the replacement delay difference Δdelay based on static timing analysis. Estimate and update the path delay margin slack as follows:

[0055] slack(new)=slack(old)-Δdelay

[0056] Where slack(old) is the delay margin before replacement; slack(new) is the delay margin after replacement; if the estimated delay margin slack for the path after the update is positive, then the replacement of the next VDDH unit continues; if the estimated delay margin slack for the path after the update is negative, then the current VDDH unit replacement is canceled, and the coarse replacement of the path ends. After the coarse replacement of the path ends, all units in the path are marked as fixed.

[0057] S5: Switch to the next path that has not undergone coarse replacement. First, based on the path delay margin slack obtained from static timing analysis and the replacement delay difference Δdelay of the existing fixed state units in the path, estimate and update the path delay margin slack as follows:

[0058] slack(new)=slack(old)-Δdelay

[0059] Where slack(old) is the delay margin before replacement; slack(new) is the delay margin after replacement;

[0060] Then, all VDDH units in non-fixed states along the path are sorted in descending order of their corresponding replacement sensitivity.

[0061] S6: Replace the non-fixed-state VDDH units with VDDL units sequentially in descending order of replacement sensitivity. After each unit replacement, estimate and update the path delay margin slack based on the replacement delay difference Δdelay of that unit. The method for estimating and updating the path delay margin slack is as follows:

[0062] slack(new)=slack(old)-Δdelay

[0063] Where slack(old) is the delay margin before replacement; slack(new) is the delay margin after replacement; if the estimated value of the delay margin slack for the path after the update is positive, then the replacement of the next VDDH unit continues; if the estimated value of the delay margin slack for the path after the update is negative, then the replacement of this VDDH unit is cancelled and the coarse replacement of the path ends. After the coarse replacement of the path is completed, all non-fixed state units in the path are marked as fixed state.

[0064] S8: Based on the judgment of whether there are still paths that have not been coarsely replaced, if yes, proceed to step S6; if no, the coarse replacement of the target chip's cells is completed, a coarse gate-level netlist is output, and all cells in the target chip are restored to a non-fixed state.

[0065] In this embodiment, the fine-tuning method based on path unit classification further optimizes the target chip. It classifies each path and unit within each path in the target chip, then performs unit replacement adjustments. This eliminates timing violations and further reduces the occurrence of low-voltage units driving high-voltage units, thereby reducing the additional leakage power consumption. The specific operation steps are as follows:

[0066] Step 1: Select any path that has not been fine-tuned, and use a static timing analysis tool to perform timing analysis on the path to obtain the accurate value of the delay margin of the path;

[0067] Step 2: If the exact value of the delay margin of the path is less than 0, it is a timing violation path and a type A replacement strategy is executed for it; if the exact value of the delay margin of the path is greater than 0, it is a timing compliant path and a type B replacement strategy is executed for it.

[0068] Step 3: After completing the fine-tuning of the path, mark all the units in the path as fixed, and no further replacement operations will be performed on the fixed units;

[0069] Step 4: Determine if there are any paths that have not been fine-tuned. If so, return to step 1; otherwise, the fine-tuning of the target chip's cells is complete, and the final gate-level netlist is output.

[0070] The specific steps for executing strategy A are as follows:

[0071] Step 1: Divide the non-fixed state VDDL units in the A-class path into three categories: A1, A2, and A3. Among them, A1 is an isolated VDDL unit, that is, a VDDL unit whose preceding and following units are both VDDH units; A2 is a boundary VDDL unit, that is, a VDDL unit in which only one of the preceding or following units is a VDDH unit; and A3 is an intermediate VDDL unit, that is, a VDDL unit in which both the preceding and following units are VDDL units.

[0072] Step 2: Sort the non-fixed state VDDL units in the path in the order of A1, A2, A3, and sort them from low to high according to the power consumption difference Δpower of each unit replacement within each category.

[0073] Step 3: Replace the non-fixed-state VDDL units in the path with VDDH units in the order described in Step 2. After each replacement, perform static timing analysis again and update the delay margin accuracy value of the path. If the delay margin accuracy value is negative, continue to replace the next non-fixed-state VDDL; if the delay margin accuracy value is positive, end the fine-tuning of the path.

[0074] The specific steps for executing strategy type B are as follows:

[0075] Step 1: Divide the non-fixed state VDDH units in the B-class path into three categories: B1, B2, and B3. Among them, B1 is an isolated VDDH unit, that is, a VDDH unit whose preceding and following units are both VDDL units; B2 is a boundary VDDH unit, that is, a VDDH unit whose preceding or following unit is only one VDDL unit; and B3 is an intermediate VDDH unit, that is, a VDDH unit whose preceding and following units are both VDDH units.

[0076] Step 2: Sort the non-fixed state VDDH units in the path in the order of B1, B2, B3, and sort them from low to high within each category according to the replacement delay difference Δdelay.

[0077] Step 3: Replace the non-fixed-state VDDH units in the path with VDDL units in the order described in Step 2. After each replacement, perform static timing analysis again to update the accurate value of the delay margin of the path. If the accurate value of the delay margin is positive, continue to replace the next non-fixed-state VDDH unit; if the accurate value of the delay margin is negative, cancel the replacement of the VDDH unit and end the fine-tuning of the path.

[0078] While the present invention has been described above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A voltage distribution method for a dual-rail standard cell library, characterized by, First, a sensitivity-based coarse cell replacement is performed on each dual-track standard cell on each path in the target chip to obtain a target chip where the estimated delay margin of each path is the minimum positive value. Then, a fine cell adjustment based on path cell classification is performed on the target chip to eliminate the error caused by the coarse estimation of delay margin during the coarse replacement, so as to obtain a target chip where the accurate delay margin value of each path is the minimum positive value, while minimizing circuit power consumption. The coarse replacement of the unit includes the following steps S1 to S7; S1: Use VDDH standard cells for logic synthesis to obtain a target chip with all VDDH cells, and generate a gate-level netlist of all VDDH cells, and then perform back-end placement and routing on the target chip. S2: Perform static timing analysis on the target chip with all VDDH units to obtain the delay margin slack of all paths in the target chip, as well as the delay (VDDH) and power (VDDH) of each VDDH unit. S3: Calculate the delay (VDDL) and power (VDDL) after each VDDH unit is replaced with the corresponding VDDL unit, and then calculate the replacement delay difference Δdelay, replacement power difference Δpower, and replacement sensitivity for each unit. S4: Based on the target chip with all VDDH cells, arbitrarily select a path. First, sort all VDDH cells on the path in descending order of their corresponding replacement sensitivity. Then, replace the VDDH cells on the path with VDDL cells in sequence. After each cell replacement, obtain the path delay margin slack and the replacement delay difference Δdelay of the cell based on static timing analysis. Estimate and update the path delay margin slack. If the estimated value of the path delay margin slack is positive after the update, continue to replace the next VDDH cell. If the estimated value of the path delay margin slack is negative after the update, cancel the current VDDH cell replacement and end the coarse replacement of the path. After the coarse replacement of the path ends, mark all cells in the path as fixed. S5: Switch to the next path that has not been coarsely replaced. First, based on the path delay margin slack obtained from the static timing analysis and the replacement delay difference Δdelay of the existing fixed state units in the path, estimate and update the path delay margin slack. Then, sort all non-fixed state VDDH units on the path in descending order of their corresponding replacement sensitivity. S6: Replace the non-fixed VDDH cells in the path with VDDL cells in descending order of replacement sensitivity. After each cell replacement, continue to estimate and update the path delay margin slack based on the replacement delay difference Δdelay of the cell. If the estimated value of the path delay margin slack is positive, continue to replace the next VDDH cell. If the estimated value of the path delay margin slack is negative, cancel the current VDDH cell replacement and end the coarse replacement of the path. After completing the coarse replacement of the path, mark all non-fixed cells in the path as fixed. S7: Based on whether there are still paths that have not been coarsely replaced, if yes, proceed to step S6; if no, the coarse replacement of the target chip's cells is completed, a coarse gate-level netlist is output, and all cells in the target chip are restored to a non-fixed state. Fine-tuning of the unit includes the following steps; Step 1: Select any path that has not been fine-tuned, and use a static timing analysis tool to perform timing analysis on the path to obtain the accurate value of the delay margin of the path; Step 2: If the exact value of the delay margin of the path is less than 0, it is a timing violation path and a type A replacement strategy is executed for it; if the exact value of the delay margin of the path is greater than 0, it is a timing compliant path and a type B replacement strategy is executed for it. Step 3: After completing the fine-tuning of the path, mark all the units in the path as fixed, and no further replacement operations will be performed on the fixed units; Step 4: Determine if there are any paths that have not been fine-tuned. If so, return to step 1; otherwise, the fine-tuning of the target chip's cells is complete, and the final gate-level netlist is output. The A-type strategy includes the following steps: Step 1: Divide the non-fixed state VDDL units in the A-class path into three categories: A1, A2, and A3. Among them, A1 is an isolated VDDL unit, that is, a VDDL unit whose preceding and following units are both VDDH units; A2 is a boundary VDDL unit, that is, a VDDL unit in which only one of the preceding or following units is a VDDH unit; and A3 is an intermediate VDDL unit, that is, a VDDL unit in which both the preceding and following units are VDDL units. Step 2: Sort the non-fixed state VDDL units in the path in the order of A1, A2, A3, and sort them from low to high according to the power consumption difference Δpower of each unit replacement within each category. Step 3: Replace the non-fixed-state VDDL units in the path with VDDH units in the order described in Step 2. After each replacement, perform static timing analysis again and update the delay margin accuracy value of the path. If the delay margin accuracy value is negative, continue to replace the next non-fixed-state VDDL; if the delay margin accuracy value is positive, end the fine-tuning of the path. The B-type strategy includes the following steps: Step 1: Divide the non-fixed state VDDH units in the B-class path into three categories: B1, B2, and B3. Among them, B1 is an isolated VDDH unit, that is, a VDDH unit whose preceding and following units are both VDDL units; B2 is a boundary VDDH unit, that is, a VDDH unit whose preceding or following unit is only one VDDL unit; and B3 is an intermediate VDDH unit, that is, a VDDH unit whose preceding and following units are both VDDH units. Step 2: Sort the non-fixed state VDDH units in the path in the order of B1, B2, B3, and sort them from low to high within each category according to the replacement delay difference Δdelay. Step 3: Replace the non-fixed-state VDDH units in the path with VDDL units in the order described in Step 2. After each replacement, perform static timing analysis again to update the accurate value of the delay margin of the path. If the accurate value of the delay margin is positive, continue to replace the next non-fixed-state VDDH unit; if the accurate value of the delay margin is negative, cancel the replacement of the VDDH unit and end the fine-tuning of the path.

2. The voltage allocation method for a dual-track standard cell library according to claim 1, characterized in that, The dual-track standard cell library consists of VDDH standard cells and VDDL standard cells. The VDDH standard cells and VDDL standard cells are connected to the same set of high and low voltage power lines. The PMOS source and substrate of the VDDH standard cell are connected to the high voltage power line for power supply, while the low voltage power line is left floating. The PMOS source of the VDDL standard cell is connected to the low voltage power line for power supply, while the substrate is connected to the high voltage power line for power supply.

3. The voltage allocation method for a dual-track standard cell library according to claim 1, characterized in that, The calculation formulas for delay (VDDL), power (VDDL), replacement delay difference Δdelay, replacement power difference Δpower, and replacement sensitivity in the sensitivity-based coarse replacement step S3 are as follows: ； ； ； ； ； in, VDDH is the scaling factor, obtained from simulation fitting; VDDL is the high-voltage power supply voltage; VTH is the threshold voltage of the transistor in the dual-rail standard cell library, obtained from the transistor simulation model or simulation provided by the process manufacturer.

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