Shift register, driving method and scan driving circuit

Abstract

The present invention provides a shift register, a driving method, and a scan drive circuit. The shift register includes: a first output module electrically connected to a first node, a first power supply voltage signal terminal, and an output terminal of the shift register; a first output control module electrically connected to a trigger signal input terminal, a first clock signal terminal, and a second node; a first coupling module electrically connected to the second node; and a first switch module electrically connected to the second node and the first node, respectively. In a low-level output phase, the first output control module transmits a conduction level to the second node, the first switch module is turned on, and the potential of the second node is lowered through the parasitic capacitance of the first switch module and / or the coupling effect of the first coupling module. The conduction level of the second node after being pulled down is transmitted to the first node, and the first output module is turned on to transmit a low-level voltage signal to the output terminal. The present invention can improve the G-direction horizontal stripes of a display panel and enhance the display effect.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular relates to a shift register, a driving method, and a scan driving circuit. Background Art

[0002] In the field of display technology, the pixel array of an organic light-emitting diode (OLED) display panel typically includes multiple rows of gate lines and multiple columns of data lines. For driving the gate lines, a scan drive circuit composed of multiple cascaded shift registers can be used to provide switching voltage signals to the multiple rows of gate lines, thereby controlling the multiple rows of gate lines to turn on in sequence.

[0003] However, the inventors of this application have discovered that the current scan driving circuit may cause poor display on the display panel when driving the display panel, such as horizontal stripes along the row direction (G direction) on the display panel. Summary of the Invention

[0004] The embodiments of the present application provide a shift register, a driving method, and a scan driving circuit, which can improve or even eliminate G-direction horizontal stripes on a display panel and enhance the display effect of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a shift register, which includes: a first output module, wherein the control end of the first output module is electrically connected to the first node, the first end of the first output module is electrically connected to the first power supply voltage signal end, and the second end of the first output module is electrically connected to the output end of the shift register; a first output control module, which is electrically connected to the trigger signal input end, the first clock signal end, and the second node; a first coupling module, wherein the first coupling module is electrically connected to the second node; a first switch module, wherein the control end of the first switch module and the first end of the first switch module are both electrically connected to the second node, and the second end of the first switch module is electrically connected to the first node. A node is electrically connected; in a low-level output stage, the first output control module transmits the conduction level of the trigger signal input terminal to the second node under the control of the first clock signal terminal, the first switch module is turned on in response to the conduction level of the second node, and the potential of the second node is pulled down by the coupling effect of the parasitic capacitance of the first switch module itself and / or the coupling effect of the first coupling module, and the conduction level of the second node after being pulled down is transmitted to the first node through the first switch module, and the first output module is turned on in response to the conduction level of the first node, and the low-level voltage signal of the first power supply voltage signal terminal is transmitted to the output terminal of the shift register.

[0006] According to the implementation of the first aspect of the present application, the shift register also includes a first potential adjustment module, the control end of the first potential adjustment module is electrically connected to the second node, the first end of the first potential adjustment module is electrically connected to the second clock signal end, and the second end of the first potential adjustment module is electrically connected to the third node; the first end of the first coupling module is electrically connected to the third node, and the second end of the first coupling module is electrically connected to the second node; in the low-level discharge maintenance stage before the low-level output stage, the second clock signal end is switched from the output cut-off level to the output on-level, the voltage value of the on-level is less than the voltage value of the cut-off level, the first potential adjustment module transmits the on-level of the second clock signal end to the third node, and the first coupling module responds to the potential change of the third node and pulls down the potential of the second node through coupling.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the shift register also includes a second potential adjustment module, the control end of the second potential adjustment module is electrically connected to the fourth node, the first end of the second potential adjustment module is electrically connected to the second power supply voltage signal end, and the second end of the second potential adjustment module is electrically connected to the third node; in the previous stage of the low-level discharge maintenance stage, the second potential adjustment module is turned on in response to the conduction level of the fourth node, and the high-level voltage signal of the second power supply voltage signal end is transmitted to the third node, and / or the first potential adjustment module is turned on in response to the conduction level of the second node, and the high-level voltage signal of the second clock signal end is transmitted to the third node.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, the first output control module includes a first protection unit and a discharge blocking unit; the control end of the first protection unit is electrically connected to the first clock signal end, the first end of the first protection unit is electrically connected to the trigger signal input end, and the second end of the first protection unit is electrically connected to the fifth node; the discharge blocking unit is connected between the fifth node and the second node; in the low-level output stage, the first protection unit and the discharge blocking unit are turned on, and the conduction level of the trigger signal input end is transmitted to the second node.

[0009] According to any of the aforementioned embodiments of the first aspect of the present application, the control end of the discharge blocking unit and the first end of the discharge blocking unit are both electrically connected to the fifth node, and the second end of the discharge blocking unit is electrically connected to the second node.

[0010] According to any of the aforementioned embodiments of the first aspect of the present application, the shift register also includes: a second output module, the control end of the second output module is electrically connected to the sixth node, the first end of the second output module is electrically connected to the second power supply voltage signal end, and the second end of the second output module is electrically connected to the output end of the shift register; a second output control module, electrically connected to the second power supply voltage signal end, the second clock signal end, the sixth node, the seventh node and the eighth node, the second output control module is used to turn on in response to the conduction level of the seventh node or the eighth node, and transmit the voltage signal of the second power supply voltage signal end or the second clock signal end to the sixth node.

[0011] According to any of the aforementioned embodiments of the first aspect of the present application, the second output control module includes a first output control unit, a second output control unit and a third output control unit, wherein: the control end of the first output control unit is electrically connected to the seventh node, the first end of the first output control unit is electrically connected to the second clock signal end, and the second end of the first output control unit is electrically connected to the ninth node; the control end of the second output control unit is electrically connected to the second clock signal end, the first end of the second output control unit is electrically connected to the ninth node, and the second end of the second output control unit is electrically connected to the sixth node; the control end of the third output control unit is electrically connected to the eighth node, the first end of the third output control unit is electrically connected to the second power supply voltage signal end, and the second end of the third output control unit is electrically connected to the sixth node.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, the shift register further includes: a first storage module, a first end of the first storage module is electrically connected to the second power supply voltage signal end, and a second end of the first storage module is electrically connected to the sixth node; a second coupling module, a first end of the second coupling module is electrically connected to the seventh node, and a second end of the second coupling module is electrically connected to the ninth node.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the shift register also includes: a first input module, the control end of the first input module is electrically connected to the first clock signal end, the first end of the first input module is electrically connected to the trigger signal input end, the second end of the first input module is electrically connected to the eighth node, and the eighth node is electrically connected to the first node; a second input module, the control end of the second input module is electrically connected to the first clock signal end, the first end of the second input module is electrically connected to the first power supply voltage signal end, the second end of the second input module is electrically connected to the fourth node, and the fourth node is electrically connected to the seventh node; a third output control module, the control end of the third output control module is electrically connected to the eighth node, the first end of the third output control module is electrically connected to the first clock signal end, and the second end of the third output control module is electrically connected to the fourth node.

[0014] According to any of the aforementioned embodiments of the first aspect of the present application, the shift register further includes: a second switch module, the control end of the second switch module is electrically connected to the first power supply voltage signal end, the first end of the second switch module is electrically connected to the eighth node, and the second end of the second switch module is electrically connected to the first node; a third switch module, the control end of the third switch module is electrically connected to the first power supply voltage signal end, the first end of the third switch module is electrically connected to the fourth node, and the second end of the third switch module is electrically connected to the seventh node.

[0015] In the second aspect, an embodiment of the present application provides a driving method, which is applied to a shift register as provided in the first aspect. The driving method includes: in a low-level output stage, providing a conduction level to the first clock signal terminal, and providing a conduction level to the trigger signal input terminal, so that the first output control module is turned on under the control of the first clock signal terminal, and the conduction level of the trigger signal input terminal is transmitted to the second node, and the coupling effect of the parasitic capacitance of the first switching module itself and / or the coupling effect of the first coupling module is used to pull down the potential of the second node. The conduction level of the second node after being pulled down is transmitted to the first node through the first switching module, and the first output module is turned on in response to the conduction level of the first node, and the low-level voltage signal of the first power supply voltage signal terminal is transmitted to the output terminal of the shift register.

[0016] According to any of the aforementioned embodiments of the second aspect of the present application, the shift register further includes a first input module, a second input module, a first potential adjustment module, a second potential adjustment module, a second output module, a second output control module, a third output control module, a first storage module, a second coupling module, a second switch module and a third switch module, the second output control module includes a first output control unit, a second output control unit and a third output control unit, the first output control module includes a first protection unit and a discharge blocking unit; before the low-level output stage, the driving method further includes: in the high-level writing stage, providing a conduction level to the first clock signal terminal, providing a conduction level to the trigger signal output The input end and the second clock signal end provide a cut-off level, the first input module and the second switch module are turned on, the eighth node and the first node are at the cut-off level, and the first output module is turned off; the sixth node maintains the cut-off level, the second output module is turned off, and the output end of the shift register maintains the voltage signal of the previous stage; the first protection unit is turned on, the fifth node is at the cut-off level, the discharge blocking unit is turned off, and the second node maintains the on level; in the high-level output stage, the eighth node and the first node are at the cut-off level, and the first output module is turned off; the sixth node is at the on level, the second output module is turned on, and the high-level voltage signal of the second power supply voltage signal end is transmitted to the output end of the shift register.

[0017] According to any of the aforementioned embodiments of the second aspect of the present application, before the high-potential writing stage, the driving method further includes: in the first discharge maintenance stage, providing a conduction level to the trigger signal input terminal and the first clock signal terminal, providing a cutoff level to the second clock signal terminal, the first input module is turned on under the control of the first clock signal terminal, the second switch module is turned on under the control of the first power supply voltage signal terminal, the eighth node and the first node are at the conduction level; the third output control unit is turned on, the sixth node is at the cutoff level, the second output module is turned off, and the output terminal of the shift register maintains an output low-level voltage signal; the first output control module is turned on, the second node is at the conduction level, the first potential adjustment module is turned on, and the third node is at the cutoff level; in the low-level discharge maintenance stage, the trigger is turned on. The signal input terminal and the second clock signal terminal provide a conduction level, and a cutoff level is provided to the first clock signal terminal. The eighth node maintains the conduction level, the sixth node maintains the cutoff level, and the second output module is turned off; the third output control module and the third switch module are turned on, the fourth node and the seventh node are at the cutoff level, and the second potential adjustment module and the first output control unit are turned off; the third node is switched from the cutoff level to the conduction level, and the coupling module responds to the potential change of the third node and pulls down the potential of the second node through coupling. The conduction level of the second node after being pulled down is transmitted to the first node through the first switch module, and the first output module is turned on in response to the conduction level of the first node, and the low-level voltage signal of the first power supply voltage signal terminal is transmitted to the output terminal of the shift register.

[0018] According to any of the aforementioned embodiments of the second aspect of the present application, the high-level output stage specifically includes a first high-level output stage, a second high-level output stage, and a third high-level output stage, wherein:

[0019] In the first high-level output stage, a conduction level is provided to the second clock signal terminal, an off-level is provided to the trigger signal input terminal and the first clock signal terminal, the eighth node and the first node maintain the off-level, and the first output module is turned off; the fourth node and the seventh node maintain the conduction level, the second coupling module pulls down the potential of the seventh node through coupling, the first output control unit and the second output control unit are turned on, the sixth node is at the conduction level, the second output module is turned on, and the high-level voltage signal of the second power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third node and the fifth node are at the off-level, and the second node maintains the conduction level;

[0020] In the second high-level output stage, a conduction level is provided to the first clock signal terminal, an off-level is provided to the trigger signal input terminal and the second clock signal terminal, the eighth node and the first node maintain the off-level, and the first output module is turned off; the second input module and the third switch module are turned on, the fourth node and the seventh node are at the conduction level, the first output control unit is turned on, the ninth node is at the off-level, the second output control unit is turned off, the sixth node maintains the conduction level, the second output module is turned on, and the high-level voltage signal at the second power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third node and the fifth node are at the off-level, and the second node maintains the conduction level;

[0021] In the third high-level output stage, a conduction level is provided to the trigger signal input terminal and the second clock signal terminal, and a cutoff level is provided to the first clock signal terminal, the eighth node and the first node maintain the cutoff level, and the first output module is turned off; the fourth node and the seventh node maintain the conduction level, the second coupling module lowers the potential of the seventh node through coupling, the first output control unit and the second output control unit are turned on, the sixth node is at the conduction level, the second output module is turned on, and the high-level voltage signal of the second power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third node and the fifth node are at the cutoff level, and the second node maintains the conduction level.

[0022] According to any of the aforementioned embodiments of the second aspect of the present application, after the low-level output stage, the driving method also includes: in the low-level maintenance output stage, providing a conduction level to the trigger signal input terminal and the second clock signal terminal, providing a cutoff level to the first clock signal terminal, the eighth node and the first node maintain the conduction level, the first output module is turned on, and the low-level voltage signal of the first power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third output control unit is turned on, the sixth node is at the cutoff level, and the second output module is turned off.

[0023] In a third aspect, an embodiment of the present application provides a scan driving circuit, which includes a plurality of cascaded shift registers as provided in the first aspect.

[0024] The shift register, driving method, and scan driving circuit of the embodiments of the present application provide a novel shift register circuit structure and corresponding driving timing. In a low-level output phase, the first output control module transmits the conduction level of the trigger signal input terminal to the second node under the control of the first clock signal terminal. The first switch module turns on in response to the conduction level of the second node. The potential of the second node is lowered through the coupling effect of the parasitic capacitance of the first switch module itself and / or the coupling effect of the first coupling module. The lowered conduction level of the second node is transmitted to the first node through the first switch module, thereby lowering the potential of the first node (i.e., the control terminal of the first output module) to a lower level, increasing the switching degree of the first output module. This results in a step-free waveform when the output terminal of the shift register switches to outputting a low-level voltage signal. The low-level voltage signal output by the output terminal of the shift register is no longer affected by the threshold voltage of the first output module. This can improve or even eliminate the problem of G-direction horizontal stripes on the display panel caused by inconsistent threshold voltages of the first output module, thereby improving the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 A schematic diagram of a waveform of a voltage signal output by a shift register in the related art;

[0027] Figure 2 A circuit diagram of a shift register provided in an embodiment of the present application;

[0028] Figure 3 Another circuit diagram of a shift register provided in an embodiment of the present application;

[0029] Figure 4 A further circuit diagram of a shift register provided in an embodiment of the present application;

[0030] Figure 5 A further circuit diagram of a shift register provided in an embodiment of the present application;

[0031] Figure 6 A further circuit diagram of a shift register provided in an embodiment of the present application;

[0032] Figure 7 A further circuit diagram of a shift register provided in an embodiment of the present application;

[0033] Figure 8A further circuit diagram of a shift register provided in an embodiment of the present application;

[0034] Figure 9 for Figure 8 A driving timing diagram corresponding to the shift register shown;

[0035] Figure 10 A schematic diagram of a process flow of a driving method provided in an embodiment of the present application;

[0036] Figure 11 A circuit diagram of a scan driving circuit provided in an embodiment of the present application;

[0037] Figure 12 A schematic structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0039] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0040] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0041] It should be noted that the transistors in the embodiments of the present application may be either N-type transistors or P-type transistors. The following description will be made using a P-type transistor as an example. For an N-type transistor, the on-level is a high level, and the off-level is a low level. That is, when the gate of the N-type transistor is at a high level, the first and second poles thereof are conductive, and when the gate of the N-type transistor is at a low level, the first and second poles thereof are disconnected. For a P-type transistor, the on-level is a low level, and the off-level is a high level. That is, when the control terminal of the P-type transistor is at a low level, the first and second poles thereof are conductive, and when the control terminal of the P-type transistor is at a high level, the first and second poles thereof are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and, depending on the signal of the gate of each transistor and its type, its first electrode can be used as the source and the second electrode as the drain, or its first electrode can be used as the drain and the second electrode as the source, without making any distinction here. In addition, the on-level and off-level in the embodiments of the present invention are both general terms, the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / off the transistor.

[0042] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0043] In the embodiment of the present application, the first node to the ninth node (collectively referred to as nodes) are defined only for the convenience of describing the circuit structure, and the first node to the ninth node are not actual circuit units.

[0044] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0045] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0046] With the development of OLED display technology, users have increasingly stringent requirements for the specifications of OLED display panels. For example, in terms of refresh rate, users are required to operate at a low refresh rate (such as 1Hz) to reduce the power consumption of display products.

[0047] Current OLED display panels include low-temperature polycrystalline silicon (LTPS) display panels. LTPS display panels, that is, pixel circuits in display panels, are all LTPS thin-film transistors. LTPS thin-film transistors (TFTs) can flow large currents and have good stability, but at the same time, LTPS thin-film transistors have large leakage currents, which makes it difficult for LTPS thin-film transistors that drive OLEDs to operate at low frequencies (such as 1Hz) while maintaining image quality. In order to achieve the function of low refresh frequency, the TFT connected to the storage capacitor can be designed as an oxide semiconductor TFT, such as indium gallium zinc oxide (IGZO) TFT. Because the drain electrode of IGZO TFT is low, it can usually reduce leakage current by three orders of magnitude compared to conventional P-type LTPS TFTs. This display panel that includes both LTPS TFTs and IGZO TFTs in the pixel circuit is called an LTPO display panel.

[0048] Figure 1 FIG. 1 is a waveform diagram of a voltage signal output by a shift register in the related art. Figure 1 As shown, a step waveform appears when the shift register switches to outputting a low-level voltage signal. The voltage value corresponding to the step waveform is related to the threshold voltage Vth of the transistor in the shift register that outputs the low-level voltage signal (referred to as the output transistor). For example, the theoretical voltage value of the step waveform is: VGL'-2*Vth. Where VGL' represents the voltage value of the first power supply voltage signal output by the first power supply voltage signal terminal.

[0049] Continue to see Figure 1 The threshold voltages (Vth) of output transistors at different locations on the display panel may vary, resulting in different voltage values ​​for the step waveforms output by the shift registers at different locations. When the threshold voltages (Vth) of the output transistors fluctuate in the row scanning direction, this can lead to differences in brightness across different rows, resulting in G-direction horizontal stripes on the display panel and poor display quality.

[0050] In view of the above research findings of the inventors, the embodiments of the present application provide a shift register, a driving method and a scan driving circuit. The shift register, the driving method and the scan driving circuit provided in the embodiments of the present application can be applied to LTPS display panels, as well as to LTPO display panels, and in particular can be used to drive IGZO TFTs.

[0051] The technical concept of the embodiments of the present application is to provide a new circuit structure of a shift register and a corresponding driving timing. In the low-level output stage, the first output control module transmits the conduction level of the trigger signal input terminal to the second node under the control of the first clock signal terminal. The first switch module is turned on in response to the conduction level of the second node. The potential of the second node is lowered through the coupling effect of the parasitic capacitance of the first switch module itself and / or the coupling effect of the first coupling module. The conduction level of the second node after being lowered is transmitted to the first node through the first switch module, thereby lowering the potential of the first node (i.e., the control terminal of the first output module) to a lower level, increasing the switching degree of the first output module, and thus ensuring that the output terminal of the shift register switches to outputting a low-level voltage signal without a step waveform. The low-level voltage signal output by the output terminal of the shift register is no longer affected by the threshold voltage of the first output module. In this way, the problem of G-direction horizontal stripes on the display panel caused by inconsistent threshold voltages of the first output module can be improved or even eliminated, thereby improving the display effect of the display panel.

[0052] The following first introduces the shift register provided in the embodiment of the present application.

[0053] Figure 2 A circuit diagram of a shift register provided in an embodiment of the present application. Figure 2 As shown, the shift register 20 may include a first output module 201 , a first output control module 202 , a first coupling module 203 and a first switch module 204 .

[0054] The control terminal of the first output module 201 is electrically connected to the first node N1, the first terminal of the first output module 201 is electrically connected to the first power supply voltage signal terminal VGL, and the second terminal of the first output module 201 is electrically connected to the output terminal OUT of the shift register 20. The first power supply voltage signal terminal VGL can be a negative power supply voltage signal terminal, that is, it can output a negative power supply voltage signal.

[0055] The first output control module 202 is electrically connected to the trigger signal input terminal SIN, the first clock signal terminal SCK1 and the second node N2. The first output control module 202 can be used to adjust the potential of the second node N2.

[0056] The first coupling module 203 may be electrically connected to the second node N2 , and the first coupling module 203 may lower the potential of the second node N2 through its own coupling effect.

[0057] The control terminal of the first switch module 204 and the first terminal of the first switch module 204 can both be electrically connected to the second node N2, and the second terminal of the first switch module 204 is electrically connected to the first node N1. The first switch module 204 can be turned on under the control of the second node N2, and write the electrical signal of the second node N2 to the first node N1, thereby regulating the potential of the first node N1.

[0058] In the low-level output stage, the first output control module 202 can transmit the conduction level (e.g., low level) of the trigger signal input terminal SIN to the second node N2 under the control of the first clock signal terminal SCK1. Since the second node N2 is at the conduction level, the first switch module 204 is turned on in response to the conduction level of the second node N2. In some examples, the potential of the second node N2 can be pulled to a lower level by the coupling effect of the first coupling module 203 itself. In other examples, such as Figure 2 As shown, the first switch module 204 forms a parasitic capacitor Cx between its control terminal and the first node N1. In the previous stage of the low-level output phase, the first node N1 is at the cut-off level (i.e., high potential). When the first node N1 switches from a high potential to a low potential in the low-level output phase, the potential of the second node N2 can be pulled down by the coupling effect of the parasitic capacitor Cx. The conduction level after the second node N2 is pulled down is transmitted to the first node N1 through the first switch module 204, so that the potential of the first node N1 (i.e., the control terminal of the first output module 201) is pulled down to a lower level. The first output module 204 is turned on in response to the conduction level of the first node N1, and transmits the low-level voltage signal of the first power supply voltage signal terminal VGL to the output terminal OUT of the shift register 20, thereby causing the output terminal OUT of the shift register 20 to output a low-level voltage signal.

[0059] Through the cooperation of the first output control module 202, the first coupling module 203, and the first switching module 204, the potential of the first node N1 (i.e., the control end of the first output module 201) can be pulled down to a relatively low level, thereby increasing the switching degree of the first output module 201. This results in a step-free waveform when the output end of the shift register switches to outputting a low-level voltage signal. This ensures that the low-level voltage signal outputted by the output end of the shift register is no longer affected by the threshold voltage Vth of the first output module 201. This can improve or even eliminate the G-direction horizontal stripes on the display panel caused by inconsistent threshold voltage Vth of the first output module 201, thereby improving the display quality of the display panel.

[0060] Continue to see Figure 2According to some embodiments of the present application, the first end of the first coupling module 203 can optionally be electrically connected to the potential-changing terminal VB, and the second end of the first coupling module 203 can be electrically connected to the second node N2. During the low-level output phase, the voltage value of the electrical signal output by the potential-changing terminal VB can jump from high to low, i.e., the voltage value decreases. Because the potential of the first end of the first coupling module 203 jumps to a low level, the coupling effect of the first coupling module 203 can lower the potential of the second node N2. The conduction level of the second node N2 after being lowered is transmitted to the first node N1 via the first switching module 204, causing the potential of the first node N1 to be lowered to a lower level.

[0061] Figure 3 Another circuit diagram of the shift register provided in the embodiment of the present application. Figure 3 As shown, in some specific embodiments, the shift register 20 may optionally further include a first potential regulating module 301. A control terminal of the first potential regulating module 301 is electrically connected to the second node N2, a first terminal of the first potential regulating module 301 is electrically connected to the second clock signal terminal SCK2, and a second terminal of the first potential regulating module 301 is electrically connected to the third node N3. The first potential regulating module 301 can be used to regulate the potential of the third node N3. A first terminal of the first coupling module 203 is electrically connected to the third node N3, and a second terminal of the first coupling module 203 is electrically connected to the second node N2.

[0062] The low-level output stage may also include a low-level discharge maintenance stage. During the low-level discharge maintenance stage, the second clock signal terminal SCK2 switches from outputting a cutoff level to outputting a conduction level, wherein the voltage value of the conduction level is less than the voltage value of the cutoff level. That is, the voltage value of the second clock signal output by the second clock signal terminal SCK2 changes from high to low. The first potential adjustment module 301 is turned on in response to the conduction level of the second node N2. The first potential adjustment module 301 transmits the conduction level of the second clock signal terminal SCK2 to the third node N3. The potential of the third node N3 changes from high to low. In response to the potential change of the third node N3, the first coupling module 203 pulls down the potential of the second node N2 through its own coupling action.

[0063] In this way, by adding the first potential regulating module 301, in the low-level discharge maintenance stage, the potential of the third node N3 is adjusted by the first potential regulating module 301, and the coupling effect of the first coupling module 203 can pull down the potential of the second node N2, thereby pulling down the potential of the first node N1 to a lower level, so that the voltage value of the low-level voltage signal output from the output end of the shift register is lower, that is, the output low-level voltage signal is more sufficient.

[0064] Similarly, in other embodiments of the present application, during the low-level output phase, the voltage value of the second clock signal outputted by the second clock signal terminal SCK2 can be controlled to jump from high to low, and the potential of the second node N2 can be pulled down by the coupling effect of the first coupling module 203 or the coupling effect of the parasitic capacitance of the first switching module itself, thereby pulling down the potential of the first node N1 to a lower level. In this way, the output terminal of the shift register can be switched to output a low-level voltage signal without a step waveform, so that the low-level voltage signal outputted by the output terminal of the shift register is no longer affected by the threshold voltage Vth of the first output module 201. This can improve or even eliminate the problem of G-direction horizontal stripes on the display panel caused by the inconsistent threshold voltage Vth of the first output module 201, thereby improving the display effect of the display panel.

[0065] Of course, in some other embodiments of the present application, the second clock signal terminal SCK2 connected to the first end of the first potential adjustment module 301 can also be replaced with other signal terminals, such as other clock signal terminals. In the low-level output stage, the voltage value output by the replaced signal terminal jumps from high to low, so that the coupling effect of the first coupling module 203 or the coupling effect of the parasitic capacitance of the first switching module itself can be used to pull down the potential of the second node N2, thereby lowering the potential of the first node N1 to a lower level, improving or even eliminating the problem of G-direction horizontal stripes on the display panel caused by the inconsistent threshold voltage Vth of the first output module 201, thereby improving the display effect of the display panel.

[0066] Continue to see Figure 3 In some specific embodiments, the shift register 20 may optionally further include a second potential regulating module 302. A control terminal of the second potential regulating module 302 may be electrically connected to the fourth node N4, a first terminal of the second potential regulating module 302 may be electrically connected to the second power supply voltage signal terminal VGH, and a second terminal of the second potential regulating module 302 may be electrically connected to the third node N3.

[0067] In the preceding phase of the low-level discharge sustain phase, the second potential regulating module 302 may be turned on in response to the conduction level of the fourth node N4, transmitting the high-level voltage signal of the second power supply voltage signal terminal VGH to the third node N3. That is, in the preceding phase of the low-level discharge sustain phase, the high-level voltage signal of the second power supply voltage signal terminal VGH may be transmitted to the third node N3, causing the third node N3 to be at a high potential. And / or, in the preceding phase of the low-level discharge sustain phase, the first potential regulating module 301 may be turned on in response to the conduction level of the second node N2, transmitting the high-level voltage signal of the second clock signal terminal SCK2 to the third node N3. Thus, in the preceding phase of the low-level discharge sustain phase, the high-level voltage signal of the second power supply voltage signal terminal VGH and / or the second clock signal terminal SCK2 is transmitted to the third node N3, causing the third node N3 to be at a high potential.

[0068] Thus, during the low-level discharge sustain phase, as the voltage of the second clock signal output by the second clock signal terminal SCK2 drops from high to low, the potential of the third node N3 drops from high to low. Under the coupling action of the first coupling module 203, the potential of the second node N2 is pulled down, for example, to VGL'-3*Vth-VGH'. Wherein, VGL' represents the voltage value of the conduction-level voltage signal output by the first power supply voltage signal terminal VGL, Vth represents the threshold voltage of the first output module 201, and VGH' represents the voltage value of the high-level voltage signal output by the second power supply voltage signal terminal VGH. The conduction level of the second node N2 after being pulled down is transmitted to the first node N1 via the first switch module 204, causing the potential of the first node N1 to be pulled down to a lower level, for example, to VGL'-4*Vth-VGH'. In this way, the switching degree of the first output module 201 can be increased, so that the voltage value of the on-level voltage signal (low-level voltage signal) output by the first output module 201 is equal to or approximately equal to VGL' without a step waveform, thereby improving or even eliminating the problem of G-direction horizontal stripes on the display panel caused by inconsistent threshold voltage Vth of the first output module 201, thereby improving the display effect of the display panel.

[0069] Figure 4 This is another circuit diagram of a shift register provided in an embodiment of the present application. Figure 4As shown, according to some embodiments of the present application, optionally, the first output control module 202 may include a first protection unit 401 and a discharge blocking unit 402. The control end of the first protection unit 401 is electrically connected to the first clock signal end SCK1, the first end of the first protection unit 401 is electrically connected to the trigger signal input end SIN, and the second end of the first protection unit 401 is electrically connected to the fifth node N5. The discharge blocking unit 402 is connected between the fifth node N5 and the second node N2. The advantage of setting the discharge blocking unit 402 is that the function of the discharge blocking unit 402 is similar to that of a diode, that is, it has a unidirectional conduction function and can block Figure 4 The current in the direction indicated by the middle arrow passes through, which prevents the second node N2 from discharging to the trigger signal input terminal SIN, so that the second node N2 can continue to maintain a low potential.

[0070] The advantage of providing the first protection unit 401 is that, because the potential of the trigger signal input terminal SIN continuously changes, if the discharge blocking unit 402 is directly connected to the trigger signal input terminal SIN, the potential at one end of the discharge blocking unit 402 will also continuously change, thereby affecting the performance and lifespan of the discharge blocking unit 402. However, after adding the first protection unit 401, the first protection unit 401 is turned on only when the first clock signal terminal SCK1 outputs a conductive level, thereby reducing the potential change at one end of the discharge blocking unit 402 and improving the lifespan and performance of the discharge blocking unit 402.

[0071] In the low-level output stage, both the first protection unit 401 and the discharge blocking unit 402 may be turned on, thereby transmitting the on-level of the trigger signal input terminal SIN to the second node N2 .

[0072] Continue to see Figure 4 In some specific embodiments, the discharge blocking unit 402 can optionally be a switching device, such as a thin film transistor. The control terminal of the discharge blocking unit 402 and the first terminal of the discharge blocking unit 402 can be connected to each other, so that the discharge blocking unit 402 forms a diode structure. Specifically, the control terminal of the discharge blocking unit 402 and the first terminal of the discharge blocking unit 402 can both be electrically connected to the fifth node N5, and the second terminal of the discharge blocking unit 402 can be electrically connected to the second node N2.

[0073] In this way, the control end of the discharge blocking unit 402 and the first end of the discharge blocking unit 402 are connected to each other, so that the discharge blocking unit 402 forms a diode structure, which can prevent the second node N2 from discharging to the trigger signal input terminal SIN, so that the second node N2 can continue to maintain a low potential.

[0074] Figure 5 This is another circuit diagram of a shift register provided in an embodiment of the present application. Figure 5 As shown, according to some embodiments of the present application, optionally, the shift register 20 may further include a second output module 501 and a second output control module 502 .

[0075] The control terminal of the second output module 501 can be electrically connected to the sixth node N6, the first terminal of the second output module 501 can be electrically connected to the second power supply voltage signal terminal VGH, and the second terminal of the second output module 501 can be electrically connected to the output terminal OUT of the shift register 20. In the high-level voltage signal output stage, the second output module 501 can be turned on under the control of the sixth node N6, and transmit the high-level voltage signal (i.e., the high-level voltage signal) of the second power supply voltage signal terminal VGH to the output terminal OUT of the shift register 20, so that the output terminal OUT of the shift register 20 can output the high-level voltage signal.

[0076] The second output control module 502 is electrically connected to the second power supply voltage signal terminal VGH, the second clock signal terminal SCK2, the sixth node N6, the seventh node N7, and the eighth node N8. The second output control module 502 can be turned on in response to the on-levels of the seventh node N7 and the second clock signal terminal SCK2, transmitting the voltage signal of the second clock signal terminal SCK2 to the sixth node N6. Furthermore, the second output control module 502 can be turned on in response to the on-level of the eighth node N8, transmitting the voltage signal of the second power supply voltage signal terminal VGH to the sixth node N6. The second output control module 502 can be used to adjust the potential of the sixth node N6.

[0077] In the low-level output stage, the second output control module 502 can be turned on in response to the on-level of the eighth node N8, transmitting the high-level voltage signal of the second power supply voltage signal terminal VGH to the sixth node N6, so that the sixth node N6 is at the off-level. The second output module 501 is turned off in response to the off-level of the sixth node N6, thereby ensuring that the output terminal OUT of the shift register 20 can well output a low-level voltage signal.

[0078] Continue to see Figure 5 According to some embodiments of the present application, optionally, the second output control module 502 may include a first output control unit 5021, a second output control unit 5022, and a third output control unit 5023, wherein:

[0079] The control end of the first output control unit 5021 is electrically connected to the seventh node N7, the first end of the first output control unit 5021 is electrically connected to the second clock signal end SCK2, and the second end of the first output control unit 5021 is electrically connected to the ninth node N9.

[0080] The control end of the second output control unit 5022 is electrically connected to the second clock signal end SCK2, the first end of the second output control unit 5022 is electrically connected to the ninth node N9, and the second end of the second output control unit 5022 is electrically connected to the sixth node N6.

[0081] The first output control unit 5021 can be turned on under the control of the seventh node N7, and the second output control unit 5022 can be turned on under the control of the second clock signal terminal SCK2. The clock signal provided by the second clock signal terminal SCK2 can be transmitted to the sixth node N6 through the turned-on first output control unit 5021 and the turned-on second output control unit 5022, thereby adjusting the potential of the sixth node N6.

[0082] A control terminal of the third output control unit 5023 is electrically connected to the eighth node N8, a first terminal of the third output control unit 5023 is electrically connected to the second power supply voltage signal terminal VGH, and a second terminal of the third output control unit 5023 is electrically connected to the sixth node N6. The third output control unit 5023 can be turned on under the control of the eighth node N8 to transmit the high-level voltage signal of the second power supply voltage signal terminal VGH to the sixth node N6, thereby adjusting the potential of the sixth node N6.

[0083] For example, in the low-level output stage, the third output control unit 5023 can be turned on under the control of the eighth node N8, and transmit the high-level voltage signal of the second power supply voltage signal terminal VGH to the sixth node N6, so that the sixth node N6 is at the cut-off level, thereby turning off the second output module 501.

[0084] Figure 6 This is another circuit diagram of a shift register provided in an embodiment of the present application. Figure 6 As shown, according to some embodiments of the present application, optionally, the shift register 20 may further include a first storage module 601. A first end of the first storage module 601 may be electrically connected to the second power supply voltage signal terminal VGH, and a second end of the first storage module 601 may be electrically connected to the sixth node N6. The first storage module 601 may be used to maintain the potential of the sixth node N6. For example, in a high-level output phase, the first storage module 601 may maintain the potential of the sixth node N6 to effectively prevent the sixth node N6 from being repeatedly written to a conduction level, thereby reducing power consumption.

[0085] Continue to see Figure 6According to some embodiments of the present application, the shift register 20 may optionally further include a second coupling module 602, wherein a first end of the second coupling module 602 is electrically connected to the seventh node N7, and a second end of the second coupling module 602 is electrically connected to the ninth node N9. The second coupling module 602 can lower the potential of the seventh node N7 through coupling, thereby enabling the second output control unit 5022 to be more completely turned on, thereby enabling the potential of the ninth node N9 to be equal to or approximately equal to the voltage value of the clock signal provided by the second clock signal terminal SCK2.

[0086] Figure 7 This is another circuit diagram of a shift register provided in an embodiment of the present application. Figure 7 As shown, according to some embodiments of the present application, optionally, the shift register 20 may further include a first input module 701 , a second input module 702 and a third output control module 703 .

[0087] The control terminal of the first input module 701 can be electrically connected to the first clock signal terminal SCK1, the first terminal of the first input module 701 can be electrically connected to the trigger signal input terminal SIN, and the second terminal of the first input module 701 can be electrically connected to the eighth node N8, and the eighth node N8 is electrically connected to the first node N1. Under the control of the first clock signal terminal SCK1, the first input module 701 can be turned on to transmit the voltage signal of the trigger signal input terminal SIN to the eighth node N8 to achieve potential adjustment of the eighth node N8. Since the eighth node N8 is electrically connected to the first node N1, the potential of the first node N1 can also be adjusted.

[0088] The control terminal of the second input module 702 is electrically connected to the first clock signal terminal SCK1. The first terminal of the second input module 702 is electrically connected to the first power supply voltage signal terminal VGL. The second terminal of the second input module 702 is electrically connected to the fourth node N4, and the fourth node N4 is electrically connected to the seventh node N7. The second input module 702 can be turned on under the control of the first clock signal terminal SCK1 and transmit the conduction level voltage signal of the first power supply voltage signal terminal VGL to the fourth node N4 to adjust the potential of the fourth node N4. Since the fourth node N4 is electrically connected to the seventh node N7, the potential of the seventh node N7 can also be adjusted.

[0089] A control terminal of the third output control module 703 is electrically connected to the eighth node N8, a first terminal of the third output control module 703 is electrically connected to the first clock signal terminal SCK1, and a second terminal of the third output control module 703 is electrically connected to the fourth node N4. The third output control module 703 can be turned on under the control of the eighth node N8 to transmit the clock signal of the first clock signal terminal SCK1 to the fourth node N4, thereby adjusting the potential of the fourth node N4.

[0090] In the low-level output phase, the first input module 701 can be turned on under the control of the first clock signal terminal SCK1, transmitting the conduction level of the trigger signal input terminal SIN to the first node N1 or the eighth node N8. The second input module 702 can be turned on under the control of the first clock signal terminal SCK1, transmitting the conduction level voltage signal of the first power supply voltage signal terminal VGL to the fourth node N4. The third output control module 703 can be turned on under the control of the eighth node N8, transmitting the conduction level of the first clock signal terminal SCK1 to the fourth node N4.

[0091] Continue to see Figure 7 According to some embodiments of the present application, optionally, the shift register 20 may further include a second switch module 704, wherein the control terminal of the second switch module 704 is electrically connected to the first power supply voltage signal terminal VGL, the first terminal of the second switch module 704 is electrically connected to the eighth node N8, and the second terminal of the second switch module 704 is electrically connected to the first node N1. Due to the switching characteristics of the transistor itself, when the difference between the voltage value Vg at the control terminal of the second switch module 704 and the voltage value Vs at the second terminal of the second switch module 704 is less than or equal to the absolute value of the threshold voltage of the second switch module 704 |V th |, that is, V g -V s =|V th |, the second switch module 704 will be turned off. In this way, when the potential of the first node N1 is pulled low, the second switch module 704 is turned off, which can prevent the potential of the eighth node N8 from being continuously pulled low, thereby reducing the voltage difference between the gate-drain or gate-source of each transistor connected to the eighth node N8, and improving circuit stability.

[0092] Continue to see Figure 7 According to some embodiments of the present application, the shift register 20 may optionally further include a third switch module 705, wherein a control terminal of the third switch module 705 is electrically connected to the first power supply voltage signal terminal VGL, a first terminal of the third switch module 705 is electrically connected to the fourth node N4, and a second terminal of the third switch module 705 is electrically connected to the seventh node N7. Similarly, when the potential of the seventh node N7 is pulled low, the third switch module 705 is turned off, thereby preventing the potential of the fourth node N4 from being continuously pulled low, thereby reducing the voltage difference between the gate-drain or gate-source of each transistor connected to the fourth node N4, and improving circuit stability.

[0093] For ease of understanding, the shift register 20 provided in the embodiment of the present application is described in detail below in conjunction with some specific application examples.

[0094] Figure 8 This is another circuit diagram of a shift register provided in an embodiment of the present application. Figure 8 As shown, according to some embodiments of the present application, the first output module 201 may optionally include a first transistor T1. The first output control module 202 may include a first protection unit 401 and a discharge blocking unit 402. The first protection unit 401 may include a second transistor T2, and the discharge blocking unit 402 may include a third transistor T3. The first coupling module 203 may include a first coupling capacitor C1.

[0095] The first switching module 204 may include a fourth transistor T4. The first potential regulating module 301 may include a fifth transistor T5, and the second potential regulating module 302 may include a sixth transistor T6. The second output module 501 may include a seventh transistor T7. The second output control module 502 may include a first output control unit 5021, a second output control unit 5022, and a third output control unit 5023. The first output control unit 5021 may include an eighth transistor T8, the second output control unit 5022 may include a ninth transistor T9, and the third output control unit 5023 may include a tenth transistor T10.

[0096] The first storage module 601 may include a first storage capacitor C2. The second coupling module 602 may include a second coupling capacitor C2. The first input module 701 may include an eleventh transistor T11, the second input module 702 may include a twelfth transistor T12, the third output control module 703 may include a thirteenth transistor T13, the second switch module 704 may include a fourteenth transistor T14, and the third switch module 705 may include a fifteenth transistor T15.

[0097] A gate of the first transistor T1 is electrically connected to the first node N1 , a first electrode of the first transistor T1 is electrically connected to the first power voltage signal terminal VGL, and a second electrode of the first transistor T1 is electrically connected to the output terminal OUT of the shift register 20 .

[0098] A gate of the second transistor T2 is electrically connected to the first clock signal terminal SCK1 , a first electrode of the second transistor T2 is electrically connected to the trigger signal input terminal SIN, and a second electrode of the second transistor T2 is electrically connected to the fifth node N5 .

[0099] A gate electrode of the third transistor T3 and a first electrode of the third transistor T3 are both electrically connected to the fifth node N5 , and a second electrode of the third transistor T3 is electrically connected to the second node N2 .

[0100] The first plate of the first coupling capacitor C1 is electrically connected to the third node N3 , and the second plate of the first coupling capacitor C1 is electrically connected to the second node N2 .

[0101] A gate electrode of the fourth transistor T4 and a first electrode of the fourth transistor T4 may be electrically connected to the second node N2 , and a second electrode of the fourth transistor T4 is electrically connected to the first node N1 .

[0102] A gate of the fifth transistor T5 is electrically connected to the second node N2 , a first electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal SCK2 , and a second electrode of the fifth transistor T5 is electrically connected to the third node N3 .

[0103] A gate of the sixth transistor T6 may be electrically connected to the fourth node N4 , a first electrode of the sixth transistor T6 is electrically connected to the second power supply voltage signal terminal VGH, and a second electrode of the sixth transistor T6 is electrically connected to the third node N3 .

[0104] A gate of the seventh transistor T7 may be electrically connected to the sixth node N6 , a first electrode of the seventh transistor T7 is electrically connected to the second power supply voltage signal terminal VGH, and a second electrode of the seventh transistor T7 is electrically connected to the output terminal OUT of the shift register 20 .

[0105] A gate of the eighth transistor T8 is electrically connected to the seventh node N7 , a first electrode of the eighth transistor T8 is electrically connected to the second clock signal terminal SCK2 , and a second electrode of the eighth transistor T8 is electrically connected to the ninth node N9 .

[0106] A gate of the ninth transistor T9 is electrically connected to the second clock signal terminal SCK2 , a first electrode of the ninth transistor T9 is electrically connected to the ninth node N9 , and a second electrode of the ninth transistor T9 is electrically connected to the sixth node N6 .

[0107] A gate of the tenth transistor T10 is electrically connected to the eighth node N8 , a first electrode of the tenth transistor T10 is electrically connected to the second power supply voltage signal terminal VGH, and a second electrode of the tenth transistor T10 is electrically connected to the sixth node N6 .

[0108] A first plate of the first storage capacitor C2 may be electrically connected to the second power voltage signal terminal VGH, and a second plate of the first storage capacitor C2 may be electrically connected to the sixth node N6.

[0109] A first plate of the second coupling capacitor C3 is electrically connected to the seventh node N7 , and a second plate of the second coupling capacitor C3 is electrically connected to the ninth node N9 .

[0110] A gate of the eleventh transistor T11 may be electrically connected to the first clock signal terminal SCK1 , a first electrode of the eleventh transistor T11 is electrically connected to the trigger signal input terminal SIN, and a second electrode of the eleventh transistor T11 is electrically connected to the eighth node N8 .

[0111] A gate of the twelfth transistor T12 is electrically connected to the first clock signal terminal SCK1 , a first electrode of the twelfth transistor T12 is electrically connected to the first power supply voltage signal terminal VGL, and a second electrode of the twelfth transistor T12 is electrically connected to the fourth node N4 .

[0112] A gate of the thirteenth transistor T13 is electrically connected to the eighth node N8 , a first electrode of the thirteenth transistor T13 is electrically connected to the first clock signal terminal SCK1 , and a second electrode of the thirteenth transistor T13 is electrically connected to the fourth node N4 .

[0113] A gate of the fourteenth transistor T14 is electrically connected to the first power voltage signal terminal VGL, a first electrode of the fourteenth transistor T14 is electrically connected to the eighth node N8, and a second electrode of the fourteenth transistor T14 is electrically connected to the first node N1.

[0114] A gate of the fifteenth transistor T15 is electrically connected to the first power voltage signal terminal VGL, a first electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4, and a second electrode of the fifteenth transistor T15 is electrically connected to the seventh node N7.

[0115] Figure 9 for Figure 8 The shift register shown in FIG. Figure 9 As shown, according to some embodiments of the present application, optionally, the working process of the shift register 20 provided in the embodiments of the present application may include a first discharge maintenance stage t1, a low-level discharge maintenance stage t2, a high-potential writing stage t3, a first high-level output stage t4, a second high-level output stage t5, a third high-level output stage t6, a low-level output stage t7 and a low-level maintenance output stage t8.

[0116] Combine Figure 8 and Figure 9 As shown, in the first discharge maintenance phase t1, a conduction level is provided to the trigger signal input terminal SIN and the first clock signal terminal SCK1, and a cutoff level is provided to the second clock signal terminal SCK2. The first input module 701 (i.e., the eleventh transistor T11) is turned on under the control of the first clock signal terminal SCK1, and the second switch module 704 (i.e., the fourteenth transistor T14) is turned on under the control of the first power supply voltage signal terminal SCK1. The eighth node N8 and the first node N1 are at a conduction level. The potential of the eighth node N8 and the potential of the first node N1 are both VGL'-Vth (Vth is the threshold voltage of the transistor, and Vth can be a negative value, such as Vth = -1.5V). Because the voltage value of the voltage signal output by the output terminal OUT in the previous phase is VGL', the gate-source voltage Vgs of the first output module 201 (first transistor T1) is V th|, the first transistor T1 is turned off. The third output control unit 5023 (i.e., the tenth transistor T10) is turned on, and the high-level voltage signal of the second power supply voltage signal terminal VGH is written to the sixth node N6. The sixth node N6 is at the cut-off level, and the potential of the sixth node N6 is equal to VGH'. The second output module 501 (i.e., the seventh transistor T7) is turned off. The output terminal OUT of the shift register 20 maintains the low-level voltage signal outputted in the previous stage. The first protection unit 401 (i.e., the second transistor T2) is turned on, and the potential of the fifth node N5 is VGL'-Vth. The discharge blocking unit 402 (i.e., the third transistor T3) is turned on, and the potential of the second node N2 is VGL'-2*Vth. The first potential adjustment module 301 (i.e., the fifth transistor T5) is turned on, and the third node N3 is at the cut-off level, and the potential of the third node N3 is VGH'. The first switch module 204 (i.e., the fourth transistor T4) is turned on. The second input module 702 (i.e., the twelfth transistor T12) and the third switch module 705 (i.e., the fifteenth transistor T15) are turned on, and the potentials of the fourth node N4 and the seventh node N7 are VGL'-Vth. The first output control unit 5021 (i.e., the eighth transistor T8) is turned on, and the potential of the ninth node N9 is VGL'.

[0117] During the second discharge sustaining phase t2, a conduction level is provided to the trigger signal input terminal SIN and the second clock signal terminal SCK2, and an off level is provided to the first clock signal terminal SCK1. The eighth node N8 maintains a conduction level, i.e., the potential of the eighth node N8 maintains VGL'-Vth. The third output control unit 5023 (i.e., the tenth transistor T10) remains on, the sixth node N6 maintains an off level, and the potential of the sixth node N6 is equal to VGH'. The second output module 501 (i.e., the seventh transistor T7) is turned off. The third output control module 703 (i.e., the thirteenth transistor T13) and the third switch module 705 (i.e., the fifteenth transistor T15) are turned on, and the fourth node N4 and the seventh node N7 are at an off level. The second potential regulating module 302 (i.e., the sixth transistor T6) and the first output control unit 5021 (i.e., the eighth transistor T8) are turned off. Because there's no discharge loop at the right end of second node N2, when third node N3 switches from an off-level to an on-level, the first coupling module 203 (i.e., first coupling capacitor C1) responds to the potential change at third node N3 by coupling to lower the potential of second node N2, resulting in a potential equal to VGL'-3*Vth-VGH'. The low on-level at second node N2 is transmitted to first node N1 via first switch module 204 (fourth transistor T4), resulting in a potential equal to VGL'-4*Vth-VGH'. First output module 201 (first transistor T1) turns on in response to the on-level at first node N1. First transistor T1 is linearly turned on, transmitting the low-level voltage signal from first power supply voltage signal terminal VGL to output terminal OUT of shift register 20. Ninth transistor T9 turns on, resulting in a potential of ninth node N9 equal to VGH'.

[0118] During the high-potential write phase t3, a conduction level is provided to the first clock signal terminal SCK1, and a cutoff level is provided to the trigger signal input terminal SIN and the second clock signal terminal SCK2. The first input module 701 (i.e., the eleventh transistor T11) and the second switch module 704 (i.e., the fourteenth transistor T14) are turned on, the eighth node N8 and the first node N1 are at a cutoff level, the potentials of the eighth node N8 and the first node N1 are VGH', and the first output module 201 (i.e., the first transistor T1) is turned off. The twelfth transistor T12 and the fifteenth transistor T15 are turned on, the potentials of the fourth node N4 and the seventh node N7 are VGL'-Vth. The eighth transistor T8 is turned on, and the potential of the ninth node N9 is VGH'. The sixth node N6 maintains a cutoff level, the second output module 501 (i.e., the seventh transistor T7) is turned off, and the output terminal OUT of the shift register 20 maintains the low-level voltage signal outputted in the previous stage. The first protection unit 401 (i.e., the second transistor T2) is turned on, the fifth node N5 is at the cut-off level, and the potential of the fifth node N5 is VGH'. The discharge blocking unit 402 (i.e., the third transistor T3) is turned off, the second node N2 maintains the on-level, and the potential of the second node N2 is VGL'-2*Vth.

[0119] During the first high-level output phase t4, a conduction level is provided to the second clock signal terminal SCK2, and an off-level is provided to the trigger signal input terminal SIN and the first clock signal terminal SCK1. The eighth node N8 and the first node N1 maintain an off-level, the potentials of the eighth node N8 and the first node N1 are VGH', and the first output module 201 (i.e., the first transistor T1) is turned off. The fourth node N4 and the seventh node N7 maintain an on-level, and the potential of the fourth node N4 is VGL'-Vth. The second coupling module 602 (i.e., the second coupling capacitor C3) pulls down the potential of the seventh node N7 through coupling, and the potential of the seventh node N7 is 2*VGL'-Vth-VGH'. The first output control unit 5021 (i.e., the eighth transistor T8) is turned on, and the potential of the ninth node N9 is VGL'. The second output control unit 5022 (i.e., the ninth transistor T9) is turned on, the sixth node N6 is at the on-level, and the potential of the sixth node N6 is VGL'-Vth. The second output module 501 (i.e., the seventh transistor T7) is turned on, transmitting the high-level voltage signal of the second power supply voltage signal terminal VGH to the output terminal OUT of the shift register 20. The third node N3 and the fifth node N5 are at the off-level, and the potential of the third node N3 and the fifth node N5 is VGH'. The second node N2 maintains the on-level, and the potential of the second node N2 is VGL'-2*Vth.

[0120] During the second high-level output phase t5, a conduction level is provided to the first clock signal terminal SCK1, and an off-level is provided to the trigger signal input terminal SIN and the second clock signal terminal SCK2. The eighth node N8 and the first node N1 maintain an off-level, and the first output module 201 (i.e., the first transistor T1) is turned off. The tenth transistor T0 is turned off. The second input module 702 (i.e., the twelfth transistor T12) and the third switch module 705 (i.e., the fifteenth transistor T15) are turned on, the fourth node N4 and the seventh node N7 are at an on-level, and the potentials of the fourth node N4 and the seventh node N7 are VGL'-Vth. The first output control unit 5021 is turned on, the ninth node N9 is at an off-level, and the potential of the ninth node N9 is VGH'. The second output control unit 5022 is turned off, the sixth node N6 maintains an on-level, and the potential of the sixth node N6 is VGL'-Vth. The second output module 501 is turned on, transmitting the high-level voltage signal of the second power supply voltage signal terminal VGH to the output terminal OUT of the shift register 20. The third node N3 and the fifth node N5 are at a cut-off level, and the potentials of the third node N3 and the fifth node N5 are VGH′. The second node N2 maintains a conductive level, and the potential of the second node N2 is VGL′-2*Vth.

[0121] During the third high-level output phase t6, an on-level is provided to the trigger signal input terminal SIN and the second clock signal terminal SCK2, and an off-level is provided to the first clock signal terminal SCK1. The eighth node N8 and the first node N1 maintain an off-level, and the first output module 201 (i.e., the first transistor T1) is turned off. The fourth node N4 and the seventh node N7 maintain an on-level, and the potential of the fourth node N4 is VGL'-Vth. The second coupling module 602 (i.e., the second coupling capacitor C3) pulls down the potential of the seventh node N7 through coupling, and the potential of the seventh node N7 is 2*VGL'-Vth-VGH'. The first output control unit 5021 (i.e., the eighth transistor T8) is turned on, and the potential of the ninth node N9 is VGL'. The second output control unit 5022 (i.e., the ninth transistor T9) is turned on, the sixth node N6 is at the on-level, and the potential of the sixth node N6 is VGL'-Vth. The second output module 501 (i.e., the seventh transistor T7) is turned on, transmitting the high-level voltage signal of the second power supply voltage signal terminal VGH to the output terminal OUT of the shift register 20. The third node N3 and the fifth node N5 are at the off-level, and the potential of the third node N3 and the fifth node N5 is VGH'. The second node N2 maintains the on-level, and the potential of the second node N2 is VGL'-2*Vth.

[0122] During the low-level output phase t7, a cutoff level is provided to the trigger signal input terminal SIN, the first clock signal terminal SCK1, and the second clock signal terminal SCK2. The second transistor T2 and the third transistor T3 are turned on, transmitting the on-level (e.g., low level) of the trigger signal input terminal SIN to the second node N2. The potential of the eighth node N8 is VGL'-Vth. The fourteenth transistor T14 is turned on, and the potential of the first node N1 first drops from VGH' in the previous phase to VGL'-Vth. The potential of the second node N2 is then pulled even lower by the coupling effect of the parasitic capacitance Cx of the first switch module 204 (i.e., the fourth transistor T4). Because the second node N2 is at the on-level, the first switch module 204 turns on in response to the on-level of the second node N2. The low on-level of the second node N2 is transmitted to the first node N1 through the first switch module 204, causing the potential of the first node N1 (i.e., the control terminal of the first output module 201) to be pulled down to a lower level, such as the potential of the first node N1 being VGL'-n*Vth-VGH', where n is a positive integer. The first output module 201 (first transistor T1) turns on in response to the on-level of the first node N1. The first transistor T1 is linearly turned on, transmitting the low-level voltage signal of the first power supply voltage signal terminal VGL to the output terminal OUT of the shift register 20. The tenth transistor T10 turns on, and the potential of the sixth node N6 is VGH'. The potentials of the fourth node N4 and the seventh node N7 are VGL'-Vth.

[0123] During the low-level output maintenance phase t8, a conduction level is provided to the trigger signal input terminal SIN and the second clock signal terminal SCK2, and an off-level is provided to the first clock signal terminal SCK1. The eighth node N8 and the first node N1 maintain a conduction level, the potential of the eighth node N8 maintains VGL'-Vth, and the potential of the first node N1 maintains VGL'-n*Vth-VGH'. The first output module 201 (the first transistor T1) is turned on in response to the conduction level of the first node N1. The first transistor T1 is linearly turned on, transmitting the low-level voltage signal of the first power supply voltage signal terminal VGL to the output terminal OUT of the shift register 20. The third output control unit 5023 (i.e., the tenth transistor T10) is turned on, the sixth node N6 is at an off-level, and the second output module 501 (i.e., the seventh transistor T7) is turned off.

[0124] The low level output stage during stages t7 and t8 will be repeated for a period of time thereafter, and will not be further described here.

[0125] Based on the shift register 20 provided in the above embodiment, accordingly, an embodiment of the present application further provides a driving method, which can be applied to the shift register 20 provided in the above embodiment.

[0126] Figure 10A flow chart of the driving method provided in the embodiment of the present application. Figure 10 As shown, the driving method may include the following steps:

[0127] S101. In the low-level output stage, a conduction level is provided to the first clock signal terminal, and a conduction level is provided to the trigger signal input terminal, so that the first output control module is turned on under the control of the first clock signal terminal, and the conduction level of the trigger signal input terminal is transmitted to the second node, and the coupling effect of the parasitic capacitance of the first switch module itself and / or the coupling effect of the first coupling module are used to pull down the potential of the second node. The conduction level of the second node after being pulled down is transmitted to the first node through the first switch module, and the first output module is turned on in response to the conduction level of the first node, and the low-level voltage signal of the first power supply voltage signal terminal is transmitted to the output terminal of the shift register.

[0128] In the driving method of the embodiment of the present application, in the low-level output stage, the first output control module transmits the conduction level of the trigger signal input terminal to the second node under the control of the first clock signal terminal, and the first switch module is turned on in response to the conduction level of the second node. The potential of the second node is pulled down through the coupling effect of the parasitic capacitance of the first switch module itself and / or the coupling effect of the first coupling module. The conduction level of the second node after being pulled down is transmitted to the first node through the first switch module, so that the potential of the first node (i.e., the control terminal of the first output module) is pulled down to a lower level, increasing the switching degree of the first output module, and thus making the output terminal of the shift register switch to output a low-level voltage signal without a step waveform, so that the low-level voltage signal output by the output terminal of the shift register is no longer affected by the threshold voltage of the first output module. In this way, the problem of G-direction horizontal stripes on the display panel caused by inconsistent threshold voltages of the first output module can be improved or even eliminated, thereby improving the display effect of the display panel.

[0129] According to some embodiments of the present application, optionally, the shift register also includes a first input module, a second input module, a first potential adjustment module, a second potential adjustment module, a second output module, a second output control module, a third output control module, a first storage module, a second coupling module, a second switch module and a third switch module, the second output control module includes a first output control unit, a second output control unit and a third output control unit, and the first output control module includes a first protection unit and a discharge blocking unit.

[0130] It should be noted that the connection relationship between the above modules has been described in detail above and will not be repeated here.

[0131] Accordingly, before the low-level output stage, the driving method may further include:

[0132] In the high-potential writing phase, a conduction level is provided to the first clock signal terminal, and a cutoff level is provided to the trigger signal input terminal and the second clock signal terminal. The first input module and the second switch module are turned on, the eighth node and the first node are at the cutoff level, and the first output module is turned off; the sixth node maintains the cutoff level, the second output module is turned off, and the output terminal of the shift register maintains the voltage signal of the previous phase; the first protection unit is turned on, the fifth node is at the cutoff level, the discharge blocking unit is turned off, and the second node maintains the conduction level;

[0133] In the high-level output stage, the eighth node and the first node are at the cut-off level, and the first output module is turned off; the sixth node is at the on-level, and the second output module is turned on, transmitting the high-level voltage signal at the second power supply voltage signal end to the output end of the shift register.

[0134] According to some embodiments of the present application, optionally, before the high-potential writing phase, the driving method may further include:

[0135] In the first discharge sustaining phase, a conduction level is provided to the trigger signal input terminal and the first clock signal terminal, and an off-level is provided to the second clock signal terminal. The first input module is turned on under the control of the first clock signal terminal, and the second switch module is turned on under the control of the first power supply voltage signal terminal. The eighth node and the first node are at the conduction level. The third output control unit is turned on, the sixth node is at the off-level, the second output module is turned off, and the output terminal of the shift register maintains outputting a low-level voltage signal. The first output control module is turned on, the second node is at the conduction level, the first potential adjustment module is turned on, and the third node is at the off-level.

[0136] In the low-level discharge maintenance stage, a conduction level is provided to the trigger signal input terminal and the second clock signal terminal, and a cutoff level is provided to the first clock signal terminal. The eighth node maintains the conduction level, the sixth node maintains the cutoff level, and the second output module is turned off; the third output control module and the third switch module are turned on, the fourth node and the seventh node are at the cutoff level, and the second potential adjustment module and the first output control unit are turned off; the third node is switched from the cutoff level to the conduction level, and the coupling module responds to the potential change of the third node and pulls down the potential of the second node through coupling. The conduction level of the second node after being pulled down is transmitted to the first node through the first switch module, and the first output module is turned on in response to the conduction level of the first node, and the low-level voltage signal of the first power supply voltage signal terminal is transmitted to the output terminal of the shift register.

[0137] According to some embodiments of the present application, optionally, the high-level output stage may specifically include a first high-level output stage, a second high-level output stage, and a third high-level output stage, wherein:

[0138] In the first high-level output stage, a conduction level is provided to the second clock signal terminal, an off-level is provided to the trigger signal input terminal and the first clock signal terminal, the eighth node and the first node maintain the off-level, and the first output module is turned off; the fourth node and the seventh node maintain the conduction level, the second coupling module pulls down the potential of the seventh node through coupling, the first output control unit and the second output control unit are turned on, the sixth node is at the conduction level, the second output module is turned on, and the high-level voltage signal of the second power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third node and the fifth node are at the off-level, and the second node maintains the conduction level;

[0139] In the second high-level output stage, a conduction level is provided to the first clock signal terminal, an off-level is provided to the trigger signal input terminal and the second clock signal terminal, the eighth node and the first node maintain the off-level, and the first output module is turned off; the second input module and the third switch module are turned on, the fourth node and the seventh node are at the conduction level, the first output control unit is turned on, the ninth node is at the off-level, the second output control unit is turned off, the sixth node maintains the conduction level, the second output module is turned on, and the high-level voltage signal at the second power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third node and the fifth node are at the off-level, and the second node maintains the conduction level;

[0140] In the third high-level output stage, a conduction level is provided to the trigger signal input terminal and the second clock signal terminal, and a cutoff level is provided to the first clock signal terminal, the eighth node and the first node maintain the cutoff level, and the first output module is turned off; the fourth node and the seventh node maintain the conduction level, the second coupling module lowers the potential of the seventh node through coupling, the first output control unit and the second output control unit are turned on, the sixth node is at the conduction level, the second output module is turned on, and the high-level voltage signal of the second power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third node and the fifth node are at the cutoff level, and the second node maintains the conduction level.

[0141] According to some embodiments of the present application, optionally, in the low-level maintenance output stage, a conduction level is provided to the trigger signal input terminal and the second clock signal terminal, and a cutoff level is provided to the first clock signal terminal, the eighth node and the first node maintain the conduction level, the first output module is turned on, and the low-level voltage signal of the first power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third output control unit is turned on, the sixth node is at the cutoff level, and the second output module is turned off.

[0142] It should be noted that the specific working processes of the above-mentioned first discharge maintenance stage t1, low-level discharge maintenance stage t2, high-level writing stage t3, first high-level output stage t4, second high-level output stage t5, third high-level output stage t6, low-level output stage t7 and low-level maintenance output stage t8 have been described in detail when introducing the shift register 20 and will not be repeated here.

[0143] Based on the shift register 20 provided in the above embodiment, accordingly, an embodiment of the present application further provides a scan driving circuit. The scan driving circuit may include a plurality of cascaded shift registers 20 provided in the above embodiment.

[0144] Figure 11 A circuit diagram of a scan drive circuit provided in an embodiment of the present application. Figure 11 As shown, according to some embodiments of the present application, the scan driver circuit 1200 can optionally be provided on both sides of the display panel, such as the non-display areas on the left and right sides of the display panel. That is, bilateral driving can be achieved. The scan driver circuit 1200 on each side can include multiple cascaded shift registers 20 as provided in the above embodiments.

[0145] In other embodiments, the scan driving circuit 1200 may also be located on a single side of the display panel, such as the left side or the right side of the display panel, to implement unilateral driving, which is not limited in the embodiments of the present application.

[0146] Based on the shift register 20 and the scan driving circuit provided in the above embodiment, the present application further provides a display panel, which includes the shift register 20 or the scan driving circuit provided in the above embodiment.

[0147] Based on the display panel provided in the above embodiment, the present application also provides a display device, including the display panel provided in the present application. Figure 12 , Figure 12 A schematic structural diagram of a display device provided in an embodiment of the present application. Figure 12 The provided display device 1000 includes the display panel provided by any of the above embodiments of the present application. Figure 12 In the embodiment, a mobile phone is used as an example to illustrate the display device 1000. It is understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display device with a display function, and the present application does not impose specific limitations on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the shift register 20, the scan drive circuit, or the display panel in the above embodiments, and this embodiment will not be repeated here.

[0148] It should be understood that the specific structures of the circuits provided in the drawings of the embodiments of the present application are merely examples and are not intended to limit the present application. In addition, the above embodiments provided in the present application may be combined with each other unless there is any contradiction.

[0149] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. According to the embodiments described above in accordance with the present application, these embodiments do not describe all the details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

[0150] Those skilled in the art should understand that the above embodiments are illustrative rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, the specification and the claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity involves "one" but does not exclude multiple; the terms "first" and "second" are used to identify names rather than to indicate any specific order. Any figure marks in the claims should not be understood as limiting the scope of protection. The fact that certain technical features appear in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A shift register, characterized in that: include: a first output module, wherein a control terminal of the first output module is electrically connected to the first node, a first terminal of the first output module is electrically connected to the first power supply voltage signal terminal, and a second terminal of the first output module is electrically connected to the output terminal of the shift register; A first output control module is electrically connected to the trigger signal input terminal, the first clock signal terminal and the second node; a first coupling module, the first coupling module being electrically connected to the second node; a first switch module, wherein the control terminal of the first switch module and the first terminal of the first switch module are both electrically connected to the second node, and the second terminal of the first switch module is electrically connected to the first node; In the low-level output stage, the first output control module transmits the conduction level of the trigger signal input terminal to the second node under the control of the first clock signal terminal. The first switch module is turned on in response to the conduction level of the second node, and the potential of the second node is pulled down through the coupling effect of the parasitic capacitance of the first switch module and / or the coupling effect of the first coupling module. The conduction level of the second node after being pulled down is transmitted to the first node through the first switch module. The first output module is turned on in response to the conduction level of the first node, and the low-level voltage signal of the first power supply voltage signal terminal is transmitted to the output terminal of the shift register. a second output module, wherein a control terminal of the second output module is electrically connected to the sixth node, a first terminal of the second output module is electrically connected to the second power supply voltage signal terminal, and a second terminal of the second output module is electrically connected to the output terminal of the shift register; a second output control module, electrically connected to the second power supply voltage signal terminal, the second clock signal terminal, the sixth node, the seventh node, and the eighth node, the second output control module being configured to be turned on in response to a conduction level of the seventh node or the eighth node, and to transmit the voltage signal of the second power supply voltage signal terminal or the second clock signal terminal to the sixth node; the second output control module comprising a first output control unit, wherein: a control terminal of the first output control unit is electrically connected to the seventh node, a first terminal of the first output control unit is electrically connected to the second clock signal terminal, and a second terminal of the first output control unit is electrically connected to the ninth node; a first storage module, wherein a first terminal of the first storage module is electrically connected to the second power supply voltage signal terminal, and a second terminal of the first storage module is electrically connected to the sixth node; A second coupling module, wherein a first end of the second coupling module is electrically connected to the seventh node, and a second end of the second coupling module is electrically connected to the ninth node.

2. The shift register according to claim 1, wherein: The shift register further includes a first potential regulating module, wherein a control terminal of the first potential regulating module is electrically connected to the second node, a first terminal of the first potential regulating module is electrically connected to the second clock signal terminal, and a second terminal of the first potential regulating module is electrically connected to the third node; A first end of the first coupling module is electrically connected to the third node, and a second end of the first coupling module is electrically connected to the second node; In the low-level discharge maintenance stage before the low-level output stage, the second clock signal end switches from the output cut-off level to the output on-level, the voltage value of the on-level is less than the voltage value of the cut-off level, the first potential adjustment module transmits the on-level of the second clock signal end to the third node, and the first coupling module responds to the potential change of the third node and pulls down the potential of the second node through coupling.

3. The shift register according to claim 2, wherein: The shift register further includes a second potential regulating module, wherein a control terminal of the second potential regulating module is electrically connected to the fourth node, a first terminal of the second potential regulating module is electrically connected to the second power supply voltage signal terminal, and a second terminal of the second potential regulating module is electrically connected to the third node; In a stage before the low-level discharge maintenance stage, the second potential adjustment module is turned on in response to the conduction level of the fourth node, and the high-level voltage signal of the second power supply voltage signal end is transmitted to the third node, and / or the first potential adjustment module is turned on in response to the conduction level of the second node, and the high-level voltage signal of the second clock signal end is transmitted to the third node.

4. The shift register according to claim 1, wherein: The first output control module includes a first protection unit and a discharge blocking unit; The control end of the first protection unit is electrically connected to the first clock signal end, the first end of the first protection unit is electrically connected to the trigger signal input end, and the second end of the first protection unit is electrically connected to the fifth node; The discharge blocking unit is connected between the fifth node and the second node; In the low-level output stage, the first protection unit and the discharge blocking unit are turned on, and the conduction level of the trigger signal input terminal is transmitted to the second node.

5. The shift register according to claim 4, wherein: The control end of the discharge blocking unit and the first end of the discharge blocking unit are both electrically connected to the fifth node, and the second end of the discharge blocking unit is electrically connected to the second node.

6. The shift register according to claim 1, wherein: The second output control module includes a second output control unit and a third output control unit, wherein: The control terminal of the second output control unit is electrically connected to the second clock signal terminal, the first terminal of the second output control unit is electrically connected to the ninth node, and the second terminal of the second output control unit is electrically connected to the sixth node; The control end of the third output control unit is electrically connected to the eighth node, the first end of the third output control unit is electrically connected to the second power supply voltage signal end, and the second end of the third output control unit is electrically connected to the sixth node.

7. The shift register according to claim 1, wherein: The shift register further includes: a first input module, wherein a control end of the first input module is electrically connected to the first clock signal end, a first end of the first input module is electrically connected to the trigger signal input end, a second end of the first input module is electrically connected to an eighth node, and the eighth node is electrically connected to the first node; a second input module, wherein a control terminal of the second input module is electrically connected to the first clock signal terminal, a first terminal of the second input module is electrically connected to the first power supply voltage signal terminal, a second terminal of the second input module is electrically connected to a fourth node, and the fourth node is electrically connected to a seventh node; a third output control module, wherein the control end of the third output control module is electrically connected to the eighth node, the first end of the third output control module is electrically connected to the first clock signal end, and the second end of the third output control module is electrically connected to the fourth node.

8. The shift register according to claim 7, wherein: The shift register further includes: a second switch module, wherein a control end of the second switch module is electrically connected to the first power supply voltage signal end, a first end of the second switch module is electrically connected to the eighth node, and a second end of the second switch module is electrically connected to the first node; a third switch module, wherein the control end of the third switch module is electrically connected to the first power supply voltage signal end, the first end of the third switch module is electrically connected to the fourth node, and the second end of the third switch module is electrically connected to the seventh node.

9. A driving method, characterized in that: Applied to the shift register according to any one of claims 1 to 8, the driving method comprises: In the low-level output stage, a conduction level is provided to the first clock signal terminal and a conduction level is provided to the trigger signal input terminal, so that the first output control module is turned on under the control of the first clock signal terminal, and the conduction level of the trigger signal input terminal is transmitted to the second node. The potential of the second node is pulled down by utilizing the coupling effect of the parasitic capacitance of the first switch module itself and / or the coupling effect of the first coupling module. The conduction level of the second node after being pulled down is transmitted to the first node through the first switch module. The first output module is turned on in response to the conduction level of the first node, and the low-level voltage signal of the first power supply voltage signal terminal is transmitted to the output terminal of the shift register.

10. The driving method according to claim 9, wherein: The shift register further includes a first input module, a second input module, a first potential adjustment module, a second potential adjustment module, a second output module, a second output control module, a third output control module, a first storage module, a second coupling module, a second switch module, and a third switch module; the second output control module includes a first output control unit, a second output control unit, and a third output control unit; the first output control module includes a first protection unit and a discharge blocking unit; Before the low level output stage, the driving method further includes: In the high-potential writing phase, a conduction level is provided to the first clock signal terminal, and an off-level is provided to the trigger signal input terminal and the second clock signal terminal. The first input module and the second switch module are turned on, the eighth node and the first node are at the off-level, and the first output module is turned off; the sixth node maintains the off-level, the second output module is turned off, and the output terminal of the shift register maintains the voltage signal of the previous phase; the first protection unit is turned on, the fifth node is at the off-level, the discharge blocking unit is turned off, and the second node maintains the conduction level; In the high-level output stage, the eighth node and the first node are at the cut-off level, and the first output module is turned off; the sixth node is at the on-level, and the second output module is turned on, transmitting the high-level voltage signal at the second power supply voltage signal end to the output end of the shift register.

11. The driving method according to claim 10, wherein: Before the high potential writing stage, the driving method further includes: In the first discharge sustaining phase, a conduction level is provided to the trigger signal input terminal and the first clock signal terminal, and an off-level is provided to the second clock signal terminal. The first input module is turned on under the control of the first clock signal terminal, and the second switch module is turned on under the control of the first power supply voltage signal terminal. The eighth node and the first node are at a conduction level. The third output control unit is turned on, the sixth node is at an off-level, the second output module is turned off, and the output terminal of the shift register maintains outputting a low-level voltage signal. The first output control module is turned on, the second node is at a conduction level, the first potential adjustment module is turned on, and the third node is at an off-level. In the low-level discharge maintenance stage, a conduction level is provided to the trigger signal input terminal and the second clock signal terminal, and a cutoff level is provided to the first clock signal terminal, the eighth node maintains the conduction level, the sixth node maintains the cutoff level, and the second output module is turned off; the third output control module and the third switch module are turned on, the fourth node and the seventh node are at the cutoff level, and the second potential adjustment module and the first output control unit are turned off; the third node is switched from the cutoff level to the conduction level, and the coupling module responds to the potential change of the third node and pulls down the potential of the second node through coupling. The conduction level of the second node after being pulled down is transmitted to the first node through the first switch module, and the first output module is turned on in response to the conduction level of the first node, and the low-level voltage signal of the first power supply voltage signal terminal is transmitted to the output terminal of the shift register.

12. The driving method according to claim 10 or 11, characterized in that: The high-level output stage specifically includes a first high-level output stage, a second high-level output stage and a third high-level output stage, wherein: In the first high-level output stage, a conduction level is provided to the second clock signal terminal, an off-level is provided to the trigger signal input terminal and the first clock signal terminal, the eighth node and the first node maintain the off-level, and the first output module is turned off; the fourth node and the seventh node maintain the conduction level, the second coupling module pulls down the potential of the seventh node through coupling, the first output control unit and the second output control unit are turned on, the sixth node is at the conduction level, the second output module is turned on, and the high-level voltage signal of the second power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third node and the fifth node are at the off-level, and the second node maintains the conduction level; In the second high-level output stage, a conduction level is provided to the first clock signal terminal, an off-level is provided to the trigger signal input terminal and the second clock signal terminal, the eighth node and the first node maintain the off-level, and the first output module is turned off; the second input module and the third switch module are turned on, the fourth node and the seventh node are at the conduction level, the first output control unit is turned on, the ninth node is at the off-level, the second output control unit is turned off, the sixth node maintains the conduction level, the second output module is turned on, and the high-level voltage signal at the second power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third node and the fifth node are at the off-level, and the second node maintains the conduction level; In the third high-level output stage, a conduction level is provided to the trigger signal input terminal and the second clock signal terminal, and an off-level is provided to the first clock signal terminal, the eighth node and the first node maintain the off-level, and the first output module is turned off; the fourth node and the seventh node maintain the conduction level, the second coupling module lowers the potential of the seventh node through coupling, the first output control unit and the second output control unit are turned on, the sixth node is at the conduction level, the second output module is turned on, and the high-level voltage signal of the second power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third node and the fifth node are at the off-level, and the second node maintains the conduction level.

13. The driving method according to claim 10 or 11, characterized in that: After the low level output stage, the driving method further includes: In the low-level maintenance output stage, a conduction level is provided to the trigger signal input terminal and the second clock signal terminal, and an off-level is provided to the first clock signal terminal. The eighth node and the first node maintain the conduction level, the first output module is turned on, and the low-level voltage signal of the first power supply voltage signal terminal is transmitted to the output terminal of the shift register; the third output control unit is turned on, the sixth node is at the off-level, and the second output module is turned off.

14. A scanning driving circuit, characterized in that: A shift register comprising a plurality of cascaded shift registers according to any one of claims 1 to 8.

Images