Shift register, gate drive circuit, display panel and driving method

Abstract

This application provides a shift register, a gate driving circuit, a display panel, and a driving method. The shift register includes a first input module, a second input module, a bootstrap module, and an output module. The first input module is electrically connected to a first clock signal terminal, a control signal terminal, and a first node. The second input module is electrically connected to a control signal terminal, a first power supply signal terminal, a second power supply signal terminal, a second clock signal terminal, and a second node. The output module is electrically connected to the first node, the second node, the bootstrap module, the first power supply signal terminal, the second power supply signal terminal, and an output terminal. The bootstrap module includes a switching unit and a bootstrap unit. The control terminal, a first terminal, and a second terminal of the switching unit are electrically connected to the output module, the second clock signal terminal, and the first terminal of the bootstrap unit, respectively. The second terminal of the bootstrap unit is electrically connected to the output module. The technical solution of this application can improve the stability of the output signal.

Description

Technical Field

[0001] This application relates to display technology, and more particularly to a shift register, a gate driving circuit, a display panel, and a driving method. Background Technology

[0002] The LTPO (Low Temperature Polycrystalline Oxide) pixel circuit in related technologies has high requirements for driving the shift register (GOA). The output stability of traditional shift registers is poor and they are prone to fluctuations with the clock signal, which cannot meet the driving requirements of LTPO pixel circuits for shift registers. Summary of the Invention

[0003] This application provides a shift register, a gate driving circuit, a display panel, and a driving method to solve the problems existing in related technologies. The technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a shift register, including: a first input module, a second input module, a bootstrap module, and an output module;

[0005] The first input module is electrically connected to the first clock signal terminal, the control signal terminal, and the first node respectively. The first input module is used to control the connection and disconnection between the control signal terminal and the first node based on the clock signal provided by the first clock signal terminal.

[0006] The second input module is electrically connected to the control signal terminal, the first power signal terminal, the second power signal terminal, the second clock signal terminal, and the second node, respectively. The second input module is used to control the connection and disconnection between the first power signal terminal and the second node based on the signals provided by the control signal terminal and the second clock signal terminal.

[0007] The output module is electrically connected to the first node, the second node, the bootstrap module, the first power signal terminal, the second power signal terminal, and the output terminal, respectively. The output module is used to control the on / off state between the first power signal terminal and the output terminal based on the potential of the first node, the potential of the second node, and the adjustment of the bootstrap module, and to control the on / off state between the second power signal terminal and the output terminal.

[0008] The bootstrap module includes a switching unit and a bootstrap unit. The control terminal, first terminal, and second terminal of the switching unit are electrically connected to the output module, the second clock signal terminal, and the first terminal of the bootstrap unit, respectively. The second terminal of the bootstrap unit is electrically connected to the output module. The switching unit is used to control the on / off state between the second clock signal terminal and the bootstrap unit based on the potential of the output module. The bootstrap unit is used to bootstrap the potential of the output module.

[0009] In a second aspect, embodiments of this application provide a gate driving circuit, including: cascaded multi-stage shift registers, each stage of the shift register being the shift register provided in the first aspect of embodiments of this application;

[0010] The control signal terminal of the first-stage shift register is electrically connected to the frame start signal terminal;

[0011] For two adjacent shift registers, the output of the previous shift register is electrically connected to the control signal terminal of the next shift register.

[0012] Thirdly, embodiments of this application provide a display panel, including: a pixel circuit and a gate driving circuit provided in the second aspect of embodiments of this application;

[0013] The gate drive circuit is electrically connected to the pixel circuit, and the gate drive circuit is used to provide the gate drive signal to the pixel circuit.

[0014] Fourthly, embodiments of this application provide a driving method applied to the shift register provided in the first aspect of embodiments of this application, the method comprising:

[0015] In the first stage, the control signal terminal provides a first potential signal. The first input module controls the connection or disconnection between the control signal terminal and the first node based on the clock signal provided by the first clock signal terminal. The switching unit controls the connection between the second clock signal terminal and the bootstrap unit based on the first potential of the output module. The bootstrap unit bootstraps the first potential of the output module. The output module controls the connection between the first power signal terminal and the output terminal based on the potential of the first node, the potential of the second node, and the bootstrap function of the bootstrap unit.

[0016] In the second stage, the second input module controls the second power signal terminal to disconnect from the second node based on the second potential signal provided by the control signal terminal, the second input module controls the first power signal terminal to conduct or disconnect from the second node based on the clock signal provided by the second clock signal terminal, and the output module controls the second power signal terminal and the output terminal to conduct based on the potential of the second node.

[0017] The advantages or beneficial effects of the above technical solutions include at least the following:

[0018] The bootstrap module in the shift register includes a switching unit and a bootstrap unit. The switching unit is connected between the second clock signal terminal and the bootstrap unit. It can transmit the clock signal provided by the second clock signal terminal to the bootstrap unit and isolate the direct signal transmission between the second clock signal terminal and the bootstrap unit. This can reduce the impact of signal fluctuations at the second clock signal terminal on the bootstrap unit. When bootstrapping the output module's potential through the bootstrap unit, it can reduce the impact of signal fluctuations at the second clock signal terminal on the output module, thereby making the output module and the output signal of the output terminal connected to the output module more stable.

[0019] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0020] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0021] Figure 1 This is a schematic diagram of the circuit principle of an LTPO pixel circuit in related technologies;

[0022] Figure 2 A schematic diagram of the structural framework of a shift register provided in an embodiment of this application;

[0023] Figure 3 A schematic diagram of the circuit principle of a shift register provided in an embodiment of this application;

[0024] Figure 4 A flowchart illustrating a driving method provided in an embodiment of this application;

[0025] Figure 5 for Figure 3 The diagram shows the signal timing of each signal terminal and node of the shift register.

[0026] Figure 6 This is a schematic diagram of the structural framework of a gate driving circuit provided in an embodiment of this application;

[0027] Figure 7 A simulation diagram illustrating the sequential output of cascaded shift registers;

[0028] Figure 8 Another simulation diagram showing the output of each cascaded shift register in turn;

[0029] Figure 9 This is another simulation diagram showing the output of each cascaded shift register. Detailed Implementation

[0030] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0031] The relevant technologies involved in this application are first introduced as follows:

[0032] The circuit structure of an LTPO pixel circuit in related technologies is as follows: Figure 1 As shown, the device includes transistors M1 to M7, capacitors Cst and C_Data, and a light-emitting device EL. The input signals include: drive signals (N-Scan, P-Scan), data signal Data, light-emitting signal EM, high-level signal ELVDD, low-level signal ELVSS, and initialization signals (Vinit1 and Vinit2). Transistors M1, M2, M5, and M6 require a stable shift register to drive them.

[0033] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments.

[0034] This application provides a shift register, such as Figure 2 As shown, the shift register includes: a first input module 100, a second input module 200, an output module 300, and a bootstrap module 400.

[0035] The first input module 100 is electrically connected to the first clock signal terminal CK1, the control signal terminal STV, and the first node N1. The first input module 100 is used to control the connection and disconnection between the control signal terminal STV and the first node N1 based on the clock signal provided by the first clock signal terminal CK1. For example, when the clock signal provided by the first clock signal CK1 is at a first potential, the first input module 100 can enable the control signal terminal STV and the first node N1 to conduct, transmitting the signal provided by the control signal terminal STV to the first node N1. When the clock signal provided by the first clock signal CK1 is at a second potential, the first input module 100 can disconnect the control signal terminal STV and the first node N1.

[0036] The second input module 200 is electrically connected to the control signal terminal STV, the first power signal terminal VGL, the second power signal terminal VGH, the second clock signal terminal CK2, and the second node N2, respectively. The second input module 200 is used to control the connection and disconnection between the first power signal terminal VGL and the second node N2 based on the signals provided by the control signal terminal STV and the second clock signal terminal CK2. For example, when the signal provided by the second clock signal terminal CK2 is at a first potential, the second input module 200 can control the first power signal terminal VGL to conduct between the first power signal terminal and the second node N2; when the signal provided by the second clock signal terminal CK2 is at a second potential, the second input module 200 can control the first power signal terminal VGL to disconnect between the first power signal terminal and the second node N2; when the signal provided by the control signal terminal STV is at a first potential, the second input module 200 can control the second power signal terminal VGH to conduct between the second node N2; and when the signal provided by the control signal terminal STV is at a second potential, the second input module 200 can control the second power signal terminal VGH to disconnect between the second node N2.

[0037] Output module 300 is electrically connected to the first node N1, the second node N2, the bootstrap module 400, the first power signal terminal VGL, the second power signal terminal VGH, and the output terminal OUT. Output module 300 controls the connection and disconnection between the first power signal terminal VGL and the output terminal OUT based on the potential of the first node N1, the potential of the second node N2, and the adjustment of the bootstrap module. It also controls the connection and disconnection between the second power signal terminal VGH and the output terminal. When the connection between the first power signal terminal VGL and the output terminal OUT is active, the output terminal OUT can output the signal provided by the first power signal terminal VGL. When the connection between the first power signal terminal VGL and the output terminal OUT is closed, the output terminal OUT cannot output the signal provided by the first power signal terminal VGL. When the connection between the second power signal terminal VGH and the output terminal OUT is active, the output terminal OUT can output the signal provided by the second power signal terminal VGH. When the connection between the second power signal terminal VGH and the output terminal OUT is closed, the output terminal OUT cannot output the signal provided by the second power signal terminal VGH.

[0038] The bootstrap module 400 includes a switching unit and a bootstrap unit. The control terminal, first terminal, and second terminal of the switching unit are electrically connected to the output module 300, the second clock signal terminal CK2, and the first terminal of the bootstrap unit, respectively. The second terminal of the bootstrap unit is electrically connected to the output module 300. The switching unit is used to control the switching between the second clock signal terminal CK2 and the bootstrap unit based on the potential of the output module 300. The bootstrap unit is used to bootstrap the potential of the output module 300.

[0039] In the shift register provided in this application embodiment, the bootstrap module includes a switching unit and a bootstrap unit. The switching unit is connected between the second clock signal terminal CK2 and the bootstrap unit, and can transmit the clock signal provided by the second clock signal terminal CK2 to the bootstrap unit. It can isolate the direct signal transmission between the second clock signal terminal CK2 and the bootstrap unit, thereby reducing the influence of the signal fluctuation of the second clock signal terminal CK2 on the bootstrap unit. When bootstrapping the potential of the output module 300 through the bootstrap unit, it can reduce the influence of the signal fluctuation of the second clock signal terminal CK2 on the output module 300, thereby making the output module and the output signal of the output terminal connected to the output module more stable.

[0040] In one alternative implementation, refer to Figure 3 For example, output module 300 may include a first output unit 301 and a second output unit 302.

[0041] The first output unit 301 can be electrically connected to the first node N1, the first power signal terminal VGL, and the output terminal, respectively. The first output unit 301 can be used to control the connection and disconnection between the first power signal terminal VGL and the output terminal OUT based on the potential of the first node N1 and the bootstrap function of the bootstrap unit. For example, based on the potential of the first node N1 and the bootstrap function of the bootstrap unit, when the potential of the output control node in the first output unit 301 is the first potential, the first output unit 301 can control the first power signal terminal VGL and the output terminal OUT to be connected, so that the output terminal OUT can output the signal provided by the first power signal terminal VGL. When the potential of the output control node in the first output unit 301 is the second potential, the first output unit 301 can control the first power signal terminal VGL and the output terminal OUT to be disconnected, so that the output terminal OUT cannot output the signal provided by the first power signal terminal VGL.

[0042] The second output unit 302 can be electrically connected to the second node N2, the second power signal terminal VGH, and the output terminal, respectively. The second output unit 302 is used to control the connection and disconnection between the second power signal terminal VGH and the output terminal OUT based on the potential of the second node N2. For example, when the potential of the second node N2 is the first potential, the second output unit 302 can control the connection between the second power signal terminal VGH and the output terminal OUT, so that the output terminal OUT can output the signal provided by the second power signal terminal VGH. When the potential of the second node N2 is the second potential, the second output unit 302 can control the connection between the second power signal terminal VGH and the output terminal OUT to be disconnected, so that the output terminal OUT cannot output the signal provided by the second power signal terminal VGH.

[0043] The first input module 100 and the first output unit 301 can form a first output path for outputting the signal provided by the first power signal terminal VGL. The second input module 200 and the second output unit can form a second output path for outputting the signal provided by the second power signal terminal VGH. The signal provided by the first power signal terminal VGL can be a signal at a first potential, and the signal provided by the second power signal terminal VGH can be a signal at a second potential. The first output path can cooperate with the second output path to achieve the output of different signals at different stages.

[0044] In one alternative implementation, refer to Figure 3 For example, the first output unit 301 may include a first transistor T1 and a second transistor T2. The control electrode, first electrode, and second electrode of the first transistor T1 may be electrically connected to the first power supply signal terminal VGL, the first node N1, and the third node N3, respectively. The control electrode, first electrode, and second electrode of the second transistor T2 may be electrically connected to the third node N3, the first power supply signal terminal VGL, and the output terminal OUT, respectively. The aforementioned output control node may be the third node N3.

[0045] In one example, the first transistor T1 can be turned on under the control of the first potential signal provided by the first power supply signal terminal VGL, transmitting the potential signal of the first node N1 to the third node N3. The potential of the third node N3 can control the on / off state of the second transistor T2. For example, when the potential of the third node N3 is the first potential, the second transistor T2 can be turned on, thereby connecting the first power supply signal terminal VGL and the output terminal OUT. When the potential of the third node N3 is the second potential, the second transistor T2 can be turned off, thereby disconnecting the first power supply signal terminal VGL and the output terminal OUT.

[0046] By placing the first transistor T1 between the first node N1 and the third node N3, direct signal transmission between the two nodes can be isolated, thereby isolating the signal fluctuations of the first clock signal terminal CK1 from the influence of the third node N3, maintaining the stability of the turn-on voltage at the third node N3, and maintaining the stability of the second transistor T2 under the control of the turn-on voltage of the third node N3, ultimately making the output of the output terminal connected to the second transistor T2 more stable.

[0047] In another embodiment, the first output unit 301 may include a second transistor T2, the control electrode, the first electrode, and the second electrode of the second transistor T2 being electrically connected to the first node N1, the first power supply signal terminal VGL, and the output terminal OUT, respectively. The second transistor T2 can be turned on or off under the control of the potential of the first node N1.

[0048] In one alternative implementation, refer to Figure 3For example, in the bootstrap module 400, the switching unit may include a third transistor T3, and the bootstrap unit may include a first capacitor C1. The control electrode, the first electrode, and the second electrode of the third transistor T3 are electrically connected to the first output unit 301, the second clock signal terminal CK2, and the first terminal (e.g., the positive plate) of the first capacitor C1, respectively. The second terminal (e.g., the negative plate) of the first capacitor C1 is electrically connected to the first output unit 301.

[0049] In one example, refer to Figure 3 The control terminal of the third transistor T3 and the second terminal of the first capacitor C1 can both be electrically connected to the third node N3 in the first output unit 301. The third transistor T3 can be turned on or off under the control of the potential of the third node N3. When the third transistor T3 is turned on, the clock signal provided by the second clock signal terminal CK2 can be transmitted to the first capacitor C1. The first capacitor C1 can bootstrap the potential of the third node N3 in the first output unit 301.

[0050] In another example, the control terminal of the third transistor T3 and the second terminal of the first capacitor C1 can both be electrically connected to the first node N1. Figure 3 (This connection method is not shown), thereby electrically connecting to the first output unit 301 through the first node N1. The third transistor T3 can be turned on or off under the control of the potential of the first node N1. When the third transistor T3 is turned on, the clock signal provided by the second clock signal terminal CK2 can be transmitted to the first capacitor C1, and the first capacitor C1 can bootstrap the potential of the first node N1.

[0051] In one optional embodiment, the second output unit 302 may include a fourth transistor T4 and a fifth transistor T5. The control electrode, first electrode, and second electrode of the fourth transistor T4 may be electrically connected to the first power supply signal terminal VGL, the second node N2, and the fourth node N4, respectively. The control electrode, first electrode, and second electrode of the fifth transistor T5 may be electrically connected to the fourth node N4, the second power supply signal terminal VGH, and the output terminal OUT, respectively.

[0052] In one example, the fourth transistor T4 can be turned on under the control of the first potential signal provided by the first power supply signal terminal VGL. The potential of the fourth node N4 is adjusted based on the potential of the second node N2. The potential of the fourth node N4 can control the on / off state of the fifth transistor T5. For example, when the potential of the second node N2 is the first potential, the tenth transistor T10 can be turned on, thereby connecting the second power supply signal terminal VGH and the output terminal OUT. When the potential of the second node N2 is the second potential, the tenth transistor T10 can be turned off, thereby disconnecting the second power supply signal terminal VGH and the output terminal OUT.

[0053] By placing the fourth transistor T4 between the second node N2 and the fourth node N4, the direct signal transmission between the two nodes can be isolated, thereby isolating the signal fluctuations of the second clock signal terminal CK2 from the fourth node N4 and maintaining the stability of the turn-on voltage at the fourth node N4. Under the control of the turn-on voltage of the fourth node N4, the stability of the fifth transistor T5 can be maintained, and ultimately the output of the output terminal connected to the fifth transistor T5 can be more stable.

[0054] In another embodiment, the second output unit 302 may include a fifth transistor T5. The control electrode, first electrode, and second electrode of the fifth transistor T5 may be electrically connected to the second node N2, the second power signal terminal VGH, and the output terminal OUT, respectively. The fifth transistor T5 may be turned on or off under the control of the potential of the second node N2.

[0055] Reference Figure 3 For example, the first output unit 301 may further include a second capacitor C2, whose two ends are electrically connected to the control electrode and the first electrode of the second transistor T2, respectively, to achieve noise reduction and cooperate with the first capacitor C1 to stabilize the turn-on voltage of the second transistor T2. The second output unit 302 may further include a third capacitor C3, whose two ends are electrically connected to the control electrode and the first electrode of the fifth transistor T5, respectively, to achieve noise reduction.

[0056] In one alternative implementation, refer to Figure 3 For example, the output module 400 may also include an output control unit 303, which may be electrically connected to the first output unit 301, the second power signal terminal VGH, and the second output unit 301 respectively. The output control unit 303 may be used to control the on / off state between the second power signal terminal VGH and the second output unit based on the potential of the first output unit.

[0057] Reference Figure 3 For example, the output control unit 303 may include a sixth transistor T6. The control electrode, first electrode, and second electrode of the sixth transistor T6 may be electrically connected to the third node N3, the second power supply signal terminal VGH, and the fourth node N4, respectively. The potential of the third node N3 may control the on / off state of the sixth transistor T6. For example, when the potential of the third node N3 is the first potential, the sixth transistor T6 may be turned on. The sixth transistor T6 may adjust the potential of the fourth node N4 based on the second potential signal provided by the second power supply signal terminal VGH, so that when the first output unit 301 outputs a signal to the output terminal, the second output unit 302 may stop outputting.

[0058] In one alternative implementation, refer to Figure 3For example, the second input module 200 may include a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a fourth capacitor C4. The control terminal, first terminal, and second terminal of the seventh transistor T7 may be electrically connected to the control signal terminal STV, the first power signal terminal VGL, and the fifth node N5, respectively; the control terminal, first terminal, and second terminal of the eighth transistor T8 may be electrically connected to the fifth node N5, the second power signal terminal VGH, and the first terminal of the fourth capacitor C4, respectively; the control terminal, first terminal, and second terminal of the ninth transistor T9 may be electrically connected to the second clock signal terminal CK2, the first power signal terminal VGL, and the second node N2, respectively; and the second terminal of the fourth capacitor C4 may be electrically connected to the second node N2.

[0059] The seventh transistor T7 can be turned on or off under the control of the signal provided by the control signal terminal STV. When turned on, it can adjust the potential of the fifth node N5 based on the signal provided by the first power signal terminal VGL. The eighth transistor T8 can be turned on or off under the control of the potential of the fifth node N5. When turned on, it can charge the first terminal of the fourth capacitor C4 based on the signal provided by the second power signal terminal VGH. The ninth transistor T9 can be turned on or off under the control of the clock signal provided by the second clock signal terminal CK2. When turned on, it can adjust the potential of the second node N2 based on the signal provided by the first power signal terminal VGL. The potential of the second node N2 can charge the second terminal of the fourth capacitor C4. Based on the above structure of the second input module 200, the turn-on voltage for shifting can be realized through the cooperation of the signal of the control signal terminal STV and the signal of the second clock signal terminal CK2.

[0060] In one alternative implementation, the fifth node N5 can also be electrically connected to the control signal terminal STV to receive the signal provided by the control signal terminal STV and further control the eighth transistor T8, which can be used in conjunction with the signals of other nodes to achieve shifting.

[0061] In another alternative implementation, refer to Figure 3 The second input module 200 may further include a fifth capacitor C5, with its two ends electrically connected to the control signal terminal STV and the fifth node N5, respectively. The control signal terminal STV can be transmitted to the fifth node N5 through the fifth capacitor C5, improving the stability of the fifth node N5 and enabling it to stably control the eighth transistor T8. This, in turn, improves the output stability of the output terminal OUT, preventing any impact on the next-stage shift register.

[0062] In one optional implementation, the first input module 100 may include a tenth transistor T10, whose control terminal, first terminal, and second terminal are electrically connected to a first clock signal terminal CK1, a control signal terminal STV, and a first node N1, respectively. When the first clock signal terminal CK1 is at a first potential, the tenth transistor T10 can be turned on to transmit the signal from the control signal terminal STV to the first node N1; when the first clock signal terminal CK1 is at a second potential, the tenth transistor T10 can be turned off.

[0063] Each transistor in the embodiments of this application can be a thin-film transistor, a field-effect transistor, or other switching devices with the same characteristics. The embodiments of this application use thin-film transistors as an example for explanation. The source and drain of each transistor can be structurally symmetrical, so their structures can be indistinguishable. In the embodiments of this application, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal, and the other as the second terminal. The gate of the transistor can be referred to as the control terminal. Furthermore, according to their characteristics, transistors can be classified into N-type and P-type transistors. Figure 3 The P-type transistor shown is merely an example and is not intended to limit the embodiments of this application. When the transistor is a P-type transistor, the turn-on voltage is a low potential and the turn-off voltage is a high potential. In the embodiments of this application, the first potential can be a low potential and the second potential can be a high potential. When the transistor is an N-type transistor, the turn-on voltage is a high potential and the turn-off voltage is a low potential. In the embodiments of this application, the first potential can be a high potential and the second potential can be a low potential.

[0064] The shift register provided in this application embodiment can output a high-level signal as a scan drive signal to achieve forward scanning (or positive voltage scanning) to meet the driving requirements of LTPO pixel circuits, or it can output low-level information as a scan drive signal to achieve reverse scanning (or negative voltage scanning) to meet the possible driving requirements of other pixel circuits.

[0065] Based on the same technical concept, this application also provides a driving method, which can be applied to any shift register provided in this application, such as... Figure 4 As shown, the method includes the following steps S401-S402:

[0066] S401, in the first stage, the control signal terminal provides a first potential signal, the first input module controls the connection or disconnection between the control signal terminal and the first node based on the clock signal provided by the first clock signal terminal, the switching unit controls the connection between the second clock signal terminal and the bootstrap unit based on the first potential of the output module, the bootstrap unit bootstraps the first potential of the output module, and the output module controls the connection between the first power signal terminal and the output terminal based on the potential of the first node, the potential of the second node and the bootstrap function of the bootstrap unit.

[0067] In one example, the clock signal provided by the first clock signal terminal CK1 can be a pulse signal that jumps between a first potential and a second potential. In the first stage, the clock signal provided by the first clock signal terminal CK1 jumps periodically between the first potential and the second potential. When the signal provided by the first clock signal terminal CK1 is at the first potential, the first input module can make the control signal terminal STV and the first node N1 conduct, so that the potential of the first node N1 can be adjusted based on the signal provided by the control signal terminal STV. When the signal provided by the first clock signal CK1 is at the second potential, the first input module can make the control signal terminal STV and the first node N1 disconnected, so that the first node N1 cannot be adjusted based on the signal provided by the control signal terminal STV.

[0068] After the output module controls the connection between the first power signal terminal VGL and the output terminal, the output terminal can output the signal provided by the first power signal terminal VGL. Simultaneously with the connection between the first power signal terminal VGL and the output terminal, the second input module can control the connection between the second power signal terminal VGH and the second node N2 based on the first potential signal provided by the control signal terminal STV. The clock signal provided by the second clock signal terminal CK2 can be a pulse signal that jumps between the first and second potentials. In the first stage, the clock signal provided by the second clock signal terminal CK2 periodically jumps between the first and second potentials. When the signal provided by the second clock signal terminal CK2 is at the first potential, the second input module can be turned on, adjusting the potential of the second node N2 based on the signal provided by the first power signal terminal VGL. The output module can also control the connection between the second power signal terminal VGH and the output terminal based on the potential of the second node N2, so that the output terminal only outputs the signal from the first power signal terminal VGL in the first stage.

[0069] S402, in the second stage, the second input module controls the second power supply signal terminal to disconnect from the second node based on the second potential signal provided by the control signal terminal, the second input module controls the first power supply signal terminal to conduct or disconnect from the second node based on the clock signal provided by the second clock signal terminal, and the output module controls the second power supply signal terminal and the output terminal to conduct based on the potential of the second node.

[0070] After the output module controls the conduction between the second power signal terminal VGH and the output terminal, the output terminal can output the signal provided by the second power signal terminal VGH. Simultaneously with connecting the first power signal terminal VGL and the output terminal, the second input module can control the disconnection between the second power signal terminal VGH and the second node N2 based on the first potential signal provided by the control signal terminal STV. The clock signal provided by the second clock signal terminal CK2 can be a pulse signal that jumps between the first and second potentials. In the first stage, the clock signal provided by the second clock signal terminal CK2 periodically jumps between the first and second potentials. When the signal provided by the second clock signal terminal CK2 is at the first potential, the second input module can adjust the potential of the second node N2 based on the signal provided by the first power signal terminal VGL. The output module can control the disconnection between the second power signal terminal VGH and the output terminal based on the potential of the second node N2, so that the output terminal only outputs the signal from the first power signal terminal VGL in the first stage.

[0071] In an optional implementation, when the output module includes a first output unit and a second output unit, in step S401 above, the output module controls the connection between the first power signal terminal VGL and the output terminal based on the potential of the first node N1, the potential of the second node N2, and the bootstrap function of the bootstrap unit. This can include: the first output unit in the output module controlling the connection between the first power signal terminal VGL and the output terminal based on the potential of the first node N1, the potential of the second node N2, and the bootstrap function of the bootstrap unit. For example, based on the potential of the first node N1 and the bootstrap function of the bootstrap unit, when the potential of the output control node in the first output unit is a first potential, the first output unit 401 can control the connection between the first power signal terminal VGL and the output terminal OUT, so that the output terminal OUT can output the signal provided by the first power signal terminal VGL. When the potential of the output control node in the first output unit 401 is a second potential, the first output unit 401 can control the disconnection between the first power signal terminal VGL and the output terminal OUT, so that the output terminal OUT cannot output the signal provided by the first power signal terminal VGL.

[0072] In step S402 above, the output module controls the conduction between the second power signal terminal VGH and the output terminal based on the potential of the second node N2. This can include: the second output unit in the output module controlling the conduction between the second power signal terminal VGL and the output terminal based on the potential of the second node N2. For example, when the potential of the second node N2 is the first potential, the second output unit 402 can control the conduction between the second power signal terminal VGH and the output terminal OUT, so that the output terminal OUT can output the signal provided by the second power signal terminal VGL. When the potential of the second node N2 is the second potential, the second output unit 402 can control the disconnection between the second power signal terminal VGH and the output terminal OUT, so that the output terminal OUT cannot output the signal provided by the second power signal terminal VGH.

[0073] In an optional implementation, when the switching unit includes a third transistor T3 and the bootstrap unit includes a first capacitor C1, in the above step S401, the switching unit controls the second clock signal terminal CK2 and the bootstrap unit to conduct based on the first potential of the output module, and the bootstrap unit bootstraps the first potential of the output module. This can include: the third transistor T3 controls the second clock signal terminal CK2 and the first capacitor C1 to conduct based on the potential of the first output unit, transmitting the signal provided by the second clock signal terminal CK2 to the first capacitor C1, and the first capacitor C1 bootstraps the potential of the first output unit.

[0074] In an optional implementation, the driving method provided in this application embodiment may further include: in a first stage, the output control unit in the output module controls the conduction between the second power signal terminal VGH and the second output unit based on the potential of the first output unit, thereby adjusting (e.g., raising) the potential of the second output unit based on the signal provided by the second power signal terminal VGH, so that the second output unit stops outputting signals to the output terminal.

[0075] Figure 5 It shows Figure 3 The signal timing diagrams for each signal terminal and node in the shift register shown below are for reference. Figure 3 and Figure 5 The working principle of the shift register provided in the embodiments of this application will be introduced.

[0076] Reference Figure 3 and Figure 5 In the first stage T1, i.e. the charging stage, the signal provided by the control signal terminal STV is a low-potential signal, and the signals provided by the first clock signal terminal CK1 and the second clock signal terminal CK2 are pulse signals. The first output path controls the output terminal OUT to output the low-potential signal provided by the first power signal terminal VGL, and the second output path controls the output terminal OUT to stop outputting the high-potential signal provided by the second power signal terminal VGH.

[0077] The working principle of the first output path of T1 in the first stage is as follows: When the first clock signal terminal CK1 jumps to a low potential, the tenth transistor T10 turns on, transmitting the low potential signal provided by the control signal terminal STV to the first node N1 to pull down the potential of the first node N1. Under the control of the low potential signal provided by the first power signal terminal VGL, the first transistor T1 turns on, transmitting the low potential signal of the first node N1 to the third node N3 to pull down the potential of the third node N3. Under the control of the low potential signal of the third node N3, the third transistor T3 turns on. When the second clock signal terminal CK2 jumps to a low potential, it can be transmitted to the first capacitor C1 through the third transistor T3. The first capacitor C1 bootstraps the potential of the third node N3, causing the potential of the third node N3 to continue to drop. Thus, the third node N3 can control the second transistor T2 to turn on fully, so that the output terminal OUT can output the low potential signal provided by the first power signal terminal VGL.

[0078] The working principle of the second output path of T1 in the first stage is as follows: Under the control of the low potential provided by the control signal terminal STV, the seventh transistor T7 is turned on, transmitting the low potential signal of the first power supply signal terminal VGL to the fifth node N5 to keep the fifth node N5 at a low potential. Under the control of the low potential signal of the fifth node N5, the eighth transistor T8 is turned on, and the high potential signal provided by the second power supply signal terminal VGH charges one terminal of the fourth capacitor C4. When the second clock signal terminal CK2 jumps to a low potential, the ninth transistor T9 is turned on, transmitting the low potential signal of the first power supply signal terminal VGL to the second node N2 to pull down the potential of the second node N2. N2 charges the other terminal of the fourth capacitor C4; under the control of the low potential signal provided by the first power supply signal terminal VGL, the fourth transistor T4 turns on, transmitting the low potential signal of the second node N2 to the fourth node N4 to pull down the potential of the fourth node N4. At the same time, under the control of the low potential signal of the third node N3, the sixth transistor T6 turns on, transmitting the high potential signal provided by the second power supply signal terminal VGH to the fourth node N4 to raise the potential of the fourth node N4. As a result, the potential of the fourth node N4 is not low enough to control the fifth transistor T5 to turn on, so the output terminal OUT cannot output the high potential signal provided by the second power supply signal terminal VGH.

[0079] Reference Figure 3 and Figure 5In the second stage T2, i.e. the output stage, the signal provided by the control signal terminal STV changes from low potential to high potential and from high potential to low potential. The signals provided by the first clock signal terminal CK1 and the second clock signal terminal CK2 are still pulse signals. The second output path controls the output terminal OUT to output the high potential signal provided by the second power signal terminal VGH as the driving signal for driving the pixel. The first output path controls the output terminal OUT to stop outputting the low potential signal provided by the first power signal terminal VGL.

[0080] The working principle of the first output path in the second stage T2 is as follows: When the first clock signal terminal CK1 jumps to a low potential, the tenth transistor T10 turns on, transmitting the high potential signal provided by the control signal terminal STV to the first node N1 to raise the potential of the first node N1. Under the control of the low potential signal provided by the first power signal terminal VGL, the first transistor T1 turns on, transmitting the high potential signal of the first node N1 to the third node N3 to raise the potential of the third node N3. Under the control of the high potential signal of the third node N3, the sixth transistor T6, the third transistor T3, and the second transistor T2 are all turned off, so the output terminal OUT stops outputting the low potential signal provided by the first power signal terminal VGL, and the sixth transistor T6 will not raise the potential of the fourth node N4, thus avoiding affecting the normal output of the output terminal OUT.

[0081] The working principle of the second output path of T2 in the second stage is as follows: After the signal at the control signal terminal STV changes from low to high, the seventh transistor T7 is turned off, and the first power supply signal terminal VGL cuts off the potential control of the fifth node N5. At this time, the high potential signal at the control signal terminal STV is written to the fifth node N5 through the fifth capacitor C5, raising the potential of the fifth node N5. Under the control of the high potential of the fifth node N5, the eighth transistor T8 is turned off. When the second clock signal terminal CK2 jumps to low, the ninth transistor T9 is turned on, transmitting the low potential signal at the first power supply signal terminal VGL to the second node N2 to pull down the potential of the second node N2. Under the control of the low potential signal provided by the first power supply signal terminal VGL, the fourth transistor T4 is turned on, transmitting the low potential signal at the second node N2 to the fourth node N4 to pull down the potential of the fourth node N4. Under the control of the low potential of the fourth node N4, the fifth transistor T5 is turned on, causing the output terminal OUT to output the high potential signal provided by the second power supply signal terminal VGH.

[0082] For a period of time after the signal at the control signal terminal STV changes from high to low, the signal at the first clock signal terminal CK1 is high, the tenth transistor T10 is off, and the first node N1 and the third node N3 remain at high levels. This allows the sixth transistor T6, the third transistor T3, and the second transistor T2 to remain off. The sixth transistor T6 will not raise the potential of the fourth node N4, and the second transistor T2 will not output a low-level signal at the first power supply signal terminal VGL. The output terminal can continue to maintain a high-level signal output until the signal at the first clock signal terminal CK1 jumps to a low level, thereby completing one scan output of the drive signal.

[0083] Based on the same technical concept, this application embodiment also provides a display panel, including a pixel circuit and a gate driving circuit, wherein the gate driving circuit is electrically connected to the pixel circuit and is used to provide a gate driving signal to the pixel circuit.

[0084] Reference Figure 6 For example, the gate driving circuit may include cascaded multi-stage shift registers, each of which can be any type of shift register provided in the embodiments of this application. The control signal terminal of the first-stage shift register is electrically connected to the frame start signal terminal. For two adjacent shift register stages, the output terminal of the previous stage shift register is electrically connected to the control signal terminal of the next stage shift register. The output terminal of each stage shift register can also be electrically connected to the corresponding row of pixel circuits, and each stage shift register can drive one row of pixel circuits. Figure 6 Four shift registers are shown as examples, namely GOA1, GOA2, GOA3 and GOA4. This number is only for example and is not intended to limit the number of cascaded shift registers.

[0085] The pixel circuit connected to the shift register can be an LTPO pixel circuit, for example... Figure 1 The pixel circuit shown is as follows: Figure 1 In the circuit shown, the output of each stage of the shift register can be connected to the gate of at least one of transistors M1, M2, M5, and M6 in the corresponding row of pixel circuits to provide gate drive signals to transistors M1, M2, M5, and M6. In other examples, each stage of the shift register can also be electrically connected to other transistors in the corresponding row of pixel circuits, such as transistors M4 and / or M7, to provide gate drive signals to transistors M4 and / or M7. It is understood that in practical use, the specific transistors in the pixel circuit to which the output of the shift register is connected can be determined according to the specific driving requirements.

[0086] In one alternative implementation, refer to Figure 6In odd-level shift registers, the first clock signal terminal CK1 can be used to receive the first clock signal CKV1, and the second clock signal terminal CK1 can be used to receive the second clock signal CKV2. Similarly, in even-level shift registers, the first clock signal terminal CK1 can be used to receive the second clock signal CKV2, and the second clock signal terminal CK2 can be used to receive the first clock signal CKV1. Each shift register stage receives two clock signals, and the vertical shift scanning of the gate drive circuit can be achieved based on the coordinated control of these two clock signals.

[0087] During the vertical shift scanning process of the gate drive circuit, the shift duration of the output of the subsequent shift register relative to the output of the previous shift register can be adjusted according to actual needs. In order to achieve flexible adjustment of this interval duration, the pulse width, duty cycle and other parameters of each input signal of the shift register can be flexibly set.

[0088] Figures 7 to 9 A simulation diagram showing the cascaded shift registers outputting one stage at a time is shown. Figures 7 to 9 In this diagram, the STV signal is the frame start signal provided by the control signal terminal STV, the CK1 signal is the clock signal provided by the first clock signal terminal CK1, the CK2 signal is the clock signal provided by the second clock signal terminal CK2, the OUT1 signal is the drive signal output by the first-stage shift register, the OUT2 signal is the drive signal output by the second-stage shift register, and the OUT3 signal is the drive signal output by the third-stage shift register.

[0089] exist Figure 7 In the example, the pulse widths of CK1 and CK2 are both 1H, the pulse width of STV is 5H, the shift duration of OUT1 relative to STV is 1H, the shift duration of OUT2 relative to OUT1 is 1H, and the shift duration of OUT3 relative to OUT2 is 1H.

[0090] exist Figure 8 In the example, the pulse widths of CK1 and CK2 are both 1H, the pulse width of STV is 14H, the shift duration of OUT1 relative to STV is 1H, the shift duration of OUT2 relative to OUT1 is 1H, and the shift duration of OUT3 relative to OUT2 is 1H.

[0091] exist Figure 9 In the example, the pulse widths of CK1 and CK2 are both 3H, the pulse width of STV is 14H, the shift duration of OUT1 relative to STV is 2H, the shift duration of OUT2 relative to OUT1 is 2H, and the shift duration of OUT3 relative to OUT2 is 2H.

[0092] like Figures 7 to 9 The step-by-step shifting method shown can meet the driving requirements of LTPO pixel circuits and supports PWM (Pulse width modulation) function.

[0093] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0094] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0095] The term "comprising" as used in this application means the stated feature, integer, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term "and / or" as used herein includes all or any unit and all combination of one or more associated listed items.

[0096] It should be understood that when we say a component is "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or there may be an intermediate component. Furthermore, the term "connected" or "coupled" as used here can include wireless connections or wireless coupling.

[0097] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0098] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A shift register, characterized in that, include: The module consists of a first input module, a second input module, a bootstrap module, and an output module. The first input module is electrically connected to the first clock signal terminal, the control signal terminal, and the first node, respectively. The first input module is used to control the connection and disconnection between the control signal terminal and the first node based on the clock signal provided by the first clock signal terminal. The second input module is electrically connected to the control signal terminal, the first power signal terminal, the second power signal terminal, the second clock signal terminal, and the second node, respectively. The second input module is used to control the connection and disconnection between the first power signal terminal and the second node based on the signals provided by the control signal terminal and the second clock signal terminal. The output module is electrically connected to the first node, the second node, the bootstrap module, the first power signal terminal, the second power signal terminal, and the output terminal, respectively. The output module is used to control the connection and disconnection between the first power signal terminal and the output terminal based on the potential of the first node, the potential of the second node, and the adjustment of the bootstrap module, and to control the connection and disconnection between the second power signal terminal and the output terminal. The bootstrap module includes a switching unit and a bootstrap unit. The control terminal, first terminal, and second terminal of the switching unit are electrically connected to the output module, the second clock signal terminal, and the first terminal of the bootstrap unit, respectively. The second terminal of the bootstrap unit is electrically connected to the output module. The switching unit is used to control the on / off state between the second clock signal terminal and the bootstrap unit based on the potential of the output module. The bootstrap unit is used to bootstrap the potential of the output module. The output module includes a first output unit and a second output unit; The switching unit includes a third transistor, and the bootstrap unit includes a first capacitor; the control electrode, the first electrode, and the second electrode of the third transistor are electrically connected to the first output unit, the second clock signal terminal, and the first terminal of the first capacitor, respectively, and the second terminal of the first capacitor is electrically connected to the first output unit.

2. The shift register according to claim 1, characterized in that, The first output unit is electrically connected to the first node, the first power signal terminal, and the output terminal respectively. The first output unit is used to control the on / off state between the first power signal terminal and the output terminal based on the potential of the first node and the bootstrap function of the bootstrap unit. The second output unit is electrically connected to the second node, the second power signal terminal, and the output terminal, respectively. The second output unit is used to control the on / off state between the second power signal terminal and the output terminal based on the potential of the second node.

3. The shift register according to claim 2, characterized in that, The first output unit includes: a first transistor and a second transistor; The control electrode, first electrode, and second electrode of the first transistor are electrically connected to the first power signal terminal, the first node, and the third node, respectively. The control electrode, first electrode, and second electrode of the second transistor are electrically connected to the third node, the first power signal terminal, and the output terminal, respectively.

4. The shift register according to any one of claims 1-3, characterized in that, The second output unit includes: a fourth transistor and a fifth transistor; The control electrode, first electrode, and second electrode of the fourth transistor are electrically connected to the first power signal terminal, the second node, and the fourth node, respectively. The control electrode, first electrode, and second electrode of the fifth transistor are electrically connected to the fourth node, the second power signal terminal, and the output terminal, respectively.

5. The shift register according to any one of claims 1-3, characterized in that, The output module also includes an output control unit; The output control unit is electrically connected to the first output unit, the second power signal terminal, and the second output unit respectively. The output control unit is used to control the on / off connection between the second power signal terminal and the second output unit based on the potential of the first output unit.

6. The shift register according to any one of claims 1-3, characterized in that, The second input module includes: a seventh transistor, an eighth transistor, a ninth transistor, and a fourth capacitor; The control electrode, first electrode, and second electrode of the seventh transistor are electrically connected to the control signal terminal, the first power signal terminal, and the fifth node, respectively. The control electrode, first electrode, and second electrode of the eighth transistor are electrically connected to the fifth node, the second power signal terminal, and the first terminal of the fourth capacitor, respectively. The control electrode, first electrode, and second electrode of the ninth transistor are electrically connected to the second clock signal terminal, the first power signal terminal, and the second node, respectively. The second terminal of the fourth capacitor is electrically connected to the second node.

7. The shift register according to claim 6, characterized in that, The second input module also includes: a fifth capacitor; The two ends of the fifth capacitor are electrically connected to the control signal terminal and the fifth node, respectively.

8. A gate driving circuit, characterized in that, include: A cascaded multi-stage shift register, wherein each stage shift register is a shift register as described in any one of claims 1-7; The control signal terminal of the first-stage shift register is electrically connected to the frame start signal terminal; For two adjacent shift registers, the output of the previous shift register is electrically connected to the control signal terminal of the next shift register.

9. The gate driving circuit according to claim 8, characterized in that, The first clock signal terminal of the odd-level shift register is used to receive the first clock signal, and the second clock signal terminal of the odd-level shift register is used to receive the second clock signal. The first clock signal terminal of the even-numbered stage shift register is used to connect to the second clock signal, and the second clock signal terminal of the even-numbered stage shift register is used to connect to the first clock signal.

10. A display panel, characterized in that, include: Pixel circuit and gate driving circuit as described in claim 8 or 9; The gate driving circuit is electrically connected to the pixel circuit, and the gate driving circuit is used to provide a gate driving signal to the pixel circuit.

11. A driving method, characterized in that, Applied to a shift register as described in any one of claims 1-7, the method comprises: In the first stage, the control signal terminal provides a first potential signal, the first input module controls the connection or disconnection between the control signal terminal and the first node based on the clock signal provided by the first clock signal terminal, the switching unit controls the connection between the second clock signal terminal and the bootstrap unit based on the first potential of the output module, the bootstrap unit bootstraps the first potential of the output module, and the output module controls the connection between the first power signal terminal and the output terminal based on the potential of the first node, the potential of the second node and the bootstrap function of the bootstrap unit. In the second stage, the second input module controls the disconnection between the second power signal terminal and the second node based on the second potential signal provided by the control signal terminal, the second input module controls the conduction or disconnection between the first power signal terminal and the second node based on the clock signal provided by the second clock signal terminal, and the output module controls the conduction between the second power signal terminal and the output terminal based on the potential of the second node.

12. The driving method according to claim 11, characterized in that, The output module controls the connection between the first power signal terminal and the output terminal based on the potential of the first node, the potential of the second node, and the bootstrap function of the bootstrap unit, including: The first output unit in the output module controls the connection between the first power signal terminal and the output terminal based on the potential of the first node, the potential of the second node, and the bootstrap function of the bootstrap unit. The output module controls the conduction between the first power signal terminal and the output terminal based on the potential of the second node, including: The second output unit in the output module controls the connection between the first power signal terminal and the output terminal based on the potential of the second node.

13. The driving method according to claim 12, characterized in that, The switching unit controls the conduction between the second clock signal terminal and the bootstrap unit based on the first potential of the output module. The bootstrap unit bootstraps the first potential of the output module, including: The third transistor in the switching unit controls the conduction between the second clock signal terminal and the first capacitor in the bootstrap unit based on the potential of the first output unit, transmitting the signal provided by the second clock signal terminal to the first capacitor, and the first capacitor bootstraps the potential of the first output unit.

14. The driving method according to claim 12 or 13, characterized in that, Also includes: In the first stage, the output control unit in the output module controls the conduction between the second power signal terminal and the second output unit based on the potential of the first output unit.

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