Semiconductor structure and method of forming a semiconductor structure

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a gate structure on the substrate; forming a first recess in the substrate on both sides of the gate structure, a bottom surface of the first recess being a concave arc surface; performing a modification treatment on a sidewall surface of the first recess; forming a second recess and a modification layer on a sidewall surface and a bottom surface of the second recess, a thickness of the modification layer at a corner of the sidewall surface and the bottom surface of the second recess being greater than a thickness of the modification layer on a sidewall of the second recess; and removing the modification layer, a bottom surface of the second recess being parallel to a surface of the substrate. The semiconductor structure formed by the method has improved performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method of the semiconductor structure. BACKGROUND

[0002] In the advanced semiconductor manufacturing industry technology, in order to improve the stress of the transistor channel region, enhance the carrier mobility; wherein the embedded silicon germanium or phosphorus silicon is used to form the source region and the drain region, so as to exert stress on the channel region, so that the performance of the metal oxide semiconductor is obviously improved. In order to achieve better results, it is generally necessary to form a recess by etching before epitaxial silicon germanium of the source and drain region, and then epitaxially grow silicon germanium in the recess to enhance the effect of exerting stress and improve the performance of the semiconductor structure.

[0003] However, the growth effect of the epitaxial layer in the prior art still needs to be improved. SUMMARY

[0004] The technical problem solved by the present application is to provide a semiconductor structure and a forming method of the semiconductor structure to improve the growth effect of the epitaxial layer.

[0005] To solve the above technical problems, the technical scheme of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate; forming a gate structure on the substrate; forming a first recess in the substrate on both sides of the gate structure, the bottom surface of the first recess being a recessed arc surface; performing modification treatment on the side wall surface of the first recess to form a second recess and a modification layer located on the side wall surface and the bottom surface of the second recess, the thickness of the modification layer at the corner of the side wall surface and the bottom surface of the second recess being greater than the thickness of the side wall of the second recess; removing the modification layer, and the bottom surface of the second recess being parallel to the surface of the substrate.

[0006] Optionally, the method for forming the first recess comprises: using the gate structure as a mask, and using a first etching process to etch the substrate to form an initial first recess in the substrate on both sides of the gate structure; using a second etching process to etch the side wall of the initial first recess to form the first recess.

[0007] Optionally, the first etching process is an anisotropic dry etching process; the parameters of the anisotropic dry etching process include: the gas is a mixed gas of hydrogen and nitrogen trifluoride, the gas flow range is 20 standard milliliters per minute to 1000 standard milliliters per minute, the gas pressure range is 10 millitorr to 500 millitorr, the power range is 20 watts to 1200 watts, the voltage range is 50 volts to 500 volts, and the bias voltage range is 50 volts to 500 volts.

[0008] Optionally, the second etching process is an isotropic dry etching process; parameters of the isotropic dry etching process include: the gas is a mixture of hydrogen and ammonia, the gas flow range is 20 standard milliliters per minute to 1000 standard milliliters per minute, the gas pressure range is 10 millitorr to 500 millitorr, the power range is 20 watts to 1200 watts, and the voltage range is 50 volts to 500 volts.

[0009] Optionally, the crystal plane of the substrate surface is a (100) crystal plane.

[0010] Optionally, the process of modifying the first recess sidewall surface includes an oxidation process.

[0011] Optionally, the oxidation process includes a rapid thermal oxidation process; parameters of the rapid thermal oxidation process include: the gas is oxygen or a gas containing oxygen, the gas flow range is 10 standard milliliters per minute to 300 standard milliliters per minute, the temperature range is 700 degrees Celsius to 1100 degrees Celsius, and the pressure range is 20 millitorr to 200 millitorr.

[0012] Optionally, the oxidation rate of the oxidation process along the <111> crystal direction is greater than the oxidation rate along the <100> crystal direction or the <110> crystal direction.

[0013] Optionally, the material of the substrate includes silicon, and the material of the modification layer includes silicon oxide.

[0014] Optionally, the process of removing the modification layer includes a wet etching process, and the etching rate of the wet etching process on the modification layer is greater than the etching rate on the substrate.

[0015] Optionally, the first recess aspect ratio range is 2 to 5.

[0016] Optionally, it further includes: forming a source-drain doped region in the second recess.

[0017] Optionally, the material of the source-drain doped region includes silicon germanium or phosphorus silicon.

[0018] Optionally, the process of forming the source-drain doped region includes an epitaxial growth process.

[0019] Optionally, the substrate further has a fin structure, and the gate structure crosses the fin structure.

[0020] Optionally, it further includes: a side wall located on the sidewall of the gate structure; and a protection layer located on the top of the gate structure.

[0021] Correspondingly, the technical scheme of the present application also provides a semiconductor structure, comprising: a substrate; a gate structure on the substrate; a side wall on the side wall of the gate structure; a second groove in the substrate on both sides of the gate structure, the second groove being outside the side wall, the bottom surface of the second groove being parallel to the surface of the substrate, and the corner between the bottom of the second groove and the side wall being in a circular arc shape; and a source-drain doped region in the second groove.

[0022] Optionally, the substrate further has a fin structure and an isolation structure, the isolation structure being on the side wall of the fin structure and the top surface of the isolation structure being lower than the top surface of the fin structure; and the gate structure crossing the fin structure, the second groove being in the fin structure on both sides of the gate structure.

[0023] Optionally, the material of the source-drain doped region comprises silicon germanium or phosphorus silicon.

[0024] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0025] In the technical scheme of the present application, the surface of the side wall of the first groove is modified to form a modified layer, the thickness of the modified layer at the corner of the first groove being greater than the thickness of the modified layer at the side wall of the first groove, and then the modified layer is removed to form a second groove, the bottom plane of the second groove being parallel to the surface of the substrate. The bottom plane of the second groove is parallel to the surface of the substrate, so that the bottom plane of the second groove is a (100) crystal plane, which is beneficial to the growth of the material of the source-drain doped region on the (100) crystal plane, so that the crystal lattice of the material of the formed source-drain doped region is more regular, the source-drain doped region structure after the combination of each crystal lattice has fewer defects, the stress of the source-drain doped region on the channel can be improved, the mobility of electrons or holes can be improved, and the performance of the semiconductor structure can be improved.

[0026] Further, the process of modifying the surface of the side wall of the first groove comprises a thermal oxidation process. The thermal oxidation process has the highest oxidation rate of silicon on a (111) crystal plane, and the corner position of the side wall and the bottom of the second groove is close to the (111) crystal plane, so that the thickness of the formed modified layer at the corner of the second groove is greater than the thickness of the modified layer at the side wall of the second groove, more material of the corner of the first groove can be removed in the subsequent removal of the modified layer, so that the bottom plane of the formed second groove is parallel to the surface of the substrate, and more (100) crystal planes are obtained. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 And Figure 2 is a cross-sectional structure schematic diagram of the process of forming the semiconductor structure in an embodiment;

[0028] Figures 3 to 8is a schematic diagram of a cross-sectional structure of a semiconductor structure forming process in an embodiment of the present application. DETAILED DESCRIPTION

[0029] As described in the background, the growth effect of the epitaxial layer in the prior art needs to be improved. The present application will be analyzed and described in combination with specific embodiments.

[0030] Figure 1 and Figure 2 is a schematic diagram of a cross-sectional structure of a semiconductor structure forming process in an embodiment of the present application.

[0031] Referring to Figure 1 , a substrate 100 is provided; a gate structure 102 is formed on the substrate 100; and a source-drain opening 101 is formed in the substrate 100 on both sides of the gate structure 102.

[0032] Referring to Figure 2 , a source-drain doped region 103 is formed in the source-drain opening 201.

[0033] In the forming process of the semiconductor structure, the shape of the source-drain opening 101 is usually "U" shaped, that is, the bottom plane of the source-drain opening 101 is a non-(100) crystal plane. The material of the source-drain doped region 103 is usually silicon germanium or phosphorus silicon, and the process for forming the silicon germanium or phosphorus silicon is an epitaxial growth process. The growth rate of the precursors of the epitaxial growth process is faster on the (100) crystal plane and the (110) crystal plane. Since the bottom plane of the source-drain opening 101 is a non-(100) crystal plane, the material crystal lattice interface of the source-drain doped region 103 grown in all directions in the source-drain opening 101 is irregular, and defects such as gaps or holes are generated when each crystal lattice merges, thereby affecting the stress of the source-drain doped region 103 on the channel.

[0034] To solve the above problems, the technical scheme of the present application modifies the surface of the side wall of the first groove to form a modified layer, the thickness of the modified layer at the corner of the first groove is greater than the thickness of the modified layer at the side wall of the first groove, and then the modified layer is removed to form a second groove, the bottom plane of the second groove is parallel to the surface of the substrate. The bottom plane of the second groove is parallel to the surface of the substrate, so that the bottom plane of the second groove is a (100) crystal plane, thereby facilitating the growth of the material of the source-drain doped region on the (100) crystal plane in the subsequent formation of the source-drain doped region in the second groove, making the material crystal lattice of the formed source-drain doped region more regular, and the source-drain doped region structure after the merging of each crystal lattice has fewer defects, which can improve the stress of the source-drain doped region on the channel, improve the mobility of electrons or holes, and thus improve the performance of the semiconductor structure.

[0035] In order to make the above-mentioned purposes, features and benefits of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0036] Figures 3 to 8 FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor structure forming process according to an embodiment of the present application.

[0037] Referring to FIG. 1, a substrate 200 is provided. Figure 3

[0038] In this embodiment, the material of the substrate 200 is silicon.

[0039] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0040] In this embodiment, the crystal plane of the surface of the substrate 200 is a (100) crystal plane.

[0041] In other embodiments, the substrate further has a fin structure and an isolation structure on the substrate, the isolation structure is located on the sidewall of the fin structure and the top surface of the isolation structure is lower than the top surface of the fin structure, and the crystal plane of the surface of the substrate and the crystal plane of the top surface of the fin structure are (100) crystal planes.

[0042] Referring to FIG. 2, a gate structure 201 is formed on the substrate 200. Figure 4

[0043] The gate structure 201 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer.

[0044] In this embodiment, the gate structure 201 further includes a work function layer (not shown) between the gate dielectric layer and the gate electrode layer.

[0045] The material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide; the material of the gate electrode layer includes a metal, and the metal includes tungsten; and the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0046] In other embodiments, the gate structure includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer. The material of the gate dielectric layer includes silicon oxide or a low-K (K is less than 3.9) material; and the material of the gate electrode layer includes polysilicon.

[0047] ​​In the embodiment, a protection layer 203 is further formed on the top of the gate structure 201; and a side wall 202 is further formed on the sidewall of the gate structure 201 and the sidewall of the protection layer 203.

[0048] The material of the protection layer 203 comprises a dielectric material, which comprises one or more of a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride and silicon oxycarbonitride. In the embodiment, the material of the protection layer 203 comprises silicon nitride.

[0049] The material of the side wall 202 comprises a dielectric material, which comprises one or more of a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride and silicon oxycarbonitride. In the embodiment, the material of the protection layer 203 comprises silicon nitride.

[0050] In other embodiments, the substrate further has a fin structure, and the gate structure is across the fin structure.

[0051] For reference Figure 5 A first recess 204 is formed in the substrate 200 on both sides of the gate structure 201, and the bottom surface of the first recess 204 is a concave arc surface.

[0052] The method for forming the first recess 204 comprises: using the gate structure 201 as a mask, and using a first etching process to etch the substrate 200, so as to form an initial first recess (not shown) in the substrate 200 on both sides of the gate structure 201; and using a second etching process to etch the sidewall of the initial first recess, so as to form the first recess 204.

[0053] In the embodiment, the aspect ratio of the first recess 204 ranges from 2 to 5. In other embodiments, the aspect ratio of the first recess can be set according to actual requirements of the device.

[0054] In the embodiment, the first etching process is an anisotropic dry etching process; and the parameters of the anisotropic dry etching process comprise: a mixed gas of hydrogen and nitrogen trifluoride, a gas flow ranging from 20 standard milliliters per minute to 1000 standard milliliters per minute, a gas pressure ranging from 10 millitorr to 500 millitorr, a power ranging from 20 watts to 1200 watts, a voltage ranging from 50 volts to 500 volts, and a bias voltage ranging from 50 volts to 500 volts. The anisotropic dry etching process has strong direction selectivity.

[0055] The anisotropic dry etching process has a fast etching rate in the direction perpendicular to the surface of the substrate 200, and can quickly form an initial first groove with a preset depth. The crystal plane of the surface of the substrate 200 is a (100) crystal plane, so that the sidewall of the initial first groove formed by the anisotropic dry etching process is a (110) crystal plane.

[0056] In the embodiment, the second etching process is an isotropic dry etching process, and parameters of the isotropic dry etching process include: a mixed gas of hydrogen and ammonia as the gas, a gas flow range of 20 standard milliliters per minute to 1000 standard milliliters per minute, a gas pressure range of 10 millitorr to 500 millitorr, a power range of 20 watts to 1200 watts, and a voltage range of 50 volts to 500 volts.

[0057] The isotropic dry etching process has weak direction selectivity, can simultaneously etch all directions of the sidewall and the bottom of the initial first groove, and can form the first groove 204 with a large preset width. When a source / drain doping region is formed in the second groove formed after modification, the volume of the source / drain doping region is large, which can generate a large stress on the channel, thereby improving the mobility of the channel carrier.

[0058] Since the isotropic dry etching process simultaneously etches all directions of the sidewall and the bottom of the initial first groove, the isotropic dry etching process has weak direction selectivity, the sidewall of the initial first groove is perpendicular to the surface of the substrate 200, so that the etching rate of the sidewall of the initial first groove by the isotropic dry etching process is uniform, the sidewall of the first groove 204 is consistent with the direction of the sidewall of the initial first groove, and the sidewall of the first groove 204 is a (110) crystal plane perpendicular to the surface of the substrate 200. Since the isotropic dry etching process has weak direction selectivity, the isotropic dry etching process etches the corner between the sidewall and the bottom of the initial first groove, and also etches the bottom of the initial first groove. There is a certain difference in etching rate in different directions, so that the bottom of the first groove 204 formed is a concave arc surface.

[0059] Please refer to Figure 6 The sidewall surface of the first groove 204 is modified to form a second groove 205 and a modified layer 206 on the sidewall surface and the bottom surface of the second groove 205. The thickness d1 of the modified layer 206 at the corner of the sidewall surface and the bottom surface of the second groove 205 is greater than the thickness d2 of the sidewall of the second groove 205.

[0060] The modification process of the sidewall surface of the first groove 204 includes an oxidation process.

[0061] In the embodiment, the oxidation rate along the <111> crystal direction is greater than the oxidation rate along the <100> crystal direction or the <110> crystal direction. Due to the difference in the arrangement density and bonding force of silicon atoms on different crystal planes, the energy required for opening chemical bonds of different crystal planes to form oxides is different under different temperature conditions when the sidewall surface of the first groove 204 is oxidized. Under the conditions in the embodiment, the oxidation rate along the <111> crystal direction is greater than the oxidation rate along the <100> crystal direction or the <110> crystal direction.

[0062] In the embodiment, when the oxidation temperature is greater than 700 ℃, the ratio of the oxidation rate along the <111> crystal direction to the oxidation rate along the <110> crystal direction to the oxidation rate along the <100> crystal direction is 1.3:1.1:1.0.

[0063] The oxidation rate along the <111> crystal direction is greater than the oxidation rate along the <100> crystal direction or the <110> crystal direction. The corner position of the sidewall and the bottom of the first groove 204 is close to the (111) crystal plane, and the sidewall of the first groove 204 is the (110) crystal plane, so that when the sidewall and the bottom of the first groove 204 are modified by the oxidation process, the thickness d1 of the modified layer 206 formed at the corner of the sidewall surface and the bottom surface of the second groove 205 is greater than the thickness d2 of the sidewall of the second groove 205, and more material of the corner of the first groove 204 can be removed when the modified layer 206 is removed, so that the bottom plane of the second groove 205 is parallel to the surface of the substrate 200, thereby obtaining more (100) crystal planes.

[0064] In the embodiment, the oxidation process includes a rapid thermal oxidation process, and the parameters of the rapid thermal oxidation process include: the gas is oxygen or a gas containing oxygen, the gas flow range is 10 standard milliliters per minute to 300 standard milliliters per minute, the temperature range is 700 degrees Celsius to 1100 degrees Celsius, and the pressure range is 20 millitorr to 200 millitorr. The temperature range is 700 degrees Celsius to 1100 degrees Celsius to ensure that the oxidation rate along the <111> crystal direction is greater than the oxidation rate along the <100> crystal direction or the <110> crystal direction.

[0065] In the embodiment, the material of the substrate 200 includes silicon, and the material of the modified layer 206 includes silicon oxide.

[0066] Please refer to Figure 7 , the bottom surface of the second groove 205 is parallel to the surface of the substrate 200, and the corner between the bottom and the sidewall of the second groove 205 is in an arc shape.

[0067] In the embodiment, the process of removing the modified layer 206 includes a wet etching process, and the etching rate of the modified layer 206 is greater than that of the substrate 200. Thus, the wet etching process can remove the modified layer 206 completely, so that the exposed bottom plane of the second groove 205 is parallel to the surface of the substrate 200, and more (100) crystal faces are obtained.

[0068] Since the thickness d1 of the modified layer 206 at the corner of the bottom surface and the sidewall surface of the second groove 205 is greater than the thickness d2 of the sidewall of the second groove 205, when the modified layer 206 is removed, the material of the sidewall surface and the bottom surface of the first groove 204 is also consumed more, which makes the bottom plane of the second groove 205 formed to be substantially parallel to the surface of the substrate 200, and more (100) crystal faces are obtained.

[0069] Please refer to Figure 8 The source-drain doped region 207 is formed in the second groove 205.

[0070] The material of the source-drain doped region 207 includes silicon germanium or phosphorus silicon.

[0071] In the embodiment, the process of forming the source-drain doped region 207 includes an epitaxial growth process.

[0072] Since the bottom plane of the second groove 205 has more (100) crystal faces, when the source-drain doped region 207 is formed in the second groove 205, the material of the source-drain doped region 207 is beneficial to grow on the (100) crystal face, so that the material lattice of the formed source-drain doped region 207 is more regular, the structure of the source-drain doped region 207 after the combination of each crystal lattice has less defects, the stress of the source-drain doped region 207 on the channel can be improved, the mobility of the electron or hole is improved, and the performance of the semiconductor structure is improved.

[0073] Correspondingly, the embodiment of the present application also provides a semiconductor structure, please continue to refer to Figure 8 , comprising:

[0074] The substrate 200;

[0075] The gate structure 201 located on the substrate 200;

[0076] The side wall 202 located on the sidewall of the gate structure;

[0077] The second groove located in the substrate 200 on both sides of the gate structure 201, the second groove is located outside the side wall 202, the bottom surface of the second groove is parallel to the surface of the substrate 200, and the corner between the bottom of the second groove and the sidewall is in an arc shape;

[0078] The source-drain doped region 207 located in the second groove.

[0079] In other embodiments, the substrate further has a fin structure and an isolation structure on the substrate, the isolation structure is located on the sidewall of the fin structure and the top surface of the isolation structure is lower than the top surface of the fin structure; the gate structure is across the fin structure, and the second recess is located in the fin structure on both sides of the gate structure.

[0080] In the embodiment, the material of the source-drain doped region 207 includes silicon germanium or phosphorus silicon.

[0081] The bottom plane of the second recess is (100) crystal plane, so that when the source-drain doped region 207 is formed in the second recess, the material of the source-drain doped region 207 grows on the (100) crystal plane, so that the material lattice of the formed source-drain doped region 207 is more regular, the structure of the source-drain doped region 207 after the combination of each lattice has less defects, the stress of the source-drain doped region 207 on the channel can be improved, the mobility of the electron or hole is improved, and the performance of the semiconductor structure is improved.

[0082] Although the present application has been disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A gate structure is formed on the substrate; A first groove is formed in the substrate on both sides of the gate structure, and the bottom surface of the first groove is a concave arc surface; The surface of the sidewall of the first groove is modified by a thermal oxidation process to form a second groove and a modified layer located on the sidewall and bottom surfaces of the second groove. The thickness of the modified layer at the corner of the sidewall and bottom surfaces of the second groove is greater than the thickness of the sidewall of the second groove. The cross-sectional shape of the first groove is different from that of the second groove. Remove the modified layer from the sidewall surface and bottom surface of the second groove to expose the second groove, the bottom surface of the second groove is parallel to the substrate surface, and the corner between the bottom of the second groove and the sidewall is rounded.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the first groove includes: using the gate structure as a mask, etching the substrate using a first etching process to form an initial first groove in the substrate on both sides of the gate structure; and using a second etching process to etch the sidewalls of the initial first groove to form the first groove.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The first etching process is an anisotropic dry etching process; the parameters of the anisotropic dry etching process include: the gas is a mixture of hydrogen and nitrogen trifluoride, the gas flow rate is in the range of 20 standard milliliters per minute to 1000 standard milliliters per minute, the gas pressure is in the range of 10 millitor to 500 millitor, the power is in the range of 20 watts to 1200 watts, the voltage is in the range of 50 volts to 500 volts, and the bias voltage is in the range of 50 volts to 500 volts.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The second etching process is an isotropic dry etching process; the parameters of the isotropic dry etching process include: the gas is a mixture of hydrogen and ammonia, the gas flow rate is in the range of 20 standard milliliters per minute to 1000 standard milliliters per minute, the gas pressure is in the range of 10 millitor to 500 millitor, the power is in the range of 20 watts to 1200 watts, and the voltage is in the range of 50 volts to 500 volts.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The crystal plane of the substrate surface is (100).

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The parameters of the thermal oxidation process include: the gas is oxygen or a gas containing oxygen, the gas flow rate is in the range of 10 standard milliliters per minute to 300 standard milliliters per minute, the temperature range is 700 degrees Celsius to 1100 degrees Celsius, and the pressure range is 20 millitors to 200 millitors.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The thermal oxidation process along <111> The oxidation rate along the crystal orientation is greater than that along the direction of oxidation. <100> Crystal orientation or <110> Oxidation rate of crystal orientation.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The substrate is made of silicon, and the modified layer is made of silicon oxide.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process for removing the modified layer includes a wet etching process, wherein the etching rate of the modified layer is greater than the etching rate of the substrate.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The depth-to-width ratio of the first groove is in the range of 2 to 5.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: Source / drain doped regions are formed within the second groove.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The source / drain doped regions are made of silicon-germanium or silicon-phosphorus.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process for forming source and drain doped regions includes epitaxial growth.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate also has a fin structure, and the gate structure spans the fin structure.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: Sidewall located on the sidewall of the gate structure; A protective layer located on top of the gate structure.

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