Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the sacrificial layer in the channel stack includes two layers of first sacrificial layer and a second sacrificial layer sandwiched between the two layers of first sacrificial layer, the channel stack of the transistor region is first annealed to improve the diffusion uniformity between the adjacent first and second sacrificial layers, thereby improving the lateral depth uniformity of the inner recess; and the second sacrificial layer and the first sacrificial layer have an etching selectivity ratio, in the process of etching the second sacrificial layer laterally, the first sacrificial layer protects the channel layer, at the same time that the initial inner recess depth meets the requirements, the flatness of the end of the second sacrificial layer and the mixed layer exposed by the initial inner recess is improved; in addition, the interdiffusion ability between the first sacrificial layer and the channel layer is lower than the interdiffusion ability between the first and second sacrificial layers, after the annealing treatment, the thickness of the mixed layer between the adjacent first sacrificial layer and the channel layer is small, the flatness of the inner recess sidewall is improved, and the damage to the channel layer is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. BACKGROUND

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration, and the semiconductor process node is following the development trend of Moore's law and is continuously decreasing. As the most basic semiconductor device, transistors are currently widely used. Therefore, as the element density and integration of semiconductor devices increase, in order to adapt to the reduction of the process node, the channel length of the transistor has to be shortened.

[0003] In order to better adapt to the requirement of device size scaling, semiconductor technology gradually begins to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors and fork sheet transistors. SUMMARY

[0004] The problem solved by embodiments of the present application is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0005] To solve the above problems, the embodiment of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate, including a transistor region, the substrate is provided with an initial stack structure covering the substrate, the initial stack structure is used for forming a stack structure in the transistor region, the initial stack structure comprises one or more stacked channel stacks, the channel stack comprises a sacrificial layer and a channel layer on the sacrificial layer, the sacrificial layer comprises two layers of first sacrificial layers and a second sacrificial layer sandwiched between the two layers of first sacrificial layers, the interdiffusion ability of the materials of the first sacrificial layer and the channel layer is lower than the interdiffusion ability of the materials of the first sacrificial layer and the second sacrificial layer, and the second sacrificial layer and the first sacrificial layer have an etching selectivity ratio; annealing the channel stack of the transistor region; patterning the initial stack structure to form a stack structure on the substrate in the transistor region; forming a gate structure on the substrate after the annealing process, the gate structure crosses the stack structure and covers part of the top and part of the sidewall of the stack structure; forming a source-drain recess in the stack structure on both sides of the gate structure; laterally etching the second sacrificial layer exposed by the source-drain recess in the direction perpendicular to the sidewall of the gate structure to form an initial inner recess connected with the source-drain recess, the initial inner recess is located between adjacent first sacrificial layers; laterally etching the first sacrificial layer exposed by the source-drain recess in the direction perpendicular to the sidewall of the gate structure to make the end of the remaining first sacrificial layer flush with the end of the second sacrificial layer exposed by the initial inner recess, forming an inner recess, the inner recess is located between adjacent channel layers or between the channel layer and the substrate; sequentially forming an inner sidewall in the inner recess and a source-drain doped layer in the source-drain recess.

[0006] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0007] The method for forming a semiconductor structure provided by the embodiment of the present application includes: forming a channel stack layer on a substrate, the channel stack layer including a plurality of stacked channel layers and a plurality of stacked sacrificial layers, the plurality of stacked channel layers including a first channel layer and a second channel layer, the first channel layer and the second channel layer being made of different materials, the plurality of stacked sacrificial layers including a first sacrificial layer and a second sacrificial layer, the first sacrificial layer and the second sacrificial layer being made of different materials, the first sacrificial layer and the second sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the first sacrificial layer having an etching selectivity, and the second sacrificial layer and the first sacrificial layer being arranged in a sandwich manner, the first sacrificial layer and the second channel layer having a lower interdiffusion ability than the first sacrificial layer and the secondIn summary, the embodiment of the present application adopts the second sacrificial layer and the first sacrificial layer with etching selectivity, and performs annealing treatment on the channel stack of the transistor region, and forms the inner groove by sequentially laterally etching the second sacrificial layer and the first sacrificial layer, so as to improve the lateral depth uniformity of the inner groove and the flatness of the sidewall of the inner groove, and correspondingly improve the uniformity of the lateral size of the inner sidewall, so as to improve the uniformity of the capacitance between the gate and the contact plug, and meanwhile, it is beneficial to reduce the probability of damage of the exposed channel layer of the inner groove, and further improve the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figures 1 to 3 is a structure schematic diagram corresponding to each step in an embodiment of a semiconductor structure forming method;

[0009] Figures 4 to 18 is a structure schematic diagram corresponding to each step in an embodiment of a semiconductor structure forming method. DETAILED DESCRIPTION

[0010] At present, the performance of the semiconductor structure still needs to be improved. Now, the reason why the performance needs to be improved is analyzed in combination with a semiconductor structure forming method.

[0011] Figures 1 to 3 is a structure schematic diagram corresponding to each step in an embodiment of a semiconductor structure forming method.

[0012] REFERENCE Figure 1 , a substrate is provided, including a substrate 10 and a fin 11 standing on the substrate 10, a top of the fin 11 is formed with a stack structure 25, the stack structure 25 includes one or more stacked channel stacks 20, the channel stack 20 includes a sacrificial layer 21 and a channel layer 22 located on the sacrificial layer 21, a pseudo gate structure 30 is formed on the substrate and crosses the stack structure 25, and the pseudo gate structure 30 covers part of the top and part of the sidewall of the stack structure 25.

[0013] REFERENCE Figure 2 , the stack structure 25 on both sides of the pseudo gate structure 30 is removed, and a source-drain groove 40 is formed in the stack structure 25 on both sides of the pseudo gate structure 30. The source-drain groove 40 is used to form a source-drain doped layer.

[0014] REFERENCE Figure 3 , the sacrificial layer 21 exposed by a part of the width of the source-drain groove 40 is laterally etched in a direction perpendicular to the sidewall of the gate structure 30, an inner groove 50 connected with the source-drain groove 40 is formed, and the inner groove 50 is located between adjacent channel layers 21 or between the channel layer 21 and the substrate. The inner groove 50 is used to form an inner sidewall.

[0015] In order to reduce damage to the channel layer 22 in the process of etching the sacrificial layer 21, there is usually an etching selectivity ratio between the sacrificial layer 21 and the channel layer 22, that is, the etching process of the sacrificial layer 21 has a relatively large etching rate on the sacrificial layer 21 and a relatively low etching rate on the channel layer 22.

[0016] However, it is found through research that under high-temperature conditions, the adjacent sacrificial layer 21 and the channel layer 22 in the stack structure 25 are prone to inter-material diffusion, thereby forming a mixed layer (not shown in the figure) at the interface between the adjacent sacrificial layer 21 and the channel layer 22. Affected by the sequence of the growth processes of the film layers in the stack structure 25, the film layer that bears more thermal budget has a thicker mixed layer. For example, the sacrificial layer 21 and the channel layer 22 are formed by epitaxy, which has a certain process temperature. In the process of forming the stack structure 25, the formed film layers are affected by the epitaxy process of the subsequent film layers, that is, the film layer closer to the top of the substrate bears more thermal budget, and the mixed layer between the adjacent sacrificial layer 21 and the channel layer 22 has a corresponding larger thickness.

[0017] The mixed layer is formed by inter-material diffusion of the adjacent sacrificial layer 21 and the channel layer 22 at the interface. Correspondingly, the etching rate of the mixed layer by the etching process of the sacrificial layer 21 is usually between the sacrificial layer 21 and the channel layer 22, and is slower than the etching rate of the sacrificial layer 21. In the process of etching the exposed part of the width of the sacrificial layer 21 in the source-drain recess 40 in the lateral direction, the mixed layer also needs to be etched, but is affected by the difference in etching rate of the etching process on the sacrificial layer 21 and the mixed layer. After the formation of the inner recess 50, the U-shaped morphology (as shown in the figure) of the sidewall of the inner recess 50 is easily caused, that is, the flatness of the sidewall of the inner recess 50 is relatively low. Figure 3 In order to improve the flatness of the sidewall of the inner recess 50, the mixed layer can be etched by increasing the etching amount, but this is likely to cause damage to the channel layer 22.

[0018] Moreover, the thickness uniformity of the mixed layer is poor. The film layer closer to the top of the substrate bears more thermal budget, and the mixed layer between the adjacent sacrificial layer 21 and the channel layer 22 has a corresponding larger thickness. In the process of forming the inner recess 50, the etching of the mixed layer with a larger thickness is more difficult, thereby causing poor uniformity of the lateral depth of the inner recess 50, and correspondingly causing poor uniformity of the lateral size of the inner sidewall, and further reducing the uniformity of the capacitance between the gate and the contact plug. For example, as shown in Figure 3As shown, taking an example that the stack structure 25 includes two stacked channel stacks 20, the lateral depth d1 of the inner recess 50 close to the substrate is less than the lateral depth d2 of the inner recess 50 away from the substrate.

[0019] Therefore, there is an urgent need to provide a new forming method to reduce the probability of damage to the exposed channel layer of the inner recess while improving the lateral depth uniformity of the inner recess and the flatness of the sidewall of the inner recess.

[0020] To solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate including a transistor region, the substrate being provided with an initial stack structure covering the substrate, the initial stack structure being used to form a stack structure located in the transistor region, the initial stack structure including one or more stacked channel stacks, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, the sacrificial layer including two layers of first sacrificial layers and a second sacrificial layer sandwiched between the two layers of first sacrificial layers, the material interdiffusion ability of the first sacrificial layer and the channel layer being lower than the material interdiffusion ability of the first sacrificial layer and the second sacrificial layer, and the second sacrificial layer and the first sacrificial layer having an etching selectivity ratio; performing an annealing treatment on the channel stack of the transistor region; patterning the initial stack structure to form a stack structure on the substrate in the transistor region; forming a gate structure on the substrate after the annealing treatment, the gate structure crossing the stack structure and covering part of the top and part of the sidewall of the stack structure; forming a source-drain recess in the stack structure on both sides of the gate structure; laterally etching the second sacrificial layer exposed by a part of the width of the source-drain recess in a direction perpendicular to the sidewall of the gate structure to form an initial inner recess in communication with the source-drain recess, the initial inner recess being located between adjacent first sacrificial layers; laterally etching the first sacrificial layer exposed by a part of the width of the source-drain recess in a direction perpendicular to the sidewall of the gate structure so that the end of the remaining first sacrificial layer is flush with the end of the second sacrificial layer exposed by the initial inner recess to form an inner recess, the inner recess being located between adjacent channel layers or between the channel layer and the substrate; sequentially forming an inner sidewall located in the inner recess and a source-drain doped layer located in the source-drain recess.

[0021] The adjacent film layers in the channel stack are prone to inter-material diffusion at the interface under high temperature conditions, thereby forming a mixed layer at the interface of the adjacent film layers, and the thickness of the mixed layer corresponding to the film layer subjected to more thermal budget is greater due to the sequence of the growth process of each film layer in the channel stack. Therefore, the annealing process is performed first to play a re-diffusion effect, so as to improve the inter-material diffusion uniformity of the adjacent first and second sacrificial layers, thereby improving the thickness uniformity of the mixed layer at the interface of the adjacent first and second sacrificial layers, and correspondingly, the uniformity of the lateral etching amount in the process of forming the initial inner recess is improved, and then the lateral depth uniformity of the inner recess is improved. Moreover, the second sacrificial layer and the first sacrificial layer have an etching selectivity ratio, so that the first sacrificial layer can protect the channel layer in the process of laterally etching the second sacrificial layer, which facilitates the lateral etching of the mixed layer between the second sacrificial layer and the first sacrificial layer, so that the flatness of the end of the second sacrificial layer and the mixed layer exposed by the initial inner recess can be improved while the lateral depth of the initial inner recess meets the process requirement by controlling the etching process. In addition, the inter-material diffusion ability of the first sacrificial layer and the channel layer is lower than that of the first sacrificial layer and the second sacrificial layer, so that the inter-material diffusion mainly occurs at the interface of the first and second sacrificial layers. Therefore, the thickness of the mixed layer at the interface of the adjacent first sacrificial layer and the channel layer is smaller, which makes the influence of the mixed layer between the adjacent first sacrificial layer and the channel layer on the etching process smaller in the process of laterally etching the first sacrificial layer, and the flatness of the inner recess sidewall can be improved and the damage to the channel layer can be reduced under the condition that the first sacrificial layer and the mixed layer between the adjacent first sacrificial layer and the channel layer are laterally etched. At the same time, since the second sacrificial layer and the first sacrificial layer have an etching selectivity ratio, the influence on the sidewall morphology of the initial recess is small during the lateral etching, so as to ensure the flatness of the inner recess sidewall. In summary, the lateral depth uniformity of the inner recess and the flatness of the inner recess sidewall can be improved simultaneously according to the embodiment of the present application, and the lateral size uniformity of the inner sidewall is improved accordingly, so as to improve the uniformity of the capacitance between the gate and the contact plug, and at the same time, the probability of damage to the channel layer exposed by the inner recess is reduced, so as to improve the performance of the semiconductor structure.

[0022] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0023] Figures 4 to 18 is a structure schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application.

[0024] In combination with reference Figure 4 and Figure 5 ,Figure 4 is a top view, Figure 5 is Figure 4 is a cross-sectional view along the AA1 cut line, providing a substrate (not labeled) including a transistor region 100C, the substrate having formed thereon an initial stack structure 205 covering the substrate, the initial stack structure 205 being used to form a stack structure in the transistor region 100C, the initial stack structure 205 including one or more stacked channel stacks 230, the channel stack 230 including a sacrificial layer 210 and a channel layer 220 on the sacrificial layer 210, the sacrificial layer 210 including two layers of a first sacrificial layer 211 and a second sacrificial layer 212 sandwiched between the two layers of the first sacrificial layer 211, the first sacrificial layer 211 and the channel layer 220 having a lower interdiffusion capability than the first sacrificial layer 211 and the second sacrificial layer 212, and the second sacrificial layer 212 and the first sacrificial layer 211 having an etch selectivity.

[0025] The substrate is used to provide a process platform for forming a semiconductor structure. In this embodiment, the semiconductor structure is a Gate-all-around (GAA) transistor. In other embodiments, the semiconductor structure can also be a Forksheet transistor.

[0026] In this embodiment, the substrate includes a substrate 100 and a fin material layer 115 covering the substrate 100. The fin material layer 115 is used to form a fin standing on the substrate 100. In other embodiments, the substrate can also be a planar substrate.

[0027] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0028] In this embodiment, the material of the fin material layer 115 is the same as that of the substrate 300, and the material of the fin material layer 115 is silicon.

[0029] In this embodiment, the substrate includes a transistor region 100C, and during subsequent patterning of the initial stack structure 205, the initial stack structure 205 in the transistor region 100C is retained, thereby forming a strip-shaped stack structure. Specifically, the initial stack structure 205 covers the fin material layer 115.

[0030] The initial stack structure 205 comprises one or more stacked channel stacks 230, each of which comprises a sacrificial layer 210 and a channel layer 220 on the sacrificial layer 210. The stacking direction of the channel stacks 230 is perpendicular to the surface of the substrate 100.

[0031] The channel stacks 230 provide a process basis for the subsequent formation of the suspended channel layers 220.

[0032] Specifically, the sacrificial layer 210 is used to support the channel layer 220, so that after the sacrificial layer 210 is removed, the channel layer 220 can be suspended and spaced. The sacrificial layer 210 also occupies space for the subsequent formation of the device gate structure.

[0033] The channel layer 220 is used to provide a conductive channel of a transistor. The material of the channel layer 220 includes silicon, silicon germanium, germanium, or group III-V semiconductor material. The material of the channel layer 220 is determined according to the channel conductivity type and performance requirements of the transistor.

[0034] Correspondingly, according to the material of the channel layer 220, the material of the sacrificial layer 210 is selected to have an etching selectivity with the channel layer 220, and the material of the sacrificial layer 210 satisfies: the sacrificial layer 210 and the channel layer 220 can be alternately formed. For example, the channel layer 220 can be epitaxially grown on the surface of the sacrificial layer 210, and the sacrificial layer 210 can be epitaxially grown on the surface of the channel layer 220.

[0035] In this embodiment, the sacrificial layer 210 comprises two layers of first sacrificial layers 211 and a second sacrificial layer 212 sandwiched between the two layers of first sacrificial layers 211. The interdiffusion ability between the materials of the first sacrificial layer 211 and the channel layer 220 is lower than the interdiffusion ability between the materials of the first sacrificial layer 211 and the second sacrificial layer 212, and the second sacrificial layer 212 and the first sacrificial layer 211 have an etching selectivity.

[0036] The adjacent film layers in the channel stack 230 are prone to inter-material diffusion at the interface under high-temperature conditions, thereby forming a mixed layer at the interface of the adjacent film layers, for example, a mixed layer at the interface of the adjacent channel layer 220 and the first sacrificial layer 211, and a mixed layer at the interface of the adjacent second sacrificial layer 212 and the first sacrificial layer 211. Therefore, by making the inter-material diffusion capability of the first sacrificial layer 211 and the channel layer 220 lower than the inter-material diffusion capability of the first sacrificial layer 211 and the second sacrificial layer 212, the inter-material diffusion mainly occurs at the interface of the first sacrificial layer 211 and the second sacrificial layer 212, and the thickness of the mixed layer between the adjacent first sacrificial layer 211 and the channel layer 220 is small, which makes the influence of the mixed layer between the adjacent first sacrificial layer 211 and the channel layer 220 on the etching process small in the subsequent lateral etching process of the first sacrificial layer 211, so as to reduce the probability of U-shaped morphology of the inner recess sidewall (i.e., improve the flatness of the inner recess sidewall) and reduce the damage to the channel layer 220 after the lateral etching is completed.

[0037] Moreover, the second sacrificial layer 212 and the first sacrificial layer 211 have an etching selectivity ratio, so as to be able to etch the second sacrificial layer 212 and the first sacrificial layer 211 in sequence in different etching steps.

[0038] It should be noted that, for the convenience of illustration, the mixed layer between the adjacent first sacrificial layer 211 and the channel layer 220, and the mixed layer between the adjacent channel layer 220 and the first sacrificial layer 211 are not shown in the embodiment.

[0039] In the embodiment, the material of the first sacrificial layer 211 includes silicon germanium or a group III-V semiconductor material, and the material of the second sacrificial layer 212 includes germanium, silicon germanium or a group III-V semiconductor material. The materials of the first sacrificial layer 211 and the second sacrificial layer 212 are reasonably selected according to the conditions to be met by the first sacrificial layer 211 and the second sacrificial layer 212, and the material of the channel layer 220.

[0040] As an example, the material of the channel layer 220 is silicon, the material of the first sacrificial layer 211 includes Si 1-x Ge x , and the material of the second sacrificial layer 212 includes Si 1-y Ge y , wherein x < y. That is, the Ge (germanium) concentration in the first sacrificial layer 211 is lower than the Ge concentration in the second sacrificial layer 212.

[0041] In the silicon germanium, the higher the germanium concentration, the faster the etching rate, therefore, by making the germanium concentration in the second sacrificial layer 212 higher, the etching rate of subsequent etching of the second sacrificial layer 212 is increased, and the damage to the first sacrificial layer 211 is reduced, thereby making the etching selectivity between the second sacrificial layer 212 and the first sacrificial layer 211.

[0042] Moreover, the etching selectivity of silicon germanium and silicon is high, and the etching selectivity of germanium and silicon is also high, by selecting Si 1-x Ge x as the material of the first sacrificial layer 211, and selecting Si 1-y Ge y as the material of the second sacrificial layer 212, the impact of the process of etching the sacrificial layer 210 on the channel layer 220 can be effectively reduced, thereby facilitating to ensure the quality of the channel layer 220.

[0043] In the material of the second sacrificial layer 212, the germanium concentration should not be too small, that is, the value of y should not be too small. If the germanium concentration is too small, that is, the value of y is too small, the etching resistance of the second sacrificial layer 212 is too large, the second sacrificial layer 212 is not easy to be etched, thereby easily causing damage to the first sacrificial layer 211 in the process of etching the second sacrificial layer 212, thereby making it difficult to etch the second sacrificial layer 212 and the second sacrificial layer 212 in different steps in sequence, also leading to the protection effect of the first sacrificial layer 211 on the channel layer 220 to be poor. Therefore, in the embodiment, the germanium concentration in the second sacrificial layer 212 is 40% to 100%, that is, in the material Si 1-y Ge y of the second sacrificial layer 212, the value of y is 0.4 to 1.

[0044] The germanium concentration in the first sacrificial layer 211 should not be too low or too high, that is, the value of x should not be too small or too large. If the germanium concentration in the first sacrificial layer 211 is too low, that is, the value of x is too small, it is difficult to obtain a high etching selectivity between the first sacrificial layer 211 and the channel layer 220, and the channel layer 220 is easily damaged in the subsequent etching process of the first sacrificial layer 211. If the germanium concentration in the first sacrificial layer 211 is too high, that is, the value of x is too large, it is easy to cause the material interdiffusion ability between the first sacrificial layer 211 and the channel layer 220 to be too large, thereby causing the thickness of the mixed layer between the adjacent first sacrificial layer 211 and the channel layer 220 to be too large. Accordingly, the mixed layer between the adjacent first sacrificial layer 211 and the channel layer 220 has a greater impact on the etching process when the first sacrificial layer 211 is etched subsequently. After the second lateral etching is completed, the flatness of the inner groove sidewall is easily reduced, and the probability of damage to the channel layer 220 is increased. Moreover, it is also easy to cause the etching selectivity between the second sacrificial layer 212 and the first sacrificial layer 211 to fail to meet the process requirements. Therefore, in the embodiment, the germanium concentration in the first sacrificial layer 211 is 10% to 20%, that is, in the material Si 1-x Ge x of the first sacrificial layer 211, the value of x is 0.1 to 0.2.

[0045] In the embodiment, the material of the channel layer 220 is silicon, the germanium concentration in the first sacrificial layer 211 is 10% to 20%, and the germanium concentration in the second sacrificial layer 212 is 40% to 100%. Therefore, the difference in germanium concentration between the channel layer 220 and the first sacrificial layer 211 is smaller than the difference in germanium concentration between the first sacrificial layer 211 and the second sacrificial layer 212, so that the material interdiffusion ability between the first sacrificial layer 211 and the channel layer 220 is lower than the material interdiffusion ability between the first sacrificial layer 211 and the second sacrificial layer 212.

[0046] In the sacrificial layer 210, the thickness of the single-layer first sacrificial layer 211 should not be too small or too large. If the thickness of the first sacrificial layer 211 is too small, the protection effect of the first sacrificial layer 211 on the channel layer 220 is poor in the subsequent lateral etching process of the second sacrificial layer 212 to form the initial inner groove, thereby increasing the probability of the initial inner groove exposing the bottom surface or the top surface of the channel layer 220, and further increasing the probability of damage to the channel layer 220. If the thickness of the first sacrificial layer 211 is too large, the difficulty of laterally etching the first sacrificial layer 211 is correspondingly increased, which correspondingly easily increases the probability of damage to the channel layer 220 in the lateral etching process of the first sacrificial layer 211. Therefore, in the embodiment, the thickness of the first sacrificial layer 211 is 10 nm to 50 nm. to

[0047] The thickness of the second sacrificial layer 212 in the sacrificial layer 210 should not be too small or too large. If the thickness of the second sacrificial layer 212 is too small, the ratio of the lateral depth to the longitudinal height of the initial inner recess formed will be too large when the second sacrificial layer 212 is laterally etched, which will increase the difficulty of laterally etching the second sacrificial layer 212, and the total thickness of the sacrificial layer 210 is usually a fixed value, which will also correspondingly result in that the thickness of the first sacrificial layer 211 is too large, which will increase the difficulty of laterally etching the first sacrificial layer 211, and further increase the probability of damage to the channel layer 220 in the process of laterally etching the first sacrificial layer 211; if the thickness of the second sacrificial layer 212 is too large, the thickness of the first sacrificial layer 211 will be too small, which will result in that the protection effect of the first sacrificial layer 211 on the channel layer 220 is poor. Therefore, in the embodiment, the thickness of the second sacrificial layer 212 is 10-100 nm, preferably 20-50 nm. to

[0048] In other embodiments, according to the material of the channel layer, the first and second sacrificial layers can also be made of other materials, for example, when the material of the channel layer is silicon germanium, the material of the first sacrificial layer is silicon, and the material of the second sacrificial layer is a group III-V semiconductor material.

[0049] It should be noted that the substrate can include device regions for forming different device types (for example, an NMOS region for forming an NMOS transistor and a PMOS region for forming a PMOS transistor), and therefore, according to the device type in each device region, the material of each film layer in the corresponding channel stack can also be different.

[0050] In the embodiment, the initial stack structure 205 includes three stacked channel stacks 230, which are taken as an example for description. In other embodiments, the channel stack can also be of other quantities.

[0051] In the embodiment, the epitaxial growth process is used to form the sacrificial layer 210 and the channel layer 220, that is, the epitaxial growth process is used to alternately grow the sacrificial layer 210 and the channel layer 220.

[0052] Epitaxial growth allows for better control of process parameters, resulting in high process controllability and making it easier to obtain precise film thickness dimensions. Furthermore, epitaxial growth facilitates the formation of films with fewer impurities, leading to higher film quality in the channel stack 230. In addition, the channel layer 220 is made of silicon, while the first sacrificial layer 211 and the second sacrificial layer 212 are both made of silicon germanide. With these material settings, the sacrificial layer 210 and the channel layer 220 can be grown alternately using epitaxial growth, facilitating the formation of the initial stack structure 205 in the same process.

[0053] It should be noted that the epitaxial process has a certain process temperature, and the adjacent film layers in the channel stack 230 are prone to intermaterial diffusion under high temperature conditions, thereby forming a mixed layer at the interface of adjacent film layers. Furthermore, influenced by the growth sequence of the film layers in the channel stack, the film layer bearing more heat budget corresponds to a thicker mixed layer. Specifically, the film layers in the initial stack structure 205 are stacked sequentially. During the formation of the initial stack structure 205, the already formed film layers are affected by the epitaxial process corresponding to subsequent film layers. That is, the closer the film layer is to the top of the substrate, the greater the impact of the high temperature conditions in the epitaxial process, and the greater the heat budget it bears. Correspondingly, the thicker the mixed layer at the interface of the adjacent first sacrificial layer 211 and second sacrificial layer 212 is, the closer it is to the top of the substrate.

[0054] In this embodiment, during the step of providing the substrate, a hard mask material layer 245 is also formed on the top of the initial stacked structure 205.

[0055] The hard mask material layer 245 is then patterned to form a hard mask layer, which serves as a mask for patterning the initial stacked structure 205.

[0056] The hard mask material layer 245 can be made of silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), amorphous carbon (aC), silicon oxycarbonide (SiOCN), or a stack thereof. In this embodiment, the hard mask material layer 245 is made of silicon nitride.

[0057] refer to Figure 6 For the transistor region 100C (e.g. Figure 4 The channel stack 230 (as shown) is subjected to annealing treatment 235.

[0058] As described above, the adjacent film layers in the channel stack 230 are prone to inter-material diffusion under high-temperature conditions, thereby forming a mixed layer at the interface of the adjacent film layers. The thickness of the mixed layer corresponding to the film layer that bears more thermal budget is greater due to the sequence of the growth process of the film layers in the channel stack. Therefore, the annealing process 235 is performed on the channel stack 230 of the transistor region 100C first to achieve the effect of material re-diffusion, thereby improving the uniformity of the inter-material diffusion degree of the adjacent first and second sacrificial layers 211 and 212 and the thickness uniformity of the mixed layer at the interface of the adjacent first and second sacrificial layers 211 and 212. Subsequently, the second sacrificial layer 212 exposed by the source / drain recess in the direction perpendicular to the sidewall of the gate structure is laterally etched to form an initial inner recess connected to the source / drain recess, and the first sacrificial layer 211 exposed by the source / drain recess is laterally etched so that the end of the remaining first sacrificial layer 211 is flush with the end of the second sacrificial layer 212 exposed by the initial inner recess, thereby forming an inner recess. Accordingly, the thickness uniformity of the mixed layer at the interface of the adjacent first and second sacrificial layers 211 and 212 is improved, which is conducive to improving the uniformity of the lateral etching amount and thereby improving the lateral depth uniformity of the initial inner recess and further improving the lateral depth uniformity of the inner recess.

[0059] It should be noted that, at a fixed annealing temperature, the inter-material diffusion degree of the adjacent film layers at the interface will reach saturation, thereby achieving the effect of improving the uniformity of the diffusion degree.

[0060] It should be further noted that, by performing the annealing process 235 first to improve the thickness uniformity of the mixed layer at the interface of the adjacent film layers, the thickness uniformity of the mixed layer can still be ensured even if subsequent processes are performed under high-temperature conditions, because the film layers in the channel stack 230 are generally affected by the high-temperature conditions in the same way.

[0061] In this embodiment, the annealing process 205 is performed after forming the initial stack structure 205 and before patterning the initial stack structure 205.

[0062] Correspondingly, as an example, the annealing process 205 is performed on the entire initial stack structure 205.

[0063] By performing the annealing process 205 before patterning the initial stack structure 205, the annealing efficiency is improved.

[0064] Specifically, the annealing process 205 is performed after forming the hard mask material layer 245 and before patterning the hard mask material layer 245.

[0065] During the annealing process 205, the hard mask material layer 245 protects the top of the initial stack structure 205, and in particular, the density of the hard mask material layer 245 is generally high, which is beneficial to reduce the probability of damage to the initial stack structure 205 during the annealing process 205, and also beneficial to improve the flexibility of the gas used in the annealing process 205.

[0066] In this embodiment, the annealing process 205 is performed in an atmosphere containing nitrogen-containing gas.

[0067] By selecting nitrogen-containing gas, the influence of the gas used in the annealing process 205 on the channel stack 230 is further reduced (for example, the channel stack 230 is prevented from being oxidized during the annealing process 205), thereby reducing the influence on subsequent processes and facilitating the performance of the channel layer 220.

[0068] Specifically, the nitrogen-containing gas includes one or more of N2, N2O and NH3, thereby improving the process compatibility of the nitrogen-containing gas. As an example, the nitrogen-containing gas is N2.

[0069] It should be noted that the process temperature of the annealing process should not be too low or too high. The process temperature of the annealing process is used to provide the kinetic energy of inter-material diffusion. If the process temperature is too low, the uniformity of the inter-material diffusion degree of the adjacent first and second sacrificial layers 211 and 212 is poor, which is not conducive to improving the thickness uniformity of the mixed layer at the interface between the adjacent first and second sacrificial layers 211 and 212. If the process temperature is too high, the lattice of each film layer in the channel stack 230 is easily damaged, which adversely affects the subsequent processes and the performance of the channel layer 220. In addition, if the process temperature is too high, the inter-material diffusion degree is too large, which not only adversely affects the subsequent processes, but also affects the effective thickness of the channel layer 220, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the process temperature of the annealing process is 500-800 degrees Celsius. For example, the process temperature of the annealing process is 550 degrees Celsius, 600 degrees Celsius, 700 degrees Celsius or 750 degrees Celsius.

[0070] It should be further noted that the annealing process should not be too short or too long. If the process time is too short, it is not enough to provide sufficient time for the material interdiffusion degree of the adjacent first and second sacrificial layers 211 and 212 to be close to the same, thereby adversely affecting the thickness uniformity of the mixed layer between the adjacent first and second sacrificial layers 211 and 212; if the process time is too long, the material interdiffusion degree reaches saturation, which causes waste of process time and cost. Therefore, in the embodiment, the annealing process time is 0.5-5 hours. For example, the annealing process time is 1 hour, 2 hours, 2.5 hours or 3 hours.

[0071] With reference to Figure 7 and Figure 8 , Figure 7 is a top view, Figure 8 is Figure 7 a sectional view along the AA1 cutting line, the initial stack structure 205 is patterned (as shown in Figure 6 ), forming a stack structure 200 (as shown in Figure 4 ) on the base of the transistor region 100C (as shown in Figure 8 ).

[0072] By forming the stack structure 200, the formation position of the transistor is defined, preparing for subsequent formation of the gate structure and source / drain doped layer.

[0073] In the embodiment, after the annealing process 235 (as shown in Figure 6 ) is performed on the transistor region 100C, the hard mask material layer 245 (as shown in Figure 6 ) is patterned before the initial stack structure 205 is patterned, forming a hard mask layer 240.

[0074] The hard mask layer 240 is used as a mask for etching the initial stack structure 205.

[0075] In the embodiment, the hard mask layer 240 is also used to define the stop position of the planarization process in the subsequent formation of the isolation layer, and plays a role in protecting the top of the stack structure 200.

[0076] Specifically, the hard mask material layer 245 can be patterned by single lithography and etching process, self-aligned double patterning (SADP) process, self-aligned quadruple patterning (SAQP) process, or twice lithography and etching process (LELE), etc.

[0077] Correspondingly, the initial stack structure 205 is patterned with the hard mask layer 240 as a mask.

[0078] In this embodiment, the exposed initial stack structure 205 is etched by using an anisotropic etching process (e.g., an anisotropic dry etching process), so as to improve the profile quality and size accuracy of the stack structure 200.

[0079] It is to be noted that the initial stack structure 205 covers the fin material layer 115, and therefore, after the initial stack structure is patterned, the fin material layer 115 is also patterned to form the fin 110 standing on the substrate 100.

[0080] It is to be further noted that the annealing process 235 is performed before the initial stack structure 205 is patterned in this embodiment. In other embodiments, the annealing process can also be performed after the stack structure is formed and before the gate structure is formed.

[0081] In combination with reference to Figure 9 After the annealing process 235, an isolation layer 101 is formed in the base of the side of the stack structure 200, and the isolation layer 101 exposes the stack structure 200.

[0082] The isolation layer 101 is used to achieve electrical isolation between different transistors. Specifically, the isolation layer 101 is a shallow trench isolation structure.

[0083] The material of the isolation layer 101 is an insulating material. As an example, the material of the isolation layer 101 is silicon oxide. Silicon oxide has good insulation and small stress, which is beneficial to improve the process reliability. In other embodiments, the material of the isolation layer can also be silicon oxynitride or other applicable insulating materials.

[0084] In this embodiment, the step of forming the isolation layer 101 in the base of the side of the stack structure 200 includes forming the isolation layer 101 on the substrate 100 of the side of the fin 110, and the isolation layer 101 surrounds the sidewall of the fin 110.

[0085] In this embodiment, the annealing process 235 performed before is a first annealing process 235, and the process of forming the isolation layer 101 includes a second annealing process.

[0086] Specifically, the step of forming the isolation layer 101 comprises: forming an initial isolation layer on the substrate 100 at the side of the fin 110, the initial isolation layer covering the top of the hard mask layer 240; performing a planarization process on the initial isolation layer with the top of the hard mask layer 240 as a stop position; performing a second annealing process on the remaining initial isolation layer after the planarization process; and etching back a partial thickness of the initial isolation layer after the second annealing process to expose the stack structure 200, the remaining initial isolation layer covering the sidewall of the fin 110 as the isolation layer 101.

[0087] In the second annealing process, the density of the initial isolation layer is improved, and the density of the isolation layer is correspondingly improved.

[0088] As an example, before etching back a partial thickness of the initial isolation layer after the first annealing process, the hard mask layer 240 is removed. In other embodiments, the hard mask layer can also be removed after etching back a partial thickness of the initial isolation layer according to process requirements.

[0089] It should be noted that in other embodiments, the second annealing process can be performed on the initial isolation layer before the planarization process.

[0090] It should also be noted that in other embodiments, the channel stack of the transistor region can also be annealed in the annealing step of forming the isolation layer. That is, the first annealing process and the second annealing process are the same step.

[0091] The annealing process of the channel stack in the annealing step of the isolation layer process can save process steps, thereby reducing process cost and improving process efficiency.

[0092] Correspondingly, the annealing temperature can be reasonably set in the process of forming the isolation layer to meet the requirements of the density of the isolation layer and the processing effect of the channel stack.

[0093] Reference Figure 10 After the annealing process 235, a gate structure 300 is formed on the substrate, the gate structure 300 crossing the stack structure 200 and covering part of the top and part of the sidewall of the stack structure 200.

[0094] Specifically, the gate structure 300 is a pseudo gate structure, which occupies a space position for subsequent formation of a device gate structure.

[0095] In this embodiment, the gate structure 300 includes a pseudo gate layer. The material of the pseudo gate layer includes polysilicon, amorphous silicon or amorphous carbon.

[0096] It is to be noted that the gate structure 300 can further include a gate oxide layer between the dummy gate layer and the stack structure 200. As an example, the material of the gate oxide layer is silicon oxide.

[0097] In this embodiment, the forming method further includes: forming a gate sidewall 330 on the sidewall of the gate structure 300. The gate sidewall 330 is used to protect the sidewall of the gate structure 300 and the sidewall of the device gate structure formed later, and is also used to define the forming position of the source / drain doped layer.

[0098] The gate sidewall 330 can be a single-layer structure or a stack structure, and the material of the gate sidewall 330 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon oxynitride, boron nitride, and boron carbon nitride.

[0099] Referring to Figure 11 The source / drain recess 340 is formed in the stack structure 200 on both sides of the gate structure 300.

[0100] The source / drain recess 340 is used to provide a spatial position for the source / drain doped layer formed later, and is also used to provide a process operation basis for laterally etching the second sacrificial layer 212 and the first sacrificial layer 211 to form an inner recess.

[0101] In this embodiment, the bottom of the source / drain recess 340 exposes the fin 110.

[0102] As an example, an anisotropic etching process (for example, a dry etching process) is used to etch the stack structure 200 on both sides of the gate structure 300 to form the source / drain recess 340.

[0103] Correspondingly, after the source / drain recess 340 is formed, the sidewall of the source / drain recess 340 exposes the sacrificial layer 210, thereby preparing for the subsequent lateral etching.

[0104] Referring to Figure 12 The second sacrificial layer 212 exposed by the source / drain recess 340 is laterally etched in a direction perpendicular to the sidewall of the gate structure 300 to form an initial inner recess 350 connected to the source / drain recess 340, and the initial inner recess 350 is located between adjacent first sacrificial layers 211.

[0105] The initial inner recess 350 is formed by laterally etching part of the width of the second sacrificial layer 212, so as to improve the flatness of the end of the second sacrificial layer 212 exposed by the initial inner recess 350 and the flatness of the end of the mixed layer between the adjacent second sacrificial layer 212 and the first sacrificial layer 211, and to prepare for the subsequent lateral etching of part of the width of the first sacrificial layer 211.

[0106] The second sacrificial layer 212 and the first sacrificial layer 211 have an etching selectivity ratio, and the second sacrificial layer 212 exposed by the source-drain recess 340 is first laterally etched by a partial width, and then the first sacrificial layer 211 is laterally etched by a partial width. Therefore, in the process of laterally etching the second sacrificial layer 212, the first sacrificial layer 211 can protect the channel layer 220, which facilitates lateral etching of the mixed layer between the second sacrificial layer 212 and the first sacrificial layer 211, so that the flatness of the end of the second sacrificial layer 212 and the mixed layer exposed by the initial inner recess 350 can be improved by controlling the etching process while the lateral depth of the initial inner recess 350 meets the process requirements. Here, lateral refers to the direction perpendicular to the sidewall of the gate structure 300.

[0107] Moreover, the aforementioned annealing process 235 facilitates improving the uniformity of the diffusion degree between the materials of the adjacent second sacrificial layer 212 and the first sacrificial layer 211, thereby improving the thickness uniformity of the mixed layer between the second sacrificial layer 212 and the first sacrificial layer 211, which correspondingly improves the thickness uniformity of the second sacrificial layer 212. Therefore, in the process of forming the initial inner recess 350, the uniformity of the lateral etching amount can be improved, and the lateral depth uniformity of the initial inner recess 350 can be improved.

[0108] In this embodiment, the isotropic etching process (for example, a wet etching process) is used to laterally etch the second sacrificial layer 212 exposed by the source-drain recess 340 by a partial width.

[0109] In this embodiment, the material of the first sacrificial layer 211 includes Si 1-x Ge x The material of the second sacrificial layer 212 includes Si 1-y Ge y , and x < y, that is, the germanium concentration in the second sacrificial layer 212 is higher than that in the first sacrificial layer 211. Therefore, in the step of laterally etching the second sacrificial layer 212 exposed by the source-drain recess 340 by a partial width, the etching rate of the etching process for the second sacrificial layer 212 with a higher germanium concentration is adjusted by controlling the etching parameters, so that the etching amount of the first sacrificial layer 211 is reduced in the process of laterally etching the second sacrificial layer 212.

[0110] Specifically, the etching selectivity ratio between the second sacrificial layer 212 and the first sacrificial layer 211 can be adjusted by selecting a suitable etching solution or other process parameters.

[0111] It should be noted that in the step of laterally etching the second sacrificial layer 212 exposed by the partial width of the source-drain recess 340, the etching selectivity between the second sacrificial layer 212 and the first sacrificial layer 211 should not be too small. If the etching selectivity between the second sacrificial layer 212 and the first sacrificial layer 211 is too small, in the process of laterally etching the second sacrificial layer 212, the etching rate of the first sacrificial layer 211 is prone to be too large, that is, the etching loss of the first sacrificial layer 211 is prone to be too large, and the uniformity of the etching loss is difficult to control, so it is not conducive to improving the flatness of the inner recess by laterally etching the first sacrificial layer 211, and the protection effect of the first sacrificial layer 211 on the channel layer 220 is also prone to be poor, thereby increasing the probability of damage to the channel layer 220. In the embodiment, in the step of laterally etching the second sacrificial layer 212 exposed by the partial width of the source-drain recess 340, the etching selectivity between the second sacrificial layer 212 and the first sacrificial layer 211 is greater than 8:1.

[0112] It should also be noted that in the step of laterally etching the second sacrificial layer 212 exposed by the partial width of the source-drain recess 340, the minimum residual thickness of the first sacrificial layer 211 should not be too small. If the minimum residual thickness of the first sacrificial layer 211 is too small, the process window of laterally etching the second sacrificial layer 212 is prone to be too small, which is affected by the process stability, and the probability of the bottom surface or the top surface of the channel layer 220 being exposed in the environment of laterally etching the second sacrificial layer 212 and being damaged is correspondingly high. Therefore, in the embodiment, after the second sacrificial layer 212 exposed by the partial width of the source-drain recess 340 is laterally etched, the minimum residual thickness of the first sacrificial layer 211 is greater than That is, after the second sacrificial layer 212 exposed by the partial width of the source-drain recess 340 is laterally etched, it is necessary to ensure that the thickness of the thinnest position of the first sacrificial layer 211 is greater than

[0113] Therefore, in the embodiment, by reasonably setting the etching selectivity between the second sacrificial layer 212 and the first sacrificial layer 211, the formation thickness of the second sacrificial layer 212, and the formation thickness of the first sacrificial layer 211, it is beneficial to ensure that the first sacrificial layer 211 has a large enough residual thickness.

[0114] In the embodiment, in the step of laterally etching the second sacrificial layer 212 exposed by the partial width of the source-drain recess 340, the etching selectivity between the second sacrificial layer 212 and the channel layer 220 is greater than 5:1, thereby increasing the process window of laterally etching the second sacrificial layer 212, for example, even if the bottom surface or the top surface of the channel layer 220 is exposed in the environment of laterally etching the second sacrificial layer 212, the probability of the channel layer 220 being damaged is relatively low.

[0115] The second sacrificial layer 212 and the first sacrificial layer 211 have an etching selectivity ratio, and in the process of laterally etching the second sacrificial layer 212 exposed by the source-drain recess 340 in part of the width, the first sacrificial layer 211 can protect the channel layer 220, so that the etching selectivity ratio between the second sacrificial layer 212 and the channel layer 220 can be appropriately reduced, which correspondingly reduces the limitation on the material selection of each film layer in the channel stack 230, thereby reducing the process difficulty.

[0116] As described above, the interface between the second sacrificial layer 212 and the first sacrificial layer 211 is prone to form a mixed layer (not shown in the figure), so in the process of laterally etching the second sacrificial layer 212 exposed by the source-drain recess 340 in part of the width, the mixed layer between the second sacrificial layer 212 and the first sacrificial layer 211 is also laterally etched. Specifically, by controlling the etching process, the etching of the mixed layer at the contact between the adjacent second sacrificial layer 212 and the first sacrificial layer 211 can be realized.

[0117] In which, due to the high uniformity of the thickness of the mixed layer between the adjacent second sacrificial layer 212 and the first sacrificial layer 211, the flatness of the end of the second sacrificial layer 212 and the mixed layer exposed by the initial inner recess 350, and the lateral depth uniformity of the initial inner recess 350 are improved.

[0118] Reference Figure 13 In the direction perpendicular to the sidewall of the gate structure 300, the first sacrificial layer 211 exposed by the source-drain recess 340 in part of the width is laterally etched, so that the end of the remaining first sacrificial layer 211 is flush with the end of the second sacrificial layer 212 exposed by the initial inner recess 350, forming an inner recess 360, which is located between adjacent channel layers 220, or between the channel layer 220 and the substrate (not labeled).

[0119] The material interdiffusion ability of the first sacrificial layer 211 and the channel layer 220 is lower than the material interdiffusion ability of the first sacrificial layer 211 and the second sacrificial layer 212, so that the material interdiffusion mainly occurs at the interface between the first sacrificial layer 211 and the second sacrificial layer 212. Therefore, the thickness of the mixed layer at the interface between the adjacent first sacrificial layer 211 and the channel layer 220 is small, so that the mixed layer between the adjacent first sacrificial layer 211 and the channel layer 220 has little effect on the etching process during the lateral etching of the partial width of the first sacrificial layer 211. In this way, the probability of the U-shaped morphology of the side wall of the inner recess 360 can be reduced (i.e., the flatness of the side wall of the inner recess 360 is improved) after the lateral etching is completed (i.e., the lateral etching is completed for the first sacrificial layer 211 and the mixed layer between the adjacent first sacrificial layer 211 and the channel layer 220).

[0120] In addition, the thickness uniformity of the mixed layer at the interface between the adjacent first sacrificial layer 211 and the channel layer 220 can also be improved by the aforementioned annealing process 235. Therefore, due to the small thickness of the mixed layer between the adjacent first sacrificial layer 211 and the channel layer 220 and the high thickness uniformity of the mixed layer, the damage to the channel layer 220 can be reduced when the inner recess 360 with a high flatness of the side wall is obtained.

[0121] Meanwhile, since the second sacrificial layer 222 and the first sacrificial layer 211 have an etching selectivity ratio, the etching has little effect on the side wall morphology of the initial recess 350 during the lateral etching, thereby further improving the flatness of the side wall of the inner recess 360.

[0122] In summary, in the embodiment, the sacrificial layer 210 has a stacked structure, the sacrificial layer 210 includes the second sacrificial layer 212 and the first sacrificial layer 211 with an etching selectivity ratio, the first sacrificial layer 211 covers the two opposite surfaces of the second sacrificial layer 212, and the channel layer 230 of the transistor region 100C is subjected to the annealing process 235 (as shown in FIG. 2B). Figure 6 In addition, the inner recess 360 is formed by sequentially laterally etching the second sacrificial layer 212 and the first sacrificial layer 211 in different etching steps, thereby improving the lateral depth uniformity of the inner recess 360 and the flatness of the side wall of the inner recess 360, reducing the probability of damage to the channel layer 220 exposed by the inner recess 360, and improving the performance of the semiconductor structure.

[0123] In the embodiment, the isotropic etching process (for example, a wet etching process) is used to laterally etch the partial width of the first sacrificial layer 211 exposed by the source-drain recess 340.

[0124] In the embodiment, the material of the first sacrificial layer 211 includes Si 1-x Gex The material of the second sacrificial layer 212 comprises Si 1-y Ge y x < y, that is, the concentration of germanium in the second sacrificial layer 212 is higher than that in the first sacrificial layer 211, so in the step of laterally etching the first sacrificial layer 211 exposed by the source / drain recess 340 to a partial width, by controlling the etching parameters, the etching rate of the first sacrificial layer 211 with lower germanium concentration is made greater, so that the etching amount of the second sacrificial layer 212 is reduced in the process of laterally etching the first sacrificial layer 211.

[0125] Specifically, the etching selectivity between the first sacrificial layer 211 and the second sacrificial layer 212 in the process of etching the first sacrificial layer 211 can be adjusted by selecting appropriate etching solution or other process parameters.

[0126] After the first sacrificial layer 211 is laterally etched, the final inner recess 360 is formed, so the etching selectivity between the first sacrificial layer 211 and the second sacrificial layer 212 in the step of laterally etching the first sacrificial layer 211 is higher than that in the step of laterally etching the second sacrificial layer 212. Specifically, the etching selectivity between the second sacrificial layer 212 and the first sacrificial layer 211 in the step of laterally etching the second sacrificial layer 212 is a first value, the etching selectivity between the first sacrificial layer 211 and the second sacrificial layer 212 in the step of laterally etching the first sacrificial layer 211 is a second value, and the second value is greater than the first value.

[0127] It should be noted that the etching selectivity between the first sacrificial layer 211 and the second sacrificial layer 212 in the step of laterally etching the first sacrificial layer 211 exposed by the source / drain recess 340 to a partial width should not be too small. If the etching selectivity between the first sacrificial layer 211 and the second sacrificial layer 212 is too small, the etching rate of the second sacrificial layer 212 is likely to be too large in the process of laterally etching the first sacrificial layer 211, that is, the etching loss of the second sacrificial layer 212 is too large, and the uniformity of the etching loss is difficult to control, so it is not conducive to improving the flatness of the side wall of the inner recess 360. In the embodiment, the etching selectivity between the first sacrificial layer 211 and the second sacrificial layer 212 in the step of laterally etching the first sacrificial layer 211 exposed by the source / drain recess 340 to a partial width is greater than 10:1.

[0128] In the step of etching the first sacrificial layer 211 exposed by the source-drain recess 340 in the embodiment, the etching selectivity between the first sacrificial layer 211 and the channel layer 220 is greater than 5:1, so as to increase the process window of etching the first sacrificial layer 211, and reduce the probability of damaging the channel layer 220 while obtaining the inner recess 360 with high sidewall flatness.

[0129] The thickness of the mixed layer between the adjacent first sacrificial layer 211 and the channel layer 200 is small, and the thickness uniformity of the mixed layer is high, which is beneficial to reduce the process difficulty of obtaining the inner recess 360 with high sidewall flatness and the probability of damaging the channel layer 220, so the etching selectivity between the first sacrificial layer 211 and the channel layer 220 can be appropriately reduced, which correspondingly reduces the limitation on the material selection of each film layer in the channel stack 230, thereby reducing the process difficulty.

[0130] Reference Figure 14 The inner spacer 370 located in the inner recess 360 is formed.

[0131] The inner spacer 370 serves to isolate the subsequently formed device gate structure and source-drain doped layer, increases the distance between the device gate structure and the source-drain doped layer, and is beneficial to reduce the capacitance between the gate and the contact plug. The gate refers to the device gate structure, and the contact plug refers to the plug electrically connected to the source-drain doped layer.

[0132] In the embodiment, the lateral depth uniformity of the inner recess 360 is high, and the sidewall flatness of the inner recess 360 is high, thereby improving the lateral size uniformity of the inner spacer 370, and further improving the uniformity of the capacitance between the gate and the contact plug, and correspondingly improving the performance of the semiconductor structure.

[0133] After the gate structure 300 is removed, the remaining sacrificial layer 210 between the inner spacers 370 also needs to be removed, and the device gate structure surrounding and covering the channel layer 220 is formed, so the lateral depth uniformity of the inner recess 360 is improved, and the width uniformity of the device gate structure between the channel layers 220 and the device gate structure between the channel layer 220 and the substrate is correspondingly improved, thereby further improving the performance of the semiconductor structure.

[0134] Specifically, the step of forming the inner sidewall 370 includes: forming an inner sidewall material layer (not shown in the figure) covering the top and sidewall of the gate structure 300, the sidewall of the channel layer 220, and the top of the substrate and isolation layer 101, the inner sidewall material layer also filling in the inner recess 360; removing the inner sidewall material layer located at the top and sidewall of the gate structure 300, the sidewall of the channel layer 220, and the top of the substrate and isolation layer 101, leaving the inner sidewall material layer located in the inner recess 360 as the inner sidewall 370.

[0135] In the embodiment, an etching process (for example, a maskless etching process) is used to remove the exposed inner sidewall material layer, while the inner sidewall material layer in the inner recess 360 is shielded by the channel layer 220 and is retained.

[0136] The material of the inner sidewall 370 can include one or more of silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) and ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6).

[0137] Reference Figure 15 After the inner sidewall 370 is formed, a source / drain doped layer 380 is formed in the source / drain recess 340 (as shown in Figure 14 .

[0138] The source / drain doped layer 380 is used as a source region or a drain region of a transistor.

[0139] In the embodiment, the source / drain doped layer 380 is formed in the source / drain recess 340 by epitaxial growth.

[0140] Specifically, in a direction perpendicular to the sidewall of the gate structure 300, the source / drain doped layer 380 covers the end of the channel layer 220 and the sidewall of the inner sidewall 370.

[0141] The doping type of the source / drain doped layer 380 is the same as the channel conduction type of the corresponding transistor. When the transistor is a PMOS transistor, the material of the source / drain doped layer 380 includes silicon germanium doped with P-type ions or silicon doped with P-type ions, the P-type ions including B, Ga or In. When the transistor is an NMOS transistor, the material of the source / drain doped layer 380 includes silicon doped with N-type ions or silicon carbide doped with N-type ions, the N-type ions including P, As or Sb.

[0142] Reference Figure 16 In the source / drain recess 340 (as shown in Figure 14After forming the source-drain doped layer 380 in the embodiment, the method further comprises: forming an interlayer dielectric layer 102 on the substrate at the side of the gate structure 300, the interlayer dielectric layer 102 exposing the top of the gate structure 300.

[0143] The interlayer dielectric layer 102 is used to realize electrical isolation between adjacent devices.

[0144] Specifically, the interlayer dielectric layer 102 is formed by using a deposition process and a planarization process (e.g., a chemical mechanical polishing process) in sequence. As an example, the top of the interlayer dielectric layer 102 is flush with the top of the gate structure 300.

[0145] The material of the interlayer dielectric layer 102 is an insulating material. As an example, the material of the interlayer dielectric layer 102 is silicon oxide.

[0146] Referring to Figure 17 After forming the interlayer dielectric layer 102, the gate structure 300 is removed, and a gate opening 391 is formed in the interlayer dielectric layer 102; through the gate opening 391, the sacrificial layer 230 is removed, and a via 392 is formed in communication with the gate opening 391.

[0147] The gate opening 391 and the via 392 are used to provide a spatial position for a device gate structure to be formed subsequently.

[0148] In the embodiment, the gate opening 391 extends across the stack structure 340.

[0149] As described above, the uniformity of the lateral dimension of the inner sidewall 370 of the via 392 is high, and the flatness of the sidewall of the exposed inner sidewall 370 of the via 392 is also high. In the extension direction of the channel layer 220, the lateral dimension of the via 392 is also high, thereby facilitating the improvement of the sidewall profile quality and the uniformity of the lateral dimension of the device gate structure to be formed subsequently in the via 392.

[0150] In the embodiment, the gate structure 300 is removed by using one or both of a dry etching process and a wet etching process.

[0151] In the embodiment, the sacrificial layer 230 is removed by using an isotropic etching process (e.g., a wet etching process). As an example, by reasonably controlling etching parameters, the etching rates of the first sacrificial layer 211 and the second sacrificial layer 212 are made close to each other, and a high etching selectivity between the sacrificial layer 210 and the channel layer 220 is obtained, thereby enabling the first sacrificial layer 211 and the second sacrificial layer 212 to be etched and removed, and reducing the damage to the channel layer 220.

[0152] Referring toFigure 18 A device gate structure 400 is formed in the gate opening 391 (as shown) and the via 392 (as shown), which includes a gate dielectric layer 410 surrounding the channel layer 220, and a gate electrode layer 420 on the gate dielectric layer 410. Figure 17 Figure 17 The device gate structure 400 is used to control the on or off of the conductive channel of the transistor. In this embodiment, the device gate structure 400 is a metal gate structure. In other embodiments, the device gate structure can also be other types of gate structures according to the performance requirements of the transistor.

[0153] The gate dielectric layer 410 is used to isolate the gate electrode layer 420 and the conductive channel. The material of the gate dielectric layer 410 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0154] In this embodiment, the device gate structure 400 is a metal gate structure, therefore, the gate dielectric layer 410 includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0155] It should be noted that the gate dielectric layer 410 can also include a gate oxide layer between the high-k gate dielectric layer and the channel layer 220. For example, the gate oxide layer can include an interface layer (IL). As an example, the material of the gate oxide layer can be silicon oxide.

[0156] The gate electrode layer 420 is used to lead out the electrical property of the device gate structure 400. The material of the gate electrode layer 420 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0157] The gate electrode layer 420 can include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 420 can only include a work function layer. The work function layer is used to adjust the threshold voltage of the formed transistor.

[0158] The gate electrode layer 420 can include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 420 can only include a work function layer. The work function layer is used to adjust the threshold voltage of the formed transistor.

[0159] ​Although the present application has been disclosed with reference to the above embodiments, the application is not limited to the above embodiments. It will be apparent to those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising: The method comprises the following steps: providing a substrate including a transistor region, the substrate having an initial stack structure formed thereon, the initial stack structure being used to form a stack structure on the transistor region, the initial stack structure including one or more stacked channel stacks, the channel stack including a sacrificial layer and a channel layer on the sacrificial layer, the sacrificial layer including two layers of first sacrificial layers and a second sacrificial layer sandwiched between the two layers of first sacrificial layers, the first sacrificial layer and the channel layer having a lower inter-material diffusion capability than the first sacrificial layer and the second sacrificial layer, and the second sacrificial layer and the first sacrificial layer having an etching selectivity ratio; performing an annealing process on the channel stack of the transistor region, the annealing process being used to saturate the inter-material diffusion of adjacent film layers at an interface; patterning the initial stack structure to form a stack structure on the substrate in the transistor region; forming a gate structure on the substrate after the annealing process, the gate structure crossing the stack structure and covering part of the top and part of the sidewall of the stack structure; forming source-drain recesses in the stack structure on both sides of the gate structure; laterally etching the second sacrificial layer exposed by the source-drain recesses in a direction perpendicular to the sidewall of the gate structure to form initial inner recesses connected to the source-drain recesses, the initial inner recesses being located between adjacent first sacrificial layers; laterally etching the first sacrificial layer exposed by the source-drain recesses in a direction perpendicular to the sidewall of the gate structure to make the end of the remaining first sacrificial layer flush with the end of the second sacrificial layer exposed by the initial inner recesses, forming inner recesses located between adjacent channel layers or between the channel layer and the substrate; forming inner sidewalls in the inner recesses and source-drain doped layers in the source-drain recesses in sequence.

2. The method of forming a semiconductor structure of claim 1, wherein, Before the annealing process and before the gate structure is formed on the substrate, the method further comprises forming an isolation layer in the substrate on the side of the stack structure, the isolation layer exposing the stack structure.

3. The method of forming a semiconductor structure of claim 1, wherein, Before the gate structure is formed on the substrate, the method further comprises forming an isolation layer in the substrate on the side of the stack structure, the isolation layer exposing the stack structure. In the annealing step of forming the isolation layer, the channel stack of the transistor region is annealed.

4. The method of forming a semiconductor structure of claim 1, wherein, The sacrificial layer and the channel layer are formed by an epitaxial growth process.

5. The method of forming a semiconductor structure of claim 1, wherein, The annealing process is performed after the initial stack structure is formed and before the initial stack structure is patterned.

6. The method of forming a semiconductor structure of claim 5, wherein, In the step of providing the substrate, a hard mask material layer is further formed on the top of the initial stack structure. After the transistor region is annealed, the method further comprises patterning the hard mask material layer to form a hard mask layer. The initial stack structure is patterned using the hard mask layer as a mask.

7. The method of forming a semiconductor structure of claim 2, wherein, In the step of providing the substrate, the substrate includes a substrate and a fin material layer covering the substrate, and the initial stack structure covers the fin material layer. After patterning the initial stack structure, before forming the gate structure on the substrate, further comprising: patterning the fin material layer to form fins standing on the substrate; The step of forming an isolation layer in the substrate on the side of the stack structure comprises: forming an isolation layer on the substrate on the side of the fins, the isolation layer surrounding the sidewall covering the fins.

8. The method of forming a semiconductor structure of claim 1, wherein, The annealing process is performed in an atmosphere containing nitrogen gas.

9. The method of forming a semiconductor structure of claim 8, wherein, The nitrogen-containing gas comprises one or more of N2, N2O and NH3.

10. The method of forming a semiconductor structure of claim 1, wherein, The parameters of the annealing process comprise: a process temperature of 500-800 degrees Celsius, and a process time of 0.5-5 hours.

11. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the gate structure on the substrate, the gate structure is a dummy gate structure; After forming the source / drain doped layer in the source / drain recess, further comprising: forming an interlayer dielectric layer on the substrate on the side of the gate structure, the interlayer dielectric layer exposing the top of the gate structure; Removing the gate structure to form a gate opening in the interlayer dielectric layer; Through the gate opening, removing the sacrificial layer to form a via communicating with the gate opening; Forming a device gate structure in the gate opening and the via, the device gate structure comprising a gate dielectric layer surrounding the channel layer, and a gate electrode layer on the gate dielectric layer.

12. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, the material of the channel layer comprises silicon, silicon germanium, germanium or a group III-V semiconductor material, the material of the first sacrificial layer comprises silicon germanium or a group III-V semiconductor material, and the material of the second sacrificial layer comprises germanium, silicon germanium or a group III-V semiconductor material.

13. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, the material of the first sacrificial layer includes Si 1-x Ge x , the material of the second sacrificial layer includes Si 1-y Ge y , and x < y.

14. The method of forming a semiconductor structure of claim 13, wherein, The concentration of Ge in the first sacrificial layer is 10-20%, and the concentration of Ge in the second sacrificial layer is 40-100%.

15. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, the thickness of the first sacrificial layer is 20-40 Å, and the thickness of the second sacrificial layer is 40-100 Å.

16. The method of forming a semiconductor structure of claim 1, wherein, After laterally etching the second sacrificial layer exposed by the source / drain recess in a direction perpendicular to the sidewall of the gate structure by a partial width, the minimum remaining thickness of the first sacrificial layer is greater than 10 Å.

17. The method of forming a semiconductor structure of claim 1, wherein, In the step of laterally etching the second sacrificial layer exposed by the source / drain recess in a direction perpendicular to the sidewall of the gate structure by a partial width, the etching selectivity ratio between the second sacrificial layer and the channel layer is greater than 5:

1. In the step of laterally etching the first sacrificial layer exposed by the source / drain recess in a direction perpendicular to the sidewall of the gate structure by a partial width, the etching selectivity ratio between the first sacrificial layer and the channel layer is greater than 5:

1.

18. The method of forming a semiconductor structure of claim 1, wherein, In the step of laterally etching the second sacrificial layer exposed by the source / drain recess in a direction perpendicular to the sidewall of the gate structure by a partial width, the etching selectivity ratio between the second sacrificial layer and the first sacrificial layer is greater than 8:

1.

19. The method of forming a semiconductor structure of claim 1, wherein, In the step of laterally etching the first sacrificial layer exposed by the source / drain recess in a direction perpendicular to the sidewall of the gate structure by a partial width, the etching selectivity ratio between the first sacrificial layer and the second sacrificial layer is greater than 10:

1.

20. The method of forming a semiconductor structure of claim 11, wherein, In the step of forming a device gate structure in the gate opening and the via, the material of the gate dielectric layer comprises one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3, and the material of the gate electrode layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

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