A MOM capacitor and integrated circuit

Abstract

This invention relates to a MOM capacitor and an integrated circuit, comprising an upper electrode assembly and a lower electrode assembly with mirror-symmetrical electrode patterns. The upper electrode assembly includes a first main electrode and a second interdigital electrode separated from each other, and the lower electrode assembly includes a second main electrode and a first interdigital electrode separated from each other. The first and second main electrodes are serpentine in shape and include multiple gaps. The second interdigital electrode is disposed at the gap of the first main electrode, and the first interdigital electrode is disposed at the gap of the second main electrode. The upper and lower electrode assemblies include a first end and a second end, and the first and second interdigital electrodes are flush with each other at either the first or second end. The projection of the first main electrode onto the lower electrode assembly partially coincides with the projection of the second main electrode, and the projection of the second interdigital electrode onto the lower electrode assembly partially coincides with the projection of the first interdigital electrode. This invention can improve the capacitance per unit area of ​​the MOM capacitor.

Description

Technical Field

[0001] This invention relates to the field of electronic components technology, specifically to a MOM capacitor and an integrated circuit. Background Technology

[0002] Capacitors are commonly used electronic components in integrated circuits and are an important building block. They are widely used in chips for memory, microwave, radio frequency, smart cards, high voltage, and filtering. MOM (metal-oxide-metal) capacitors are a common capacitor structure. MOM capacitors are also crucial components in many integrated circuits, significantly optimizing their performance.

[0003] Existing MOM capacitors typically feature comb-like metal interdigitates arranged with alternating polarities in the vertical direction, with interdigitates of the same polarity connected to metal electrodes. This structural design results in low space utilization and a small capacitance per unit area for MOM capacitors. Summary of the Invention

[0004] Based on the above situation, in order to solve the problems of low space utilization and small capacitance per unit area of ​​MOM capacitors, the main objective of this invention is to provide a MOM capacitor and integrated circuit that can improve the space utilization and capacitance per unit area of ​​MOM capacitors.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A MOM capacitor includes at least two electrode assemblies, wherein the two electrode assemblies are an upper electrode assembly and a lower electrode assembly stacked and spaced apart, the upper electrode assembly and the lower electrode assembly are parallel to each other, and the electrode pattern of the upper electrode assembly is mirror-symmetrical to the electrode pattern of the lower electrode assembly.

[0007] The upper electrode assembly includes a first main electrode and a plurality of second interdigital electrodes that are separated from each other, and the lower electrode assembly includes a second main electrode and a plurality of first interdigital electrodes that are separated from each other; the first main electrode and the first interdigital electrodes are connected, and the second main electrode and the second interdigital electrodes are connected.

[0008] Both the first main electrode and the second main electrode are serpentine in shape, and the serpentine shape includes multiple gaps. A second interdigital electrode is disposed at each gap of the first main electrode; a first interdigital electrode is disposed at each gap of the second main electrode; both the upper electrode assembly and the lower electrode assembly include opposing first and second ends, and the first main electrode and the second interdigital electrode are flush with each other at the first end or the second end; the second main electrode and the first interdigital electrode are flush with each other at the first end or the second end.

[0009] The projection of the first main electrode on the lower electrode assembly partially overlaps with that of the second main electrode, and the projection of the second interdigital electrode on the lower electrode assembly partially overlaps with that of the first interdigital electrode.

[0010] Preferably, the first main electrode includes a first longitudinal electrode extending along a first direction and a first transverse electrode extending along a second direction, the first longitudinal electrode and the first transverse electrode being alternately connected to form the serpentine shape; the first direction is perpendicular to the second direction;

[0011] The second main electrode includes a second longitudinal electrode extending along a first direction and a second transverse electrode extending along a second direction, the second longitudinal electrode and the second transverse electrode being alternately connected to form the serpentine shape;

[0012] The first lateral electrode and the second lateral electrode are located at the first end or the second end;

[0013] The first interdigital electrode and the second interdigital electrode extend along a first direction at the gap;

[0014] The projection of the first longitudinal electrode within the lower electrode assembly completely coincides with that of the second longitudinal electrode.

[0015] Preferably, the planar area of ​​the first longitudinal electrode and the second interdigital electrode is A, and the area of ​​the projection of the first longitudinal electrode and the second interdigital electrode onto the lower electrode assembly that overlaps with the electrode pattern of the lower electrode assembly is B, where B>0.9A.

[0016] Preferably, the first lateral electrode is electrically connected to the first interdigital electrode located directly below it via a conductive material;

[0017] The second lateral electrode is electrically connected to the second interdigital electrode located directly above it via a conductive material.

[0018] Preferably, the first lateral electrode and the first interdigital electrode located directly below it have through holes, and the second lateral electrode and the second interdigital electrode located directly above it also have through holes. The conductive material is disposed in the through holes, and the extension direction of the conductive material is perpendicular to the first direction and the second direction.

[0019] Preferably, the dimension L1 of the first lateral electrode in the first direction is greater than the dimension L1' of the first interdigitated electrode in the second direction;

[0020] The dimension L2 of the second lateral electrode in the first direction is greater than the dimension L2' of the second interdigital electrode in the second direction;

[0021] Where L1 = (1.5-3)L1', L2 = (1.5-3)L2'.

[0022] Preferably, the dimensions L1' of the first interdigitated electrode in the second direction and the dimensions L2' of the second interdigitated electrode in the second direction are both 50nm-70nm;

[0023] And / or, the distance D1 between the first interdigital electrode and the first main electrode and the distance D2 between the second interdigital electrode and the second main electrode are both 50nm-70nm.

[0024] Preferably, the first lateral electrode, the second lateral electrode, the first longitudinal electrode, the second longitudinal electrode, the first interdigitated electrode, and the second interdigitated electrode are all linear in shape.

[0025] Preferably, the number of electrode assemblies is several blocks, the several electrode assemblies are stacked and spaced apart, and the electrode pattern and connection relationship of any two adjacent electrode assemblies are the same as the electrode pattern and connection relationship of the upper electrode assembly and the lower electrode assembly.

[0026] Preferably, the MOM capacitor further includes an insulating dielectric layer, in which each of the electrode components is embedded to isolate the upper electrode components and the lower electrode components, the first main electrode and the second interdigital electrode in the same upper electrode component, and the second main electrode and the first interdigital electrode in the same lower electrode component.

[0027] Preferably, the MOM capacitor further includes: the MOM capacitor further includes terminals, the terminals being disposed at the first lateral electrode and / or the second lateral electrode.

[0028] Preferably, the MOM capacitor further includes terminals disposed at the first end or the second end, and disposed at the free ends of adjacent first longitudinal electrodes and second interdigital electrodes or disposed at the free ends of adjacent second longitudinal electrodes and first interdigital electrodes.

[0029] Preferably, the MOM capacitor further includes a first terminal and a second terminal, wherein the first terminal and the second terminal are disposed on the same side or opposite side of the same electrode assembly, or on the same side or different sides of different electrode assemblies.

[0030] To further address the aforementioned technical problems, the present invention also provides an integrated circuit, comprising the aforementioned MOM capacitor and a plurality of electronic components, wherein at least a portion of the MOM capacitor and the electronic components are electrically connected.

[0031] Preferably, the MOM capacitor is connected to the electronic component via a first trace and a second trace, wherein the length difference between the first trace and the second trace is less than the height of the MOM capacitor.

[0032] Preferably, the integrated circuit is designed with a process of 28nm-40nm, and the width of the first interdigital electrode and the second interdigital electrode in the MOM capacitor is 50nm-70nm.

[0033] And / or, the distance between the first interdigital electrode and the second main electrode and the distance between the second interdigital electrode and the first main electrode are 50nm-70nm.

[0034] The beneficial effects of the present invention are as follows: The electrode assembly in the MOM capacitor provided by the present invention is divided into an upper electrode assembly and a lower electrode assembly. The upper electrode assembly and the lower electrode assembly are parallel to each other. The electrode pattern of the upper electrode assembly is mirror-symmetrical to the electrode pattern of the lower electrode assembly. The front and back sides of the same electrode assembly can be used as the upper electrode assembly and the lower electrode assembly respectively, which can simplify the manufacturing process of the electrode assembly. The upper electrode assembly includes a first main electrode and multiple second interdigital electrodes that are separated from each other, and the lower electrode assembly includes a second main electrode and multiple first interdigital electrodes that are separated from each other. The first main electrode and the first interdigital electrodes are connected, and the second main electrode and the second interdigital electrodes are connected. Both the first main electrode and the second main electrode are serpentine in shape, and the serpentine shape includes multiple gaps. A second interdigital electrode is disposed at each gap of the first main electrode. A first interdigital electrode is disposed at each gap of the second main electrode. The projection of the first main electrode on the lower electrode assembly partially overlaps with the second main electrode, and the projection of the second interdigital electrode on the lower electrode assembly partially overlaps with the first interdigital electrode. With the above structure, a part of an electrode is located in the upper electrode assembly and another part is located in the lower electrode assembly, which can enhance the mutual coupling area between the two electrodes distributed vertically. Placing the interdigital electrodes in the gaps of the serpentine main electrodes can enable the interdigital electrodes to couple with the main electrodes in three directions, thereby significantly improving the capacitance per unit area of ​​the MOM capacitor. The first main electrode and the second interdigital electrode are both flush with each other at either the first or the second end; the second main electrode and the first interdigital electrode are both flush with each other at either the first or the second end, so that the interdigital electrode can extend as much as possible, further increasing the coupling area with the main electrode and improving the capacitance of the capacitor.

[0035] Other beneficial effects of the present invention will be explained in detail through the introduction of specific technical features and technical solutions in specific embodiments. Those skilled in the art should be able to understand the beneficial technical effects brought about by these technical features and technical solutions through the introduction of these technical features and technical solutions. Attached Figure Description

[0036] A preferred embodiment of the MOM capacitor of the present invention will now be described with reference to the accompanying drawings. In the drawings:

[0037] Figure 1 This is a side view of one embodiment of a MOM capacitor according to a preferred embodiment of the present invention.

[0038] Figure 2 Another embodiment of the MOM capacitor, which is a preferred embodiment of the present invention, is shown as a side view of multiple electrode assemblies.

[0039] Figure 3This is a three-dimensional structural schematic diagram of an embodiment of the MOM capacitor according to a preferred embodiment of the present invention.

[0040] Figure 4A This is a top view of the upper electrode assembly of an embodiment of a MOM capacitor according to a preferred embodiment of the present invention.

[0041] Figure 4B This is a top view of the lower electrode assembly of an embodiment of a MOM capacitor according to a preferred embodiment of the present invention.

[0042] Figure 5 This is a front view showing the conductive material of one embodiment of the MOM capacitor according to a preferred embodiment of the present invention.

[0043] Figure 6A This is a top view of the upper electrode assembly of another embodiment of the MOM capacitor, which is a preferred embodiment of the present invention.

[0044] Figure 6B This is a top view of the lower electrode assembly of another embodiment of the MOM capacitor, which is a preferred embodiment of the present invention.

[0045] Figure 7A This is a top view of the upper electrode assembly of another embodiment of the MOM capacitor, which is a preferred embodiment of the present invention.

[0046] Figure 7B This is a top view of the lower electrode assembly of another embodiment of the MOM capacitor, which is a preferred embodiment of the present invention.

[0047] Figure 8A This is a top view of the upper electrode assembly of another embodiment of the MOM capacitor, which is a preferred embodiment of the present invention.

[0048] Figure 8B This is a top view of the lower electrode assembly of another embodiment of the MOM capacitor, which is a preferred embodiment of the present invention.

[0049] Figure 9A This is a top view of the upper electrode assembly of another embodiment of the MOM capacitor, which is a preferred embodiment of the present invention.

[0050] Figure 9B This is a top view of the lower electrode assembly of another embodiment of the MOM capacitor, which is a preferred embodiment of the present invention.

[0051] Figure 10A This is a top view of the upper electrode assembly of another embodiment of the MOM capacitor, which is a preferred embodiment of the present invention.

[0052] Figure 10B This is a top view of the lower electrode assembly of another embodiment of the MOM capacitor, which is a preferred embodiment of the present invention. Detailed Implementation

[0053] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail, but well-known methods, processes, procedures, and elements are not described in detail in order to avoid obscuring the essence of the present invention.

[0054] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0055] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than exclusive or exhaustive; that is, they mean "including but not limited to."

[0056] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0057] A MOM capacitor includes at least two electrode assemblies, which are an upper electrode assembly and a lower electrode assembly stacked and spaced apart. The upper electrode assembly and the lower electrode assembly are parallel to each other, and the electrode pattern of the upper electrode assembly is mirror-symmetrical to the electrode pattern of the lower electrode assembly.

[0058] The upper electrode assembly includes a first main electrode and a plurality of second interdigital electrodes that are separated from each other, and the lower electrode assembly includes a second main electrode and a plurality of first interdigital electrodes that are separated from each other; the first main electrode and the first interdigital electrodes are connected, and the second main electrode and the second interdigital electrodes are connected.

[0059] Both the first main electrode and the second main electrode are serpentine in shape, and the serpentine shape includes multiple gaps. A second interdigital electrode is disposed at each gap of the first main electrode; a first interdigital electrode is disposed at each gap of the second main electrode; both the upper electrode assembly and the lower electrode assembly include opposing first and second ends, and the first main electrode and the second interdigital electrode are flush with each other at either the first or the second end; the second main electrode and the first interdigital electrode are flush with each other at either the first or the second end.

[0060] The projection of the first main electrode on the lower electrode assembly partially overlaps with that of the second main electrode, and the projection of the second interdigital electrode on the lower electrode assembly partially overlaps with that of the first interdigital electrode.

[0061] Reference Figure 1 This invention provides a MOM capacitor, comprising two electrode components 1, which are an upper electrode component 2 and a lower electrode component 3 stacked and spaced apart. The upper electrode component 2 and the lower electrode component 3 are parallel to each other, and the electrode pattern of the upper electrode component 2 is mirror-symmetrical to the electrode pattern of the lower electrode component 3. The upper electrode component 2 and the lower electrode component 3 with mirror-symmetrical electrode patterns can be formed using the same front and back sides of the electrode component 1, thereby reducing the cost of manufacturing the electrode component 1. The upper electrode component 2 and the lower electrode component 3 form a MOM capacitor.

[0062] Reference Figure 2 In another embodiment, the number of electrode components 1a is at least two, so the number of electrode components 1a can also be three, four, five, or even more. Several electrode components 1a are stacked and spaced apart, and the electrode patterns and connections between any two adjacent electrode components 1a are the same as the electrode patterns and connections between the upper electrode component 2a and the lower electrode component 3a. It can be understood that the number of electrode components 1a can be adjusted according to the specific application requirements of the MOM capacitor.

[0063] Reference Figure 3 , Figure 4A and Figure 4B The upper electrode assembly 2 includes a first main electrode 21 and a plurality of second interdigitated electrodes 22 separated from each other. The second interdigitated electrodes 22 are connected to a portion of the electrode pattern (hereinafter referred to as the second main electrode 31) in the lower electrode assembly 3. The first main electrode 21 is serpentine in shape. It can be understood that the serpentine shape is a generally S-shaped, meandering shape, such as a wave shape or a square wave shape. The serpentine first main electrode 21 includes a plurality of gaps 211. Specifically, there are multiple gaps 211 (at least two in this invention), and the number of gaps 211 is determined by the extension length of the first main electrode 21. In this embodiment, two gaps 211 are used as an example for explanation. A second interdigitated electrode 22 is provided at each gap 211 of the first main electrode 21.

[0064] The lower electrode assembly 3 includes a second main electrode 31 and a plurality of first interdigital electrodes 32 separated from each other. The first interdigital electrodes 32 are connected to the first main electrode 21, and the second interdigital electrodes 22 are connected to the second main electrode 31. The second main electrode 31 is also serpentine in shape and includes a plurality of gaps 311. Specifically, there are a plurality of gaps 311 (at least two in this invention). In this embodiment, two gaps 311 are used as an example for explanation. A first interdigital electrode 32 is provided at each gap 311 of the second main electrode 31.

[0065] The first main electrode 21 includes a first longitudinal electrode 212 extending along a first direction x and a first transverse electrode 213 extending along a second direction y. The first longitudinal electrode 212 and the first transverse electrode 213 are alternately connected to form a serpentine shape, and the first longitudinal electrode 212 and the first transverse electrode 213 are perpendicular. Specifically, the first direction x and the second direction y are perpendicular, meaning the first longitudinal electrode 212 and the first transverse electrode 213 are vertically arranged. The upper electrode assembly 2 also includes a first end 23 and a second end 24 disposed opposite to each other. The first transverse electrode 213 is located at the first end 23 or the second end 24, and the second interdigital electrode 22 is located at the gap 211 extending along the first direction x, meaning the second interdigital electrode 22 is perpendicular to the first transverse electrode 213. The second interdigital electrode 22 and the first main electrode 21 are flush with each other at the first end 23 or the second end 24. It can be understood that the free end of the second interdigital electrode 22 is flush with the first main electrode 21. By employing a serpentine-shaped first main electrode 21, the second interdigital electrode 22 can be positioned within the serpentine gap 211, allowing the second interdigital electrode 22 to be surrounded by the first main electrode 21 in three directions. This results in coupling with the first main electrode 21 in three directions within the horizontal plane formed by the first direction x and the second direction y. The second interdigital electrode 22 extends to the edge of the first end 23 or the second end 24 of the first main electrode 21 and is flush with the first main electrode 21, increasing the area of ​​the coupling region between the second interdigital electrode 22 and the first main electrode 21. This fully utilizes the space between the first end 23 and the second end 24 of the first main electrode 21, thereby increasing the capacitance per unit area of ​​the MOM capacitor.

[0066] The second main electrode 31 includes a second longitudinal electrode 312 extending along a first direction x and a second transverse electrode 313 extending along a second direction y. The second longitudinal electrode 312 and the second transverse electrode 313 are alternately connected to form a serpentine shape, and the second longitudinal electrode 312 and the second transverse electrode 313 are perpendicular to each other. Specifically, the lower electrode assembly 3 also includes a first end 33 and a second end 34 disposed opposite to each other. The second transverse electrode 313 is located at the first end 33 or the second end 34, and the first interdigital electrode 32 is located at the gap 311 and extends along the first direction x. That is, the first interdigital electrode 32 is disposed perpendicular to the second transverse electrode 313, and the first interdigital electrode 32 and the second main electrode 31 are disposed flush with the first end 33 or the second end 34. It can be understood that the free end of the first interdigital electrode 32 is disposed flush with the second main electrode 31. By employing a serpentine second main electrode 31, the first interdigital electrode 32 can be surrounded by the second main electrode 31 in three directions, thereby forming coupling with the second main electrode 31 in three directions within the horizontal plane formed by the first direction x and the second direction y. The first interdigital electrode 32 extends to the edge of the first end 33 or the second end 34 of the second main electrode 31, increasing the area of ​​the coupling region between the first interdigital electrode 32 and the second main electrode 31, making full use of the space between the first end 33 and the second end 34 of the second main electrode 31, and improving the capacitance of the MOM capacitor.

[0067] The serpentine shape of the first main electrode 21 and the second main electrode 31 increases the number of positions where the MOM capacitor can be used as a lead-out terminal. That is, both ends of the first main electrode 21 and the second main electrode 31 can be used for lead-out, increasing the number of positions where the MOM capacitor can be used to connect lines and improving the flexibility of MOM capacitor wiring.

[0068] The projection of the first longitudinal electrode 212 within the lower electrode assembly 3 completely coincides with the second longitudinal electrode 312, and the projection of the second interdigital electrode 22 on the lower electrode assembly 3 partially coincides with the first interdigital electrode 32. The portion where the projection of the first main electrode 21 onto the plane containing the second main electrode 31 coincides with the second main electrode 31, and the portion where the projection of the first interdigital electrode 32 onto the plane containing the second interdigital electrode 22 coincides with the second interdigital electrode 22, enables the upper electrode assembly 2 and the lower electrode assembly 3 to couple in the vertical direction (the vertical direction is the direction from which the upper electrode assembly 2 faces the lower electrode assembly 3), further increasing the capacitance of the MOM capacitor. It can be understood that the projection of the first longitudinal electrode 212 within the lower electrode assembly 3 does not need to completely coincide with the second longitudinal electrode 312; as long as the projection of the first main electrode 21 onto the lower electrode assembly 3 partially coincides with the second main electrode 31, the effect of increasing the capacitance value of the MOM capacitor can be achieved.

[0069] As one embodiment, the planar area of ​​the first vertical electrode 212 and the second interdigital electrode 22 is A, and the area where the projections of the first vertical electrode 212 and the second interdigital electrode 22 on the lower electrode assembly 3 overlap with the electrode pattern of the lower electrode assembly 3 is B, where B > 0.9A. By increasing the area where the projections of the first vertical electrode 212 and the second interdigital electrode 22 on the lower electrode assembly 3 overlap with the electrode pattern of the lower electrode assembly 3, the coupling area in the vertical direction between the upper electrode assembly 2 and the lower electrode assembly 3 can be increased, thereby increasing the capacitance of the MOM capacitor. It is understood that the area B where the projections of the first vertical electrode 212 and the second interdigital electrode 22 on the lower electrode assembly 3 overlap with the electrode pattern of the lower electrode assembly 3 is not necessarily within the above range. Even if B is equal to or slightly less than 0.9A, the upper electrode assembly 2 and the lower electrode assembly 3 still have a coupling area in the vertical direction. That is, the area B where the projections of the first vertical electrode 212 and the second interdigital electrode 22 on the lower electrode assembly 3 overlap with the electrode pattern of the lower electrode assembly 3 can be changed according to the specific structure of the MOM capacitor.

[0070] In one embodiment, the planar area of ​​the first main electrode 21 and the second interdigital electrode 22 is A', and the area of ​​the region where their projections onto the lower electrode assembly 3 overlap with the electrode pattern of the lower electrode assembly 3 is B', where B' > 0.7A'. The area of ​​the overlapping electrode pattern increases the coupling area between the upper electrode assembly 2 and the lower electrode assembly 3 in the vertical direction, thereby increasing the capacitance of the MOM capacitor.

[0071] As one embodiment, refer to Figure 3 and Figure 5 The first lateral electrode 213 is electrically connected to the first interdigital electrode 32 located directly below it via a conductive material 4; the second lateral electrode 313 is electrically connected to the second interdigital electrode 22 located directly above it via a conductive material 4, the extension direction of the conductive material 4 being perpendicular to the first direction x and the second direction y. Specifically, the first lateral electrode 213 and the first interdigital electrode 32 located directly below it have through holes 5, and the conductive material 4 is disposed in the through holes 5. Similarly, the second lateral electrode 313 and the second interdigital electrode 22 located directly above it have through holes 5, and the conductive material 4 is disposed in the through holes 5. It can be understood that the specific arrangement structure of the conductive material 4 is not limited, as long as it can achieve the electrical connection between the upper electrode assembly 2 and the lower electrode assembly 3.

[0072] As another embodiment, refer to Figure 6A and Figure 6BThe first lateral electrode 213b has a dimension L1 in the first direction x that is larger than the dimension L1' of the first interdigital electrode 32b in the second direction y. Preferably, L1 = (1.5-3)L1'. The second lateral electrode 313b has a dimension L2 in the first direction x that is larger than the dimension L2' of the second interdigital electrode 22b in the second direction y. Preferably, L2 = (1.5-3)L2'. The larger width of the lateral electrodes facilitates the creation of through holes (not shown in the figure) on the surface of the electrodes to fix conductive material. It is understood that the relationship between the dimensions of the first lateral electrode 213b in the first direction and the first interdigital electrode 32b in the second direction y, and the relationship between the dimensions of the second lateral electrode 313b in the first direction x and the second interdigital electrode 22b in the second direction y, can also be other ranges, which can be changed according to the specific structure of the MOM capacitor.

[0073] As one embodiment, the MOM capacitor is integrated within the chip. When the chip operates in a low-voltage environment and meets the process design conditions, the width of the interdigitated electrodes (first interdigitated electrode, second interdigitated electrode) and the spacing between the interdigitated electrodes and the main electrodes (first main electrode and second main electrode) are taken as the minimum values ​​designed in the process, so that the capacitance value reaches its maximum value within a certain size range. As another embodiment, during layout design, a voltage less than 1.2V for the MOM capacitor is considered low voltage. At this voltage, if a 28nm design process is used, the dimensions L1' of the first interdigitated electrode 32 in the second y-direction and L2' of the second interdigitated electrode 22 in the second y-direction can be set to a minimum of 50nm; if a 40nm design process is used, the dimensions L1' of the first interdigitated electrode 32 in the second y-direction and L2' of the second interdigitated electrode 22 in the second y-direction can be set to a minimum of 70nm. Setting L1' and L2' to the minimum dimensions under the given design process ensures that the capacitance value reaches its maximum value within a certain size range.

[0074] As one embodiment, when the integrated circuit using MOM capacitors is operating at low voltage, if a 28nm design process is used, the minimum distance D1 between the first interdigital electrode 32 and the second main electrode 31, and the minimum distance D2 between the second interdigital electrode 22 and the first main electrode 21 can be set to 50nm; if a 40nm design process is used, the minimum distance D1 between the first interdigital electrode 32 and the second main electrode 31, and the minimum distance D2 between the second interdigital electrode 22 and the first main electrode 21 can be set to 70nm; setting D1 and D2 to the minimum size under the current design process allows the capacitance value to reach its maximum value within a certain size range.

[0075] As one example, when an integrated circuit using MOM capacitors is operating at low voltage, if a 28nm design process is used, L1', L2', D1, and D2 can all be set to a minimum size of 50nm; if a 40nm design process is used, L1', L2', D1, and D2 can all be set to a minimum size of 70nm. Setting L1', L2', D1, and D2 to the minimum size of the design process ensures that the capacitance value reaches its maximum within a certain size range. It can be understood that when the design process is between 28nm and 40nm, the dimensions of L1', L2', D1, and D2 can also change within the range of 50nm to 70nm depending on the design process, so that the capacitance value reaches its maximum within a certain size range.

[0076] In one embodiment, the width of the first longitudinal electrode 212 is the same as the width of the second interdigital electrode 22, and the width of the second longitudinal electrode 312 is the same as the width of the first interdigital electrode 32. Here, the width refers to the dimension of the electrodes in the second direction y. Neither the surface of the first longitudinal electrode 212 nor the second longitudinal electrode 312 needs to have through holes 5 or smaller through holes 5 to fix the conductive material. Therefore, the widths of the first longitudinal electrode 212 and the second interdigital electrode 22 can be set to be the same, and the widths of the second longitudinal electrode 312 and the first interdigital electrode 32 can be set to be the same, improving the overall integrity of the MOM capacitor. It is understood that the widths of the first longitudinal electrode 212, the second longitudinal electrode 312, the first interdigital electrode 32, and the second interdigital electrode 22 are not necessarily in the above-described dimensional relationship and can be changed according to the specific operating requirements of the MOM capacitor.

[0077] As one embodiment, the MOM capacitor further includes terminals (not shown in the figure). The terminals can be located at a first end or a second end, and can be located at the free ends of adjacent first longitudinal electrode 212 and second interdigital electrode 22, or at the free ends of adjacent second longitudinal electrode 312 and first interdigital electrode 32. Since the first main electrode 21 and the second main electrode 31 are serpentine in shape, terminals can be provided at both ends of the first main electrode 21, the second main electrode 31, the first interdigital electrode 32, and the second interdigital electrode 22 for wire output. Figure 3(Points P1-P8 in the diagram) Therefore, when connecting MOM capacitors, single-sided / double-sided routing can be used on the same layer or on different layers. For example, the terminals can be divided into first terminals and second terminals. The first terminal of the MOM capacitor is set at P1, and the second terminal is set at P2. That is, the first terminal and the second terminal are set on the same side of the same electrode assembly 1, which is single-sided routing on the same layer. The first terminal of the MOM capacitor is set at P1, and the second terminal is set at P5. That is, the first terminal and the second terminal are located on opposite sides of the same electrode assembly, which is double-sided routing on the same layer. The first terminal of the MOM capacitor is set at P1, and the second terminal is set at P4. That is, the first terminal and the second terminal are located on the same side of different electrode assemblies, which is single-sided routing on different layers. The first terminal of the MOM capacitor is set at P1, and the second terminal is set at P7. That is, the first terminal and the second terminal are located on opposite sides of different electrode assemblies, which is double-sided routing on different layers. The above-mentioned terminal block placement greatly improves the flexibility of capacitor wiring. Placing the terminal block at the free ends of the adjacent first longitudinal electrode 212 and second interdigital electrode 22 or at the free ends of the adjacent second longitudinal electrode 312 and first interdigital electrode 32 can greatly reduce the length difference of the wiring at both ends of the MOM capacitor.

[0078] As one embodiment, the terminal block can also be disposed on the surface of the first longitudinal electrode 212, the first transverse electrode 213, the second longitudinal electrode 312, and the second transverse electrode 313. Figure 3 (As indicated on pages P9-P12), this further enhances the flexibility of MOM capacitor wiring. It can be understood that the specific location of the terminals can be changed according to the different wiring requirements of the MOM capacitor.

[0079] As one embodiment, the MOM capacitor further includes an insulating dielectric layer, in which each electrode assembly 1 is embedded to isolate each upper electrode assembly 2 and lower electrode assembly 3, the first main electrode 21 and the second interdigital electrode 22 in the same upper electrode assembly 2, and the second main electrode 31 and the first interdigital electrode 32 in the same lower electrode assembly 3. It is understood that the specific structure for isolating the upper electrode assembly 2 and lower electrode assembly 3, the first main electrode 21 and the second interdigital electrode 22 in the same upper electrode assembly 2, and the second main electrode 31 and the first interdigital electrode 32 in the same lower electrode assembly 3 is not limited, as long as it serves to isolate the aforementioned structures.

[0080] Reference Figure 7A and Figure 7BThe serpentine-shaped first main electrode 21c includes three gaps 211c, and the serpentine-shaped second main electrode 31c includes three gaps 311c. It can be understood that the number of gaps in the first main electrode 21c and the second main electrode 31c is not limited. The serpentine-shaped first main electrode 21c can extend continuously, forming multiple gaps, with two first longitudinal electrodes and one first transverse electrode forming the gaps 211c as a unit.

[0081] As one embodiment, the first transverse electrode 213, the second transverse electrode 313, the first longitudinal electrode 212, the second longitudinal electrode 312, the first interdigitated electrode 32, and the second interdigitated electrode 22 are all linear. The linear structure facilitates manufacturing and can increase the area of ​​the overlapping portion of the electrode patterns of the upper electrode assembly 2 and the lower electrode assembly 3 in the vertical direction, increase the vertical coupling area of ​​the upper electrode assembly 2 and the lower electrode assembly 3, and increase the capacitance per unit area of ​​the capacitor.

[0082] As another embodiment, refer to Figure 8A and Figure 8B The first transverse electrode 213d and the second transverse electrode 313d can be curved, while the first longitudinal electrode 212d, the second longitudinal electrode 312d, the first interdigital electrode 32d, and the second interdigital electrode 22d remain straight. It is understood that the specific structure of the first transverse electrode 213d and the second transverse electrode 313d is not limited, as long as a serpentine shape can be formed for the first main electrode 21d and the second main electrode 31d, and gaps are formed to accommodate the first interdigital electrode 32d and the second interdigital electrode 22d, and the first main electrode 21d and the second main electrode 31d can partially overlap in the vertical direction (aiming to increase the overlapping area), thus achieving the function of increasing the capacitance of the MOM capacitor.

[0083] As another embodiment, refer to Figure 9A and Figure 9B The first longitudinal electrode 212e, the first transverse electrode 213e, the second longitudinal electrode 312e, and the second transverse electrode 313e are straight lines, while the first interdigital electrode 32e and the second interdigital electrode 22e can have a wavy structure. Specifically, the wavy structure can be a regular or irregular curve with symmetrical sides. It can be understood that the shape of the first interdigital electrode 32e and the second interdigital electrode 22e is not limited, as long as they can be accommodated in the gap between the serpentine first main electrode 21e and the second main electrode 31e, and the first interdigital electrode 32e and the second interdigital electrode 22e can partially overlap in the vertical direction (aiming to increase the overlapping area), thus achieving the function of increasing the capacitance of the MOM capacitor.

[0084] As another embodiment, refer to Figure 10A and Figure 10B The first lateral electrode 213f, the first interdigital electrode 32f, the second lateral electrode 313f, and the second interdigital electrode 22f are all straight lines, while the first longitudinal electrode 212f and the second longitudinal electrode 312f can have a wavy structure. It is understood that the specific structure of the first longitudinal electrode 212f and the second longitudinal electrode 312f is not limited, as long as a serpentine shape can be formed for the first main electrode 21f and the second main electrode 31f, creating a gap to accommodate the first interdigital electrode 32f and the second interdigital electrode 22f, and the first main electrode 21d and the second main electrode 31d can partially overlap in the vertical direction (aiming to increase the overlapping area), thus achieving the function of increasing the capacitance of the MOM capacitor.

[0085] It is understood that the shapes of the first transverse electrode 213, the second transverse electrode 313, the first longitudinal electrode 212, the second longitudinal electrode 312, the first interdigital electrode 32, and the second interdigital electrode 22 do not necessarily have to be all straight. They can be partially straight, partially wavy, or other shapes, or all wavy or other shapes. The specific shapes are not limited, as long as the first main electrode 21 and the second main electrode 31 can form a gap to accommodate and surround the first interdigital electrode 32 and the second interdigital electrode 22, and the first main electrode 21 and the second main electrode 31, and the first interdigital electrode 32 and the second interdigital electrode 22 can partially overlap in the vertical direction, thereby increasing the capacitance of the MOM capacitor. It is understood that irregular electrode edges, such as wavy ones, are beneficial for improving the capacitive coupling effect.

[0086] On the other hand, this application also provides an integrated circuit, including the above-mentioned MOM capacitor and several other electronic devices, wherein the MOM capacitor and the electronic devices are electrically connected.

[0087] In one embodiment, the MOM capacitor is connected to the electronic component via a first trace and a second trace. The length difference between the first trace and the second trace is less than the height of the MOM capacitor, where the height is the dimension along the arrangement direction of the upper and lower electrode assemblies. For example, the first trace is placed at the first end (P1) of the first longitudinal electrode, and the second trace is placed at the first end (P2) of the second interdigital electrode adjacent to P1. In this case, the positions of the first trace and the second trace connected to the MOM capacitor are very close, which is particularly suitable for electronic components with short-distance connection ports. This reduces the length difference between the first trace and the second trace, improving the applicability of the MOM capacitor, especially for circuits sensitive to trace length differences. By using a serpentine shape for the first and second main electrodes, and coordinating the placement of the first and second interdigital electrodes, terminals can be provided at both ends of the first longitudinal electrode, the second longitudinal electrode, the first interdigital electrode, and the second interdigital electrode for trace routing to meet the minimum trace difference.

[0088] Currently, the MOM capacitors used in integrated circuits, under low-voltage operating conditions, have their interdigitated electrode width and the spacing between the interdigitated electrode and the main electrode set to the minimum values ​​specified in the process design. This ensures that the capacitance value of the MOM capacitor reaches its maximum value within a certain size range. As an example, when the integrated circuit design process provided in this application is 28nm, the minimum width of the first and second interdigitated electrodes in the MOM capacitor can be set to 50nm. When the integrated circuit design process is 40nm, the minimum width of the first and second interdigitated electrodes in the MOM capacitor can be set to 70nm, ensuring that the capacitance value reaches its maximum value within a certain size range.

[0089] As one embodiment, when the integrated circuit design process provided in this application is 28nm, the minimum distance between the first interdigital electrode and the second main electrode and the minimum distance between the second interdigital electrode and the first main electrode in the MOM capacitor can be set to 50nm; when the integrated circuit design process is 40nm, the minimum distance between the first interdigital electrode and the second main electrode and the minimum distance between the second interdigital electrode and the first main electrode can be set to 70nm, so that the capacitance value reaches the maximum value within a certain size range.

[0090] As one embodiment, when the integrated circuit design process provided in this application is 28nm, the width of the first interdigital electrode, the width of the second interdigital electrode, the distance between the first interdigital electrode and the second main electrode, and the distance between the second interdigital electrode and the first main electrode can all be set to a minimum of 50nm. When the integrated circuit design process provided in this application is 40nm, the width of the first interdigital electrode, the width of the second interdigital electrode, the distance between the first interdigital electrode and the second main electrode, and the distance between the second interdigital electrode and the first main electrode can all be set to a minimum of 70nm, thereby enabling the capacitance value of the MOM capacitor to reach its maximum value within a certain size range. It can be understood that when the integrated circuit design process is between 28nm and 40nm, the width of the first interdigital electrode, the width of the second interdigital electrode, the distance between the first interdigital electrode and the second main electrode, and the distance between the second interdigital electrode and the first main electrode can be changed within the range of 50nm-70nm depending on the process involved, so that the capacitance value reaches its maximum value within a certain size range.

[0091] Those skilled in the art will understand that, without conflict, the above-mentioned preferred solutions can be freely combined and superimposed.

[0092] It should be understood that the above embodiments are merely exemplary and not restrictive. Various obvious or equivalent modifications or substitutions that can be made by those skilled in the art regarding the above details without departing from the basic principles of the present invention will be included within the scope of the claims of the present invention.

Claims

1. A MOM capacitor, characterized in that, It includes at least two electrode assemblies, which are an upper electrode assembly and a lower electrode assembly stacked and spaced apart. The upper electrode assembly and the lower electrode assembly are parallel to each other, and the electrode pattern of the upper electrode assembly is mirror-symmetrical to the electrode pattern of the lower electrode assembly. The upper electrode assembly includes a first main electrode and a plurality of second interdigital electrodes that are separated from each other, and the lower electrode assembly includes a second main electrode and a plurality of first interdigital electrodes that are separated from each other; The first main electrode is connected to the first interdigital electrode, and the second main electrode is connected to the second interdigital electrode; Both the first main electrode and the second main electrode are serpentine in shape, and the serpentine shape includes multiple gaps. The second interdigitated electrode is disposed at each gap of the first main electrode. The first interdigitated electrode is disposed at the gap of each of the second main electrodes; the upper electrode assembly and the lower electrode assembly each include a first end and a second end opposite to each other, the first main electrode and the second interdigitated electrode are disposed flush with the first end or the second end; the second main electrode and the first interdigitated electrode are disposed flush with the first end or the second end. The projection of the first main electrode on the lower electrode assembly partially overlaps with that of the second main electrode, and the projection of the second interdigital electrode on the lower electrode assembly partially overlaps with that of the first interdigital electrode.

2. The MOM capacitor as described in claim 1, characterized in that, The first main electrode includes a first longitudinal electrode extending along a first direction and a first transverse electrode extending along a second direction, the first longitudinal electrode and the first transverse electrode being alternately connected to form the serpentine shape; the first direction is perpendicular to the second direction; The second main electrode includes a second longitudinal electrode extending along a first direction and a second transverse electrode extending along a second direction, the second longitudinal electrode and the second transverse electrode being alternately connected to form the serpentine shape; The first lateral electrode and the second lateral electrode are located at the first end or the second end; The first interdigital electrode and the second interdigital electrode extend along a first direction at the gap; The projection of the first longitudinal electrode within the lower electrode assembly completely coincides with that of the second longitudinal electrode.

3. The MOM capacitor as described in claim 2, characterized in that, The planar area of ​​the first longitudinal electrode and the second interdigital electrode is A, and the area of ​​the overlapping region between the projection of the first longitudinal electrode and the second interdigital electrode on the lower electrode assembly and the electrode pattern of the lower electrode assembly is B, where B>0.9A.

4. The MOM capacitor as described in claim 2, characterized in that, The first lateral electrode is electrically connected to the first interdigital electrode located directly below it via a conductive material; The second lateral electrode is electrically connected to the second interdigital electrode located directly above it via a conductive material.

5. The MOM capacitor as described in claim 4, characterized in that, The first lateral electrode and the first interdigital electrode located directly below it have through holes, and the second lateral electrode and the second interdigital electrode located directly above it also have through holes. The conductive material is disposed in the through holes, and the extension direction of the conductive material is perpendicular to the first direction and the second direction.

6. The MOM capacitor as described in claim 5, characterized in that, The dimension L1 of the first lateral electrode in the first direction is greater than the dimension L1' of the first interdigitated electrode in the second direction; The dimension L2 of the second lateral electrode in the first direction is greater than the dimension L2' of the second interdigital electrode in the second direction; Where L1 = (1.5-3)L1', L2 = (1.5-3)L2'.

7. The MOM capacitor as described in claim 2, characterized in that, The dimensions L1' of the first interdigitated electrode in the second direction and the dimension L2' of the second interdigitated electrode in the second direction are both 50nm-70nm; And / or, the distance D1 between the first interdigital electrode and the first main electrode and the distance D2 between the second interdigital electrode and the second main electrode are both 50nm-70nm.

8. The MOM capacitor as described in claim 2, characterized in that, The first lateral electrode, the second lateral electrode, the first longitudinal electrode, the second longitudinal electrode, the first interdigitated electrode, and the second interdigitated electrode are all linear in shape.

9. The MOM capacitor as described in any one of claims 1-8, characterized in that, The number of electrode assemblies is several, and the several electrode assemblies are stacked and spaced apart. The electrode pattern and connection relationship of any two adjacent electrode assemblies are the same as the electrode pattern and connection relationship of the upper electrode assembly and the lower electrode assembly.

10. The MOM capacitor according to any one of claims 1-8, characterized in that, The MOM capacitor further includes an insulating dielectric layer, in which each of the electrode components is embedded to isolate the upper electrode components and the lower electrode components, the first main electrode and the second interdigital electrode in the same upper electrode component, and the second main electrode and the first interdigital electrode in the same lower electrode component.

11. The MOM capacitor according to any one of claims 2-8, characterized in that, The MOM capacitor further includes: the MOM capacitor further includes terminals, the terminals being disposed at the first lateral electrode and / or the second lateral electrode.

12. The MOM capacitor according to any one of claims 2-8, characterized in that, The MOM capacitor further includes terminals disposed at the first end or the second end, and disposed at the free ends of adjacent first longitudinal electrodes and second interdigital electrodes or at adjacent second longitudinal electrodes and first interdigital electrodes.

13. The MOM capacitor according to any one of claims 1-8, characterized in that, The MOM capacitor further includes a first terminal and a second terminal, wherein the first terminal and the second terminal are disposed on the same side or opposite side of the same electrode assembly, or on the same side or different sides of different electrode assemblies.

14. An integrated circuit, characterized in that, It includes the MOM capacitor as described in any one of claims 1-13 and a plurality of electronic components, wherein at least a portion of the MOM capacitor and the electronic components are electrically connected.

15. The integrated circuit as described in claim 14, characterized in that: The MOM capacitor is connected to the electronic component via a first trace and a second trace, wherein the length difference between the first trace and the second trace is less than the height of the MOM capacitor.

16. The integrated circuit as claimed in claim 14, characterized in that, The integrated circuit is designed using a process technology of 28nm-40nm. The width of the first interdigital electrode and the second interdigital electrode in the MOM capacitor is 50nm-70nm, and / or the distance between the first interdigital electrode and the second main electrode and the distance between the second interdigital electrode and the first main electrode are 50nm-70nm.

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