Group iii nitride diode devices, methods of making and applications thereof

Abstract

The application discloses a III-nitride diode device, a manufacturing method thereof and application. The III-nitride diode device comprises a III-nitride heterojunction, a two-dimensional electron gas is formed in the III-nitride heterojunction; a first electrode and a second electrode are electrically connected through the two-dimensional electron gas; the III-nitride diode device further comprises a plurality of third semiconductors, the third semiconductors are arranged in cooperation with the heterojunction, any two adjacent third semiconductors are arranged at intervals, each third semiconductor can deplete the two-dimensional electron gas under the third semiconductor, and the plurality of third semiconductors are electrically connected with the first electrode respectively. The manufacturing method provided by the application reduces the opening voltage and interface state influence of the device, improves the dynamic characteristics and reliability of the device, and is simple in process and easy to integrate.

Description

Technical Field

[0001] This invention relates to a diode, and more particularly to a group III nitride diode device, its fabrication method, and its application, belonging to the field of semiconductor technology. Background Technology

[0002] Group III nitrides (such as gallium nitride, GaN) possess excellent material properties such as large bandgap, high breakdown field strength, high electron mobility, and high electron saturation drift velocity, making them highly suitable for next-generation power electronic systems. Gallium nitride transistors based on the p-GaN / AlGaN / GaN structure have been commercialized and are being developed towards monolithic integration to leverage the high switching frequency and high conversion efficiency of GaN devices. In power electronic systems, diodes are indispensable components. However, traditional diodes are Schottky diodes fabricated using Schottky contacts. The conventional process for fabricating GaN Schottky diodes in the p-GaN / AlGaN / GaN structure is quite complex, involving the removal of the surface p-GaN and etching the AlGaN barrier layer. Controlling the depth, roughness, and uniformity is difficult. Furthermore, GaN Schottky diodes themselves still suffer from numerous problems, including high turn-on voltage, large reverse leakage current, low reverse breakdown voltage, and metal selection issues. Summary of the Invention

[0003] The main objective of this invention is to provide a group III nitride diode device, its fabrication method, and its application, in order to overcome the shortcomings of the prior art.

[0004] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0005] This invention provides 1. a group III nitride diode device, comprising:

[0006] A first semiconductor and a second semiconductor are combined to form a heterojunction, and a two-dimensional electron gas is formed within the heterojunction;

[0007] A first electrode and a second electrode, which are electrically connected via the two-dimensional electronic gas;

[0008] The characteristic feature is that the group III nitride diode device further includes:

[0009] A plurality of third semiconductors are disposed in conjunction with the heterojunction, wherein any two adjacent third semiconductors are spaced apart from each other, each third semiconductor is capable of depleting the two-dimensional electron gas located below it, and the plurality of third semiconductors are also electrically contacted with the first electrode.

[0010] In one specific embodiment, the first electrode includes:

[0011] The first part forms a first type of electrical contact with the two-dimensional electron gas;

[0012] The second part forms a second type of electrical contact with a plurality of the third semiconductors;

[0013] Furthermore, the first part and the second part are electrically connected.

[0014] In one specific embodiment, the first type of electrical contact includes an ohmic contact, and the second type of electrical contact includes an ohmic contact or a Schottky contact.

[0015] In one specific embodiment, any two adjacent third semiconductors are electrically isolated from each other by a high-resistivity material, and / or, the plurality of said third semiconductors are electrically isolated from the second electrode by a high-resistivity material.

[0016] In one specific embodiment, the high-resistivity material is formed by transforming a first region of a continuous third semiconductor layer, and a plurality of the third semiconductors are distributed in a second region of the third semiconductor layer;

[0017] Alternatively, the plurality of said third semiconductors may be formed by transforming a second region of a continuous high-resistivity material layer, wherein the high-resistivity material is distributed within a first domain of the high-resistivity material layer.

[0018] In one specific embodiment, the third semiconductor is a p-type semiconductor.

[0019] In one specific embodiment, the material of the third semiconductor includes a p-type wide bandgap semiconductor.

[0020] In one specific embodiment, the p-type wide bandgap semiconductor includes a p-type group III nitride.

[0021] In one specific embodiment, the p-type group III nitride includes p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN, etc.

[0022] In one specific embodiment, the p-type wide bandgap semiconductor includes p-NiO.

[0023] In one specific embodiment, the high-resistivity material is high-resistivity GaN, high-resistivity AlGaN, high-resistivity Ga2O3, high-resistivity InGaN, or high-resistivity InN, etc.

[0024] In one specific embodiment, a plurality of the third semiconductors are distributed in a continuous third semiconductor layer, and a fourth semiconductor is further disposed in the region between any two adjacent third semiconductors in the third semiconductor layer, and the fourth semiconductor cooperates with the third semiconductor layer to form a pn junction.

[0025] In one specific embodiment, the fourth semiconductor is an n-type semiconductor, and the material of the n-type semiconductor includes n-type GaN, n-type Ga2O3, n-type In2O3, n-type InGaN, or n-type InN, etc.

[0026] In one specific embodiment, the first electrode and the second electrode are the anode and the cathode, respectively.

[0027] In one specific embodiment, the first semiconductor, the second semiconductor, and the third semiconductor are stacked sequentially, the first part of the first electrode and the second electrode are both disposed on the second semiconductor, and the second part of the first electrode is disposed on the first part and multiple third semiconductors.

[0028] In one specific embodiment, the second portion of the first electrode completely covers the plurality of third semiconductors.

[0029] In one specific embodiment, the plurality of third semiconductors are arranged at intervals along a specified direction, wherein the two ends of any one of the third semiconductors point to the first portion of the first electrode and the second electrode, respectively.

[0030] In one specific embodiment, the width of the third semiconductor is not less than 2μm, the length is 10nm-10μm, and the spacing between two adjacent third semiconductors is 1nm-10μm.

[0031] In one specific embodiment, the thickness of the third semiconductor is 10 nm to 1 μm.

[0032] In one specific embodiment, the materials of both the first semiconductor and the second semiconductor are selected from group III nitrides.

[0033] In one specific embodiment, the material of the first semiconductor includes GaN.

[0034] In one specific embodiment, the material of the second semiconductor includes Al. x Ga (1-x) N, AlInGaN or In x Al (1-x) N, 0 < x ≤ 1.

[0035] In one specific embodiment, the group III nitride diode device further includes a field plate.

[0036] This invention also provides a method for fabricating a group III nitride diode device, comprising:

[0037] The steps of fabricating a first semiconductor and a second semiconductor include forming a heterojunction by combining the first semiconductor and the second semiconductor, and forming a two-dimensional electron gas within the heterojunction.

[0038] The steps for fabricating the first electrode and the second electrode are as follows: the first electrode and the second electrode are electrically connected through the two-dimensional electronic gas.

[0039] The manufacturing method further includes:

[0040] The step of fabricating a plurality of third semiconductors involves the plurality of third semiconductors being configured in conjunction with the heterojunction, wherein any two adjacent third semiconductors are spaced apart from each other, each third semiconductor is capable of depleting the two-dimensional electron gas located below it, and the plurality of third semiconductors are also electrically contacted with a first electrode.

[0041] In one specific embodiment, the manufacturing method specifically includes:

[0042] A first semiconductor, a second semiconductor, and a continuous third semiconductor layer are sequentially formed, wherein the third semiconductor layer includes a first region and a second region.

[0043] The first region is subjected to a conversion process to form a high-resistivity material, and the high-resistivity material electrically isolates the plurality of third semiconductors distributed in the second region from each other;

[0044] Alternatively, a first semiconductor, a second semiconductor, and a continuous high-resistivity material layer may be formed sequentially, wherein the high-resistivity material layer includes a first region and a second region.

[0045] The second region is subjected to a conversion process to form a plurality of the third semiconductors, and a high-resistivity material distributed in the first region electrically isolates the plurality of the third semiconductors from each other.

[0046] In one specific embodiment, the fabrication method further includes: electrically isolating the plurality of third semiconductors from the second electrode using the high-resistivity material.

[0047] In one specific embodiment, the method for performing the conversion treatment includes any one or more combinations of H ion implantation, H plasma treatment, H doping annealing, N ion implantation, F ion implantation, Ar ion implantation, Fe ion implantation, and oxygen plasma treatment, but is not limited thereto.

[0048] In one specific embodiment, the manufacturing method specifically includes:

[0049] The first semiconductor and the second semiconductor are formed sequentially;

[0050] Multiple third semiconductors are formed by selective epitaxial growth on the second semiconductor.

[0051] In one specific embodiment, the manufacturing method specifically includes:

[0052] The first semiconductor and the second semiconductor are formed sequentially;

[0053] Multiple third semiconductors and high-resistivity materials are selectively epitaxially grown on the second semiconductor, and any two adjacent third semiconductors are electrically isolated from each other by the high-resistivity material.

[0054] In one specific embodiment, the manufacturing method specifically includes:

[0055] A first semiconductor, a second semiconductor, and a continuous third semiconductor layer are formed sequentially, wherein the third semiconductor layer comprises a plurality of the aforementioned third semiconductors;

[0056] A fourth semiconductor is grown on the region between any two adjacent third semiconductors in the third semiconductor layer, and the fourth semiconductor is combined with the third semiconductor layer to form a pn junction.

[0057] In one specific embodiment, the third semiconductor is a p-type semiconductor.

[0058] In one specific embodiment, the material of the third semiconductor includes a p-type wide bandgap semiconductor.

[0059] In one specific embodiment, the p-type wide bandgap semiconductor includes a p-type group III nitride.

[0060] In one specific embodiment, the p-type group III nitride includes p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN, etc.

[0061] In one specific embodiment, the p-type wide bandgap semiconductor includes p-NiO.

[0062] In one specific embodiment, the fourth semiconductor is an n-type semiconductor, and the material of the n-type semiconductor includes n-type GaN, n-type Ga2O3, n-type In2O3, n-type InGaN, or n-type InN, etc.

[0063] This invention also provides a group III nitride semiconductor device, comprising:

[0064] A first semiconductor and a second semiconductor are combined to form a heterojunction, and a two-dimensional electron gas is formed within the heterojunction;

[0065] A first electrode and a second electrode, which are electrically connected via the two-dimensional electronic gas;

[0066] The source, drain, and gate are provided, wherein the source and drain are electrically connected via the two-dimensional electron gas, and the gate is disposed between the source and drain.

[0067] The group III nitride semiconductor device also includes:

[0068] A plurality of third semiconductors are disposed in conjunction with the heterojunction, wherein any two adjacent third semiconductors are spaced apart from each other, each third semiconductor is capable of depleting the two-dimensional electron gas located below it, and the plurality of third semiconductors are also electrically contacted with the first electrode respectively.

[0069] Furthermore, the first electrode is also electrically connected to the source electrode.

[0070] In one embodiment, the group III nitride semiconductor device further includes a fifth semiconductor disposed between the gate and the heterojunction, and the fifth semiconductor is capable of depleting the two-dimensional electron gas located below it.

[0071] In one specific embodiment, the fifth semiconductor is electrically isolated from the source and drain via a high-resistivity material, wherein the high-resistivity material is formed by transforming a first region of a continuous fifth semiconductor layer, and the fifth semiconductor is distributed in a second region of the fifth semiconductor layer; or, the fifth semiconductor is formed by transforming a second region of a continuous high-resistivity material layer, and the high-resistivity material is distributed in a first region of the high-resistivity material layer.

[0072] In one specific embodiment, the first electrode includes:

[0073] The first part forms a first type of electrical contact with the two-dimensional electron gas;

[0074] The second part forms a second type of electrical contact with a plurality of the third semiconductors;

[0075] Furthermore, the first part and the second part are electrically connected.

[0076] In one specific embodiment, a second portion of the first electrode is partially disposed between the source and the drain.

[0077] In one specific embodiment, the first type of electrical contact includes an ohmic contact, and the second type of electrical contact includes an ohmic contact or a Schottky contact.

[0078] In one specific embodiment, any two adjacent third semiconductors are electrically isolated from each other by a high-resistivity material, and / or, the plurality of said third semiconductors are electrically isolated from the second electrode by a high-resistivity material.

[0079] In one specific embodiment, the high-resistivity material is formed by transforming a first region of a continuous third semiconductor layer, and a plurality of the third semiconductors are distributed in a second region of the third semiconductor layer; or, the plurality of the third semiconductors are formed by transforming a second region of a continuous high-resistivity material layer, and the high-resistivity material is distributed in a first region of the high-resistivity material layer.

[0080] In one specific embodiment, a plurality of the third semiconductors are distributed in a continuous third semiconductor layer, and a fourth semiconductor is further disposed in the region between any two adjacent third semiconductors in the third semiconductor layer, and the fourth semiconductor cooperates with the third semiconductor layer to form a pn junction.

[0081] In one specific embodiment, both the third semiconductor and the fifth semiconductor are p-type semiconductors.

[0082] In one specific embodiment, both the third semiconductor and the fifth semiconductor are made of p-type wide bandgap semiconductor.

[0083] In one specific embodiment, the p-type wide bandgap semiconductor includes a p-type group III nitride.

[0084] In one specific embodiment, the p-type group III nitride includes p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN, etc.

[0085] In one specific embodiment, the p-type wide bandgap semiconductor includes p-NiO.

[0086] In one specific embodiment, the fourth semiconductor is an n-type semiconductor, and the material of the n-type semiconductor includes n-type GaN, n-type Ga2O3, n-type In2O3, n-type InGaN, or n-type InN.

[0087] In one specific embodiment, the first electrode and the second electrode are the anode and the cathode, respectively.

[0088] In one specific embodiment, the first semiconductor, the second semiconductor, and the third semiconductor are stacked sequentially, the first part of the first electrode and the second electrode are both disposed on the second semiconductor, and the second part of the first electrode is disposed on the first part and multiple third semiconductors.

[0089] In one specific embodiment, the plurality of third semiconductors are arranged at intervals along a specified direction, wherein the two ends of any one of the third semiconductors point to the first portion of the first electrode and the second electrode, respectively.

[0090] Compared with the prior art, the advantages of the present invention include:

[0091] 1) The present invention provides a group III nitride diode device, wherein the bar-shaped p-GaN array hybrid anode structure can flexibly adjust the turn-on voltage by adjusting the widths of different p-GaN and HR-GaN, thereby obtaining a diode with a low turn-on voltage;

[0092] 2) The group III nitride diode device provided in this embodiment of the invention can improve the breakdown voltage and on-resistance of the device by expanding the lateral dimension of the p-GaN array portion;

[0093] 3) The method for fabricating a group III nitride diode device provided in this embodiment of the invention does not require etching of the anode region of the device, thus avoiding the problems of uniformity, repeatability and damage introduced by the etching process.

[0094] 4) The method for fabricating a group III nitride diode device provided in this embodiment of the invention reduces the influence of interface states and improves the reliability of the device;

[0095] 5) The method for fabricating a group III nitride diode device provided in this embodiment of the invention also reduces the influence of parasitic capacitance and improves the frequency characteristics of the device.

[0096] 6) The method for fabricating a group III nitride diode device provided in this embodiment of the invention is simple, has good repeatability, and is compatible with p-GaN gate HEMT device technology and easy to integrate. Attached Figure Description

[0097] Figure 1a , Figure 1b This is a schematic diagram of the structure of a group III nitride diode device provided in a typical embodiment of the present invention;

[0098] Figures 2-5 This is a schematic diagram of the fabrication process of a group III nitride diode device provided in a typical embodiment of the present invention;

[0099] Figure 6a , Figure 6b , Figure 6c , Figure 6d , Figure 6e This is a typical embodiment of the present invention, showing the variation curve of 2DEG concentration for a group III nitride diode device under different p-GaN strip array sizes;

[0100] Figure 7a , Figure 7b , Figure 7c , Figure 7d This is a simulation test result of the forward characteristics of a group III nitride diode device provided in a typical embodiment of the present invention;

[0101] Figure 8a This is a schematic diagram of the structure of a group III nitride diode device integrated with a GaN HEMT, provided in a typical embodiment of the present invention;

[0102] Figure 8b This is a schematic diagram of the electrode structure of a group III nitride diode device integrated with a GaN HEMT, provided in a typical embodiment of the present invention.

[0103] Figure 9a , Figure 9b This is a schematic diagram of the structure of a current sensor provided in a typical embodiment of the present invention;

[0104] Figure 9c This is a test curve of a current sensor provided in a typical embodiment of the present invention. Detailed Implementation

[0105] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0106] An embodiment of the present invention provides a group III nitride diode, such as... Figure 1a , Figure 1b As shown, this invention involves forming a p-GaN array (i.e., formed by a regular arrangement of multiple spaced third semiconductors, the same below; the material can also be p-type semiconductor materials such as p-AlGaN) on a group III nitride heterojunction, and fabricating it as shown in the figure. Figure 1a The device structure shown is epitaxially compatible with commercially available enhancement-mode p-GaN gate GaN high electron mobility transistors (HEMTs), meaning that it is possible to integrate the HEMT and the diode on the same wafer.

[0107] The present invention provides a group III nitride diode, wherein the anode of the group III nitride diode comprises two different metals, one of which is metal A (i.e., the first part of the aforementioned first electrode, hereinafter the same) that forms an ohmic contact with a two-dimensional electron gas (2DEG), and the other is metal B (i.e., the second part of the aforementioned first electrode, hereinafter the same) that forms an ohmic contact or a Schottky contact with p-GaN (i.e., the aforementioned third semiconductor, hereinafter the same), and metal B connects metal A and p-GaN.

[0108] The present invention provides a group III nitride diode in which multiple p-GaNs connected to the anode have a discontinuous structure along the width of the anode (or along the radial direction of the anode if the anode of the device is circular). It can be understood that the multiple p-GaNs are oriented and arranged along the width of the anode, and a high-resistivity material can be disposed between two adjacent p-GaNs, such as HR-GaN.

[0109] Specifically, the group III nitride diode provided in this embodiment of the invention can also adjust the turn-on voltage of the diode by adjusting the periodic structure and size of the p-GaN array, thereby forming an extremely low turn-on voltage. The inventors of this case have found that the structure of the group III nitride diode provided in this embodiment of the invention not only does not impair the reverse breakdown voltage characteristics of the device, but the structure is also compatible with transistor devices, which helps to realize device integration.

[0110] The core design concept of a group III nitride diode device provided in this invention embodiment is to use H plasma treatment (hereinafter referred to as "H treatment"), or H treatment followed by annealing, or annealing p-GaN under NH3 atmosphere and fabricating it into a strip p-GaN array hybrid anode planar structure. This anode structure can achieve a low turn-on voltage and an adjustable turn-on voltage, and can improve the breakdown voltage of the device.

[0111] Compared to traditional etching techniques, the fabrication method for a group III nitride diode device provided in this invention utilizes H-plasma or similar methods to treat p-type semiconductor materials to form an oriented p-type semiconductor array, eliminating the need for etching and complex surface repair processes. Compared to etched groove techniques, this invention proposes for the first time a strip-shaped p-GaN array hybrid anode planar structure, which is less complex to fabricate, has high reliability, and its fabrication process is compatible with GaN HEMTs, facilitating integration.

[0112] The following will further explain the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the semiconductor epitaxial growth, etching and other processes used in the embodiments of the present invention are known to those skilled in the art.

[0113] Please see Figure 1a and Figure 1b A group III nitride diode device includes: a buffer layer and a group III nitride heterojunction sequentially disposed on a substrate, wherein a two-dimensional electron gas is formed in the group III nitride heterojunction; and

[0114] The device comprises a cathode, an anode, a p-type semiconductor array, and a high-resistivity material. The anode includes a first portion and a second portion electrically connected to each other. The first portion and the cathode are electrically connected to a two-dimensional electron gas in the group III nitride heterojunction. The second portion forms an ohmic contact or a Schottky contact with the third semiconductor array and completely masks the p-type semiconductor array.

[0115] The p-type semiconductor array includes a plurality of p-type semiconductors disposed on a group III nitride heterojunction. The plurality of p-type semiconductors are arranged sequentially at intervals along the width direction of the first portion of the anode. The two ends of the p-type semiconductors point to the first portion of the anode and the cathode, respectively. The high-resistivity material is disposed between two adjacent p-type semiconductors and between the p-type semiconductors and the cathode.

[0116] Specifically, the first part, the second part, and the cathode of the anode can all be metal electrodes. The first part and the cathode of the anode can be the same metal. For example, the first part and the cathode of the anode can be metal A. The second part of the anode and the first part of the anode are different metals. For example, the second part of the anode can be metal B.

[0117] Specifically, the working principle and simulation test results of a group III nitride diode device provided in this embodiment of the invention are as follows:

[0118] This invention provides a group III nitride diode device that controls the 2DEG concentration in the channel portion through a p-GaN strip array structure below the metal electrode B. When no anode bias is applied, the 2DEG in the channel portion is depleted or partially depleted, and the device is in a "off" state. When a forward anode bias is applied, since p-GaN / AlGaN / GaN can be regarded as a "pin" diode, the depletion region in the channel portion narrows, the 2DEG recovers, and the device begins to "conduct" in the forward direction. When a reverse anode bias is applied, the "pin" diode turns off, the depletion region widens, and the device is in a "off" state. The forward turn-on voltage of this device structure can be regarded as the threshold voltage of a HEMT device with a p-GaN strip array gate structure.

[0119] The inventors in this case tested the group III nitride diode device using Silvaco-TCAD simulation software. The test results showed that the 2DEG concentration varied under different p-GaN strip array sizes as follows: Figure 6a , Figure 6b , Figure 6c , Figure 6d As shown.

[0120] The inventors in this case also conducted simulation tests on the forward characteristics of the group III nitride diode device. The test results show that, under different p-GaN strip array sizes, the turn-on voltage of the device varies as follows: Figure 7a , Figure 7b , Figure 7c As shown in the data, compared to diodes with a single p-GaN anode, diodes with a p-GaN strip array anode have a lower turn-on voltage and a higher current density, which means that the device has a significant performance improvement.

[0121] The inventors in this case tested the group III nitride diode device using Silvaco-TCAD simulation software. The test results showed that the 2DEG concentration varied under different p-GaN strip array sizes as follows: Figure 6a , Figure 6b , Figure 6c , Figure 6d , Figure 6e As shown, the 2DEG concentration varies with the size of the p-GaN strip array—the larger the size, the higher the concentration; the smaller the size, the lower the concentration. Appropriately high 2DEG concentrations contribute to achieving low turn-on voltages.

[0122] The inventors also conducted simulation tests comparing the forward characteristics of the group III nitride diode device and the device in Comparative Example 1. The results showed that the turn-on voltage of the device in Comparative Example 1 was approximately 1.23V (current density 1mA / mm), while the turn-on voltage of the group III nitride diode devices in this case was all less than 0.3V. Furthermore, the turn-on voltage decreased continuously with the increase of the p-GaN strip array size (the turn-on voltage of the 2μm device was as low as 0.16V). The change in the turn-on voltage of the device is as follows: Figure 7a , Figure 7b , Figure 7c , Figure 7d As shown in the data, compared to diodes with a single p-GaN anode, diodes with a p-GaN strip array anode have a lower turn-on voltage and a higher current density, which means that the device has a significant performance improvement.

[0123] Please see Figures 2-5 A method for fabricating a group III nitride diode device may include the following steps:

[0124] 1) Employ epitaxial technologies such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE) to grow substrate / buffer layer / group III nitride heterojunction / p-type semiconductor material structures;

[0125] It should be noted that the substrate can be Si, SOI, SiC, GaN, or sapphire, and the substrate thickness can range from 100 μm to 10 mm; the buffer layer can be high-resistivity GaN, and the buffer layer thickness can range from 100 nm to 1 mm; the group III nitride heterojunction can be AlGaN / GaN heterojunction, AlInN / GaN heterojunction, AlGaN / InGaN / GaN heterojunction, AlGaN / AlN / GaN heterojunction, etc.; the group III nitride heterojunction thickness can range from 10 nm to 10 μm; the p-type semiconductor can be p-GaN or p-AlGaN, and the thickness can range from 10 nm to 1 μm.

[0126] 2) Dry or wet etching techniques such as reactive ion etching and ion beam etching are used to remove p-type semiconductor materials (such as p-GaN) and part or all of the barrier layer (such as AlGaN) in the cathode and anode regions; the etched regions can be determined by photolithography or mask transfer techniques; it should be noted that highly doped n-GaN can be epitaxially grown in the etched regions in this step.

[0127] 3) Metal electrodes A are fabricated in the cathode and anode regions using metal deposition techniques such as electron beam evaporation or sputtering. Then, metal electrodes A are annealed to form good ohmic contact. The annealing area can be determined by techniques such as photolithography and mask transfer.

[0128] 4) Provide equipment capable of generating hydrogen (H) plasma, not limited to equipment such as reactive ion etching (ICP, RIE), using H plasma to treat the p-type semiconductor located in the anode region, and simultaneously treating the p-type semiconductor between the cathode and anode regions with H plasma to form a high-resistivity material. The purpose is to release electrons at the channel, thereby forming multiple p-type semiconductors arranged at intervals in the anode region. The p-type semiconductors can deplete the two-dimensional electron gas distributed below them, while the two-dimensional electron gas distributed below the high-resistivity material is retained to form a channel;

[0129] The H-plasma treatment area can be determined by techniques such as photolithography and mask transfer. The planar geometry of multiple p-type semiconductors can be regular or irregular. The parallel channel shapes can be the same or different, and the number of channels can be adjusted (greater than 1). The channel width can range from a few nanometers to a few micrometers, i.e., 1nm to 10μm. Of course, annealing, wet etching, or surface oxidation can also be used to optimize the channel surface in order to reduce surface defects and passivate surface defect states.

[0130] 5) Use metal deposition techniques such as electron beam evaporation or sputtering to fabricate metal electrode B, which covers multiple p-type semiconductors and metal electrode A in the anode region. The contact between metal electrode B and p-type semiconductor can be a Schottky contact, or to further reduce gate leakage current or increase the breakdown voltage of the device, a metal-insulator-semiconductor contact or a metal-oxide-semiconductor contact can be used.

[0131] It is understood that the above is merely a relatively typical fabrication method of a group III nitride diode device in the embodiments of the present invention. For the interconversion between p-type semiconductors and high-resistivity materials, the inventors of this invention also use other methods such as doping or ion implantation to treat p-type semiconductor materials to form high-resistivity materials. Of course, H plasma treatment followed by annealing can be performed first to form high-resistivity gallium nitride (HR-GaN), followed by O plasma treatment, which can also achieve the purpose of the present invention. Alternatively, high-resistivity materials can be epitaxially formed on group III nitrides first, and then multiple spaced p-type semiconductors can be formed by activating selected regions. Or, p-type semiconductor materials or HR semiconductor materials can be directly epitaxially formed in selected regions, which can also achieve the purpose of the present invention. Furthermore, n-type semiconductor materials can also be epitaxially formed in selected regions of p-type semiconductor materials, which can also achieve the purpose of the present invention.

[0132] It should be noted that the size of the metal electrode B is submicron or larger. The contact between the metal electrode B and the p-type semiconductor can be a Schottky contact, or, in order to further reduce the gate leakage current or increase the breakdown voltage of the device, a metal-insulator-semiconductor contact or a metal-oxide-semiconductor contact can also be used.

[0133] Specifically, in the channel array distributed among multiple p-type semiconductors in the anode region, the planar geometry of the channel can be regular or irregular, the side-by-side channels can be the same or different, the channel can be a single channel or multiple channels, and the channel width can range from a few nanometers to a few micrometers, i.e., 1 nm to 10 μm.

[0134] Specifically, the equipment for generating H plasma is not limited to reactive ion etching (ICP / RIE / NLD) equipment; any equipment that generates H plasma can be used. Of course, this invention is not limited to H treatment; H ion implantation, H annealing, and N ion implantation can also be used. The main purpose is to transform p-GaN into high-resistivity GaN. The position of the H plasma treatment region can be freely adjusted. The planar shape of the treatment region can be regular or irregular. The shapes of parallel channels can be the same or different. The treatment region can be a single line or multiple lines, and its width can be adjusted arbitrarily according to the distance between the device's anode and cathode.

[0135] Specifically, in embodiments of the present invention, the diode of the present invention can also be integrated with a GaN HEMT, and the integrated device structure is as follows: Figure 8a As shown, the diode in this invention is embedded in a HEMT device and applied to a GaN switching power supply;

[0136] Please participate Figure 8a and Figure 8b A group III nitride semiconductor device includes a first semiconductor and a second semiconductor, wherein the first semiconductor and the second semiconductor cooperate to form a group III nitride heterojunction, and a two-dimensional electron gas is formed within the group III nitride heterojunction;

[0137] An anode and a cathode, which are electrically connected via the two-dimensional electron gas;

[0138] The source, drain, and gate are provided, wherein the source and drain are electrically connected via the two-dimensional electron gas, and the gate is disposed between the source and drain.

[0139] The group III nitride semiconductor device also includes:

[0140] A plurality of p-type semiconductors are disposed in conjunction with the heterojunction, wherein any two adjacent p-type semiconductors are spaced apart from each other, each p-type semiconductor is capable of depleting the two-dimensional electron gas located below it, and the plurality of p-type semiconductors are also electrically contacted with the anode respectively.

[0141] Furthermore, the anode is electrically connected to the source electrode.

[0142] Specifically, the group III nitride semiconductor device further includes a high-resistivity semiconductor disposed between the gate and the heterojunction, and the high-resistivity semiconductor is capable of depleting the two-dimensional electron gas located below it.

[0143] Specifically, the high-resistivity semiconductor is electrically isolated from the source and drain via a high-resistivity material, which is formed by transforming a first region of a continuous high-resistivity semiconductor layer, and the high-resistivity semiconductor is distributed in a second region of the high-resistivity semiconductor layer; or, the high-resistivity semiconductor is formed by transforming a second region of a continuous high-resistivity material layer, and the high-resistivity material is distributed in a first region of the high-resistivity material layer.

[0144] Specifically, the high-resistivity semiconductor is electrically isolated from the source and drain via a high-resistivity material, which is formed by transforming a first region of a continuous high-resistivity semiconductor layer, and the high-resistivity semiconductor is distributed in a second region of the high-resistivity semiconductor layer; or, the high-resistivity semiconductor is formed by transforming a second region of a continuous high-resistivity material layer, and the high-resistivity material is distributed in a first region of the high-resistivity material layer.

[0145] Specifically, the first part, the second part, and the cathode of the anode can all be metal electrodes. The first part and the cathode of the anode can be the same metal. For example, the first part and the cathode of the anode can be metal A. The second part of the anode and the first part of the anode are different metals. For example, the second part of the anode can be metal B.

[0146] Specifically, the second portion of the anode is partially disposed between the source and the drain.

[0147] Specifically, the first type of electrical contact includes ohmic contacts, and the second type of electrical contact includes ohmic contacts or Schottky contacts.

[0148] Specifically, any two adjacent p-type semiconductors are electrically isolated from each other by a high-resistivity material, and / or, multiple p-type semiconductors are electrically isolated from the cathode by a high-resistivity material.

[0149] Of course, embedding the diode in this invention into a HEMT device can also serve as a current sensor, the structure of which is as follows: Figure 9a , Figure 9b As shown, the performance test results of the integrated device are as follows: Figure 9c As shown, since the diode in the sensor electrode section has a small turn-on voltage, it can obtain high sensitivity and acquire the potential of the electrode section to obtain the drain output current.

[0150] Of course, embedding the diode in this invention into a HEMT device can also serve as a current sensor, the structure of which is as follows: Figure 9a , Figure 9b As shown, the sensor electrodes are located between the gate and drain. During normal operation, the device can sense potential changes, and these potential changes and the device's output current form a dynamic one-to-one correspondence; that is, obtaining the potential allows us to determine the device's current. The performance test results of the integrated device are as follows: Figure 9c As shown, the solid curve represents the output current of the device, and the scatter curve represents the potential change obtained by the sensor. The two match well, indicating that the device has good current sensing characteristics.

[0151] Because the diodes in the sensor electrode section have a small turn-on voltage, they can achieve high sensitivity and acquire the potential of the electrode section to obtain the drain output current.

[0152] It should be noted that the purpose of this invention can also be achieved by replacing GaN with other materials that can provide heterojunctions; of course, a dielectric layer can also be added at the interface between the p-type semiconductor and the gate metal.

[0153] Example 1

[0154] A method for fabricating a group III nitride diode device includes the following steps:

[0155] 1) Growth using metal-organic chemical vapor deposition (MOCVD) as... Figure 2 The epitaxial structure shown;

[0156] The substrate is Si(111), the buffer layer is high-resistivity GaN with a thickness of 3-5 μm; the GaN channel layer in the AlGaN / GaN heterojunction has a thickness of 150-300 nm, the AlGaN barrier layer has a thickness of 20-30 nm, and the Al composition is 0.15-0.25; the p-type semiconductor material is p-GaN with a thickness of 50-100 nm.

[0157] 2) The p-GaN and part of the AlGaN layer in the cathode and anode regions were removed by reactive ion etching, and metal A (Ti / Al / Ni / Au) was fabricated in the cathode and anode regions by electron beam evaporation, respectively. Then, the metal was annealed in a nitrogen (N2) atmosphere at 800-900℃ for 30-40s.

[0158] 3) An electron beam lithography machine is used to define the strip channel array, and SiO2 is used as the subsequent etching mask with a thickness of 50-200 nm;

[0159] 4) Using reactive ion etching (ICP) equipment, the selected area of ​​p-GaN is treated with H plasma, and then annealed for 3 to 5 minutes in N2 atmosphere at 300 to 500°C to form a strip channel array. The remaining p-GaN forms a p-GaN array containing multiple p-GaNs with different orientations.

[0160] 5) Metal B (Ni / Au) is fabricated using electron beam evaporation technology. Metal B is electrically connected to metal A in the anode region and forms an ohmic contact or Schottky contact with p-GaN. Metal B completely covers the p-GaN array.

[0161] 6) A 300 nm SiN passivation layer is grown on the surface of the epitaxial structure;

[0162] 7) Openings are formed in the cathode and anode regions of the passivation layer, and a metal interconnect structure is formed to complete the integration.

[0163] Comparative Example 1

[0164] The fabrication method of a group III nitride diode device in Comparative Example 1 is basically the same as that in Example 1. The difference is that in Comparative Example 1, a monolithic p-GaN is formed in the anode region, that is, there is no channel array in the anode region.

[0165] The inventors also conducted simulation tests comparing the forward characteristics of the group III nitride diode device in Example 1 and the device in Comparative Example 1. The results showed that the turn-on voltage of the device in Comparative Example 1 was approximately 1.23V (current density 1mA / mm), while the turn-on voltage of the group III nitride diode devices in Example 1 of this invention was all less than 0.3V. Furthermore, the turn-on voltage decreased continuously with the increase of the p-GaN strip array size (the turn-on voltage of the 2μm device was as low as 0.16V). The change in the turn-on voltage of the device is as follows: Figure 7a , Figure 7b , Figure 7c As shown in the data, compared to diodes with a single p-GaN anode, diodes with a p-GaN strip array anode have a lower turn-on voltage and a higher current density, which means that the device has a significant performance improvement.

[0166] The present invention provides a method for fabricating a group III nitride diode device, which has a simple process, good repeatability, and is compatible with p-GaN gate HEMT device technology and easy to integrate.

[0167] The method for fabricating a group III nitride diode device provided in this embodiment of the invention eliminates the need for etching the anode region of the device, thus avoiding uniformity, repeatability, and damage issues introduced by the etching process. Furthermore, the method reduces the influence of interface states, improving the device's reliability. Additionally, the method also reduces the impact of parasitic capacitance, improving the device's frequency characteristics.

[0168] The bar-shaped p-GaN array hybrid anode structure in a group III nitride diode device provided by this invention can flexibly adjust the turn-on voltage by designing different widths of p-GaN and HR-GaN, and can greatly reduce the turn-on voltage of the diode; furthermore, the group III nitride diode device provided by this invention can also improve the device performance (breakdown voltage, on-resistance) by expanding the lateral dimension of the p-GaN array portion.

[0169] The present invention provides a group III nitride diode device. Due to the introduction of the channel, the current in a single channel is much smaller than that of traditional devices, so the heat dissipation is better than that of traditional devices. Therefore, it can effectively suppress the self-heating effect present in traditional heterojunction field-effect transistors.

[0170] The III-nitride diode device provided in this embodiment of the invention can be fabricated using traditional semiconductor microfabrication techniques. The equipment that can be used includes photolithography systems (such as electron beam lithography, ion beam lithography, immersion lithography, distributed exposure, and optical exposure equipment), nanoimprint technology, etching equipment (RIE, ICP, NLD, etc.), ion implantation equipment, etc.

[0171] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A III-nitride diode device, comprising: a first semiconductor and a second semiconductor, the first and second semiconductors cooperating to form a heterojunction, and a two-dimensional electron gas formed within the heterojunction; a first electrode and a second electrode, the first and second electrodes electrically connected through the two-dimensional electron gas; characterized in that the III-nitride diode device further comprises: a plurality of third semiconductors, the plurality of third semiconductors distributed within a continuous third semiconductor layer, wherein any two adjacent third semiconductors are spaced apart from each other, and the third semiconductor layer is disposed in the region between any two adjacent third semiconductors, and a fourth semiconductor is further disposed in the region between any two adjacent third semiconductors, the third semiconductor is a p-type semiconductor, the fourth semiconductor is an n-type semiconductor, the fourth semiconductor cooperates with the third semiconductor layer to form a pn junction, the plurality of third semiconductors are disposed in cooperation with the heterojunction, each of the third semiconductors is capable of depleting a portion of the two-dimensional electron gas located thereunder, and the plurality of third semiconductors are respectively in electrical contact with the first electrode.

2. The group III nitride diode device of claim 1, wherein, the first electrode comprises: a first portion in electrical contact with the two-dimensional electron gas in a first type of contact; a second portion in electrical contact with the plurality of third semiconductors in a second type of contact; and the first portion and the second portion are electrically connected.

3. The group III nitride diode device of claim 2, wherein: the first type of contact comprises an ohmic contact, and the second type of contact comprises an ohmic contact or a Schottky contact.

4. The group III nitride diode device of claim 1, wherein: the third semiconductor comprises a p-type wide-bandgap semiconductor.

5. The group III nitride diode device of claim 4, wherein: the p-type wide-bandgap semiconductor comprises a p-type III-nitride.

6. The group III nitride diode device of claim 5, wherein: the p-type III-nitride comprises p-type GaN, p-type AlGaN, p-type InGaN or p-type InN.

7. The group III nitride diode device of claim 4, wherein: the p-type wide-bandgap semiconductor comprises p-NiO.

8. The group III nitride diode device of claim 1, wherein: the n-type semiconductor comprises n-type GaN, n-type Ga2O3, n-type In2O3, n-type InGaN or n-type InN.

9. The group III nitride diode device of claim 1, wherein: the first electrode and the second electrode are respectively an anode and a cathode.

10. The group III nitride diode device of claim 1, wherein: the first semiconductor, the second semiconductor and the third semiconductor are sequentially stacked, the first portion of the first electrode and the second electrode are both disposed on the second semiconductor, and the second portion of the first electrode is disposed on the first portion and the plurality of third semiconductors.

11. The group III nitride diode device of claim 10, wherein: the second portion of the first electrode completely covers the plurality of third semiconductors.

12. The group III nitride diode device of claim 10, wherein: the plurality of third semiconductors are sequentially and spaced apart in a specified direction, and the two ends of any third semiconductor point to the first portion of the first electrode and the second electrode respectively.

13. The group III nitride diode device of claim 12, wherein: the width of the third semiconductor is not less than 2μm, the length of the third semiconductor is 10nm-10μm, and the spacing between any two adjacent third semiconductors is 1nm-10μm.

14. The group III nitride diode device of claim 10 or 13, wherein: the thickness of the third semiconductor is 10nm-1μm.

15. The group III nitride diode device of claim 1 or 10, wherein: the first semiconductor and the second semiconductor are both selected from III-nitride.

16. The group III nitride diode device of claim 15, wherein: the first semiconductor comprises GaN.

17. The group III nitride diode device of claim 15, wherein: The material of the second semiconductor includes Al x Ga (1-x) N, AlInGaN or In x Al (1-x) N, 0 < x ≤ 1.

18. The group III nitride diode device of claim 1, wherein: the III-nitride diode device further comprises a field plate. 19.A method for manufacturing a III-nitride diode device, comprising: The method comprises the following steps: The method further comprises the following steps: The third semiconductor is a p-type semiconductor, and the fourth semiconductor is an n-type semiconductor. The p-type wide-bandgap semiconductor comprises a p-type group-III nitride.

20. The method of manufacturing of claim 19, wherein: The p-type group-III nitride comprises p-type GaN, p-type AlGaN, p-type InGaN or p-type InN.

21. The method of manufacturing according to claim 20, wherein: The p-type wide-bandgap semiconductor comprises p-NiO.

22. The method of manufacturing according to claim 21, wherein: The n-type semiconductor comprises n-type GaN, n-type Ga2O3, n-type In2O3, n-type InGaN or n-type InN.

23. The method of making of claim 19, wherein: The method comprises the following steps:

24. The method of making of claim 19, wherein: The first semiconductor and the second semiconductor cooperate to form a heterojunction, and the heterojunction forms a two-dimensional electron gas; 25. A group III nitride semiconductor device, characterized by, The anode and the cathode are spaced apart on the heterojunction, and the anode and the cathode are electrically connected through the two-dimensional electron gas; The source, the drain and the gate are spaced apart on the heterojunction, the source and the drain are also electrically connected through the two-dimensional electron gas, the gate is arranged between the source and the drain, and the source, the drain, the gate and the heterojunction form a HEMT device structure; The third semiconductor is a p-type semiconductor, and the fourth semiconductor is an n-type semiconductor. The p-type wide-bandgap semiconductor comprises a p-type group-III nitride. The p-type group-III nitride comprises p-type GaN, p-type AlGaN, p-type InGaN or p-type InN. The p-type wide-bandgap semiconductor comprises p-NiO. The n-type semiconductor comprises n-type GaN, n-type Ga2O3, n-type In2O3, n-type InGaN or n-type InN. The method comprises the following steps: The first semiconductor and the second semiconductor cooperate to form a heterojunction, and the heterojunction forms a two-dimensional electron gas; The anode and the cathode are spaced apart on the heterojunction, and the anode and the cathode are electrically connected through the two-dimensional electron gas; The source, the drain and the gate are spaced apart on the heterojunction, the source and the drain are also electrically connected through the two-dimensional electron gas, the gate is arranged between the source and the drain, and the source, the drain, the gate and the heterojunction form a HEMT device structure; The third semiconductor is a p-type semiconductor, and the fourth semiconductor is an n-type semiconductor. The p-type wide-bandgap semiconductor comprises a p-type group-III nitride. The p-type group-III nitride comprises p-type GaN, p-type AlGaN, p-type InGaN or p-type InN. The p-type wide-bandgap semiconductor comprises p-NiO. The n-type semiconductor comprises n-type GaN, n-type Ga2O3, n-type In2O3, n-type InGaN or n-type InN. The anode is disposed between the gate and the drain, and includes a first portion and a second portion electrically connected, the second portion being disposed on and in electrical contact with a plurality of third semiconductors, each of the third semiconductors having two ends pointing to the first portion of the anode and the cathode, respectively, and the anode is also electrically connected to the source, the anode, the cathode, the heterojunction and the pn junction being configured to form a diode device structure.

26. The group III nitride semiconductor device of claim 25, wherein A fifth semiconductor is also included, and the fifth semiconductor is disposed between the gate and the heterojunction and is capable of depleting the two-dimensional electron gas below the fifth semiconductor.

27. The group III nitride semiconductor device of claim 26, wherein: The fifth semiconductor is electrically isolated from the source and the drain by a high-resistance material, which is formed by converting a first region of a continuous fifth semiconductor layer, and the fifth semiconductor is distributed in a second region of the fifth semiconductor layer. Alternatively, the fifth semiconductor is formed by converting a second region of a continuous high-resistance material layer, and the high-resistance material is distributed in a first region of the high-resistance material layer.

28. The group III nitride semiconductor device of claim 25, wherein: The first portion of the anode forms a first type of electrical contact with the two-dimensional electron gas, and the second portion forms a second type of electrical contact with the plurality of third semiconductors.

29. The group III nitride semiconductor device of claim 28, wherein: The first type of electrical contact includes ohmic contact, and the second type of electrical contact includes ohmic contact or Schottky contact.

30. The group III nitride semiconductor device of claim 26, wherein: The fifth semiconductor is a p-type semiconductor.

31. The group III nitride semiconductor device of claim 30, wherein: The third semiconductor and the fifth semiconductor include a p-type wide-bandgap semiconductor.

32. The group III nitride semiconductor device of claim 31, wherein: The p-type wide-bandgap semiconductor includes a p-type group III nitride.

33. The group III nitride semiconductor device of claim 32, wherein: The p-type group III nitride includes p-type GaN, p-type AlGaN, p-type InGaN or p-type InN.

34. The group III nitride semiconductor device of claim 31, wherein: The p-type wide-bandgap semiconductor includes p-NiO.

35. The group III nitride semiconductor device of claim 26, wherein: The n-type semiconductor includes n-type GaN, n-type Ga2O3, n-type In2O3, n-type InGaN or n-type InN.

36. The group III nitride semiconductor device of claim 25, wherein: The first semiconductor, the second semiconductor and the third semiconductor are sequentially stacked, and the first portion of the anode and the cathode are both disposed on the second semiconductor.

37. The group III nitride semiconductor device of claim 36, wherein: The plurality of third semiconductors are sequentially and spacedly arranged in a specified direction.

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