Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: a shallow trench isolation structure is formed in a substrate, the shallow trench isolation structure extends upward from the substrate and has a first protruding part protruding from the substrate; a local oxidation material layer is located at the junction of an active region and the shallow trench isolation structure and has a second protruding part protruding from the upper surface of the active region; a sacrificial oxide layer is located on the upper surface of the active region and is in contact with the local oxidation material layer; the sacrificial oxide layer and the second protruding part are removed to form a local oxidation layer and form a groove on the side wall of the first protruding part towards the local oxidation layer; a gate oxide layer is located on the upper surface of the active region and is in contact with the local oxidation layer; and a gate electrode is located at least on the upper surface of the gate oxide layer and fills the groove. The preparation method of the semiconductor structure optimizes the semiconductor structure, improves the reliability of the semiconductor device, and reduces the failure rate of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the continuous development of semiconductor processing technology, semiconductor devices are increasingly being used in electronics, communications and other fields due to their smaller size, higher performance and higher conversion efficiency.

[0003] However, as semiconductor device dimensions shrink, the reliability of the gate oxide layer remains a key focus and challenge in the development of various chip fabrication platforms. In the fabrication process of small-size semiconductor devices, wet etching to remove the sacrificial oxide layer can easily cause depressions at the corners of shallow trench isolation structures, resulting in a thinner gate oxide layer at the active region corners. During the reliability testing of semiconductor devices, the gate oxide layer at the active region corners is easily broken down.

[0004] Therefore, optimizing the semiconductor structure to improve the voltage withstand capability of the gate oxide layer and thus improve the reliability of semiconductor devices is an urgent problem to be solved. Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to improve the voltage withstand capability of the gate oxide layer by optimizing the semiconductor structure, thereby improving the reliability of the semiconductor device.

[0006] On one hand, embodiments of this application provide a method for fabricating a semiconductor structure, comprising the following steps: providing a substrate, wherein a shallow trench isolation structure is formed within the substrate, the shallow trench isolation structure extending upward from within the substrate and having a first protrusion protruding from the substrate. The shallow trench isolation structure isolates a plurality of spaced active regions within the substrate. A local oxide layer is formed, the local oxide layer being located at the boundary between the active regions and the shallow trench isolation structure, embedded within the active regions, and having a second protrusion protruding from the upper surface of the active regions. A sacrificial oxide layer is formed, the sacrificial oxide layer being located on the upper surface of the active regions, and on the side of the local oxide layer away from the shallow trench isolation structure, and in contact with the local oxide layer. The sacrificial oxide layer and the second protrusion are removed to form a local oxide layer, and a groove is formed on the sidewall of the first protrusion facing the local oxide layer. A gate oxide layer is formed, the gate oxide layer being located on the upper surface of the active regions, and on the side of the local oxide layer away from the shallow trench isolation structure, and in contact with the local oxide layer. A gate is formed, the gate being at least located on the upper surface of the gate oxide layer and filling the groove.

[0007] In this embodiment, the semiconductor structure is fabricated using the method described above. First, a local oxide layer extending to the upper surface of the active region is formed within the active region. This local oxide layer is located at the boundary between the active region and the shallow trench isolation structure. Second, after forming the local oxide layer, a gate oxide layer in contact with the local oxide layer is formed on the upper surface of the active region, and a gate electrode filling the trench is formed on the upper surface of the gate oxide layer. Thus, the presence of the local oxide layer increases the oxide layer thickness between the active region corner and the gate electrode, making the oxide layer at the active region corner less prone to breakdown during semiconductor device reliability testing, thereby improving the voltage withstand capability of the gate oxide layer. Therefore, the above semiconductor structure fabrication method, without increasing the use of a mask, improves the voltage withstand capability of the gate oxide layer by optimizing the semiconductor structure, thereby improving the reliability of the semiconductor device and reducing the failure rate of the semiconductor device.

[0008] Optionally, removing the sacrificial oxide layer includes using a wet etching process.

[0009] Optionally, forming a localized oxide material layer includes: forming a localized oxide material layer using a selective oxidation process.

[0010] In this embodiment, selective oxidation is a necessary conventional process for bipolar-CMOS-DMOS (BCD) technology. Therefore, selective oxidation forms a localized oxide material layer without the need for additional masks or extra process steps. The optimized semiconductor structure can then be obtained by following the normal process flow.

[0011] Optionally, the gate is located at least on the upper surface of the gate oxide layer, and filling the groove includes: the gate extending from the upper surface of the gate oxide layer through the upper surface of the local oxide layer to the upper surface of the first protrusion.

[0012] Optionally, after forming the gate, the method further includes: forming a source region and a drain region in the active region, with the source region and drain region located on opposite sides of the gate; forming a source region lead-out electrode, a drain region lead-out electrode and a gate lead-out electrode on the substrate, with the source region lead-out electrode in contact with the source region, the drain region lead-out electrode in contact with the drain region, and the gate lead-out electrode in contact with the gate.

[0013] On the other hand, embodiments of this application also provide a semiconductor structure, including: a substrate having a shallow trench isolation structure therein, the shallow trench isolation structure extending upward from within the substrate and having a first protrusion protruding from the substrate; the shallow trench isolation structure isolates a plurality of spaced active regions within the substrate. A local oxide layer is located at the boundary between the active regions and the shallow trench isolation structure and is embedded within the active regions; the sidewall of the first protrusion facing the local oxide layer has a groove. A gate oxide layer is located on the upper surface of the active regions and on the side of the local oxide layer away from the shallow trench isolation structure, and is in contact with the local oxide layer. A gate is located at least on the upper surface of the gate oxide layer and fills the groove.

[0014] In this embodiment, the semiconductor structure adopts the structure described above. This application adds a local oxide layer at the boundary between the active region and the shallow trench isolation structure. Furthermore, the gate oxide layer is located on the upper surface of the active region and contacts the local oxide layer, and the gate is on the upper surface of the gate oxide layer and fills the trench. Thus, the presence of the local oxide layer increases the oxide layer thickness between the active region corner and the gate, making the oxide layer at the active region corner less prone to breakdown during semiconductor device reliability testing. This improves the withstand voltage capability of the gate oxide layer, thereby improving the reliability of the semiconductor device and reducing its failure rate.

[0015] Optionally, the gate is located at least on the upper surface of the gate oxide layer, and filling the groove includes: the gate extending from the upper surface of the gate oxide layer through the upper surface of the local oxide layer to the upper surface of the first protrusion.

[0016] Optionally, the semiconductor structure further includes: a source region located within the active region and on one side of the gate; a drain region located within the active region and on the side of the gate away from the source region; a source region lead-out electrode located on the source region and in contact with the source region; a drain region lead-out electrode located on the drain region and in contact with the drain region; and a gate lead-out electrode located on the gate and in contact with the gate.

[0017] Optionally, the gate lead electrode is located directly above the first protrusion.

[0018] Optionally, there are multiple source regions and multiple drain regions, and the multiple source regions and multiple drain regions are arranged at intervals along the direction of the gate extension. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1An electron microscope image of a semiconductor structure;

[0021] Figure 2 This is a flowchart of a semiconductor structure fabrication method provided in one embodiment of this application;

[0022] Figure 3 This is a schematic cross-sectional view of the structure obtained in step S10 of the semiconductor structure fabrication method provided in one embodiment of this application.

[0023] Figure 4 This is a schematic cross-sectional view of the structure obtained in step S20 of the semiconductor structure fabrication method provided in one embodiment of this application;

[0024] Figure 5 This is a top view of the structure obtained in step S20 of the semiconductor structure fabrication method provided in one embodiment of this application;

[0025] Figure 6 This is a schematic cross-sectional view of the structure obtained in step S30 of the semiconductor structure fabrication method provided in one embodiment of this application;

[0026] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S40 of the semiconductor structure fabrication method provided in one embodiment of this application;

[0027] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S50 of the semiconductor structure fabrication method provided in one embodiment of this application;

[0028] Figure 9 This is a schematic cross-sectional view of the structure obtained in step S60 of the semiconductor structure fabrication method provided in one embodiment of this application.

[0029] Figure 10 This is a top view schematic diagram of the structure obtained after forming the source region lead-out electrode, the drain region lead-out electrode, and the gate lead-out electrode in a semiconductor structure fabrication method provided in one embodiment of this application.

[0030] Explanation of reference numerals in the attached figures:

[0031] 1-Substrate; 10, 10'-Active regions; 11, 11'-Shallow trench isolation structure; 111-First protrusion;

[0032] 200 - Localized oxide layer; 201 - Second protrusion; 20 - Localized oxide layer; 30 - Sacrificial oxide layer; 40, 40' - Gate oxide layer; 50 - Gate electrode;

[0033] A - Source region; B - Drain region; 101 - Source region lead-out electrode; 102 - Drain region lead-out electrode; 501 - Gate region lead-out electrode. Detailed Implementation

[0034] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0038] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] When used here, "deposition" processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0040] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0041] With the continuous development of semiconductor processing technology, semiconductor devices are increasingly being used in electronics, communications and other fields due to their smaller size, higher performance and higher conversion efficiency.

[0042] However, as semiconductor device dimensions shrink, the reliability of the gate oxide layer remains a key focus and challenge in the development of various chip fabrication platforms. In the fabrication process of small-size semiconductor devices, wet etching to remove the sacrificial oxide layer can easily cause depressions at the corners of shallow trench isolation structures, resulting in a thinner gate oxide layer at the active region corners. During the reliability testing of semiconductor devices, the gate oxide layer at the active region corners is easily broken down.

[0043] Taking a gate oxide layer thickness of 0.15 μm as an example, such as Figure 1As shown, after removing the sacrificial oxide layer, a depression easily appears at the corner of the shallow trench isolation structure 11', resulting in a thin gate oxide layer generated at the corner of the active region 10', which is only 7.283nm, while the gate oxide layer 40' at the center of the active region 10' is 13.35nm. That is, the gate oxide layer 40' generated at the corner of the active region 10' is 6.067nm less than that at the center. Therefore, the gate oxide layer 40' generated at the corner of the active region 10' becomes the most vulnerable point to breakdown during reliability testing.

[0044] Therefore, optimizing the semiconductor structure to improve the voltage withstand capability of the gate oxide layer and thus improve the reliability of semiconductor devices is an urgent problem to be solved.

[0045] Therefore, this application embodiment needs to provide a semiconductor structure and its fabrication method to improve the voltage withstand capability of the gate oxide layer by optimizing the semiconductor structure, thereby improving the reliability of the semiconductor device.

[0046] Please see Figure 2 This application provides a method for fabricating a semiconductor structure, comprising the following steps:

[0047] S10: Provides a substrate in which a shallow trench isolation structure is formed. The shallow trench isolation structure extends upward from the substrate and has a first protrusion protruding from the substrate. The shallow trench isolation structure isolates multiple spaced active regions within the substrate.

[0048] S20: A localized oxide material layer is formed. The localized oxide material layer is located at the junction of the active region and the shallow trench isolation structure, embedded in the active region, and has a second protrusion protruding from the upper surface of the active region.

[0049] S30: A sacrificial oxide layer is formed. The sacrificial oxide layer is located on the upper surface of the active region and on the side of the local oxide material layer away from the shallow trench isolation structure, and is in contact with the local oxide material layer.

[0050] S40: Remove the sacrificial oxide layer and the second protrusion to form a local oxide layer, and form a groove on the sidewall of the first protrusion facing the local oxide layer.

[0051] S50: A gate oxide layer is formed, which is located on the upper surface of the active region and on the side of the local oxide layer away from the shallow trench isolation structure, and is in contact with the local oxide layer.

[0052] S60: Form a gate, which is located at least on the upper surface of the gate oxide layer and fills the trench.

[0053] In this embodiment, the semiconductor structure is fabricated using the method described above. First, a local oxide layer extending to the upper surface of the active region is formed within the active region. This local oxide layer is located at the boundary between the active region and the shallow trench isolation structure. Second, after forming the local oxide layer, a gate oxide layer in contact with the local oxide layer is formed on the upper surface of the active region, and a gate electrode filling the trench is formed on the upper surface of the gate oxide layer. Thus, the presence of the local oxide layer increases the oxide layer thickness between the active region corner and the gate electrode, making the oxide layer at the active region corner less prone to breakdown during semiconductor device reliability testing, thereby improving the voltage withstand capability of the gate oxide layer. Therefore, the above semiconductor structure fabrication method, without increasing the use of a mask, improves the voltage withstand capability of the gate oxide layer by optimizing the semiconductor structure, thereby improving the reliability of the semiconductor device and reducing the failure rate of the semiconductor device.

[0054] The following combination Figures 3 to 10 The semiconductor structure fabrication method provided in the embodiments of this application will be described in detail.

[0055] In step S10, please refer to Figure 2 Step S10 in the middle and Figure 3 A substrate 1 is provided, and a shallow trench isolation structure 11 is formed in the substrate 1. The shallow trench isolation structure 11 extends upward from the substrate 1 and has a first protrusion 111 protruding from the substrate 1. The shallow trench isolation structure 11 isolates a plurality of spaced active regions 10 in the substrate 1.

[0056] In some examples, substrate 1 may be made of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 may be a single-layer structure or a multilayer structure. For example, substrate 1 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 may be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0057] In one example, substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate. Optionally, substrate 1 is a sapphire substrate, a silicon germanide substrate, or a silicon carbide substrate.

[0058] In some examples, the shallow trench isolation structure 11 can be an oxide isolation structure, such as a silicon oxide isolation structure.

[0059] In some examples, the active region 10 can be a columnar structure. The orthographic projection shape of the active region 10 onto the surface of the substrate 1 can be elliptical or parallelogram, etc.

[0060] In an optional embodiment, before forming the shallow trench isolation structure 11 in the substrate 1, a step of cleaning the substrate 1 may be included. By cleaning, impurities on the surface of the substrate 1 can be removed to avoid affecting subsequent processes, thereby ensuring the performance of the device.

[0061] Specifically, substrate 1 can be cleaned using a cleaning solution, which can be placed in a cleaning tank containing the cleaning solution for cleaning; alternatively, substrate 1 can be cleaned by spraying. The specific cleaning solution and cleaning process used for cleaning substrate 1 are known to those skilled in the art and will not be described in detail here.

[0062] It should be noted that after cleaning the substrate 1, the process also includes drying the substrate 1. The method for drying the substrate 1 is well known to those skilled in the art and will not be described in detail here.

[0063] In step S20, please refer to Figure 2 Step S20 in the middle Figure 4 and Figure 5 A localized oxide material layer 200 is formed. The localized oxide material layer 200 is located at the junction of the active region 10 and the shallow trench isolation structure 11, embedded in the active region 10, and has a second protrusion 201 protruding from the upper surface of the active region 10.

[0064] Optionally, the localized oxide material layer 200 includes, but is not limited to, a silicon oxide layer.

[0065] Optionally, forming the localized oxide material layer 200 includes forming the localized oxide material layer 200 using a selective oxidation process.

[0066] The selective oxidation process is a necessary conventional process for the fabrication of the semiconductor structure described above. Therefore, the selective oxidation process forms a localized oxide material layer 200 without the need for additional masks or additional process steps. The optimized semiconductor structure can then be obtained by proceeding with the normal process flow.

[0067] In some examples, the localized oxide layer 200 is beak-shaped. For example, the localized oxide layer 200 may not cover the upper surface of the active region 10, or it may cover part of the upper surface of the active region 10.

[0068] In step S30, please refer to Figure 2 Step S30 in the middle and Figure 6A sacrificial oxide layer 30 is formed, which is located on the upper surface of the active region 10 and on the side of the local oxide material layer 200 away from the shallow trench isolation structure 11, and is in contact with the local oxide material layer 200.

[0069] In some examples, the thickness of the sacrificial oxide layer 30 can be set according to actual needs.

[0070] In step S40, please refer to Figure 2 Step S40 in the middle and Figure 7 The sacrificial oxide layer 30 and the second protrusion 201 are removed to form a local oxide layer 20, and a groove is formed on the sidewall of the first protrusion 111 toward the local oxide layer 20.

[0071] Optionally, removing the sacrificial oxide layer 30 includes: removing the sacrificial oxide layer 30 using a wet etching process.

[0072] In step S50, please refer to Figure 2 S50 steps and Figure 8 A gate oxide layer 40 is formed, which is located on the upper surface of the active region 10 and on the side of the local oxide layer 20 away from the shallow trench isolation structure 11, and is in contact with the local oxide layer 20.

[0073] In some examples, the gate oxide layer 40 is located on the side of the local oxide layer 20 away from the shallow trench isolation structure 11 and is in contact with the local oxide layer 20. In this way, the gate oxide layer 40 at the corner of the active region 10 is less likely to be broken down, thereby improving the withstand voltage capability of the gate oxide layer 40.

[0074] Optionally, the gate oxide layer 40 includes, but is not limited to, a silicon oxide layer.

[0075] In some examples, the gate oxide layer 40 is located on the upper surface of the active region 10 and exposes a portion of the upper surface of the active region 10.

[0076] In step S60, please refer to Figure 2 Step S60 in the middle Figure 9 and Figure 10 A gate 50 is formed, which is located at least on the upper surface of the gate oxide layer 40 and fills the groove.

[0077] In some examples, please refer to Figure 9 as well as Figure 10The gate 50 extends from the upper surface of the gate oxide layer 40 through the upper surface of the local oxide layer 20 to the upper surface of the first protrusion 111, filling the groove. Thus, a local oxide layer 20 is formed at the corner of the gate 50 and the active region 10, making the gate oxide layer 40 at the corner of the active region 10 less prone to breakdown during semiconductor device reliability testing, thereby improving the withstand voltage capability of the gate oxide layer 40.

[0078] Optionally, please refer to Figure 10 After forming the gate 50, the process further includes: forming a source region A and a drain region B within the active region 10, with source region A and drain region B located on opposite sides of the gate 50. A source region lead-out electrode 101, a drain region lead-out electrode 102, and a gate lead-out electrode 501 are formed on the substrate 1, with the source region lead-out electrode 101 in contact with the source region A, the drain region lead-out electrode 102 in contact with the drain region B, and the gate lead-out electrode 501 in contact with the gate 50.

[0079] Based on the same inventive concept, please refer to Figure 9 as well as Figure 10 This application also provides a semiconductor structure, including: a substrate 1, a local oxide layer 20, a gate oxide layer 40, and a gate 50. The substrate 1 has a shallow trench isolation structure 11, which extends upward from the substrate 1 and has a first protrusion 111 protruding from the substrate. The shallow trench isolation structure 11 isolates a plurality of spaced active regions 10 within the substrate 1. The local oxide layer 20 is located at the junction of the active regions 10 and the shallow trench isolation structure 11, embedded within the active regions 10, and the first protrusion 111 has a groove on its sidewall facing the local oxide layer 20. The gate oxide layer 40 is located on the upper surface of the active regions 10 and on the side of the local oxide layer 20 away from the shallow trench isolation structure 11, and is in contact with the local oxide layer 20. The gate 50 is located at least on the upper surface of the gate oxide layer 40 and fills the groove.

[0080] In this embodiment, the semiconductor structure adopts the structure described above. A local oxide layer 20 is added at the junction of the active region 10 and the shallow trench isolation structure 11. Furthermore, the gate oxide layer 40 is located on the upper surface of the active region 10 and contacts the local oxide layer 20, and the gate 50 is on the upper surface of the gate oxide layer 40 and fills the trench. Thus, the presence of the local oxide layer 20 increases the oxide layer thickness between the corner of the active region 10 and the gate 50, making the oxide layer at the corner of the active region 10 less prone to breakdown during semiconductor device reliability testing. This improves the withstand voltage capability of the gate oxide layer 40, thereby improving the reliability of the semiconductor device and reducing its failure rate.

[0081] In some examples, substrate 1 may be made of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 may be a single-layer structure or a multilayer structure. For example, substrate 1 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 may be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0082] In one example, substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate. Optionally, substrate 1 is a sapphire substrate, a silicon germanide substrate, or a silicon carbide substrate.

[0083] In some examples, the shallow trench isolation structure 11 can be an oxide isolation structure, such as a silicon oxide isolation structure.

[0084] In some examples, the active region 10 can be a columnar structure. The orthographic projection shape of the active region 10 onto the surface of the substrate 1 can be elliptical or parallelogram, etc.

[0085] Optionally, the local oxide layers 20 include, but are not limited to, silicon oxide layers.

[0086] Optionally, the gate oxide layer 40 includes, but is not limited to, a silicon oxide layer.

[0087] In some examples, the gate oxide layer 40 is located on the upper surface of the active region 10 and exposes a portion of the upper surface of the active region 10.

[0088] In some examples, please refer to Figure 9 and Figure 10 The gate 50 extends from the upper surface of the gate oxide layer 40 through the upper surface of the local oxide layer 20 to the upper surface of the first protrusion 111, filling the groove. Thus, a local oxide layer 20 is formed at the corner of the gate 50 and the active region 10, making the gate oxide layer 40 at the corner of the active region 10 less prone to breakdown during semiconductor device reliability testing, thereby improving the withstand voltage capability of the gate oxide layer 40.

[0089] In some examples, please refer to Figure 10The semiconductor structure also includes: a source region A, a drain region B, a source region lead-out electrode 101, a drain region lead-out electrode 102, and a gate lead-out electrode 501. The source region A is located within the active region 10 and is situated on one side of the gate 50. The drain region B is located within the active region 10 and is situated on the side of the gate 50 furthest from the source region A. The source region lead-out electrode 101 is located on and in contact with the source region A. The drain region lead-out electrode 102 is located on and in contact with the drain region B. The gate lead-out electrode 501 is located on and in contact with the gate 50.

[0090] Optionally, the gate lead electrode 501 is located directly above the first protrusion 111.

[0091] Optionally, there are multiple source regions A and multiple drain regions B, and the multiple source regions A and multiple drain regions B are arranged at intervals along the direction extending from the gate 50.

[0092] In the description of this specification, the technical features of the above-described embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided in which a shallow trench isolation structure is formed, the shallow trench isolation structure extending upward from the substrate and having a first protrusion protruding from the substrate; the shallow trench isolation structure isolates a plurality of spaced active regions within the substrate. A localized oxide material layer is formed, which is located at the junction of the active region and the shallow trench isolation structure, embedded in the active region, and has a second protrusion protruding from the upper surface of the active region; A sacrificial oxide layer is formed, which is located on the upper surface of the active region and on the side of the local oxide material layer away from the shallow trench isolation structure, and is in contact with the local oxide material layer; Remove the sacrificial oxide layer and the second protrusion to form a local oxide layer, and form a groove on the sidewall of the first protrusion facing the local oxide layer; A gate oxide layer is formed, which is located on the upper surface of the active region and on the side of the local oxide layer away from the shallow trench isolation structure, and is in contact with the local oxide layer; A gate is formed, the gate being located at least on the upper surface of the gate oxide layer and filling the groove.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Removing the sacrificial oxide layer includes: removing the sacrificial oxide layer using a wet etching process.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of the localized oxide material layer includes: forming the localized oxide material layer using a selective oxidation process.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The gate is located at least on the upper surface of the gate oxide layer, and filling the groove includes: the gate extending from the upper surface of the gate oxide layer through the upper surface of the local oxide layer to the upper surface of the first protrusion.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The process after forming the gate also includes: A source region and a drain region are formed within the active region, wherein the source region and the drain region are located on opposite sides of the gate, respectively; A source electrode, a drain electrode, and a gate electrode are formed on the substrate. The source electrode is in contact with the source region, the drain electrode is in contact with the drain region, and the gate electrode is in contact with the gate.

6. A semiconductor structure, characterized in that, Prepared by the preparation method according to any one of claims 1 to 5, comprising: A substrate having a shallow trench isolation structure extending upward from within the substrate and having a first protrusion protruding from the substrate; the shallow trench isolation structure isolates a plurality of spaced active regions within the substrate. A localized oxide layer is located at the junction of the active region and the shallow trench isolation structure and is embedded within the active region; the first protrusion has a groove on its sidewall facing the localized oxide layer. A gate oxide layer is located on the upper surface of the active region and on the side of the local oxide layer away from the shallow trench isolation structure, and is in contact with the local oxide layer; A gate, which is located at least on the upper surface of the gate oxide layer and fills the groove.

7. The semiconductor structure according to claim 6, characterized in that, The gate is located at least on the upper surface of the gate oxide layer, and filling the groove includes: the gate extending from the upper surface of the gate oxide layer through the upper surface of the local oxide layer to the upper surface of the first protrusion.

8. The semiconductor structure according to claim 6, characterized in that, Also includes: The source region is located within the active region and is located on one side of the gate. The drain region is located within the active region and on the side of the gate furthest from the source region; A source region lead-out electrode is located on the source region and is in contact with the source region; A drain electrode is provided, located on the drain region, and in contact with the drain region. A gate lead electrode is located on the gate and is in contact with the gate.

9. The semiconductor structure according to claim 8, characterized in that, The gate lead-out electrode is located directly above the first protrusion.

10. The semiconductor structure according to claim 8, characterized in that, The number of source regions and the number of drain regions are both multiple, and the multiple source regions and the multiple drain regions are arranged at intervals along the direction of extension of the gate.

Images