Stacked nanosheet gaa-fet device and method of fabrication thereof

Abstract

This application provides a stacked nanosheet GAA-FET device and its fabrication method. A stacked layer of alternating first and second semiconductor layers is formed on a substrate; the stacked layer is etched to form fins; partial regions at both ends of the first semiconductor layer are etched from the outside in, forming second sidewalls at both ends of the first semiconductor layer; the first semiconductor layer is removed to release the nanosheet channel, with the second semiconductor layer serving as the channel; the overlapping region of the second sidewall and the channel is laterally etched to form a gap; an interface oxide layer and a first high-k dielectric layer are formed in the gap; a second high-k dielectric layer is formed between the first high-k dielectric layer and the second sidewall, and around the channel, forming a metal gate surrounding the channel. The formation of the interface oxide layer, the first high-k dielectric layer, and the second high-k dielectric layer between the channel and the second sidewall suppresses the electric field generated by the metal gate from conducting to the overlapping region of the source / drain region and the channel, weakens the electric field strength in the overlapping region, suppresses band-to-band tunneling leakage, and avoids device off-state leakage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a stacked nanosheet GAA-FET device and a manufacturing method thereof. BACKGROUND

[0002] With the continuous scaling of integrated circuit feature size, the traditional fin field-effect transistor (FinFET) with three gates or double gates is limited at the node below 3nm, and the nanoribbon gate transistor (Gate-all-around Field-Effect Transistor, GAA-FET) compatible with the mainstream post-high-k metal gate FinFET process will be the next generation of key structures to realize size scaling. The channel of the GAA-FET is mainly a stacked nanosheet structure. However, there is band-to-band tunneling (BTBT) leakage in the overlapping area between the source-drain region and the channel of the GAA-FET, which causes the off-state leakage of the device to increase sharply. SUMMARY

[0003] Therefore, the purpose of the present application is to provide a stacked nanosheet GAA-FET device and a manufacturing method thereof, which suppresses the generation of band-to-band tunneling leakage in the overlapping area between the source-drain region and the channel, avoids the off-state leakage of the device, and improves the performance of the device. The specific scheme is as follows:

[0004] In a first aspect, the present application provides a manufacturing method of a stacked nanosheet GAA-FET device, comprising:

[0005] forming a stacked layer of first semiconductor layers and second semiconductor layers alternately stacked on a substrate;

[0006] etching the stacked layer to form a fin, and forming a dummy gate and a first sidewall on the fin;

[0007] etching the first semiconductor layers from the outside to the inside in the partial area at both ends of the first semiconductor layers, and forming a second sidewall at both ends of the first semiconductor layers;

[0008] removing the first semiconductor layers to release nanosheet channels, and the second semiconductor layers as channels;

[0009] laterally etching the overlapping area of the second sidewall and the channel to form a gap;

[0010] forming an interface oxide layer and a first high-k dielectric layer in the gap;

[0011] forming a second high-k dielectric layer between the first high-k dielectric layer and the second sidewall, and around the channel, and forming a metal gate surrounding the channel.

[0012] Secondly, embodiments of this application also provide a stacked nanosheet GAA-FET device, comprising:

[0013] A substrate, and a fin located on one side of the substrate; the fin includes a plurality of second semiconductor layers, the second semiconductor layers serving as channels;

[0014] A high-k metal gate structure includes an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer, and a metal gate; the metal gate surrounds a second semiconductor layer, and the metal gate has second sidewalls at both ends; the interface oxide layer and the first high-k dielectric layer are located between the channel and the second sidewall; the second high-k dielectric layer is located between the channel and the second sidewall, and around the channel.

[0015] This application provides a stacked nanosheet GAA-FET device and its fabrication method. A stacked layer of alternating first and second semiconductor layers is formed on a substrate. The stacked layer is etched to form fins, and a dummy gate and a first sidewall are formed on the fins. Partial regions at both ends of the first semiconductor layer are etched from the outside inwards to form second sidewalls at both ends of the first semiconductor layer. The first semiconductor layer is removed to release a nanosheet channel, with the second semiconductor layer serving as the channel. Laterally, the overlapping region of the second sidewall and the channel is etched to form a gap. An interface oxide layer and a first high-k dielectric layer are formed in the gap. A second high-k dielectric layer is formed between the first high-k dielectric layer and the second sidewall, and around the channel, forming a metal gate surrounding the channel. In contrast to existing technologies where the electric field generated by the metal gate is conducted to the overlapping region of the source / drain region and the channel, leading to band-to-band tunneling leakage, in this embodiment, by forming an interface oxide layer, a first high-k dielectric layer, and a second high-k dielectric layer between the channel and the second sidewall, the conduction of the electric field to the overlapping region of the source / drain region and the channel can be suppressed, the electric field intensity in the overlapping region of the source / drain region and the channel can be weakened, and the electric field distribution in the overlapping region can be changed. This suppresses the generation of band-to-band tunneling leakage in the overlapping region of the source / drain region and the channel, avoids device off-state leakage, and improves device performance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic flowchart of a method for fabricating a stacked nanosheet GAA-FET device according to an embodiment of this application is shown;

[0018] Figures 2-21 A schematic diagram of a stacked nanosheet GAA-FET device provided in an embodiment of this application is shown. Detailed Implementation

[0019] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0020] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0021] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0022] As described in the background section, there is band-to-band tunneling (BTBT) leakage in the overlapping region of the source / drain region and the channel of the GAA-FET, which causes a sharp increase in the off-state leakage of the device.

[0023] Based on the above technical problems, this application provides a stacked nanosheet GAA-FET device and its fabrication method. The method involves forming a stacked layer of alternating first and second semiconductor layers on a substrate; etching the stacked layer to form fins, and forming a dummy gate and a first sidewall on the fins; etching a portion of the two ends of the first semiconductor layer from the outside in, forming second sidewalls at both ends of the first semiconductor layer; removing the first semiconductor layer to release the nanosheet channel, with the second semiconductor layer serving as the channel; laterally etching the overlapping area of ​​the second sidewall and the channel to form a gap; forming an interface oxide layer and a first high-k dielectric layer in the gap; forming a second high-k dielectric layer between the first high-k dielectric layer and the second sidewall, and surrounding the channel, and forming a metal gate surrounding the channel. In contrast to existing technologies where the electric field generated by the metal gate is conducted to the overlapping region of the source / drain region and the channel, leading to band-to-band tunneling leakage, in this embodiment, by forming an interface oxide layer, a first high-k dielectric layer, and a second high-k dielectric layer between the channel and the second sidewall, the conduction of the electric field to the overlapping region of the source / drain region and the channel can be suppressed, the electric field intensity in the overlapping region of the source / drain region and the channel can be weakened, and the electric field distribution in the overlapping region can be changed. This suppresses the generation of band-to-band tunneling leakage in the overlapping region of the source / drain region and the channel, avoids device off-state leakage, and improves device performance.

[0024] For ease of understanding, the following detailed description, in conjunction with the accompanying drawings, provides an embodiment of a stacked nanosheet GAA-FET device and its fabrication method.

[0025] refer to Figure 1 The diagram shown is a flowchart illustrating a method for fabricating a stacked nanosheet GAA-FET device according to an embodiment of this application. The method may include the following steps.

[0026] S101, a stacked layer of alternating first and second semiconductor layers is formed on the substrate.

[0027] In this embodiment, a substrate is provided. The substrate material can be Si or SiGe. A bulk silicon Si substrate can be used and then doped. Specifically, a highly doped well region is formed in the bulk silicon substrate by implanting impurities, diffusion, and annealing to achieve the desired well depth. For a P-type FET, the highly doped well region is an N-well, and the implanted impurity is an n-type impurity ion, such as phosphorus (P) ions. For an N-type FET, the highly doped well region is a p-well, and the implanted impurity is a p-type impurity ion, such as boron (B) ions.

[0028] In this embodiment, a stacked layer of alternating first semiconductor layer 101 and second semiconductor layer 102 can be formed on the substrate. Specifically, refer to... Figure 2 The diagram shown is a schematic diagram of the structure of a GAA-FET device provided in an embodiment of this application. The silicon dioxide (SiO2) on the surface of the bulk silicon substrate can be removed, and a stacked layer of alternating first semiconductor layer 101 and second semiconductor layer 102 can be epitaxially grown on the bulk silicon substrate 100.

[0029] The materials of the first semiconductor layer 101 and the second semiconductor layer 102 can be set according to actual needs. The first semiconductor layer 101 can be a germanium-based film layer, which can include an epitaxial germanium layer, an epitaxial silicon-germanium layer, or a combination thereof. The second semiconductor layer 102 can be an epitaxial silicon layer. For example, the first semiconductor layer / second semiconductor layer stack is SiGe / Si, and SiGe / Si periodic superlattice epitaxial growth is performed. The epitaxial process can be depressurized epitaxy or molecular beam epitaxy, etc.

[0030] S102, etch the stacked layers to form fins, and form a false gate and a first sidewall on the fins.

[0031] In this embodiment, the stacked layers can be etched to form fins, and dummy gates and first sidewalls can be formed on the fins. Specifically, refer to... Figure 3 A nanoscale array of first sidewall 104 devices can be formed using a self-aligned spacer image transfer (SIT) process. The first sidewall 104 can be silicon nitride (SiN). XThe specific formation process is as follows: a sacrificial layer 103 is deposited on the stacked layers. The sacrificial layer can be polycrystalline silicon (p-si) or amorphous silicon (a-si). Part of the sacrificial layer is etched away, and the first sidewall 104 is deposited. The material can be silicon nitride (SiN). x The remaining sacrificial layer is then etched away using anisotropic etching, leaving only the multiple periodic silicon nitride first sidewalls 104 on the stacked layer. The first sidewalls 104 can act as a hard mask in photolithography.

[0032] The epitaxially grown stacked layers are etched into multiple periodically distributed fins. The first sidewall 104 is used as a mask for etching to form fins with a stacked layer structure. The upper part of the fin is a conductive channel region formed by the stacked layers, and the lower part is a substrate, forming a structure as shown below. Figure 4 The fin shown is not only composed of stacked layer structures 101 / 102, but also includes a single-crystal silicon structure 100 extending into the substrate. The etching process is either dry etching or wet etching, such as reactive ion etching (RIE). The fin will be used to form one or more horizontal nanosheets of n-type and / or p-type field-effect transistors.

[0033] A shallow trench isolation (STI) region 105 can be formed between two adjacent fins to separate transistors on adjacent fins, such as... Figure 5 As shown. First, a dielectric insulating material is deposited, then planarized, for example using a CMP process, followed by selective etching back of the dielectric insulating material to expose a three-dimensional fin structure, forming a shallow trench isolation region 105. The upper surface of the shallow trench isolation region 105 is generally flush with the interface between the stacked layer structure in the fins and the substrate monocrystalline silicon, but may be higher or lower than this interface level. The shallow trench isolation region 105 can be formed of a suitable dielectric material, such as silicon dioxide (SiO2) or silicon nitride (SiN). x )wait.

[0034] refer to Figure 6 This is a schematic diagram of the overall structure of a stacked nanosheet GAA-FET device. Two directions are defined, and two dashed lines, XX and YY, are set. The XX line is along the fin direction and is the center line of the fin, while the YY line is perpendicular to the fin direction and is the center line of the fin. The following figures are cross-sectional schematic diagrams with the XX and YY lines.

[0035] Next, a false fence 106 and a third sidewall 107 can be formed on the fin, such as Figure 7 As shown, Figure 6In the cross-sectional view along the YY direction, a false grid 106 is formed on the exposed fin in a direction perpendicular to the fin line (i.e., the YY direction). The false grid spans the stacked layers at the top of the fin. Figure 8 for Figure 6 Cross-sectional view in the XX direction. The material used for the dummy gate 106 can be polycrystalline silicon (p-si) or amorphous silicon (a-si).

[0036] Silicon nitride (SiN) is disposed on both sides of the dummy gate along the fin direction (i.e., the XX direction). x The thickness of the third side wall 107 on both sides can be the same, such as... Figure 9 As shown.

[0037] S103, etching a portion of the two ends of the first semiconductor layer from the outside in to form a second sidewall at both ends of the first semiconductor layer.

[0038] In this embodiment, the dummy gate 106 and the third sidewall 107 can be used as masks to perform source / drain etching on the fins using an etching process, as shown in the reference. Figure 10 As shown, only the stacked layers below the dummy grid 106 and the third sidewall 107 are retained.

[0039] Next, partial areas at both ends of the first semiconductor layer 101 are etched from the outside in, forming second sidewalls 108 at both ends of the first semiconductor layer 101. Specifically, as shown... Figure 11 As shown, pull-back etching is performed to etch away a portion of the first semiconductor layer 101 from the outside to the center, so that a second sidewall 108 can be formed in the area of ​​the etched first semiconductor layer 101.

[0040] Then, silicon nitride (SiN) is deposited on the outer periphery of the fins. x Second side wall 108, reference Figure 12 As shown, the second sidewall 108 is then etched until it is flush with the second semiconductor layer 102 in the vertical direction, that is, the second sidewall 108 is formed at both ends of the first semiconductor layer 101, as shown in the reference. Figure 13 As shown.

[0041] Epitaxial growth forms source / drain regions and performs source / drain doping, such as... Figure 14 As shown, for PMOS, the source / drain region material is boron (B)-doped SiGe (SiGe:B), and for NMOS, the source / drain region material is phosphorus (P)-doped silicon (Si) (Si:P), ultimately forming the source / drain region 110. An isolation layer 111 is deposited on the surface of the dummy gate 106 and the source / drain region 110 to prevent short circuits between the dummy gate layer 106 and the source / drain region 110 in subsequent steps, and the isolation layer 111 is chemically mechanically polished to planarize it.

[0042] Then, as Figure 15 As shown, the dummy gate 106 formed by polysilicon (p-si) or amorphous silicon (a-si) is etched or etched away by selective etching or etching processes, that is, the dummy gate 106 is removed.

[0043] S104, remove the first semiconductor layer to release the nanosheet channel, and use the second semiconductor layer as the channel.

[0044] In this embodiment, the first semiconductor layer 101 can be removed to release the nanosheet channel, and the second semiconductor layer 102 can be used as the channel, as referenced. Figure 16 As shown. Specifically, the sacrificial layer, i.e., the first semiconductor layer 101, in the stacked layers is selectively etched to release the second semiconductor layer 102, i.e., to release the nanosheet channel. The width of the nanosheet 202 can range from 1 to 100 nm, the thickness can range from 1 to 30 nm, and the spacing between each nanosheet 202 can range from 3 to 30 nm.

[0045] S105, the overlapping area of ​​the second sidewall and the channel is etched laterally to form a gap.

[0046] In this embodiment, the overlapping area of ​​the second sidewall 108 and the nanosheet (NS) channel 102 can be laterally trimmed to form a gap 115, as shown in the reference. Figure 17 As shown, a high-k dielectric layer is filled between the second sidewall 108 and the second semiconductor layer 102 to suppress the conduction of electric field to the overlapping region of the source / drain region and the channel, thereby suppressing leakage current in the off-state of the device.

[0047] S106 forms an interface oxide layer and a first high-k dielectric layer in the voids.

[0048] In this embodiment, an interface oxide layer (IL) and a first high-k dielectric layer (HK1) can be deposited in the voids. The first high-k dielectric layer is an Hf-based high-k material, and the material of the first high-k dielectric layer includes at least one of the following materials: HfO2, HfSiO x HfON, HfSiON, HfAlO x HfLaO x .

[0049] In one possible implementation, when forming the interface oxide layer and the first high-k dielectric layer in the void, it can specifically involve forming an interface oxide layer and a first high-k dielectric layer surrounding the channel, removing the first high-k dielectric layer between the channels, and retaining the interface oxide layer and the first high-k dielectric layer in the void between the channel and the second sidewall.

[0050] Specifically, refer to Figure 18As shown in the figure, for simplicity, a single film layer 112 represents the interface oxide layer and the first high-k dielectric layer. During the deposition process, the interface oxide layer and the first high-k dielectric layer 112 surrounding the channels can be formed. However, the interface oxide layer and the first high-k dielectric layer between adjacent channels are undesirable. Therefore, the first high-k dielectric layer located between the channels can be selectively etched away to avoid affecting device performance, while retaining the interface oxide layer and the first high-k dielectric layer in the gaps. (Refer to...) Figure 19 This is a diagram of the device structure after the first high-k dielectric layer between the channels has been removed.

[0051] S107, a second high-k dielectric layer is formed between the first high-k dielectric layer and the second sidewall, and around the trench, and a metal grid surrounding the trench is formed.

[0052] In this embodiment, a second high-k dielectric layer (HK2) 113 can be formed between the first high-k dielectric layer and the second sidewall, and around the channel, and a metal grid 114 surrounding the channel can be formed, thereby forming a high-k metal grid structure, as shown in the reference. Figure 20 As shown, the electric field generated by the metal gate can be conducted to the overlap region between the source / drain region and the channel, leading to band-to-band tunneling leakage. By forming an interface oxide layer, a first high-k dielectric layer, and a second high-k dielectric layer between the NS channel and the second sidewall, the conduction of the electric field to the overlap region between the source / drain region and the channel can be suppressed, the electric field intensity in the overlap region can be weakened, and the electric field distribution in the overlap region can be changed. This suppresses the generation of band-to-band tunneling leakage in the overlap region between the source / drain region and the channel, avoids device off-state leakage, and improves device performance.

[0053] In this embodiment, the overlapping area of ​​the third sidewall 107 and the channel can be etched laterally to form a void 115. An interface oxide layer, a first high-k dielectric layer 112, and a second high-k dielectric layer 113 are deposited in the void. The second high-k dielectric layer 113 is also formed around the channel, thereby further suppressing the conduction of the electric field to the overlapping area of ​​the source / drain region and the channel, weakening the electric field intensity in the overlapping area of ​​the source / drain region and the channel, suppressing the generation of band tunneling leakage in the overlapping area of ​​the source / drain region and the channel, and avoiding device off-state leakage.

[0054] It is understandable that HK2 / HK1 double-layer structures can be formed simultaneously in part of the NMOS and PMOS regions of the GAA-FET device to suppress band-to-band tunneling leakage in the source-drain and channel overlap regions. Alternatively, HK2 / HK1 double-layer structures can be formed only in the NMOS or PMOS regions, or in all NMOS and PMOS regions of the GAA-FET device.

[0055] The material of the second high-k dielectric layer includes at least one of the following materials: AlO x MnO xZrO x TiO x MoO x LaO x MgO x ScO x 、YO x NdO x The sum of the thicknesses of the first high-k dielectric layer and the second high-k dielectric layer can be greater than or equal to 0.1 nm and less than or equal to 5 nm.

[0056] The metal gate 114 may include a multi-layer structure such as a capping layer TiN, a barrier layer TaN, a work function layer WFL, and a fill layer W. Figure 20 The specific film structure is not shown. Specifically, a TiN capping layer and a TaN barrier layer can be deposited to form a TiN / TaN barrier-I. Then, PMOS WFLs are deposited in both the NMOS and PMOS regions. The PMOS WFLs can be made of TiN or TiSiN. Next, the PMOS WFLs are selectively etched away in all NMOS regions, leaving the PMOS WFLs in the PMOS regions. Then, the barrier-I layer can be selectively etched in certain NMOS regions to control the residual TiN thickness. Similarly, the PMOS WFLs are selectively etched in certain PMOS regions to control the residual PMOS WFL thickness. Finally, NMOS WFLs are deposited in both the NMOS and PMOS regions. The NMOS WFLs can be made of TiAlC. x Finally, TiN / TaN barrier-II and conductive filler layer W are deposited to form a high-k metal gate structure, and CMP planarization is performed.

[0057] Next, ILD dielectric deposition is performed on top, referencing... Figure 21 A dielectric CMP layer 116 is formed, and contact hole photolithography and etching are performed on the dielectric CMP layer 116 to deposit hole silicide 117, and contact electrodes are led out. Subsequently, multilayer back-end interconnection and passivation protection processes are completed to complete the fabrication of GAA-FET device.

[0058] This application provides a method for fabricating a stacked nanosheet GAA-FET device. The method involves forming a stacked layer of alternating first and second semiconductor layers on a substrate; etching the stacked layer to form fins, and forming a dummy gate and a first sidewall on the fins; etching a portion of the two ends of the first semiconductor layer from the outside in, forming second sidewalls at both ends of the first semiconductor layer; removing the first semiconductor layer to release a nanosheet channel, with the second semiconductor layer serving as the channel; laterally etching the overlapping area of ​​the second sidewall and the channel to form a gap; forming an interface oxide layer and a first high-k dielectric layer in the gap; forming a second high-k dielectric layer between the first high-k dielectric layer and the second sidewall, and surrounding the channel, and forming a metal gate surrounding the channel. In contrast to existing technologies where the electric field generated by the metal gate is conducted to the overlapping region of the source / drain region and the channel, leading to band-to-band tunneling leakage, in this embodiment, by forming an interface oxide layer, a first high-k dielectric layer, and a second high-k dielectric layer between the channel and the second sidewall, the conduction of the electric field to the overlapping region of the source / drain region and the channel can be suppressed, the electric field intensity in the overlapping region of the source / drain region and the channel can be weakened, and the electric field distribution in the overlapping region can be changed. This suppresses the generation of band-to-band tunneling leakage in the overlapping region of the source / drain region and the channel, avoids device off-state leakage, and improves device performance.

[0059] Based on the above method for fabricating stacked nanosheet GAA-FET devices, this application also provides a stacked nanosheet GAA-FET device, see reference. Figure 21 As shown, it includes:

[0060] A substrate 100, and a fin located on one side of the substrate; the fin includes a plurality of second semiconductor layers 102, the second semiconductor layers serving as channels;

[0061] A high-k metal gate structure includes an interface oxide layer, a first high-k dielectric layer 112, a second high-k dielectric layer 113, and a metal gate 114; the metal gate 114 surrounds the second semiconductor layer 102, and the metal gate 114 has second sidewalls 108 at both ends; the interface oxide layer and the first high-k dielectric layer 112 are located between the channel and the second sidewall; the interface oxide layer and the second high-k dielectric layer 113 are located between the channel and the second sidewall, and around the channel.

[0062] Specifically, the material of the second high-k dielectric layer includes at least one of the following materials: AlO x MnO x ZrO x TiO x MoO x LaO x MgO x ScO x 、YO x NdO x .

[0063] Specifically, the first high-k dielectric layer is an Hf-based high-k material, and the material of the first high-k dielectric layer includes at least one of the following materials: HfO2, HfSiO x HfON, HfSiON, HfAlO x HfLaO x .

[0064] Specifically, the feature is that the sum of the thicknesses of the first high-k dielectric layer and the second high-k dielectric layer is greater than or equal to 0.1 nm and less than or equal to 5 nm.

[0065] In this embodiment, by forming an interface oxide layer, a first high-k dielectric layer, and a second high-k dielectric layer between the channel and the second sidewall, the conduction of the electric field to the overlapping region of the source / drain region and the channel can be suppressed, the electric field intensity of the overlapping region of the source / drain region and the channel can be weakened, and the electric field distribution of the overlapping region can be changed, thereby suppressing the generation of band-to-band tunneling leakage in the overlapping region of the source / drain region and the channel, avoiding device off-state leakage, and improving device performance.

[0066] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0067] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for fabricating a stacked nanosheet GAA-FET device, characterized in that, include: A stacked layer of alternating first and second semiconductor layers is formed on a substrate; The stacked layers are etched to form fins, and a dummy gate and a first sidewall are formed on the fins; Etch a portion of the two ends of the first semiconductor layer from the outside in to form a second sidewall at both ends of the first semiconductor layer; Remove the first semiconductor layer to release the nanosheet channel, and use the second semiconductor layer as the channel; A portion of the second sidewall near the channel is etched laterally to create a gap between the second sidewall and the channel; An interface oxide layer and a first high-k dielectric layer are formed in the voids; A second high-k dielectric layer is formed between the first high-k dielectric layer and the second sidewall, and around the channel, and a metal grid is formed surrounding the channel.

2. The manufacturing method according to claim 1, characterized in that, The formation of the interface oxide layer and the first high-k dielectric layer in the voids includes: An interface oxide layer and a first high-k dielectric layer are formed surrounding the channel; Remove the first high-k dielectric layer between the channels, and retain the interface oxide layer and the first high-k dielectric layer in the gap between the channel and the second sidewall.

3. The manufacturing method according to claim 1, characterized in that, The material of the second high-k dielectric layer includes at least one of the following materials: AlO x MnO x ZrO x TiO x MoO x LaO x MgO x ScO x 、YO x NdO x .

4. The manufacturing method according to claim 1, characterized in that, The first high-k dielectric layer is an Hf-based high-k material, and the material of the first high-k dielectric layer includes at least one of the following materials: HfO2, HfSiO x HfON, HfSiON, HfAlO x HfLaO x .

5. The manufacturing method according to any one of claims 1-4, characterized in that, The sum of the thicknesses of the first high-k dielectric layer and the second high-k dielectric layer is greater than or equal to 0.1 nm and less than or equal to 5 nm.

6. The manufacturing method according to any one of claims 1-4, characterized in that, The substrate is made of Si or SiGe.

7. A stacked nanosheet GAA-FET device, characterized in that, include: A substrate, and a fin located on one side of the substrate; the fin includes a plurality of second semiconductor layers, the second semiconductor layers serving as channels; A high-k metal gate structure includes an interface oxide layer, a first high-k dielectric layer, a second high-k dielectric layer, and a metal gate; the metal gate surrounds a middle portion of a second semiconductor layer, and the metal gate has second sidewalls at both ends, the second sidewalls overlapping the projection of the second semiconductor layer not surrounded by the metal gate in the vertical direction; the first high-k dielectric layer is located between the channel and the second sidewalls; the interface oxide layer and the second high-k dielectric layer are located between the channel and the second sidewalls, and around the periphery of the channel.

8. The stacked nanosheet GAA-FET device according to claim 7, characterized in that, The material of the second high-k dielectric layer includes at least one of the following materials: AlO x MnO x ZrO x TiO x MoO x LaO x MgO x ScO x 、YO x NdO x .

9. The stacked nanosheet GAA-FET device according to claim 7, characterized in that, The first high-k dielectric layer is an Hf-based high-k material, and the material of the first high-k dielectric layer includes at least one of the following materials: HfO2, HfSiO x HfON, HfSiON, HfAlO x HfLaO x .

10. The stacked nanosheet GAA-FET device according to any one of claims 7-9, characterized in that, The sum of the thicknesses of the first high-k dielectric layer and the second high-k dielectric layer is greater than or equal to 0.1 nm and less than or equal to 5 nm.

Images