A high frequency clock duty cycle calibration circuit

Abstract

The application relates to a high-frequency clock duty cycle calibration circuit and belongs to the microelectronic technical field. The high-frequency clock duty cycle calibration circuit comprises a clock duty cycle detection circuit and a clock duty cycle adjustment circuit. The application adopts a clock duty cycle detection circuit and a transconductance operational amplifier to form a negative feedback compensation circuit technology, so that when the input clock duty cycle is less than 50%, the output clock high level time is less than the low level time, the voltage of adjustment capacitors C1-C2 is adjusted, the change voltage of the capacitors is converted into current, the drain current of PMOS tubes M18 and NMOS tubes M25 is adjusted, and then the clock duty cycle is calibrated; the application adopts a multi-branch duty cycle adjustment circuit and a common mode feedback composed of PMOS tubes M7-M8, so that when the input clock duty cycle is less than 50%, switches S1-S3 are turned off one by one and switches S4-S6 are turned on one by one, so that the calibration value of the clock signal reaches the offset of the input clock signal, the output clock with a duty cycle of 50% is obtained, and the high-frequency clock duty cycle calibration circuit is realized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronics technology, and particularly relates to a high-frequency clock duty cycle calibration circuit. BACKGROUND

[0002] High-speed analog-to-digital converters (ADCs), high-speed serial link transceivers, clock and data recovery (CDR) circuits, etc. require accurate 50% duty cycle clocks, and as the clock speeds of communication systems and their application systems increase, clock signals are affected by circuit noise and non-ideal factors on transmission paths, resulting in clock duty cycles that do not match, which seriously affects the performance of the system, and thus the performance requirements of clock duty cycle calibration circuits are also increasing.

[0003] Figure 1 A traditional clock duty cycle calibration circuit structure uses the pull-up current of PMOS transistor M1 and PMOS transistor M2 to control the delay of the rising edge and the delay of the falling edge of the signal at the drain of NMOS transistor M4, thereby calibrating the input clock signal duty cycle. At the same time, the inverter composed of PMOS transistor M5 and NMOS transistor M6 and the inverter composed of PMOS transistor M7 and NMOS transistor M8 shape the signal and have certain driving ability. By optimizing the channel width-length ratio of PMOS transistor M1 and PMOS transistor M2, calibration can be performed within a certain input clock duty cycle range, but the clock falling edge is determined by the input pair and does not change much, and the use of the technique of optimizing the channel width-length ratio of PMOS transistor M1 and PMOS transistor M2 limits the clock signal frequency, so the traditional clock duty cycle calibration circuit has the problems of narrow calibration range and low precision, which greatly limits the application of the traditional clock duty cycle calibration circuit in high-precision systems. SUMMARY

[0004] The present application aims to solve the above problems of the prior art. A high-frequency clock duty cycle calibration circuit is proposed. The technical solution of the present application is as follows:

[0005] The application discloses a high-frequency clock duty cycle calibration circuit, which comprises a clock duty cycle detection circuit and a clock duty cycle adjustment circuit, wherein a signal output end of the clock duty cycle detection circuit is connected with a signal input end of the clock duty cycle adjustment circuit, a signal output end of the clock duty cycle adjustment circuit is connected with a signal input end of the clock duty cycle detection circuit, the clock duty cycle adjustment circuit generates an output clock signal, and the clock duty cycle detection circuit calibrates the output clock signal of the clock duty cycle adjustment circuit; the output clock signal of the clock duty cycle adjustment circuit provides a control signal for the gate of a PMOS transistor M10 and the gate of a PMOS transistor M11 in the clock duty cycle detection circuit, so that the capacitor C1 and the capacitor C2 in the clock duty cycle detection circuit obtain corresponding voltages and provide a control signal for the clock duty cycle adjustment circuit, thereby controlling the delay of the rising edge and the delay of the falling edge of the output clock signal, and finally obtaining the output clock signal.

[0006] Further, the clock duty cycle detection circuit comprises: a current source Ibias, an NMOS tube M0, a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, an NMOS tube M5, an NMOS tube M6, a PMOS tube M7, a PMOS tube M8, a PMOS tube M9, a PMOS tube M10, a PMOS tube M11, an NMOS tube M12, an NMOS tube M13, a capacitor C1, a capacitor C2, and a single-to-complementary signal circuit STC, wherein one end of the current source Ibias is connected with the source of the PMOS tube M1, the source of the PMOS tube M2, the source of the PMOS tube M7, the source of the PMOS tube M8, and an external power supply VDD respectively, the other end of the current source Ibias is connected with the drain of the NMOS tube M0, the gate of the NMOS tube M0, and the gate of the NMOS tube M5 respectively, the source of the NMOS tube M0 is connected with the source of the NMOS tube M5, the source of the NMOS tube M6, one end of the capacitor C1, the source of the NMOS tube M12, the source of the NMOS tube M13, one end of the capacitor C2, and an external ground GND respectively, the gate of the PMOS tube M1 is connected with the gate of the PMOS tube M2 and an external bias VB respectively, the drain of the PMOS tube M1 is connected with the source of the PMOS tube M3, the gate of the PMOS tube M3 is connected with the drain of the PMOS tube M3, the gate of the PMOS tube M4, and the drain of the NMOS tube M5 respectively, the drain of the PMOS tube M2 is connected with the source of the PMOS tube M4, the drain of the PMOS tube M4 is connected with the drain of the NMOS tube M6, the gate of the NMOS tube M6, the gate of the PMOS tube M9, the gate of the NMOS tube M12, and the gate of the NMOS tube M13 respectively, the other end of the capacitor C1 is connected with the gate of the PMOS tube M7, the drain of the PMOS tube M10, the drain of the NMOS tube M12, an input end H2 of a logic circuit logic, and an inverting input end of a transconductance operational amplifier Gm respectively, the other end of the capacitor C2 is connected with the gate of the PMOS tube M8, the drain of the PMOS tube M11, the drain of the NMOS tube M13, an input end H1 of the logic circuit logic, and a non-inverting input end of the transconductance operational amplifier Gm respectively, the drain of the PMOS tube M7 is connected with the drain of the PMOS tube M8 and the source of the PMOS tube M9 respectively, the drain of the PMOS tube M9 is connected with the source of the PMOS tube M10 and the source of the PMOS tube M11 respectively, the gate of the PMOS tube M10 is connected with an output end CLK1n of the single-to-complementary signal circuit STC, and the gate of the PMOS tube M11 is connected with an output end CLK1 of the single-to-complementary signal circuit STC.

[0007] Further, in the clock duty cycle detection circuit, the channel width-length ratio of the NMOS transistor M12 is a times that of the NMOS transistor M6, and the channel width-length ratio of the NMOS transistor M13 is a times that of the NMOS transistor M6, so that the ability of extracting current from the capacitors C1 and C2 is the same; the gate of the PMOS transistor M10 and the gate of the PMOS transistor M11 are controlled by the output signal end CLK1n and the output signal end CLK1 of the single-turn complementary signal circuit STC, respectively, thereby controlling the charging and discharging time of the capacitors C1 and C2; the gate of the PMOS transistor M7 and the gate of the PMOS transistor M8 are connected to the drain of the PMOS transistor M10 and the drain of the PMOS transistor M11, respectively, and form a common-mode feedback structure, which effectively suppresses the influence of the voltages of the capacitors C1 and C2 on the charging current.

[0008] Further, in the clock duty cycle detection circuit, the signals of the output signal end CLK1 and the output signal end CLK1n of the single-turn complementary signal circuit STC are complementary signals; when the output signal end CLK1 is at a low level, the PMOS transistor M11 is turned on, the PMOS transistor M10 is turned off, the capacitor C2 is charged, the capacitor C1 is discharged, the voltage V cp of the capacitor C2 rises, the drain current of the PMOS transistor M8 decreases, and the voltage V cn of the capacitor C1 decreases, thereby making the drain current of the PMOS transistor M7 increase and the drain current of the PMOS transistor M9 constant; when the output signal end CLK1 is at a high level, the PMOS transistor M11 is turned off, the PMOS transistor M10 is turned on, the capacitor C2 is discharged, the capacitor C1 is charged, the voltage V cn of the capacitor C1 rises, the drain current of the PMOS transistor M7 decreases, and the voltage V cp of the capacitor C2 decreases, thereby making the drain current of the PMOS transistor M8 increase and the drain current of the PMOS transistor M9 constant; the change voltage ΔV cp of the capacitor C2 has where I n is the discharging current provided by the NMOS transistor M13, T is the clock period, N is the duty cycle of the input clock, and C2 is the capacitance of the capacitor C2; when the duty cycle N is less than 50%, the capacitor C2 is charged, and the voltage V cp of the capacitor C2 is higher than the common-mode level; when the duty cycle N is greater than 50%, the voltage V cpBelow the common mode level. The change voltage of the capacitor C1 is similar to that of the capacitor C2; thus, the duty cycle state of the clock can be judged by the relationship between the change voltage of the capacitor C1, the capacitor C2 and their corresponding initial voltage, and the working state of the switches S1-S6 is controlled by the logic circuit logic in the clock duty cycle adjustment circuit, and the voltage of the capacitor C1 and the voltage of the capacitor C2 are converted into current signals by the transconductance operational amplifier Gm in the clock duty cycle adjustment circuit, thereby controlling the current of the clock duty cycle adjustment circuit.

[0009] Furthermore, the clock duty cycle adjustment circuit includes: a logic circuit (logic), a transconductance operational amplifier (Gm), PMOS transistors M14, M15, M16, M17, M18, and M19, NMOS transistors M20, M21, M22, M23, M24, and M25, switches S1, S2, S3, S4, S5, and S6, an inverter (INV), and a clock buffer (buf). The output terminal L1 of the logic circuit is connected to the control terminal of switch S1, and the output terminal L2 of the logic circuit is connected to the control terminal of switch S2. The logic circuit's output terminal L3 is connected to the control terminal of switch S3; the logic circuit's output terminal L4 is connected to the control terminal of switch S4; the logic circuit's output terminal L5 is connected to the control terminal of switch S5; the logic circuit's output terminal L6 is connected to the control terminal of switch S6; the source of PMOS transistor M14 is connected to one end of switch S3, one end of switch S2, one end of switch S1, the source of PMOS transistor M18, and the external power supply VDD; the gate of PMOS transistor M14 is connected to the drain of PMOS transistor M14, the inverting output terminal ICN of transconductance operational amplifier Gm, the gate of PMOS transistor M15, the gate of PMOS transistor M16, and the gate of PMOS transistor M17. The gate of switch S7 is connected to the gate of PMOS transistor M18. The other end of switch S3 is connected to the source of PMOS transistor M15. The other end of switch S2 is connected to the source of PMOS transistor M16. The other end of switch S1 is connected to the source of PMOS transistor M17. The drain of PMOS transistor M15 is connected to the drains of PMOS transistors M16, M17, M18, and M19. The gate of NMOS transistor M21 is connected to the drain of NMOS transistor M21, the non-inverting output terminal ICP of transconductance operational amplifier Gm, the gate of NMOS transistors M22, M23, M24, and M25. The source of NMOS transistor M21 is connected to one end of switch S6, one end of switch S5, one end of switch S4, the source of NMOS transistor M25, one end of capacitor C3, and external ground GND. The drain of NMOS transistor M22 is connected to the drains of NMOS transistors M23, M24, and M25, and the source of NMOS transistor M20. The source of NMOS transistor M22 is connected to the other end of switch S6, the source of NMOS transistor M23 is connected to the other end of switch S5, and the source of NMOS transistor M24 is connected to the other end of switch S4. The gate of PMOS transistor M19 is connected to the gate of NMOS transistor M20 and the external input clock signal CLK_IN.The drain of the PMOS transistor M19 is connected with the drain of the NMOS transistor M20, the other end of the capacitor C3 and the input of the inverter INV respectively, the output of the inverter INV is connected with the input of the clock buffer buf, the output of the clock buffer buf is connected with the signal input of the single transition complementary signal circuit STC and the circuit output CLK_OUT respectively.

[0010] Further, in the clock duty cycle adjustment circuit, the current provided by the transconductance operational amplifier Gm provides bias voltage for the PMOS transistors M15, M16, M17 and M18 through the PMOS transistor M14 and controls the rising edge time of the clock signal, the current provided by the transconductance operational amplifier Gm provides bias voltage for the NMOS transistors M22, M23, M24 and M25 through the NMOS transistor M21 and controls the falling edge time of the clock signal; the switches S1-S6 control the working state of the respective branches, thereby controlling the charging and discharging time of the capacitor C3 and calibrating the duty cycle of the clock.

[0011] Further, in the clock duty cycle adjustment circuit, the PMOS transistors M17 and M18 have the same channel width-length ratio, the channel width-length ratio of the PMOS transistor M16 is β1 times of that of the PMOS transistor M18, the channel width-length ratio of the PMOS transistor M15 is β2 times of that of the PMOS transistor M18, the NMOS transistors M24 and M25 have the same channel width-length ratio, the channel width-length ratio of the NMOS transistor M23 is β1 times of that of the NMOS transistor M25, the channel width-length ratio of the NMOS transistor M22 is β2 times of that of the NMOS transistor M25, the drain current of the PMOS transistor M18 is I UP , the drain current of the NMOS transistor M25 is I DOWN , the switches S1-S3 make the drain current of the PMOS transistor M19 K p times of the drain current of the PMOS transistor M18, the switches S4-S6 make the drain current of the NMOS transistor M20 K n times of the drain current of the NMOS transistor M25, wherein K p is 1≤K p ≤2+β1+β2, K n is 1≤K p ≤2+β1+β2, the flip voltage of the logic circuit composed of the PMOS transistor M19 and the NMOS transistor M20 is 0.5V DD , wherein V DD is the voltage of the external power supply VDD, and the calibration value of the clock signal is equal to the offset of the input clock signal Wherein m is the duty cycle of the output clock after clock correction and m=50%, C3 is the capacitance of capacitor C3; when the voltage of external power supply VDD and the capacitance of capacitor C3 are constant values, the offset of the input clock signal can be obtained according to the period T and the duty cycle N of the input clock, and the current I is controlled by the transconductance operational amplifier Gm of the clock duty cycle detection circuit and the clock duty cycle adjustment circuit DOWN and the current I UP and K is adjusted by the logic circuit logic of the clock duty cycle adjustment circuit n and K p so that the calibration value of the clock signal reaches the offset of the input clock signal, thereby the duty cycle of the input clock signal is effectively calibrated.

[0012] Further, in the clock duty cycle adjustment circuit, the switches S1-S3 control the drain current of PMOS tube M19, the switches S4-S6 control the drain current of NMOS tube M20, and the rising edge delay and the falling edge delay of the output clock are further controlled; the working state of the switches S1-S6 can effectively improve the detection range of the duty cycle calibration circuit of the input clock signal, so that the duty cycle offset of the input clock signal can be calibrated within the range of 20%-80%.

[0013] The advantages and beneficial effects of the present application are as follows:

[0014] The application provides a high-frequency clock duty cycle calibration circuit, which adopts a clock duty cycle detection circuit and a transconductance operational amplifier to form a negative feedback compensation circuit, so that when the input clock duty cycle is less than 50%, the high-level holding time of the output clock signal of the circuit output end CLK_OUT is less than the low-level holding time, meanwhile, the circuit output clock signal controls the gate of the PMOS transistor M10 and the gate of the PMOS transistor M11 through a single-to-complementary signal circuit, so that the on time of the PMOS transistor M11 is greater than the off time, and the on time of the PMOS transistor M10 is less than the off time, the voltage of the capacitor C2 is increased and the voltage of the capacitor C1 is decreased, the transconductance operational amplifier converts the changed voltage of the capacitor C1 and the capacitor C2 into current, and the drain current of the PMOS transistor M14 is reduced and the drain current of the NMOS transistor M21 is increased, so that the drain current of the PMOS transistor M18 is reduced and the drain current of the NMOS transistor M25 is increased, the rising time of the input signal of the inverter INV is increased and the falling time is reduced, so that the duty cycle of the clock signal is calibrated; meanwhile, the technology of the multi-branch duty cycle adjustment circuit and the technology of the common-mode feedback structure formed by the PMOS transistor M7 and the PMOS transistor M8 are adopted, so that when the input clock duty cycle is less than 50%, the voltage of the capacitor C2 is increased, the changed voltage of the capacitor is compared with the initial voltage of the capacitor, and the switches S1-S3 are sequentially turned off and the switches S4-S6 are sequentially turned on through the logic circuit logic, and then the output clock signal with the duty cycle of 50% is obtained, so that the high-frequency clock duty cycle calibration circuit is realized. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is a traditional clock duty cycle calibration circuit schematic diagram;

[0016] Figure 2 It is a high-frequency clock duty cycle calibration circuit schematic diagram provided by the application;

[0017] Figure 3 It is a simulation diagram of the high-frequency clock duty cycle calibration circuit provided by the application when the input clock frequency is 2.5GHz;

[0018] Figure 4 It is a simulation diagram of the high-frequency clock duty cycle calibration circuit provided by the application when the input clock frequency is 3.6GHz. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the application will be described clearly and specifically below with reference to the drawings in the embodiments of the application. The described embodiments are only some of the embodiments of the application.

[0020] The technical solution of the application to solve the above technical problems is:

[0021] The clock duty cycle detection circuit and the transconductance operational amplifier in the embodiments of the present application are used to form a negative feedback compensation circuit, so that when the input clock duty cycle is less than 50%, the high level holding time of the output clock signal at the output end CLK_OUT of the circuit is less than the low level holding time, and the output clock signal of the circuit controls the gate of the PMOS transistor M10 and the gate of the PMOS transistor M11 through the single-to-complementary signal circuit, so that the on time of the PMOS transistor M11 is greater than the off time thereof, and the on time of the PMOS transistor M10 is less than the off time thereof, the voltage of the capacitor C2 is raised and the voltage of the capacitor C1 is lowered, the transconductance operational amplifier converts the changed voltages of the capacitor C1 and the capacitor C2 into currents, and the drain current of the PMOS transistor M14 is reduced and the drain current of the NMOS transistor M21 is increased, so that the drain current of the PMOS transistor M18 is reduced and the drain current of the NMOS transistor M25 is increased, the rising time of the input signal of the inverter INV is increased and the falling time thereof is reduced, so as to calibrate the duty cycle of the clock signal; meanwhile, the multi-branch duty cycle adjustment circuit and the common mode feedback structure formed by the PMOS transistor M7 and the PMOS transistor M8 are used, so that when the input clock duty cycle is less than 50%, the voltage of the capacitor C2 is raised, the relationship between the changed voltage and the initial voltage of the capacitor is compared, and the switches S1 to S3 are sequentially turned off and the switches S4 to S6 are sequentially turned on through the logic circuit logic, and then the output clock signal with a duty cycle of 50% is obtained, so as to realize a high frequency clock duty cycle calibration circuit.

[0022] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in combination with the drawings of the specification and specific embodiments.

[0023] Embodiments

[0024] A high frequency clock duty cycle calibration circuit, as shown in Figure 2 includes a clock duty cycle detection circuit 1 and a clock duty cycle adjustment circuit 2.

[0025] The signal output end of the clock duty cycle detection circuit 1 is connected to the signal input end of the clock duty cycle adjustment circuit 2, the signal output end of the clock duty cycle adjustment circuit 2 is connected to the signal input end of the clock duty cycle detection circuit 1, the clock duty cycle adjustment circuit 2 generates an output clock signal, and the clock duty cycle detection circuit 1 calibrates the output clock signal of the clock duty cycle adjustment circuit 2, and then obtains the output clock signal.

[0026] The output clock signal of the clock duty cycle adjustment circuit 2 provides a control signal for the gates of PMOS M10 and PMOS M11 in the clock duty cycle detection circuit 1, so that the capacitors C1 and C2 in the clock duty cycle detection circuit 1 obtain corresponding voltages and provide a control signal for the clock duty cycle adjustment circuit 2, and then the transconductance operational amplifier Gm of the clock duty cycle adjustment circuit 2 controls the corresponding circuit to generate a current I DOWN and the current I UP The logic circuit logic controls the switches S1-S6 to adjust the current flowing through PMOS M19 and NMOS M20, and then controls the rising edge and falling edge delay of the output clock signal, so as to obtain the output clock signal.

[0027] As a preferred technical solution, as Figure 2As shown, the clock duty cycle detection circuit 1 comprises: a current source Ibias, an NMOS tube M0, a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, an NMOS tube M5, an NMOS tube M6, a PMOS tube M7, a PMOS tube M8, a PMOS tube M9, a PMOS tube M10, a PMOS tube M11, an NMOS tube M12, an NMOS tube M13, a capacitor C1, a capacitor C2, and a single-to-complementary signal circuit STC, wherein one end of the current source Ibias is connected with the source of the PMOS tube M1, the source of the PMOS tube M2, the source of the PMOS tube M7, the source of the PMOS tube M8, and an external power supply VDD respectively, the other end of the current source Ibias is connected with the drain of the NMOS tube M0, the gate of the NMOS tube M0, and the gate of the NMOS tube M5 respectively, the source of the NMOS tube M0 is connected with the source of the NMOS tube M5, the source of the NMOS tube M6, one end of the capacitor C1, the source of the NMOS tube M12, the source of the NMOS tube M13, one end of the capacitor C2, and an external ground GND respectively, the gate of the PMOS tube M1 is connected with the gate of the PMOS tube M2 and an external bias VB respectively, the drain of the PMOS tube M1 is connected with the source of the PMOS tube M3, the gate of the PMOS tube M3 is connected with the drain of the PMOS tube M3, the gate of the PMOS tube M4, and the drain of the NMOS tube M5 respectively, the drain of the PMOS tube M2 is connected with the source of the PMOS tube M4, the drain of the PMOS tube M4 is connected with the drain of the NMOS tube M6, the gate of the NMOS tube M6, the gate of the PMOS tube M9, the gate of the NMOS tube M12, and the gate of the NMOS tube M13 respectively, the other end of the capacitor C1 is connected with the gate of the PMOS tube M7, the drain of the PMOS tube M10, the drain of the NMOS tube M12, an input end H2 of a logic circuit logic, and an inverting input end of a transconductance operational amplifier Gm respectively, the other end of the capacitor C2 is connected with the gate of the PMOS tube M8, the drain of the PMOS tube M11, the drain of the NMOS tube M13, an input end H1 of the logic circuit logic, and a non-inverting input end of the transconductance operational amplifier Gm respectively, the drain of the PMOS tube M7 is connected with the drain of the PMOS tube M8 and the source of the PMOS tube M9 respectively, the drain of the PMOS tube M9 is connected with the source of the PMOS tube M10 and the source of the PMOS tube M11 respectively, the gate of the PMOS tube M10 is connected with an output end CLK1n of the single-to-complementary signal circuit STC, and the gate of the PMOS tube M11 is connected with an output end CLK1 of the single-to-complementary signal circuit STC.

[0028] The clock duty cycle adjustment circuit 2 comprises a logic circuit logic, a transconductance operational amplifier Gm, PMOS tubes M14, M15, M16, M17, M18, M19, NMOS tubes M20, M21, M22, M23, M24, M25, switches S1, S2, S3, S4, S5, S6, an inverter INV, and a clock buffer buf, wherein the output end L1 of the logic circuit logic is connected with the control end of the switch S1, the output end L2 of the logic circuit logic is connected with the control end of the switch S2, the output end L3 of the logic circuit logic is connected with the control end of the switch S3, the output end L4 of the logic circuit logic is connected with the control end of the switch S4, the output end L5 of the logic circuit logic is connected with the control end of the switch S5, the output end L6 of the logic circuit logic is connected with the control end of the switch S6, the source of the PMOS tube M14 is connected with one end of the switch S3, one end of the switch S2, one end of the switch S1, the source of the PMOS tube M18, and an external power supply VDD respectively, the gate of the PMOS tube M14 is connected with the drain of the PMOS tube M14, the inverting output end ICN of the transconductance operational amplifier Gm, the gate of the PMOS tube M15, the gate of the PMOS tube M16, the gate of the PMOS tube M17, and the gate of the PMOS tube M18 respectively, the other end of the switch S3 is connected with the source of the PMOS tube M15, the other end of the switch S2 is connected with the source of the PMOS tube M16, the other end of the switch S1 is connected with the source of the PMOS tube M17, the drain of the PMOS tube M15 is connected with the drain of the PMOS tube M16, the drain of the PMOS tube M17, the drain of the PMOS tube M18, and the source of the PMOS tube M19 respectively, the gate of the NMOS tube M21 is connected with the drain of the NMOS tube M21, the non-inverting output end ICP of the transconductance operational amplifier Gm, the gate of the NMOS tube M22, the gate of the NMOS tube M23, the gate of the NMOS tube M24, and the gate of the NMOS tube M25 respectively, the source of the NMOS tube M21 is connected with one end of the switch S6, one end of the switch S5, one end of the switch S4, the source of the NMOS tube M25, one end of the capacitor C3, and an external ground GND respectively, the drain of the NMOS tube M22 is connected with the drain of the NMOS tube M23, the drain of the NMOS tube M24, the drain of the NMOS tube M25, and the source of the NMOS tube M20 respectively, the source of the NMOS tube M22 is connected with the other end of the switch S6, the source of the NMOS tube M23 is connected with the other end of the switch S5, the source of the NMOS tube M24 is connected with the other end of the switch S4, the gate of the PMOS tube M19 is connected with the gate of the NMOS tube M20 and an external input clock signal CLK_IN respectively,The drain of the PMOS transistor M19 is connected to the drain of the NMOS transistor M20, the other end of the capacitor C3 and the input of the inverter INV, respectively, and the output of the inverter INV is connected to the input of the clock buffer buf, and the output of the clock buffer buf is connected to the signal input of the single-turn complementary signal circuit STC and the circuit output CLK_OUT, respectively.

[0029] In the clock duty cycle detection circuit 1, the NMOS transistor M0 and the NMOS transistor M5 constitute a current mirror, the PMOS transistor M1 and the PMOS transistor M2 have the same channel width-length ratio, the PMOS transistor M3 and the PMOS transistor M4 have the same channel width-length ratio, the channel width-length ratio of the NMOS transistor M12 is α times of the channel width-length ratio of the NMOS transistor M6, and the channel width-length ratio of the NMOS transistor M13 is α times of the channel width-length ratio of the NMOS transistor M6, so that the drain current I 12 of the NMOS transistor M13 is equal to the drain current I 13 of the NMOS transistor M12. 12 = I 13 = I n , wherein I n is the discharge current, so that the ability of extracting current from the capacitor C1 and the capacitor C2 is the same; the gate of the PMOS transistor M10 and the gate of the PMOS transistor M11 are controlled by the output signal end CLK1n and the output signal end CLK1 of the single-turn complementary signal circuit STC, respectively, the output signal of the signal end CLK1n and the output signal of the signal end CLK1 are a pair of complementary clock signals, and then the charging and discharging time of the capacitor C1 and the capacitor C2 is controlled; the gate of the PMOS transistor M7 and the gate of the PMOS transistor M8 are connected to the drain of the PMOS transistor M10 and the drain of the PMOS transistor M11, respectively, and constitute a common-mode feedback structure, so as to suppress the influence of the voltage of the capacitor C1 and the capacitor C2 on the charging current I p , wherein the charging current I p is the drain current of the PMOS transistor M9. When the output signal end CLK1 of the single-turn complementary signal circuit STC is at a low level, the PMOS transistor M11 is turned on, and at the same time, when the output signal end CLK1n of the single-turn complementary signal circuit STC is at a high level, the PMOS transistor M10 is turned off, at this time, the capacitor C2 is charged, the capacitor C1 is discharged, the voltage V cp on the capacitor C2 rises, the drain current of the PMOS transistor M8 decreases, the voltage V cn on the capacitor C1 decreases, the drain current of the PMOS transistor M7 increases, and then the drain current of the PMOS transistor M9 is constant; when the output signal end CLK1 of the single-turn complementary signal circuit STC is at a high level, the PMOS transistor M11 is turned off, and at the same time, when the output signal end CLK1n of the single-turn complementary signal circuit STC is at a low level, the PMOS transistor M10 is turned on, at this time, the capacitor C2 is discharged, the capacitor C1 is charged, the voltage Vcn The rising makes the drain current of PMOS M7 drop, the voltage V cp of capacitor C2 drop, which makes the drain current of PMOS M8 rise, and in turn makes the drain current of PMOS M9 constant. The relationship between the changed voltage AV cp of capacitor C2 and time t is

[0030]

[0031] where I n is the discharge current provided for NMOS M13, I p is the charge current provided for PMOS M9 and I p = 2I n , t1 is the duration of high level in one clock cycle, T is the clock cycle, N is the duty cycle of input clock, and C2 is the capacitance of capacitor C2. When the duty cycle N < 50%, capacitor C2 is charged, and the voltage V cp of capacitor C2 is higher than the common mode level; when the duty cycle N > 50%, the voltage V cp of capacitor C2 is lower than the common mode level. The changed voltage AV cn of capacitor C1 is similar to the changed voltage AV cp of capacitor C2. Thus, the duty cycle state of clock can be judged by the relationship between the changed voltage of capacitor and the initial voltage of capacitor, and the state of switches S1, S2, S3, S4, S5 and S6 is controlled by logic logic in the clock duty cycle adjusting circuit 2. At the same time, the voltage V cp and the voltage V cn are converted into current signals by the transconductance operational amplifier Gm in the clock duty cycle adjusting circuit 2, and in turn the current of the clock duty cycle adjusting circuit 2 is controlled.

[0032] In the clock duty cycle adjustment circuit 2, the transconductance operational amplifier Gm adopts a conventional structure. The current provided by the transconductance operational amplifier Gm provides bias voltages to PMOS transistors M15, M16, M17, and M18 through PMOS transistor M14, thereby controlling the rise time of the clock signal. The feedback current provided by the transconductance operational amplifier Gm provides bias voltages to NMOS transistors M22, M23, M24, and M25 through NMOS transistor M21, thereby controlling the fall time of the clock signal. At the same time, in order to improve the range of clock duty cycle calibration, this invention adopts a multi-branch structure, and switches S1, S2, S3, S4, S5, and S6 control the working state of each branch respectively, thereby controlling the charging and discharging time of capacitor C3, and thus calibrating the clock duty cycle. PMOS transistors M17 and M18 have the same channel width-to-length ratio. The channel width-to-length ratio of PMOS transistor M16 is β1 times that of PMOS transistor M18, and the channel width-to-length ratio of PMOS transistor M15 is β2 times that of PMOS transistor M18. NMOS transistors M24 and M25 have the same channel width-to-length ratio. The channel width-to-length ratio of NMOS transistor M23 is β1 times that of NMOS transistor M25, and the channel width-to-length ratio of NMOS transistor M22 is β2 times that of NMOS transistor M25. The drain current of PMOS transistor M18 is I. UP By controlling switches S1, S2, and S3, the current flowing through PMOS transistor M19 is made to be K times the drain current of PMOS transistor M18. p Times, where K p The range of values ​​for is 1 ≤ K p For a logic circuit composed of PMOS transistor M19 and NMOS transistor M20 branches with a voltage ≤2+β1+β2, the switching voltage is 0.5V. DD V DD If the voltage is the external power supply VDD, then capacitor C3 is charged to the switching voltage of 0.5V. DD The relationship between the process and time t is as follows:

[0033]

[0034] In the formula, C3 is the capacitance of capacitor C3, and t2 is the voltage across capacitor C3 from V... DD Discharge to The time interval (i.e., t0 to t2) is when the voltage across capacitor C3 changes from V DD Discharge to The time is given by m, where m is the duty cycle of the output clock after clock correction and m = 50%. The drain current of NMOS transistor M25 is I. DOWN, the current flowing through the NMOS transistor M20 is K times of the drain current of the NMOS transistor M25 by controlling the switches S4, S5 and S6 n , wherein K n is in the range of 1≤K n ≤2+β1+β2, the capacitor C3 is discharged to the flip voltage 0.5V DD in the process, and the relationship with the time t is

[0035]

[0036] From equation (2) and equation (3), we have

[0037]

[0038] In equation (4), the factor is the offset of the input clock signal, and the factor is the calibration value of the clock signal. When the voltage of the external power supply VDD and the capacitance of the capacitor C3 are constant, the offset of the input clock signal can be obtained according to the period T and the duty cycle N of the input clock, and the current I DOWN and the current I UP are adjusted by the transconductance operational amplifier Gm of the clock duty cycle detection circuit 1 and the clock duty cycle adjustment circuit 2, and K n and K p are adjusted by the logic circuit logic of the clock duty cycle adjustment circuit 2, so that the factor (i.e. the calibration value of the clock signal) reaches the offset of the input clock signal, thereby effectively calibrating the duty cycle of the input clock signal. Meanwhile, the switches S1, S2 and S3 are used to control the current flowing through the PMOS transistor M19, and the switches S4, S5 and S6 are used to control the current flowing through the NMOS transistor M20, thereby controlling the delay of the rising edge and the delay of the falling edge of the clock; controlling the working state of the switches S1-S6 can improve the detection range of the duty cycle calibration circuit of the input clock signal, so that the offset of the duty cycle of the input clock signal can be calibrated within the range of 20%-80%, and the multi-branch structure formed by the switches S1-S6 can effectively improve the calibration accuracy.

[0039] Figure 3 , Figure 4 is a simulation curve of a high-frequency clock duty cycle calibration circuit of the present application, wherein the abscissa is the time t, and the ordinate is the clock signal waveform. Figure 3 The simulation results show that when the frequency of the input clock is 2.5GHz and the duty cycle is 80%, the circuit obtains an output clock signal with a duty cycle of 50.1%. Figure 4The simulation result shows that when the frequency of the input clock is 3.6GHz and the duty cycle is 20%, the circuit obtains an output clock signal with a duty cycle of 50%.

[0040] In the above embodiments of the present application, the high-frequency clock duty cycle calibration circuit includes a clock duty cycle detection circuit and a clock duty cycle adjustment circuit. The clock duty cycle detection circuit and the transconductance operational amplifier are used to form a negative feedback compensation circuit. When the input clock duty cycle is less than 50%, the high-level holding time of the output clock signal at the output end CLK_OUT of the circuit is less than the low-level holding time. Meanwhile, the circuit output clock signal controls the gate of the PMOS transistor M10 and the gate of the PMOS transistor M11 through the single-to-complementary signal circuit, so that the on-time of the PMOS transistor M11 is greater than its off-time, and the on-time of the PMOS transistor M10 is less than its off-time. As a result, the voltage of the capacitor C2 rises and the voltage of the capacitor C1 falls. The transconductance operational amplifier converts the changed voltages of the capacitor C1 and the capacitor C2 into currents, and reduces the drain current of the PMOS transistor M14 and increases the drain current of the NMOS transistor M21, so as to reduce the drain current of the PMOS transistor M18 and increase the drain current of the NMOS transistor M25. The rise time of the input signal of the inverter INV is increased and the fall time is decreased, so as to calibrate the duty cycle of the clock signal. Meanwhile, the multi-branch duty cycle adjustment circuit and the common-mode feedback structure composed of the PMOS transistor M7 and the PMOS transistor M8 are used. When the input clock duty cycle is less than 50%, the voltage of the capacitor C2 rises. The changed voltage and the initial voltage of the capacitor are compared, and the switches S1 to S3 are sequentially turned off and the switches S4 to S6 are sequentially turned on through the logic circuit logic, so as to obtain an output clock signal with a duty cycle of 50%, thereby realizing a high-frequency clock duty cycle calibration circuit.

[0041] It should be further understood that the terms "comprise", "comprising", or any other variant thereof are intended to cover non-exclusive inclusions, such that processes, methods, articles, or apparatuses that comprise a list of elements are not limited to those elements, but can also include other elements not expressly listed, or can also include elements inherent in such processes, methods, articles, or apparatuses. Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0042] The above embodiments should be understood as merely illustrative of the present application and not limiting the scope of protection of the present application. After reading the content of the present application, those skilled in the art can make various modifications or changes to the present application, and these equivalent changes and modifications also fall within the scope defined by the claims of the present application.

Claims

1. A high frequency clock duty cycle calibration circuit, characterized by, The application relates to a clock duty cycle detection circuit (1) and a clock duty cycle adjustment circuit (2), wherein the signal output end of the clock duty cycle detection circuit (1) is connected with the signal input end of the clock duty cycle adjustment circuit (2), the signal output end of the clock duty cycle adjustment circuit (2) is connected with the signal input end of the clock duty cycle detection circuit (1), the clock duty cycle adjustment circuit (2) generates an output clock signal, and the clock duty cycle detection circuit (1) calibrates the output clock signal of the clock duty cycle adjustment circuit (2); the output clock signal of the clock duty cycle adjustment circuit (2) provides a control signal for the gates of PMOS tubes M10 and M11 in the clock duty cycle detection circuit (1), so that the capacitors C1 and C2 in the clock duty cycle detection circuit (1) obtain corresponding voltages and provide control signals for the clock duty cycle adjustment circuit (2), thereby controlling the delay of the rising edge and the delay of the falling edge of the output clock signal, and thus the output clock signal is obtained. ​ The clock duty cycle detection circuit (1) comprises: a current source Ibias, NMOS tube M0, PMOS tube M1, PMOS tube M2, PMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, PMOS tube M7, PMOS tube M8, PMOS tube M9, PMOS tube M10, PMOS tube M11, NMOS tube M12, NMOS tube M13, capacitor C1, capacitor C2 and single conversion complementary signal circuit STC, wherein one end of the current source Ibias is connected with the source of the PMOS tube M1, the source of the PMOS tube M2, the source of the PMOS tube M7, the source of the PMOS tube M8 and the external power supply VDD respectively, the other end of the current source Ibias is connected with the drain of the NMOS tube M0, the gate of the NMOS tube M0 and the gate of the NMOS tube M5 respectively, the source of the NMOS tube M0 is connected with the source of the NMOS tube M5, the source of the NMOS tube M6, one end of the capacitor C1, the source of the NMOS tube M12, the source of the NMOS tube M13, one end of the capacitor C2 and the external ground GND respectively, the gate of the PMOS tube M1 is connected with the gate of the PMOS tube M2 and the external bias VB respectively, the drain of the PMOS tube M1 is connected with the source of the PMOS tube M3, the gate of the PMOS tube M3 is connected with the drain of the PMOS tube M3, the gate of the PMOS tube M4 and the drain of the NMOS tube M5 respectively, the drain of the PMOS tube M2 is connected with the source of the PMOS tube M4, the drain of the PMOS tube M4 is connected with the drain of the NMOS tube M6, the gate of the NMOS tube M6, the gate of the PMOS tube M9, the gate of the NMOS tube M12 and the gate of the NMOS tube M13 respectively, the other end of the capacitor C1 is connected with the gate of the PMOS tube M7, the drain of the PMOS tube M10, the drain of the NMOS tube M12, the input end H2 of the logic circuit logic and the inverting input end of the transconductance operational amplifier Gm respectively, the other end of the capacitor C2 is connected with the gate of the PMOS tube M8, the drain of the PMOS tube M11, the drain of the NMOS tube M13, the input end H1 of the logic circuit logic and the non-inverting input end of the transconductance operational amplifier Gm respectively, the drain of the PMOS tube M7 is connected with the drain of the PMOS tube M8 and the source of the PMOS tube M9 respectively, the drain of the PMOS tube M9 is connected with the source of the PMOS tube M10 and the source of the PMOS tube M11 respectively, the gate of the PMOS tube M10 is connected with the output end CLK1n of the single conversion complementary signal circuit STC, and the gate of the PMOS tube M11 is connected with the output end CLK1 of the single conversion complementary signal circuit STC.

2. The high frequency clock duty cycle calibration circuit of claim 1, wherein, The clock duty cycle detection circuit (1), the channel width-length ratio of NMOS tube M12 is α times of NMOS tube M6, and the channel width-length ratio of NMOS tube M13 is α times of NMOS tube M6, so that the ability of extracting current from capacitor C1 and capacitor C2 is the same; the gate of PMOS tube M10 and the gate of PMOS tube M11 are controlled by the output signal end CLK1n and the output signal end CLK1 of single conversion complementary signal circuit STC respectively, thereby controlling the charging and discharging time of capacitor C1 and capacitor C2; the gate of PMOS tube M7 and the gate of PMOS tube M8 are connected with the drain of PMOS tube M10 and the drain of PMOS tube M11 respectively and constitute a common mode feedback structure, effectively inhibiting the influence of the voltage of capacitor C1 and capacitor C2 on the charging current.

3. The high frequency clock duty cycle calibration circuit of claim 1, wherein, The output signal terminals CLK1 and CLK1n of the single-turn complementary signal circuit STC in the clock duty cycle detection circuit (1) are complementary signals, when the output signal terminal CLK1 is low, the PMOS transistor M11 is on, the PMOS transistor M10 is off, the capacitor C2 is charged, the capacitor C1 is discharged, the voltage V cp of the capacitor C2 rises, the drain current of the PMOS transistor M8 falls, and the voltage V cn of the capacitor C1 falls; when the output signal terminal CLK1 is high, the PMOS transistor M11 is off, the PMOS transistor M10 is on, the capacitor C2 is discharged, the capacitor C1 is charged, the voltage V cn of the capacitor C1 rises, the drain current of the PMOS transistor M7 falls, and the voltage V cp of the capacitor C2 falls; the change voltage ΔV cp of the capacitor C2 is where I n is the discharge current provided for the NMOS transistor M13, T is the clock period, N is the duty cycle of the input clock, and C2 is the capacitance of the capacitor C2. When the duty cycle N < 50%, the capacitor C2 charges, the voltage V cp of the capacitor C2 is higher than the common mode level; when the duty cycle N > 50%, the voltage V cp of the capacitor C2 is lower than the common mode level; the varying voltage of the capacitor C1 is similar to the varying voltage of the capacitor C2; Therefore, the relationship between the change voltage of capacitor C1 and capacitor C2 and the corresponding initial voltage can determine the duty cycle state of the clock, and the working state of switches S1-S6 is controlled by the logic circuit logic in the clock duty cycle adjustment circuit (2), and the voltage of capacitor C1 and the voltage of capacitor C2 are converted into current signals by the transconductance operational amplifier Gm in the clock duty cycle adjustment circuit (2), thereby controlling the current of the clock duty cycle adjustment circuit (2).

4. The high frequency clock duty cycle calibration circuit of claim 1, wherein, The clock duty cycle adjustment circuit (2) comprises a logic circuit, a transconductance operational amplifier Gm, PMOS tubes M14, M15, M16, M17, M18, M19, NMOS tubes M20, M21, M22, M23, M24, M25, switches S1, S2, S3, S4, S5, S6, an inverter INV, and a clock buffer buf, wherein the output end L1 of the logic circuit is connected with the control end of the switch S1, the output end L2 of the logic circuit is connected with the control end of the switch S2, the output end L3 of the logic circuit is connected with the control end of the switch S3, the output end L4 of the logic circuit is connected with the control end of the switch S4, the output end L5 of the logic circuit is connected with the control end of the switch S5, the output end L6 of the logic circuit is connected with the control end of the switch S6, the source of the PMOS tube M14 is connected with one end of the switch S3, one end of the switch S2, one end of the switch S1, the source of the PMOS tube M18, and an external power supply VDD respectively, the gate of the PMOS tube M14 is connected with the drain of the PMOS tube M14, the inverting output end ICN of the transconductance operational amplifier Gm, the gate of the PMOS tube M15, the gate of the PMOS tube M16, the gate of the PMOS tube M17, and the gate of the PMOS tube M18 respectively, the other end of the switch S3 is connected with the source of the PMOS tube M15, the other end of the switch S2 is connected with the source of the PMOS tube M16, the other end of the switch S1 is connected with the source of the PMOS tube M17, the drain of the PMOS tube M15 is connected with the drain of the PMOS tube M16, the drain of the PMOS tube M17, the drain of the PMOS tube M18, and the source of the PMOS tube M19 respectively, the gate of the NMOS tube M21 is connected with the drain of the NMOS tube M21, the non-inverting output end ICP of the transconductance operational amplifier Gm, the gate of the NMOS tube M22, the gate of the NMOS tube M23, the gate of the NMOS tube M24, and the gate of the NMOS tube M25 respectively, the source of the NMOS tube M21 is connected with one end of the switch S6, one end of the switch S5, one end of the switch S4, the source of the NMOS tube M25, one end of the capacitor C3, and an external ground GND respectively, the drain of the NMOS tube M22 is connected with the drain of the NMOS tube M23, the drain of the NMOS tube M24, the drain of the NMOS tube M25, and the source of the NMOS tube M20 respectively, the source of the NMOS tube M22 is connected with the other end of the switch S6, the source of the NMOS tube M23 is connected with the other end of the switch S5, the source of the NMOS tube M24 is connected with the other end of the switch S4, the gate of the PMOS tube M19 is connected with the gate of the NMOS tube M20 and an external input clock signal CLK_IN respectively,The drain of the PMOS transistor M19 is connected to the drain of the NMOS transistor M20, the other end of the capacitor C3 and the input of the inverter INV, the output of the inverter INV is connected to the input of the clock buffer buf, the output of the clock buffer buf is connected to the signal input of the single-to-complementary signal circuit STC and the circuit output CLK_OUT respectively.

5. A high frequency clock duty cycle correction circuit as claimed in claim 4, wherein, In the clock duty cycle adjustment circuit (2), the current provided by the transconductance operational amplifier Gm provides a bias voltage for PMOS tubes M15, M16, M17 and M18 through PMOS tube M14 and controls the rising edge time of the clock signal, and the current provided by the transconductance operational amplifier Gm provides a bias voltage for NMOS tubes M22, M23, M24 and M25 through NMOS tube M21 and controls the falling edge time of the clock signal; switches S1-S6 control the working state of each branch, thereby controlling the charging and discharging time of capacitor C3 and calibrating the duty cycle of the clock.

6. A high frequency clock duty cycle correction circuit as claimed in claim 4 or 5, characterized in that, The clock duty cycle adjustment circuit (2), PMOS M17 and PMOS M18 have the same channel width-length ratio, the channel width-length ratio of PMOS M16 is β1 times of PMOS M18, the channel width-length ratio of PMOS M15 is β2 times of PMOS M18, NMOS M24 and NMOS M25 have the same channel width-length ratio, the channel width-length ratio of NMOS M23 is β1 times of NMOS M25, the channel width-length ratio of NMOS M22 is β2 times of NMOS M25, the drain current of PMOS M18 is I UP , the drain current of NMOS M25 is I DOWN , switches S1-S3 make the drain current of PMOS M19 K p times of the drain current of PMOS M18, switches S4-S6 make the drain current of NMOS M20 K n times of the drain current of NMOS M25, wherein K p is 1≤K p ≤2+β1+β2, K n is 1≤K n ≤2+β1+β2, the flip voltage of the logic circuit composed of PMOS M19 and NMOS M20 branch related MOS is 0.5V DD , wherein V DD is the voltage of external power supply VDD, then the calibration value of the clock signal is equal to the offset of the input clock signal , wherein m is the duty cycle of the output clock after clock correction and m=50%, C3 is the capacitance of capacitor C3. When the external power supply VDD voltage and the capacitance of the capacitor C3 are constant, the offset of the input clock signal can be obtained according to the period T and the duty cycle N of the input clock, and the current I is controlled by the transconductance operational amplifier Gm of the clock duty cycle detection circuit (1) and the clock duty cycle adjustment circuit (2) DOWN and the current I UP and K is adjusted by the logic circuit logic of the clock duty cycle adjustment circuit (2) n and K p , so that the calibration value of the clock signal reaches the offset of the input clock signal, and the duty cycle of the input clock signal is effectively calibrated.

7. A high frequency clock duty cycle correction circuit as claimed in claim 4 or 5, characterized in that, In the clock duty cycle adjustment circuit (2), switches S1-S3 control the drain current of PMOS tube M19, and switches S4-S6 control the drain current of NMOS tube M20, thereby controlling the delay of the rising edge and the delay of the falling edge of the output clock; controlling the working state of switches S1-S6 can effectively improve the detection range of the duty cycle calibration circuit of the input clock signal, so that the duty cycle offset of the input clock signal can be calibrated within the range of 20%-80%.

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