Phase-locked loop, radio frequency signal transmitter, radar sensor and electronic device

Abstract

The application provides a phase-locked loop, a radio frequency signal transmitter, a radar sensor and an electronic device. The phase-locked loop comprises a phase-locked loop circuit, a controlled charge compensation circuit and a digital modulation controller, wherein the phase-locked loop circuit and the charge compensation circuit are connected, and the digital modulation controller is connected to the phase-locked loop circuit and outputs a frequency control signal to make the phase-locked loop circuit generate an effective interval of a frequency modulation signal according to the frequency control signal; the digital modulation controller is also connected to the charge compensation circuit and controls the charge compensation circuit to adjust the charge in the phase-locked loop circuit in an invalid interval of the frequency modulation signal to shorten the time length of frequency recall of the frequency modulation signal.

Description

Technical Field

[0001] This application relates to the field of feedback control technology, and more specifically, to a phase-locked loop, a radio frequency signal transmitter, a radar sensor, and electronic equipment. Background Technology

[0002] Radar sensors detect objects in the surrounding environment by emitting detection signal waves. They use the reflection mechanism of electromagnetic waves by objects to sense the echo signal waves corresponding to the detection signal waves, and measure the physical quantities between the sensor and the object based on the frequency difference between transmission and reception.

[0003] To improve radar detection resolution, one approach is to transmit more frequency-modulated (FM) signals within the same timeframe. This necessitates finding methods to effectively shorten the FM signal cycle. Simultaneously, from an engineering perspective, this involves minimizing modifications to existing, stable circuitry and considering the size limitations of the radar chip. These factors combined with these considerations will lead to a solution for effectively shortening the FM cycle.

[0004] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this application provides a phase-locked loop, a radio frequency signal transmitter, a radar sensor, and an electronic device that shortens the period of the modulation waveform and achieves fast modulation functionality.

[0006] According to a first aspect of this application, a phase-locked loop (PLL) is proposed, comprising a PLL circuit, a controlled charge compensation circuit, and a digital modulation controller. The PLL circuit and the charge compensation circuit are connected, and the digital modulation controller is connected to the PLL circuit, outputting a frequency control signal such that the PLL circuit generates an effective range of a frequency-modulated signal according to the frequency control signal. The digital modulation controller is also connected to the charge compensation circuit, controlling the charge compensation circuit to adjust the charge in the PLL circuit within the ineffective range of the frequency-modulated signal, thereby shortening the time required for frequency reversal of the frequency-modulated signal.

[0007] A second aspect of this application provides a radio frequency signal transmitter, comprising: a phase-locked loop as described in the first aspect; and a radio frequency signal transmitting circuit connected to the phase-locked loop for multiplying the frequency-modulated signal provided by the phase-locked loop to output a frequency-modulated radio frequency transmitting signal.

[0008] A third aspect of this application provides a radar sensor comprising: a transmitting antenna for converting a received radio frequency transmitted signal into a detection signal wave; a receiving antenna for converting an echo signal wave into a radio frequency received signal; wherein the echo signal wave is formed by the reflection of the detection signal wave by an object; a radio frequency signal transmitter as described in the second aspect, coupled to the transmitting antenna to output the radio frequency transmitted signal; and a signal receiver, coupled to the receiving antenna, for outputting a baseband digital signal using the radio frequency received signal and a local oscillator signal.

[0009] The fourth aspect of this application provides an electronic device, characterized in that it includes a radar sensor as described in the third aspect.

[0010] This application provides a phase-locked loop, a radio frequency signal transmitter, a radar sensor, and an electronic device. Outside the effective range of the frequency-modulated signal, the control voltage of the voltage-controlled oscillator generated by the filter is adjusted to shorten the time for the phase-locked loop to recover the initial frequency, thereby reducing the period of the modulated waveform and realizing a fast modulation function.

[0011] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0012] The above and other objects, features, and advantages of this application will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings. The drawings described below are merely some embodiments of this application and are not intended to limit the scope of this application.

[0013] Figure 1 A schematic diagram of the circuit structure of a phase-locked loop in an exemplary embodiment is shown;

[0014] Figure 2 A schematic diagram of the structure of a charge compensation circuit of an exemplary embodiment is shown;

[0015] Figure 3 A schematic diagram of a digital logic control circuit of an exemplary embodiment is shown;

[0016] Figure 4 A schematic diagram of a frequency modulation signal is shown in an exemplary embodiment;

[0017] Figure 5 A signal timing diagram of a digital control logic of an exemplary embodiment is shown. Detailed Implementation

[0018] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0019] The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of these specific details, or other methods, components, materials, devices, etc. In these cases, well-known structures, methods, devices, implementations, materials, or operations will not be shown or described in detail.

[0020] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0021] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0022] For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or device.

[0023] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of exemplary embodiments, and the modules or processes in the drawings are not necessarily essential for implementing this application, and therefore cannot be used to limit the scope of protection of this application.

[0024] In some examples, rapid modulation is needed to improve radar velocity resolution, while lower transmit phase noise is required to improve target detection. However, when using a frequency-modulated continuous phase-locked loop (PLL) for modulation: to reduce phase noise, the PLL bandwidth is set to a lower value; but to achieve rapid modulation, the PLL bandwidth is set to a higher value; thus, the requirements for both reducing phase noise and rapid modulation cannot be reconciled.

[0025] To meet the detection range requirements of radar sensors, they are systematically configured with intermediate frequency (IF) and radio frequency (RF) circuits to provide the necessary bandwidth. Furthermore, the measurement accuracy of a radar sensor is related to the number of detection signal waves emitted within a given time period; for example, the more detection signal waves emitted, the higher the accuracy of the measured physical quantities of the object.

[0026] For radar sensors, the emitted detection signal wave originates from a frequency-modulated (FM) signal generated by internal circuitry. This FM signal comprises a frequency rise phase and a frequency fall phase. Typically, one phase (frequency rise or fall phase) is designated as the effective range for radar signal processing, while the other phase (frequency fall or rise phase) is considered the ineffective range. Furthermore, there is usually an idle range between adjacent FM signals to reserve a time slot for locking the phase-locked loop (PLL) that generates the FM signal.

[0027] Therefore, this application provides a phase-locked loop (PLL) designed to increase the transmission frequency of a frequency-modulated (FM) signal by shortening the duration of the invalid interval, thereby improving the accuracy of physical quantity measurements. The PLL includes a PLL circuit, a controlled charge compensation circuit, and a digital modulation controller. The digital modulation controller is connected to the PLL circuit to output a frequency control signal fn, causing the PLL circuit to generate a frequency-modulated signal fout. The digital modulation controller is also connected to the charge compensation circuit, which controls the charge compensation circuit to adjust the charge in the PLL circuit during the invalid interval of the frequency-modulated signal fout, thereby shortening the time required for frequency rewinding of the frequency-modulated signal.

[0028] Please see Figure 1 The diagram shows a schematic of a phase-locked loop (PLL) circuit. The PLL circuit includes a frequency and phase detector 11, a charge pump 12, a low-pass filter 13, a voltage-controlled oscillator (VCO) 14, and a frequency divider 15. The frequency and phase detector 11 receives a reference clock signal `fref` and a frequency divider signal `fdiv`, and detects the jumping edges of these two signals to output a frequency and phase detection signal (up, down). The charge pump 12 adjusts its output current under the control of the frequency and phase detection signal. The low-pass filter 13 filters the received current, and the filtered electrical signal is used as a control signal and output to the VCO 14. The VCO 14 adjusts the frequency of its output signal `fout` under the control of the control signal. The frequency divider divides the signal `fout` by (`fout / N`) and outputs the divided signal `fdiv`, thus achieving controlled and stable frequency control of the signal `fout` through feedback.

[0029] like Figure 1As shown, the digital modulation controller 16 is connected to the phase-locked loop circuit and outputs a frequency control signal so that the phase-locked loop circuit generates an effective range of frequency modulation signals according to the frequency control signal.

[0030] According to some embodiments, fout = fref·N. The digital modulation controller changes the division ratio N according to the preset frequency modulation rule, so that under the action of the frequency divider 15, the frequency of the signal fout output by the voltage-controlled oscillator 14 changes with time according to a certain rule to form a frequency modulation signal.

[0031] For example, the digital modulation controller 16 controls the frequency divider 15, so that the signal output by the voltage-controlled oscillator 14 is a frequency-modulated signal with a continuously linearly varying frequency, i.e., an FMCW signal. See also... Figure 4 This is a schematic diagram of a frequency modulation (FM) signal. The horizontal axis represents time t, and the vertical axis represents frequency f. fstart is the starting frequency of the sweep waveform, and fstop is the ending frequency. From t1 to t2, the FM signal frequency increases with time, and the time from t1 to t2 is the rise time. From t2 to t3, the FM signal frequency decreases rapidly with time, and the time from t2 to t3 is the fall time. From t3 to t4, the FM signal frequency remains constant with time, and the time from t3 to t4 is the idle time.

[0032] like Figure 4 As shown, the frequency-modulated signal fout includes an effective interval, an ineffective interval, and an idle interval. As mentioned earlier, the effective interval utilized by the radar sensor can correspond to... Figure 4 The rise time or fall time; the invalid interval is used to allow the phase-locked loop circuit to revert to the frequency of the frequency modulation signal, which can be... Figure 4 The down time or up time in the interval corresponds to the idle interval. Figure 4 The idle time in the process.

[0033] To shorten the invalid interval, such as Figure 1As shown, the phase-locked loop (PLL) also includes a charge compensation circuit 17. The digital modulation controller is also connected to the charge compensation circuit. During the invalid interval of the frequency modulation signal, the charge compensation circuit 17 is controlled to adjust the charge in the PLL circuit to shorten the time required for frequency rewinding of the frequency modulation signal. The charge compensation circuit 17 can adjust the charge in the PLL circuit by injecting or releasing charge. For example, adjusting the charge in the charge pump 12; adjusting the charge in the filter; or adjusting the charge to change the voltage / current of the control signal of the voltage-controlled oscillator, etc. By collecting the charge in the filter and injecting it into the PLL circuit, the charge compensation circuit 17 adjusts the charge appropriately, which can shorten the time required for frequency rewinding of the frequency modulation signal, enable the PLL circuit to quickly regain lock, or reduce inappropriate oscillations caused by lockout of the PLL. Alternatively, the charge compensation circuit 17 can adjust the appropriate charge by collecting the charge in the filter and discharging the corresponding charge through the circuit path in the phase-locked loop circuit. This can shorten the time for frequency correction of the frequency modulation signal, enable the phase-locked loop circuit to quickly regain lock, or reduce inappropriate oscillations caused by phase-locked loop loss.

[0034] like Figure 1 As shown, a first switch K1 is configured between the output terminal of the charge compensation circuit 17 and the filter 13. The first switch K1 is controlled by a digital modulation controller to be controlled to conduct during the idle interval of the frequency modulation signal fout, so that the charge compensation circuit 17 collects and stores charge from the filter 13 during the conduction of the first switch K1. The charge compensation circuit also includes an energy storage device and at least one second switch (not shown) connected between the energy storage device and the phase-locked loop circuit; wherein the second switch is controlled by the digital modulation controller to conduct during the invalid interval of the frequency modulation signal fout, so as to inject / discharge appropriate charge using the charge path in the phase-locked loop circuit. The charge compensation circuit also includes a damping device disposed on the current output path of the energy storage device to stabilize the output current.

[0035] Please see Figure 2The diagram illustrates a charge compensation circuit. A first switch K1 is positioned between the charge compensation circuit and the output of filter 131. The first switch K1 is controlled by the control signal "Idle" from the digital modulation controller to be controlled to conduct during the idle period of generating the frequency modulation signal "fout". Capacitor 171 in the charge compensation circuit stores charge during the conduction of the first switch K1. The charge compensation circuit also includes at least one second switch K2 connected between capacitor 171 and filter 131 in the phase-locked loop circuit. Filter 131 includes cascaded RC filter units, with each second switch K2 connected to each RC filter unit. During the current modulation signal control cycle, the first switch K1 conducts during the idle period, causing filter 131 to store charge in capacitor 171. During the next modulation signal control cycle, while the frequency modulation signal fout is rising, both the first switch K1 and the second switch K2 are open, and the charge compensation circuit as a whole does not participate in the generation of the frequency modulation signal FMCW by the phase-locked loop. During the invalid interval of the frequency modulation signal fout, the second switch is turned on under the control of the digital modulation controller's control signal Down. The charge on capacitor 171 is transferred to the filter LPF, causing the frequency modulation signal fout of the phase-locked loop to quickly recover from frequency fstop to frequency fstart, thereby accelerating the modulation cycle of the phase-locked loop. The charge compensation circuit also includes a buffer device, which is located on the current output path of the energy storage device.

[0036] According to the example embodiment, this application samples the control voltage of the voltage-controlled oscillator generated by the filter during the waiting time of the frequency modulation signal FMCW, and applies the voltage to the filter at the beginning of the falling time to speed up the stabilization time of the phase-locked loop, thereby reducing the period of the modulation waveform and realizing the fast modulation function.

[0037] A digital modulation controller (DMC) uses a received clock signal for logic processing, timing, or counting operations to output a frequency control signal and multiple control signals. This clock signal can be, for example, a reference clock signal taken from the input of a phase-locked loop (PLL) or a frequency-divided signal of a frequency-modulated signal. The reference clock signal can be generated by an oscillator such as a crystal oscillator. Depending on the timing of the output frequency control signal or other control signals, the DMC can generate corresponding control signals based on the reference clock signal or the frequency-divided signal. For example, the DMC can output a frequency controller based on either the reference clock signal or the frequency-divided signal, thus enabling the PLL to generate the effective range of the modulation signal. Here, although the frequency-divided signal may change in frequency or phase due to PLL unlocking, the PLL circuit is locked when the frequency control signal is output; that is, the frequency-divided signal and the reference clock signal are in phase and frequency. Therefore, either the reference clock signal or the frequency-divided signal reliably controls the effective range of the PLL circuit's output frequency-modulated signal.

[0038] Other control signals can be generated by a reference clock signal. For example, the multiple control signals include: control signal Up, control signal Idle, and control signal Down. Control signal Up represents the active range of the frequency modulation (FM) signal. Control signal Idle represents the signal controlling the charge compensation circuit to store charge during the idle range of one cycle when periodically controlling the FM signal fout. Control signal Down represents the signal controlling the charge compensation circuit to inject or discharge charge during the inactive range of the FM signal. In some examples, different edges of a control signal can be used to control the phase-locked loop (PLL) to enter different ranges within one cycle of transmitting the FM signal. For example, one type of edge of control signal Idle (such as the upper edge) is used to turn on the second switch in the charge compensation circuit, causing the PLL to enter the idle range; another type of edge of control signal Idle (such as the lower edge) is used to turn off the second switch in the charge compensation circuit and output a frequency control signal, causing the PLL to enter the active range. The digital modulation controller determines the duration of the effective interval by counting the pulses of the frequency division signal and outputs a control signal Idle with one type of jumping edge (such as an upper jumping edge) to control the first switch in the charge compensation circuit to turn on, so that the phase-locked loop enters the invalid interval. The invalid interval ends when the pulse count of the reference clock signal is determined. Another type of jumping edge of the control signal Idle (such as a lower jumping edge) controls the first switch to turn off, so that the phase-locked loop enters the idle interval from the invalid interval.

[0039] Please see Figure 3 This diagram illustrates a digital modulation controller. The digital control includes a chirp generator, a Sigma Delta modulator (SDMModulator), and a timing controller. Specifically, the chirp generator generates a frequency division ratio N sequence in real time based on the required FMCW waveform.

[0040] Nstart = fstart / fref

[0041] Nstop = fstop / fref

[0042] fstart and fstop are respectively Figure 4 The start and end frequencies of the intermediate frequency modulation signal FMCW, where fref is the frequency of the reference clock signal.

[0043] In high-precision sweep frequency waveforms, the division ratio N is usually not an integer and can be represented as If (I - integer part, f - fractional part). This fractional sequence will be modulated into an integer sequence N by a Sigma Delta modulator (SDM Modulator) and then sent to the divider DividerN.

[0044] Taking the rise time of an FM signal as the effective range of the FM signal as an example, in order to generate a fast modulation waveform, at the beginning of the fall time, the division ratio N will quickly change from Nstop back to Nstart, as follows: Figure 5 As shown, the phase-locked loop (PLL) will unlock during the down time and remain locked during the idle time and rise time. To ensure that the entire modulation cycle does not change due to the PLL unlocking, a timing controller is added to the digital control circuit. Based on the reference clock signal fref, a control signal Idle is generated to indicate the start time of the effective interval of the frequency modulation signal fout, and a control signal Down is generated to indicate the start time of the ineffective interval of the frequency modulation signal fout. These signals are output to the charge compensation circuit. A control signal Up, generated during the idle interval of the frequency modulation signal fout, is also output to the waveform generator.

[0045] According to some embodiments, when the Up signal is valid (between t1 and t2), the waveform generator starts counting from Nstart to Nstop, and the Sigma Delta modulator outputs a frequency control signal fn, causing the phase-locked loop (PLL) circuit to output a linearly frequency-modulated (FMCW) continuous frequency-modulated signal. Here, the Up signal is generated based on the fref clock, while the frequency control signal fn is generated based on the frequency divider signal fdiv. For a waveform generator using fdiv, fdiv and fref are asynchronous signals, but the changes in the Up signal occur at the beginning and end of the rise time, during which the PLL is locked, and the frequency divider signal fdiv and the reference clock signal fref are phase-synchronized. Therefore, the sampling of the Up signal by the frequency divider signal fdiv can be considered as a synchronous circuit, without introducing the metastability effects of asynchronous circuits.

[0046] During the period when the control signal Up is invalid and the control signal Down is valid (interval t2-t3), the frequency control signal fn has no output, and each of the second switches in the charge compensation circuit is turned on to distribute the pre-stored charge in the charge compensation circuit to the filter, so that the filter further reduces the voltage value of the output control signal, thereby increasing the rate of frequency descent of the signal output by the VCO.

[0047] During the period when the control signal Down is invalid and the control signal Idle is valid (interval t3-t4), each of the second switches in the charge compensation circuit is turned off and the first switch is turned on, so as to share the remaining charge in the filter with the capacitor in the charge compensation circuit.

[0048] By utilizing the charge collected from the residual charge in the filter, the frequency of the output signal of the phase-locked loop (PLL) circuit can be adjusted within the invalid interval. This effectively accelerates the recovery time of the PLL circuit from the Nstop frequency to the starting frequency Nstart, thus effectively shortening the duration of the invalid interval. Consequently, within the same time frame, the radar sensor can emit a greater number of detection electromagnetic waves, thereby improving the accuracy of detecting the physical quantities of the object.

[0049] This application also provides a radio frequency signal transmitter, which includes the phase-locked loop of this application and a radio frequency signal transmitting circuit connected to the phase-locked loop for generating the required baseband digital signal under the frequency modulation signal provided by the phase-locked loop.

[0050] The radio frequency (RF) signal transmitting circuit includes a frequency multiplier and a driver amplifier. The frequency multiplier multiplies the frequency-modulated signal to the RF band. The driver amplifier amplifies the power of the RF transmitting signal output from the frequency multiplier to match the power of the excitation antenna.

[0051] The radio frequency signal transmitting circuit may also include a phase shifter for phase control of the radio frequency transmitted signal. Different controlled groups of radio frequency transmitted signals can detect objects in different beam directions and effectively reduce signal interference between radars.

[0052] This application also provides a radar sensor configured with an antenna array. The radar sensor uses the detection signal wave emitted by the antenna array and the echo signal wave received to measure physical quantities between itself and surrounding environmental obstacles, such as measuring relative speed, relative angle, relative distance, and at least one of the three-dimensional contours of the obstacles.

[0053] Here, the radar sensor further includes: the aforementioned radio frequency (RF) signal transmitter and a signal receiver. The RF signal transmitter utilizes the continuously frequency-modulated signal generated by the phase-locked loop provided in any of the above examples, converts it into an RF transmission signal, and outputs it to a transmitting antenna, so that the transmitting antenna converts it into a probe signal wave radiated into free space. The frequency multiplier in the RF signal transmitter also uses the output RF transmission signal as a local oscillator signal, outputting it to the signal receiver.

[0054] The radio frequency (RF) signal transmitter, based on the frequency modulation signal generated by the phase-locked loop (PLL), obtains an RF transmission signal swept with a center frequency and a preset bandwidth through frequency multiplication; this signal is then fed to the transmitting antenna via a driver amplifier to transmit a corresponding detection signal wave. When the detection signal wave is reflected by an object, an echo signal wave is formed. The receiving antenna converts the echo signal wave into an RF received signal.

[0055] The signal receiver is used to perform down-conversion, filtering, analog-to-digital conversion, and other processing on the radio frequency received signal using the local oscillator signal, so as to output a baseband digital signal representing the difference frequency between the probe signal wave and the echo signal wave.

[0056] In some examples, radar sensors also include signal processors.

[0057] The signal processor is connected to the signal receiver and is used to extract measurement information from the baseband digital signal through signal processing, perform signal processing to obtain the measurement information of the object by the radar sensor, and output measurement data. The signal processing includes digital signal processing calculations such as phase, frequency, and time domain processing based on at least one signal to be processed provided by at least one receiving antenna. The measurement data includes at least one of the following: distance data representing the relative distance to at least one detected obstacle; velocity data representing the relative velocity of at least one detected obstacle; angle data representing the relative angle of at least one detected obstacle, etc.

[0058] This application also provides an electronic device that includes the radar sensor of this application.

[0059] In an optional embodiment, the aforementioned electronic device can be a component or product applied in fields such as smart homes, transportation, smart homes, consumer electronics, surveillance, industrial automation, in-cabin detection, and healthcare. For example, the electronic device can be intelligent transportation equipment (such as automobiles, bicycles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as wristbands, glasses, etc.), smart home devices (such as robot vacuum cleaners, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablets, etc.), as well as devices such as barriers, intelligent traffic lights, intelligent signs, and various industrial robotic arms (or robots). It can also be various instruments for detecting vital signs parameters and various devices equipped with such instruments, such as in-cabin detection in automobiles, indoor personnel monitoring, smart medical devices, and consumer electronic devices.

[0060] It should be clearly understood that this application describes how specific examples are formed and used, but this application is not limited to any details of these examples. Rather, based on the teachings of the disclosure of this application, these principles can be applied to many other embodiments.

[0061] Furthermore, it should be noted that the above figures are merely illustrative representations of the processes included in the method according to exemplary embodiments of this application, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0062] Exemplary embodiments of this application have been specifically shown and described above. It should be understood that this application is not limited to the detailed structures, arrangements, or implementation methods described herein; rather, this application is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A phase-locked loop, characterized in that, It includes a phase-locked loop circuit, a controlled charge compensation circuit, and a digital modulation controller, wherein the phase-locked loop circuit and the charge compensation circuit are connected, and The digital modulation controller is connected to the phase-locked loop circuit and outputs a frequency control signal so that the phase-locked loop circuit generates the effective range of the frequency modulation signal according to the frequency control signal. The digital modulation controller is also connected to the charge compensation circuit, which controls the charge compensation circuit to adjust the charge in the phase-locked loop circuit during the invalid interval of the frequency modulation signal, so as to shorten the time for frequency callback of the frequency modulation signal. The phase-locked loop circuit includes a filter, and the charge compensation circuit is connected to the output terminal of the filter and is used to adjust the voltage of the control signal output by the filter; The charge compensation circuit samples the control voltage of the voltage-controlled oscillator generated by the filter during the waiting time of the frequency modulation signal, and applies the voltage to the filter in the invalid interval.

2. The phase-locked loop as described in claim 1, characterized in that, The charge compensation circuit is connected to the output terminal of the filter, wherein: A first switch is configured between the charge compensation circuit and the output terminal. The first switch is controlled by the digital modulation controller to be turned on in a controlled manner during the idle interval between the periodic generation of the frequency modulation signal, so that the charge compensation circuit stores charge during the period when the first switch is turned on.

3. The phase-locked loop as described in claim 1, characterized in that, The charge compensation circuit includes: an energy storage device, and at least one second switch connected between the energy storage device and the filter; The second switch is controlled by the digital modulation controller to conduct within the invalid range of the frequency modulation signal, thereby injecting charge into the filter.

4. The phase-locked loop as described in claim 3, characterized in that, The charge compensation circuit also includes a damping device disposed on the current output path of the energy storage device.

5. The phase-locked loop as described in claim 3, characterized in that, The filter includes one RC filter unit or multiple cascaded RC filter units, and the second switch is connected to each RC filter unit in a one-to-one correspondence.

6. The phase-locked loop as described in claim 1, characterized in that, The duration of the effective interval is generated by timing using a frequency division signal of a reference clock signal or a frequency modulation signal.

7. The phase-locked loop as described in claim 6, characterized in that, The reference clock signal is also output to the input terminal of the phase-locked loop circuit, so that the phase-locked loop circuit can use the reference clock signal and the frequency control signal to generate the frequency modulation signal.

8. A radio frequency signal transmitter, characterized in that, include: Phase-locked loop as described in any one of claims 1-7; A radio frequency signal transmitting circuit, connected to the phase-locked loop, is used to multiply the frequency-modulated signal provided by the phase-locked loop to output a frequency-modulated radio frequency transmitting signal.

9. A radar sensor, characterized in that, include: A transmitting antenna is used to convert the received radio frequency transmitted signals into probe signal waves; A receiving antenna is used to convert echo signal waves into radio frequency received signals; wherein, the echo signal wave is formed by the reflection of the probe signal wave by an object; The radio frequency signal transmitter as described in claim 8 is coupled to the transmitting antenna to output the radio frequency transmission signal; A signal receiver, coupled to the receiving antenna, outputs a baseband digital signal using the radio frequency received signal and the local oscillator signal.

10. An electronic device, characterized in that, Including the radar sensor as described in claim 9.

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