Supply voltage tolerant phase-locked loop circuit
The phase-locked loop design addresses the challenge of operating at different supply voltages by using a supply voltage detector and voltage-to-current converter to adjust the reference current, allowing the PLL to function efficiently at 3.3 V and 5 V, thereby stabilizing frequency range and reducing power consumption.
Patent Information
- Authority / Receiving Office
- US · United States
- Patent Type
- Patents(United States)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 1996-10-04
- Publication Date
- 2000-09-19
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Analog phase-locked loops (PLL) face challenges in operating at different supply voltages, such as 3.3 V and 5 V, due to variations in frequency range caused by temperature and process conditions, leading to inefficiencies and potential instability.
A phase-locked loop design that adjusts its frequency range based on detected supply voltage by using a supply voltage detector, a voltage-to-current converter, and a differential amplifier to scale and adjust the reference voltage or current, enabling operation at multiple supply voltages.
Enables the same PLL design to operate effectively at both 3.3 V and 5 V by linearly adjusting the frequency range, reducing silicon area and power consumption while maintaining stability across varying conditions.