Method, system, storage medium, and device for chip adaptive check retransmission

Abstract

The application provides a kind of interconnection chip adaptive parallel CRC check retransmission method, system, storage medium and equipment, method includes the following steps: in chip architecture design Setting adaptive parallel CRC check module, data cache module, retransmission detection module, sending processing module and receiving processing module;With data input adaptive parallel CRC check module to carry out bit width adjustment and adaptive parallel CRC check according to the system bandwidth to the data input obtains check data, and simultaneously input data cache module carries out buffering;With input data and check data are merged into merged data and are sent to the opposite end through sending processing module;And when receiving the response data returned by the opposite end, corresponding data is taken out from the corresponding data cache module and is re-fed into adaptive parallel CRC check module to carry out CRC check and retransmission.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and specifically to a method, system, storage medium, and device for adaptive parallel CRC check retransmission of interconnect chips. Background Technology

[0002] With the rapid development of integrated circuit technology and the increasing demands for high bandwidth and high performance in fields such as video and image processing, multiprocessor technology has received increasing attention. However, the increase in the number of processors also directly increases the complexity of information interaction between processors. Interconnect chips, as a technical means to connect different processors and maintain global system data access consistency, have been studied in depth. Currently, most interconnect chips are customized for fixed systems, and their bandwidth is limited by the system bandwidth, which is generally fixed. When the system bandwidth demand increases, the interconnect chip architecture needs to be restructured. Therefore, it is necessary to design an interconnect chip with scalable bandwidth to meet the ever-increasing demand for multiprocessor interconnect transmission bandwidth. CRC (Cyclic Redundancy Check), as an effective error detection method, can detect multiple bit errors that occur during transmission and feed the results back to the sending end to provide a basis for data retransmission, thereby ensuring the reliability and stability of the system.

[0003] Interconnect chips provide data channels for information exchange between multiple processors. As an effective error detection method, CRC can detect multiple bit errors that occur during transmission and feed them back to the sending end, thereby ensuring the reliability of the system data link through data retransmission. When the system bandwidth demand increases and the number of processors increases, it is often necessary to reconstruct the interconnect chip architecture and modify the corresponding CRC detection and retransmission logic. It lacks versatility and cannot well meet the needs of bandwidth scalability.

[0004] Existing CRC detection and retransmission logic for interconnect chips is limited by information such as processor speed and number. Generally, once the system architecture is determined, the corresponding CRC detection and retransmission logic is also fixed and cannot be dynamically adjusted with the scalability of system bandwidth. It lacks versatility. In addition, each modification to the CRC check retransmission logic increases the project development cycle and costs.

[0005] Therefore, to address this problem, a better adaptive parallel CRC check retransmission mode for interconnect chips needs to be proposed. This adaptive CRC check retransmission method can be implemented for interconnect chip designs with scalable bandwidth to ensure reliable data transmission in the system. Summary of the Invention

[0006] In view of this, the purpose of this invention is to propose an improved method, system, storage medium, and device for adaptive parallel CRC check retransmission in interconnect chips, so as to implement an adaptive CRC check retransmission method for interconnect chip designs with scalable bandwidth to ensure reliable data transmission in the system.

[0007] To achieve the above objectives, in one respect, the present invention provides a method for adaptive parallel CRC check retransmission in interconnect chips, wherein the method includes the following steps:

[0008] The chip architecture design includes an adaptive parallel CRC check module, a data buffer module, a retransmission detection module, a transmission processing module, and a reception processing module.

[0009] The data is input into the adaptive parallel CRC check module to adjust the bit width of the input data according to the system bandwidth and perform adaptive parallel CRC check to obtain check data, and is simultaneously input into the data cache module for caching;

[0010] The input data and the verification data are merged into a merged data and sent to the other end through the sending processing module; and

[0011] Upon receiving the response data returned by the peer, the corresponding data is retrieved from the corresponding data cache module and retransmitted to the adaptive parallel CRC check module for CRC check and retransmission.

[0012] In some embodiments of the adaptive parallel CRC check retransmission method for interconnect chips according to the present invention, the adaptive parallel CRC check module adjusts the bit width of the input data according to the system bandwidth and obtains the check data through adaptive parallel CRC check, including the following steps:

[0013] The adaptive parallel CRC check module includes a configuration register group module, a bit width adjustment module, and a CRC check logic module.

[0014] The system configuration information is received through the configuration register group module, and system bandwidth register information is sent to the bit width adjustment submodule and the CRC check logic submodule.

[0015] The bit width adjustment module adjusts the bit width of the input data according to the system bandwidth register information.

[0016] The input data is subjected to CRC verification by the CRC verification logic module.

[0017] In some embodiments of the method for adaptive parallel CRC check retransmission of interconnect chips according to the present invention, multiple CRC check generation modules are pre-configured within the CRC check logic module for parallel CRC check functions of data with different bit widths, and one of the multiple CRC check generation modules is selected according to the system bandwidth register information to perform CRC check on the data output by the bit width adjustment module.

[0018] In some embodiments of the adaptive parallel CRC check retransmission method for interconnect chips according to the present invention, the adaptive parallel CRC check module adjusts the bit width of the input data according to the system bandwidth and obtains the check data through adaptive parallel CRC check, further comprising the following steps:

[0019] The adaptive parallel CRC check module also includes an error injection logic module;

[0020] The configuration register group module sends error injection logic control information to the error injection logic module so that the data that has passed the CRC check is injected with errors before the merged data is sent to the peer.

[0021] In some embodiments of the adaptive parallel CRC check retransmission method for interconnect chips according to the present invention, a data buffer queue of a specific depth is set inside the bit width adjustment module to buffer the input data, and data of the corresponding bit width is sequentially read from the data buffer queue according to the system bandwidth register information and output to the CRC check logic module.

[0022] In some embodiments of the method for adaptive parallel CRC check retransmission of interconnect chips according to the present invention, each of the plurality of CRC check generation modules uses the serial shift register method to derive the parallel CRC generation of the plurality of check sub-modules in each CRC check generation module to obtain the final CRC check value.

[0023] Another aspect of the present invention provides a system for adaptive parallel CRC check retransmission of interconnect chips, comprising:

[0024] A receiving and processing module, which is used to receive input data;

[0025] A data caching module is used to cache the input data;

[0026] An adaptive parallel CRC check module is used to adjust the bit width of the input data according to the system bandwidth and perform adaptive parallel CRC check to obtain check data.

[0027] A sending processing module, configured to merge the input data and the verification data into merged data and send it to the other end via the sending processing module; and

[0028] The retransmission detection module is used to retrieve the corresponding data from the corresponding data cache module and resend it to the adaptive parallel CRC check module for CRC check and retransmission when it receives the response data returned by the peer.

[0029] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission system according to the present invention, the adaptive parallel CRC check module includes a configuration register group module, a bit width adjustment module, and a CRC check logic module.

[0030] The configuration register group module is used to receive system configuration information and send system bandwidth register information to the bit width adjustment submodule and the CRC check logic submodule.

[0031] The bit width adjustment module is used to match and adjust the bit width of the input data according to the system bandwidth register information, and

[0032] The CRC check logic module is used to perform CRC check on the input data.

[0033] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission system according to the present invention, the CRC check logic module includes multiple CRC check generation modules for parallel CRC check of data with different bit widths, and

[0034] The CRC check logic module selects one of the multiple CRC check generation modules based on the system bandwidth register information to perform CRC check on the data output by the bit width adjustment module.

[0035] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission system according to the present invention, the adaptive parallel CRC check module further includes an error injection logic module, which injects errors into the data that has passed the CRC check before the merged data is sent to the peer, according to the error injection logic control information sent by the configuration register group module.

[0036] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission system according to the present invention, the bit width adjustment module is provided with a data buffer queue of a specific depth to buffer the input data, and data of the corresponding bit width is sequentially read from the data buffer queue according to the system bandwidth register information and output to the CRC check logic module.

[0037] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission system according to the present invention, each of the plurality of CRC check generation modules uses the serial shift register method to derive the parallel CRC generation of the plurality of check sub-modules in each CRC check generation module to obtain the final CRC check value.

[0038] In another aspect, the present invention provides a computer-readable storage medium storing computer program instructions that, when executed, implement the method for adaptive parallel CRC check retransmission of interconnect chips according to any of the above-described methods.

[0039] In another aspect, the present invention provides a computer device including a memory and a processor, the memory storing a computer program which, when executed by the processor, performs any of the above-described methods for adaptive parallel CRC check retransmission of interconnect chips according to the present invention.

[0040] The present invention has at least the following beneficial technical effects: The present invention proposes an adaptive parallel CRC check retransmission method for interconnect chips. When the system transmission bandwidth changes, it is not necessary to modify the check logic every time to adapt to the current bandwidth requirements of the system. Instead, the reliable transmission function of system data is guaranteed by adaptively adjusting the data bit width and performing parallel CRC check retransmission. This adaptive parallel CRC check method not only enhances the versatility, but also greatly improves the development efficiency and reduces the cost. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0042] In the diagram:

[0043] Figure 1 A schematic diagram of the adaptive parallel CRC check retransmission method for interconnect chips according to the present invention is shown;

[0044] Figure 2 A schematic block diagram of an embodiment of the bit width adjustment process in the method for adaptive parallel CRC check retransmission of interconnect chips according to the present invention is shown;

[0045] Figure 3 A schematic block diagram of an embodiment of the CRC check generation module in the method for adaptive parallel CRC check retransmission of interconnect chips according to the present invention is shown.

[0046] Figure 4 A schematic diagram illustrating the principle of CRC generation using the serial shift register method is shown in one embodiment of the adaptive parallel CRC check retransmission method for interconnect chips according to the present invention.

[0047] Figure 5 A schematic diagram illustrating the CRC generation principle of a 16-bit serial shift register method is shown in one embodiment of the adaptive parallel CRC check retransmission method for interconnect chips according to the present invention.

[0048] Figure 6 A schematic block diagram of an embodiment of an interconnect chip adaptive parallel CRC check retransmission system according to the present invention is shown;

[0049] Figure 7 A schematic block diagram is shown illustrating an embodiment of the system for adaptive parallel CRC check retransmission of interconnect chips according to the present invention applied to an interconnect chip system;

[0050] Figure 8 A schematic block diagram of an embodiment of an adaptive parallel CRC check module in an interconnect chip adaptive parallel CRC check retransmission system according to the present invention is shown.

[0051] Figure 9 A schematic diagram of an embodiment of a computer-readable storage medium for implementing an adaptive parallel CRC check retransmission method for interconnect chips according to the present invention is shown.

[0052] Figure 10 A schematic diagram of the hardware structure of an embodiment of a computer device for implementing an adaptive parallel CRC check retransmission method for interconnect chips according to the present invention is shown. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0054] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two different entities or different parameters with the same name. Therefore, "first" and "second" are merely for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as other steps or units inherent in a process, method, system, product, or device that includes a series of steps or units.

[0055] In short, this invention proposes an adaptive parallel CRC check retransmission mode for interconnect chips. By designing an adaptive parallel CRC check generation module inside the interconnect chip, the adaptive parallel CRC check module can adjust the bit width of the input data and perform adaptive parallel CRC check according to the system bandwidth. Then, the original input data and check data are merged and sent to the sending processing module to be sent to the peer to realize data interaction. The adaptive parallel CRC check module can also check the response data generated by the retransmission detection module and send it to the peer to realize the data retransmission function of the peer data buffer module, thereby ensuring the reliability of system data transmission.

[0056] Specifically, in a first aspect, the present invention provides a method 100 for adaptive parallel CRC check retransmission of interconnect chips. Figure 1 A schematic block diagram illustrating an embodiment of the interconnect chip adaptive parallel CRC check retransmission method according to the present invention is shown. Figure 1 In the illustrated embodiment, the method includes:

[0057] Step S110: In the chip architecture design, set up an adaptive parallel CRC check module, a data buffer module, a retransmission detection module, a transmission processing module, and a reception processing module;

[0058] Step S120: Input the data into the adaptive parallel CRC check module to adjust the bit width of the input data according to the system bandwidth and perform adaptive parallel CRC check to obtain the check data, and simultaneously input the data into the data buffer module for buffering;

[0059] Step S130: Merge the input data and the verification data into merged data and send it to the other end through the sending processing module;

[0060] Step S140: Upon receiving the response data returned by the other end, retrieve the corresponding data from the corresponding data cache module and resend it to the adaptive parallel CRC check module for CRC check and retransmission.

[0061] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission method 100 according to the present invention, step S120 includes the following steps:

[0062] Step S1201: Configure the configuration register group module, bit width adjustment module, and CRC check logic module in the adaptive parallel CRC check module;

[0063] Step S1202: Receive system configuration information through the configuration register group module, and send system bandwidth register information to the bit width adjustment submodule and the CRC check logic submodule;

[0064] Step S1203: The bit width adjustment module adjusts the bit width of the input data according to the system bandwidth register information;

[0065] Step S1204: Perform CRC verification on the input data through the CRC verification logic module.

[0066] The configuration register group module may include several control registers, such as the system bandwidth register for sending system bandwidth register information, and the error injection logic control register for sending error injection logic control information (described below). These registers can be configured by the system configuration module through a configuration interface to achieve functions such as system bandwidth adaptation and error injection logic enabling.

[0067] In some embodiments of the method 100 for adaptive parallel CRC check retransmission of interconnect chips according to the present invention, step S1204 specifically includes pre-setting multiple CRC check generation modules inside the CRC check logic module for parallel CRC check of data with different bit widths, and selecting one of the multiple CRC check generation modules to perform CRC check on the data output by the bit width adjustment module according to the system bandwidth register information.

[0068] According to the above embodiment of the interconnect chip adaptive parallel CRC check retransmission method 100 of the present invention, multiple parallel CRC check generation modules are preset to match and check data with different system bandwidths. The check generation method of each parallel CRC generation module is derived by the parallel conversion logic of the serial shift register. The CRC check of the current data with different bit widths can be completed within one clock cycle. The corresponding parallel CRC check generation module is adaptively selected by the configuration register to adapt to the current system bandwidth.

[0069] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission method 100 according to the present invention, step S120 further includes the following steps:

[0070] Step S1206: An error injection logic module is also set in the adaptive parallel CRC check module;

[0071] Step S1207: Send error injection logic control information to the error injection logic module through the configuration register group module, and inject errors into the data that has passed CRC verification before sending the merged data to the other end.

[0072] The error injection logic module is mainly responsible for injecting errors into the data after CRC verification before transmission. It can simulate errors that may occur during physical transmission during the design and simulation stage, thereby speeding up the debugging of the system's retransmission function. Its enable control signal comes from the system configuration. The error injection logic is implemented by inverting the corresponding bit data. The specific bit or bits of data to be injected are controlled by the system through the configuration register, which improves the development and debugging efficiency of the retransmission function.

[0073] In some embodiments of the method 100 for adaptive parallel CRC check retransmission of interconnect chips according to the present invention, in step S1203, a data buffer queue of a specific depth is set inside the bit width adjustment module to buffer the input data, and data of the corresponding bit width is sequentially read from the data buffer queue according to the system bandwidth register information and output to the CRC check logic module.

[0074] Figure 2 A schematic block diagram of an embodiment of the bit-width adjustment process in the adaptive parallel CRC check retransmission method for interconnect chips according to the present invention is shown. Figure 2 As shown, the bit width adjustment module internally employs a data buffer queue with a depth of m to buffer the input data. It obtains the current system bandwidth based on the information from the system bandwidth register, and then sequentially reads data of the corresponding bit width from the data buffer queue according to the system bandwidth information, outputting it to the subsequent CRC check logic module. Figure 2 Using half of the maximum system bandwidth, when the input is k bits (k is an even number), after being buffered by the data buffer queue and processed according to the principle of high-order data first, the output k / 2 bits of data are sent to the CRC check logic module.

[0075] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission method 100 according to the present invention, in step S1204, each of the plurality of CRC check generation modules uses the serial shift register method to derive the parallel CRC generation of the plurality of check sub-modules in each CRC check generation module to obtain the final CRC check value.

[0076] Figure 3 A schematic block diagram of an embodiment of the CRC check generation module in the adaptive parallel CRC check retransmission method for interconnect chips according to the present invention is shown. The CRC check logic module, as the core check logic, mainly selects the CRC check generation module corresponding to the current bit width based on the system bandwidth register information. A schematic diagram of each CRC check generation module is shown below. Figure 3As shown, the input data is fed into check submodules A and B respectively for parallel CRC generation, where check submodules A and B use different generator polynomials. The check data output from check submodule A is XORed with the data output from check submodule B after a one-clock delay to obtain the CRC check data at the current moment. The CRC check data at the current moment is merged and processed with the original input data and then output to the subsequent module. Simultaneously, the CRC check data at the current moment is delayed by one clock cycle and then fed into check submodules A and B for parallel CRC generation of the next data.

[0077] The parallel CRC generation of check submodule A and check submodule B can be achieved by... Figure 4 The serial shift register method shown is derived by having r one-bit registers R. i Serial input sequence and R r-1 After XORing, the values ​​are fed into the remaining registers and then XORed with the register of the previous stage to obtain the final result. Whether to perform XOR processing depends on the coefficients g of the current generator polynomial. i When g i The value of g is 1, which is then XORed and used as the new value of the current register. i If the value is 0, no XOR operation is performed; the value of the preceding register is directly received. This process is repeated r times the width of the current input data. The remaining r shift register values ​​are the final CRC checksum. The generator polynomial for a 16-bit CRC is 1 + x. 5 +x 12 +x 16 For example, that is Figure 4 Only g0, g5, and g are present. 12 The value of g is 1, and the rest are g i The value is 0, as shown in the diagram. Figure 5 As shown, when the input bit width is 176 bits, the 176 bits of data need to be serially shifted 176 times with the most significant bits first to obtain the CRC value equivalent to a single parallel input of 176 bits. This is combined with... Figure 5 The principle is that the value of each register after 176 shifts can be obtained using an iterative method. Taking R0 as an example, the derivation process is shown in the following formula.

[0078]

[0079] in This represents the value of R0 after shifting by 176. , , , , , , , This indicates the value of the corresponding bit register in the CRC register obtained from the previous data input of the current 176-bit data. This indicates the value of the corresponding bit in the input data. The values ​​of the other register bits can be derived similarly. Thus, the CRC check operation logic for inputting 176 bits of data in parallel at one time can be obtained. The input data bit width varies under different bandwidths, but the derivation logic principle is the same.

[0080] The following describes an application example of an adaptive parallel CRC check retransmission method for interconnect chips according to the present invention. It should be noted that the numbers mentioned in this embodiment are merely examples. In practice, these values ​​can be set and changed according to actual needs.

[0081] (1) Assume that the default system bandwidth is set to the maximum value during power-on initialization, and the input data is set to 352 bits, corresponding to 16 transmission channels in the physical layer. At this time, the CRC uses 32-bit check logic, and the corresponding 32-bit parallel CRC check generation module is selected according to the system bandwidth register to check the input data. The 352-bit original data and the 32-bit CRC check data are combined into 384 bits and sent to the transmission processing module for processing. After processing, the data is transmitted to the other end through 16 physical channels.

[0082] (2) If the system bandwidth register is configured to reduce the system bandwidth to half, the 352-bit input data is converted into 176-bit data by the bit width adjustment module. At this time, the CRC uses 16-bit check logic. The corresponding 16-bit parallel CRC check generation module is selected according to the system bandwidth register to check the input data. The 176-bit original data and the 16-bit CRC check data are combined into 192 bits and sent to the transmission processing module for processing. After processing, the data is transmitted to the other end through 8 physical channels. At this time, the other 8 physical transmission channels can be turned off to reduce power consumption.

[0083] (3) When the system bandwidth is adjusted again, the current bandwidth is obtained through the system bandwidth register, the input data is adjusted through the bit width adjustment module, the corresponding CRC parallel verification module is selected to verify the data, and then the data is sent to the other end through the corresponding physical channel.

[0084] (4) When the error injection logic module enable control signal is valid (the configuration register group module sends the error injection logic control information), the data after CRC verification is first processed for error injection, and then the data is sent to the other end through the physical channel.

[0085] (5) After receiving the data, the other end first performs reception processing and retransmission detection. If the data is found to be incorrect by performing CRC check on the received data, it will send the response data back to the sending end.

[0086] (6) After receiving the response data packet, the sending end learns of the transmission error, retrieves the corresponding data from the corresponding data cache module and retransmits it, thereby ensuring the reliability of the entire data link.

[0087] The adaptive parallel CRC check retransmission method for interconnect chips according to the present invention obtains the current system bandwidth through configuration registers and adjusts the data bit width accordingly before performing adaptive parallel CRC check retransmission to ensure reliable data transmission. Furthermore, the addition of error injection logic accelerates the debugging and development of the retransmission function. This method avoids the need to redesign the system architecture and recode the check logic to adapt to changes in system bandwidth when requirements change, thus enhancing versatility, significantly improving development efficiency, and reducing costs.

[0088] A second aspect of the present invention also provides a system 20 for adaptive parallel CRC check retransmission of interconnect chips. Figure 6 A schematic block diagram of an embodiment of a system 20 for adaptive parallel CRC check retransmission of interconnect chips according to the present invention is shown. Figure 6 As shown, the system includes:

[0089] The receiving and processing module 21 is used to receive input data;

[0090] Data caching module 22, which is used to cache input data;

[0091] Adaptive parallel CRC check module 23 is used to adjust the bit width of the input data according to the system bandwidth and obtain check data through adaptive parallel CRC check.

[0092] Sending processing module 24, which is used to merge the input data and the verification data into merged data and send it to the other end; and

[0093] The retransmission detection module 25 is used to retrieve the corresponding data from the corresponding data buffer module and resend it to the adaptive parallel CRC check module 23 for CRC check and retransmission when it receives the response data returned by the peer.

[0094] Specifically, the adaptive parallel CRC check module 23 can receive input data and is connected to the data buffer module 22. The data buffer module 22 can re-send the buffered data into the adaptive parallel CRC check module 23 for CRC check based on the retransmission information generated by the retransmission detection module 25 and then send it to the peer. At the same time, the response data generated by the retransmission detection module 25 is also sent into the adaptive parallel CRC check module 23 for CRC check and then sent to the peer. This enables the retransmission function of the peer data link.

[0095] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission system 200 according to the present invention, the adaptive parallel CRC check module 23 includes a configuration register group module 231, a bit width adjustment module 232, and a CRC check logic module 233. The configuration register group module 231 receives system configuration information and sends system bandwidth register information to the bit width adjustment submodule and the CRC check logic submodule. The bit width adjustment module 232 adjusts the bit width of the input data according to the system bandwidth register information. The CRC check logic module 233 performs CRC check on the input data.

[0096] Specifically, the CRC check logic module can internally pre-set n (n is a natural number greater than 1) CRC check generation modules, which can realize the parallel CRC check function of data with different bit widths, and configure the MUX according to the register information to select one as the final CRC check module to check the data output by the bit width adjustment module.

[0097] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission system 200 according to the present invention, the CRC check logic module 233 includes multiple CRC check generation modules for parallel CRC check of data with different bit widths, and the CRC check logic module 233 selects one of the multiple CRC check generation modules to perform CRC check on the data output by the bit width adjustment module 232 according to the system bandwidth register information.

[0098] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission system 200 according to the present invention, the adaptive parallel CRC check module 23 further includes an error injection logic module 234, which injects errors into the data that has passed the CRC check before sending the merged data to the other end according to the error injection logic control information sent by the configuration register group module 231.

[0099] The error injection logic module 234 determines whether to enable error injection of the CRC-verified data based on the enable control signal (error injection logic control information sent by the configuration register group module 231), thereby accelerating the simulation verification of the retransmission function.

[0100] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission system 200 according to the present invention, the bit width adjustment module 232 internally sets a data buffer queue of a specific depth to buffer the input data, and sequentially reads data of the corresponding bit width from the data buffer queue according to the system bandwidth register information and outputs it to the CRC check logic module 233.

[0101] In some embodiments of the interconnect chip adaptive parallel CRC check retransmission system 200 according to the present invention, each of the multiple CRC check generation modules uses the serial shift register method to derive the parallel CRC generation of multiple check sub-modules in each CRC check generation module to obtain the final CRC check value.

[0102] A third aspect of the present invention also provides a computer-readable storage medium. Figure 9 A schematic diagram of a computer-readable storage medium illustrating an adaptive parallel CRC check retransmission method for interconnect chips according to an embodiment of the present invention is shown. Figure 9 As shown, the computer-readable storage medium 300 stores computer program instructions 310, which can be executed by a processor. When executed, the computer program instructions 310 implement the method of any of the above embodiments.

[0103] It should be understood that, without conflict, all the embodiments, features and advantages described above for the method of adaptive parallel CRC check retransmission of interconnect chips according to the present invention are equally applicable to the system and storage medium of adaptive parallel CRC check retransmission of interconnect chips according to the present invention.

[0104] A fourth aspect of the present invention also provides a computer device 400, including a memory 420 and a processor 410, wherein the memory stores a computer program, which, when executed by the processor, implements the method of any of the above embodiments.

[0105] like Figure 10 The diagram shown is a hardware structure schematic of an embodiment of a computer device for implementing the method of adaptive parallel CRC check retransmission of interconnect chips provided by the present invention. Figure 10 Taking the computer device 400 shown as an example, this computer device includes a processor 410 and a memory 420, and may also include an input device 430 and an output device 440. The processor 410, memory 420, input device 430, and output device 440 can be connected via a bus or other means. Figure 10 Taking a bus connection as an example, input device 430 can receive input digital or character information, and generate signal inputs related to the adaptive parallel CRC check retransmission of the interconnect chip. Output device 440 may include display devices such as a display screen.

[0106] Memory 420, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the resource monitoring method in this embodiment. Memory 420 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created by the use of the resource monitoring method, etc. In addition, memory 420 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 420 may optionally include memory remotely located relative to processor 410, and these remote memories can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0107] The processor 410 executes various server functions and data processing by running non-volatile software programs, instructions, and modules stored in the memory 420, thereby implementing the resource monitoring method of the above method embodiment.

[0108] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0109] Finally, it should be noted that the computer-readable storage medium (e.g., memory) described herein can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which can act as external cache memory. By way of example, and not limitation, RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices disclosed herein are intended to include, but are not limited to, these and other suitable types of memory.

[0110] The various exemplary logic blocks, modules, and circuits described herein can be implemented or performed using the following components designed to perform the functions herein: general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP, and / or any other such configuration.

[0111] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0112] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0113] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for adaptive parallel CRC check retransmission in interconnect chips, characterized in that, Includes the following steps: The chip architecture design includes an adaptive parallel CRC check module, a data buffer module, a retransmission detection module, a transmission processing module, and a reception processing module. The data is input into the adaptive parallel CRC check module to adjust the bit width of the input data according to the system bandwidth and perform adaptive parallel CRC check to obtain check data, and is simultaneously input into the data cache module for caching; The input data and the verification data are merged into merged data and sent to the other end through the sending processing module; as well as Upon receiving the response data returned by the peer, the corresponding data is retrieved from the corresponding data cache module and retransmitted into the adaptive parallel CRC check module for CRC check and retransmission; The adaptive parallel CRC check module includes a CRC check logic module, comprising check submodules A and B for selecting different generator polynomials. The check data output from check submodule A is XORed with the check data output from check submodule B after a one-beat delay to obtain the current CRC check data. This current CRC check data is then merged with the currently input data and output to the next stage module. The current CRC check data is then delayed by one beat and fed back into check submodules A and B for the parallel CRC generation of the next data. The parallel CRC generation of check submodules A and B can be derived using the serial shift register method, where there are r one-bit registers R. i Serial input sequence and R r The XORed values ​​are then fed into the remaining registers and XORed with the registers of the previous level to obtain the result. The CRC check logic module includes multiple CRC check generation modules for parallel CRC check of data with different bit widths.

2. The method according to claim 1, characterized in that, The adaptive parallel CRC check module adjusts the bit width of the input data according to the system bandwidth and performs adaptive parallel CRC check to obtain the check data, including the following steps: The adaptive parallel CRC check module includes a configuration register group module and a bit width adjustment module. The system configuration information is received through the configuration register group module, and the system bandwidth register information is sent to the bit width adjustment module and the CRC check logic module. The bit width adjustment module adjusts the bit width of the input data according to the system bandwidth register information. The input data is subjected to CRC verification by the CRC verification logic module.

3. The method according to claim 2, characterized in that, Based on the system bandwidth register information, one of the multiple CRC check generation modules is selected to perform CRC check on the data output by the bit width adjustment module.

4. The method according to claim 2, characterized in that, The adaptive parallel CRC check module, which adjusts the bit width of the input data according to the system bandwidth and performs adaptive parallel CRC check to obtain the check data, also includes the following steps: The adaptive parallel CRC check module also includes an error injection logic module; The configuration register group module sends error injection logic control information to the error injection logic module, and the data that has passed the CRC check is injected with errors before the merged data is sent to the peer.

5. The method according to claim 2, characterized in that, A data buffer queue of a specific depth is set up inside the bit width adjustment module to buffer the input data. According to the system bandwidth register information, data of the corresponding bit width is read from the data buffer queue and output to the CRC check logic module.

6. The method according to claim 2, characterized in that, Each of the multiple CRC check generation modules uses the serial shift register method to derive the parallel CRC generation of multiple check sub-modules in each CRC check generation module, so as to obtain the final CRC check value.

7. A system for adaptive parallel CRC check retransmission of interconnect chips, characterized in that, include: A receiving and processing module, which is used to receive input data; A data caching module is used to cache the input data; An adaptive parallel CRC check module is used to adjust the bit width of the input data according to the system bandwidth and perform adaptive parallel CRC check to obtain check data. A sending processing module is used to merge the input data and the verification data into merged data and send it to the other end through the sending processing module. as well as A retransmission detection module is used to retrieve the corresponding data from the corresponding data cache module and resend it to the adaptive parallel CRC check module for CRC check and retransmission when the response data returned by the peer is received. The adaptive parallel CRC check module includes a CRC check logic module, comprising check submodules A and B for selecting different generator polynomials. The check data output from check submodule A is XORed with the check data output from check submodule B after a one-beat delay to obtain the current CRC check data. This current CRC check data is then merged with the input data and output to the next stage module. The current CRC check data is then delayed by one beat and fed back into check submodules A and B for the generation of the parallel CRC for the next data. The parallel CRC generation of check submodules A and B can be derived using the serial shift register method, where there are r one-bit registers R. i Serial input sequence and R r The XORed values ​​are then fed into the remaining registers and XORed with the registers of the previous level to obtain the result. The CRC check logic module includes multiple CRC check generation modules for parallel CRC check of data with different bit widths.

8. The system according to claim 7, characterized in that, The adaptive parallel CRC check module includes a configuration register group module and a bit width adjustment module. The configuration register group module is used to receive system configuration information and send system bandwidth register information to the bit width adjustment module and the CRC check logic module. The bit width adjustment module is used to match and adjust the bit width of the input data according to the system bandwidth register information, and The CRC check logic module is used to perform CRC check on the input data.

9. The system according to claim 8, characterized in that, The CRC check logic module selects one of the multiple CRC check generation modules based on the system bandwidth register information to perform CRC check on the data output by the bit width adjustment module.

10. The system according to claim 8, characterized in that, The adaptive parallel CRC check module also includes an error injection logic module. The error injection logic module injects errors into the data that has passed the CRC check before the merged data is sent to the peer, based on the error injection logic control information sent by the configuration register group module.

11. The system according to claim 8, characterized in that, The bit width adjustment module has a data buffer queue of a specific depth to buffer the input data. According to the system bandwidth register information, it reads data of the corresponding bit width from the data buffer queue and outputs it to the CRC check logic module.

12. The system according to claim 8, characterized in that, Each of the multiple CRC check generation modules uses the serial shift register method to derive the parallel CRC generation of multiple check sub-modules in each CRC check generation module, so as to obtain the final CRC check value.

13. A computer-readable storage medium, characterized in that, The device stores computer program instructions, which, when executed, implement the method for adaptive parallel CRC check retransmission of interconnect chips as described in any one of claims 1-6.

14. A computer device comprising a memory and a processor, characterized in that, The memory stores a computer program, which, when executed by the processor, performs the method for adaptive parallel CRC check retransmission of interconnect chips as described in any one of claims 1-6.

Images