Semiconductor test structure and method for preparing the same

Abstract

The present invention discloses a semiconductor test structure and a method for preparing the same. The semiconductor test structure includes: a first test module, the first test module includes at least one first sub-test module extending along a first direction, and the first sub-test module includes a plurality of first test units formed on a semiconductor substrate; the plurality of first test units are arranged at intervals along the first direction, and the critical dimensions of the plurality of first test units gradually change along the first direction, so as to test different process windows of a semiconductor device in the first direction. The present invention can test different process windows of a semiconductor device, so as to select a suitable critical dimension applicable to a target film layer and / or a target structure to optimize the process window, and then apply the optimized process window to a corresponding semiconductor device manufacturing process, so as to effectively improve the preparation yield of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and particularly to a semiconductor test structure and a preparation method thereof. Background Art

[0002] With the continuous development of integrated circuit technology, in order to improve circuit integration and speed, multi-layer metal wiring is mostly used in the metal layers of large-scale integrated circuits. Multi-layer metallization generates the need to fill contact holes (CTs) with metal to form electrical paths between metal layers. During the wafer production process, due to the continuous upgrade of technology nodes and the gradual reduction of product process dimensions, the requirements for the etching process window of contact holes are getting higher and higher.

[0003] Static random access memory (SRAM) is widely used due to its low-voltage operation and high speed. To ensure that SRAM can obtain the maximum capacity, the smallest size allowed by the design rule is used in the new technology nodes. Among them, the SRAM with six transistors T1 to T6 as a storage unit is the most common, as Figure 1 shown. The six transistors T1 to T6 are connected to the corresponding bit lines BL, complementary bit lines BLB, and word line WL.

[0004] In the 6T-SRAM layout, shared contact holes (Share CT) are widely used due to their small occupied area. As Figure 2 shown, in the 6T-SRAM layout, the shared contact hole 23 falls on the active area (AA) 21 and the gate (Gate) 22, and a contact hole (CT) 24 is also provided on the active area 21. Since the shared contact hole has a large critical dimension (CD) in the manufacturing process, it will cause excessive consumption of metal silicide during the etching process, increasing the contact resistance. At the same time, since the shared contact hole falls on different regions during the etching process, its etching will also affect the sidewall gate structure topography.

[0005] Therefore, how to effectively detect the over-etching amount of metal silicide in the hole structure etching and the influence of shared contact holes with different critical dimensions on the gate sidewall topography is an urgent problem to be solved at present. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a semiconductor test structure and a preparation method thereof to effectively detect the over-etching amount of metal silicide in the hole structure etching and the influence of shared contact holes with different critical dimensions on the gate sidewall topography.

[0007] To solve the above problems, an embodiment of the present invention provides a semiconductor test structure, including: a first test module, the first test module includes at least one first sub-test module extending along a first direction, and the first sub-test module includes a plurality of first test units formed on a semiconductor substrate; a plurality of the first test units are arranged at intervals along the first direction, and critical dimensions of the plurality of first test units gradually change along the first direction, so as to test different process windows of a semiconductor device in the first direction.

[0008] In some embodiments, the critical dimensions gradually increase in an arithmetic or geometric progression along the first direction.

[0009] In some embodiments, the first test module includes a plurality of first sub-test modules extending along the first direction and arranged at intervals along a second direction, and the plurality of first sub-test modules are arranged in the same manner; wherein, the second direction is perpendicular to the first direction.

[0010] To solve the above problems, an embodiment of the present invention further provides a method for manufacturing a semiconductor test structure, including: providing a semiconductor substrate; forming a plurality of first test units arranged at intervals along the first direction on the semiconductor substrate, so as to form a first test module including at least one first sub-test module extending along the first direction, and critical dimensions of the plurality of first test units gradually change along the first direction, so as to test different process windows of a semiconductor device in the first direction.

[0011] In some embodiments, the method further includes: forming a plurality of second test units arranged at intervals along the second direction on the semiconductor substrate, so as to form a second test module including at least one second sub-test module extending along the second direction, and critical dimensions of the plurality of second test units gradually change along the second direction, so as to test different process windows of a semiconductor device in the second direction; wherein, the second test module is adjacent to the first test module, and the second direction is perpendicular to the first direction.

[0012] The present invention improves the semiconductor test structure by arranging test units with gradually changing critical dimensions in a certain direction to test different process windows of a semiconductor device in this direction, so as to effectively detect the over-etching amount of metal silicide in the hole structure etching and the influence of shared contact holes with different critical dimensions on the sidewall topography of the gate, thereby selecting a suitable critical dimension applicable to the target film layer and / or target structure to optimize the process window, and then applying the optimized process window to the corresponding semiconductor device manufacturing process to effectively improve the manufacturing yield of the semiconductor device. Further, by arranging test units with gradually changing critical dimensions in different directions respectively, different process windows of a semiconductor device are tested in different directions. Brief Description of the Drawings

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0014] Figure 1 Schematic circuit diagram of an embodiment of 6T-SRAM;

[0015] Figure 2 Layout layout of an embodiment of 6T-SRAM;

[0016] Figure 3 Schematic structural diagram of a semiconductor test structure provided by an embodiment of the present invention;

[0017] Figure 4 Top view of a semiconductor test structure provided by an embodiment of the present invention;

[0018] Figure 5 Cross-sectional view of a semiconductor test structure provided by an embodiment of the present invention;

[0019] Figure 6 Schematic diagram of the steps of a method for manufacturing a semiconductor test structure provided by an embodiment of the present invention. Detailed Description of the Embodiments

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present invention.

[0021] To clearly illustrate the present invention, the following gives the definitions of some technical terms in the present invention.

[0022] Contact hole (CT): An opening in the insulating layer between the first metal layer and the active region or polysilicon, used to form a contact between the first metal layer and the active region or polysilicon.

[0023] Shared contact hole (Share CT): A type of contact hole that serves as a common contact hole for two or more components (such as a gate and a source or a gate and a drain) at the same time.

[0024] Via (VIA): An opening in the insulating layer between metal layers, used to connect the corresponding metal layers.

[0025] Critical Dimension (CD): It refers to the width of a pattern or the width of a characteristic line obtained under a specific exposure intensity threshold / under specific etching conditions. The minimum feature size on a silicon wafer is also called the critical dimension or the feature size.

[0026] Surface protection layer (Spacer): It can protect the sidewalls of the gate, preventing damage to the sidewalls of the gate during the semiconductor structure formation process and extending the service life of the gate sidewalls. The Spacer process is a self-aligned dual imaging technology that uses micro-optical nanotechnology.

[0027] An embodiment of the present invention provides a semiconductor test structure, which can be used to test the process window of semiconductor devices such as SRAM and DRAM, and then optimize the process window of semiconductor devices according to the test results.

[0028] Please refer to Figures 3 to 5 , wherein, Figure 3 is a schematic structural diagram of the semiconductor test structure provided by an embodiment of the present invention, Figure 4 is a top view of the semiconductor test structure provided by an embodiment of the present invention, Figure 5 is a cross-sectional view of the semiconductor test structure provided by an embodiment of the present invention. For ease of explanation, in the following embodiments, the first direction is the X-axis direction in the Cartesian coordinate system, the second direction is the Y-axis direction in the Cartesian coordinate system, and the third direction is the Z-axis direction in the Cartesian coordinate system.

[0029] As Figure 3 shown, the semiconductor test structure 30 described in this embodiment includes: a first test module 31, and the first test module 31 includes at least one first sub-test module 311 extending along the first direction X. The first sub-test module 311 includes a plurality of first test units 3111 formed on a semiconductor substrate 301; the plurality of first test units 3111 are arranged at intervals along the first direction X, and the critical dimensions CD (shown in Figure 4 ) of the plurality of first test units 3111 gradually change along the first direction X to be used for testing different process windows of semiconductor devices in the first direction X. The intervals of the plurality of first test units 3111 along the first direction X can be the same to facilitate the implementation of the manufacturing process.

[0030] Specifically, the loss of the target film layer (such as a metal silicide layer) and / or the morphology of the target structure (such as a gate structure) under corresponding critical dimensions can be detected through failure analysis, so as to select appropriate critical dimensions applicable to the target film layer and / or the target structure to optimize the process window. Then, the optimized process window is applied to the corresponding semiconductor device manufacturing process, which can effectively improve the manufacturing yield of semiconductor devices. The failure analysis can specifically be to detect and analyze each first test unit of each first sub-test module by using electrical tests and physical, metallographic, and chemical analysis techniques. For example, the film layer of each first sub-test module can be sliced along the first direction X to detect the loss of the target film layer and / or the morphology of the target structure.

[0031] As Figure 4 shown, in this embodiment, the critical dimension CD gradually increases in an arithmetic or geometric sequence along the first direction X. For example, the critical dimension CD gradually increases at a ratio of 5% along the first direction X, CD1 < CD2 <... < CDn. By gradually changing the critical dimension CD, the change in the loss of the target film layer and / or the change in the morphology of the target structure caused by different critical dimensions CD can be effectively tested. For the convenience of illustrating the improvement points of the present invention, only the relative position relationship between the shared contact hole 41 with gradually changing critical dimension CD, the gate 42, and the semiconductor substrate 301 is shown in the figure, and the illustration of other related film layers / components is omitted.

[0032] As Figure 5 shown, in this embodiment, each of the first test units 3111 includes: a plurality of first grooves 51, a first film layer to be tested 52, a plurality of first gate structures 53, a second film layer to be tested 54, and a plurality of first hole structures 55.

[0033] Specifically, a plurality of first grooves 51 are formed in the active region of the semiconductor substrate 301 and are arranged at intervals along the first direction X. A first film layer to be tested 52 is formed in the first grooves 51. A plurality of first gate structures 53 are formed on the semiconductor substrate 301 and are arranged at intervals along the first direction X. Among them, each first gate structure 53 is disposed adjacent to a first film layer to be tested 52 (specifically, on the side away from the surface spacer, the first film layer to be tested 52 is disposed adjacent to the first gate structure 53). A second film layer to be tested 54 is formed on the surface of the first gate structure 53 away from the semiconductor substrate 301. A plurality of first hole structures 55 are formed by etching corresponding regions of the first film layer to be tested 52 and the second film layer to be tested 54 by using a critical dimension CD that gradually changes along the first direction X. The plurality of first hole structures 55 are arranged at intervals along the first direction X, and each first hole structure 55 is disposed adjacent to a first gate structure 53 (specifically, on the side away from the surface spacer, the first hole structure 55 is disposed adjacent to the first gate structure 53). Among them, according to the critical dimension CD of each first hole structure 55 in the first sub-test module 311, and the loss amounts of the first film layer to be tested 52 and the second film layer to be tested 54, the process window test result of the semiconductor device in the first direction X is obtained.

[0034] In some embodiments, the first hole structure 55 is selected from any one of a shared contact hole (Share CT), a contact hole (CT), or a via (VIA); the materials of the first film layer to be tested 52 and the second film layer to be tested 54 are both salicide. By failure analysis, the loss amount of the first film layer to be tested 52 corresponding to the first hole structure 55 with the corresponding critical dimension in the active region, the loss amount of the second film layer to be tested 54 in the corresponding region of the first gate structure 53, and the morphology of the first gate structure 53 are detected, and the process window test result of the semiconductor device in the first direction X is obtained.

[0035] Figure 5 The illustrated embodiment shows that different shared contact hole CDs result in changes in the remaining amount of salicide. Specifically, in the figure, Y1 to Yn are used to indicate the remaining amount of salicide in the first film layer to be tested 52, and X1 to Xn are used to indicate the remaining amount of salicide in the second film layer to be tested 54. The first gate structure 53 includes a gate oxide layer (Gate OX) 531, a gate (Gate) 532, and a surface spacer (Spacer) 533 stacked in sequence. The material of the gate 532 can specifically be polysilicon (PolySilicon). Specifically, by failure analysis, the loss amounts of salicide in the active region and the corresponding region of the gate structure, and the morphology of the gate structure are detected. From Figure 5As can be seen from the cross-sectional view shown, in the first direction X, as the shared contact holes CD gradually increase (CD1 < CD2 <... < CDn), the loss of metal silicide gradually increases (Y1 < Y2 <... < Yn, X1 < X2 <... < Xn).

[0036] It can be seen from Figure 5 the cross-sectional view shown that the etch safety window (Window) of the hole structure (contact hole / shared contact hole / through hole) is about 30% for over-etch (OE). When the critical dimension of the hole structure is small, resulting in a small OE (e.g., < 30%), due to insufficient over-etching, the loss of metal silicide is too small, which may lead to poor contact, such as Figure 5 the first test unit 3111 shown in the leftmost one in Figure 5 . When the critical dimension of the hole structure is large, resulting in a large OE (e.g., > 50%), due to excessive over-etching, the loss of metal silicide is too much, which may lead to an increase in contact resistance, such as

[0037] Please continue to refer to Figure 3 , in this embodiment, the first test module 31 includes a plurality of first sub-test modules 311 arranged at intervals along the second direction Y and extending along the first direction X. The settings of the plurality of first sub-test modules 311 are the same (specific reference Figures 4 to 5 shown). Among them, the second direction Y is perpendicular to the first direction X. That is, in this embodiment, a plurality of identical first sub-test modules 311 can be arranged in the second direction Y of the first test module 31. By statistically analyzing the test results of the plurality of identical first sub-test modules 311, the distribution of the process window test results of the semiconductor device in the first direction X can be obtained, improving the accuracy of the test results, and thus providing a more optimized process window. The intervals of the plurality of first sub-test modules 311 along the second direction Y can be the same to facilitate the implementation of the manufacturing process.

[0038] Please continue to refer to Figure 3, in this embodiment, the semiconductor test structure 30 further includes a second test module 32. The second test module 32 includes at least one second sub-test module 321 extending along the second direction Y. The second sub-test module 321 includes a plurality of second test units 3211 formed on the semiconductor substrate 301. The plurality of second test units 3211 are arranged at intervals along the second direction Y, and the critical dimensions CD of the plurality of second test units 3211 gradually change along the second direction Y, so as to test different process windows of the semiconductor device in the second direction Y. Wherein, the second test module 32 is adjacent to the first test module 31, and the second direction Y is perpendicular to the first direction X. The intervals of the plurality of second test units 3211 along the second direction Y can be the same, which is convenient for the implementation of the manufacturing process. There may be an interval between the second test module 32 and the first test module 31.

[0039] In some embodiments, the arrangement of the second sub-test module 321 is the same as that of the first sub-test module 311 (specific reference Figures 4 to 5 as shown); by providing the first test module 31 and the second test module 32, different process windows of the semiconductor device can be tested simultaneously in the first direction X and the second direction Y, so as to select a suitable critical dimension applicable to the target film layer and / or the target structure to optimize the process window, and then apply the optimized process window to the corresponding semiconductor device manufacturing process to effectively improve the manufacturing yield of the semiconductor device. Specifically, each second test unit of each second sub-test module can be detected and analyzed by using electrical tests and physical, metallographic and chemical analysis techniques, etc. For example, the film layer of each second sub-test module can be sliced along the second direction Y to detect the loss amount of the target film layer and / or the morphology of the target structure.

[0040] Please continue to refer to Figure 3 , in this embodiment, the second test module 32 includes a plurality of second sub-test modules 321 extending along the second direction Y and arranged at intervals along the first direction X. The arrangements of the plurality of second sub-test modules 321 are the same and are all the same as the arrangement of the first sub-test module 311. That is to say, in this embodiment, a plurality of identical second sub-test modules 321 can be provided in the first direction X of the second test module 32. By statistically analyzing the test results of the plurality of identical second sub-test modules 321, the distribution of the test results of the process window of the semiconductor device in the second direction Y can be obtained, the accuracy of the test results can be improved, and a more optimized process window can be provided. The intervals of the plurality of second sub-test modules 321 along the first direction X can be the same, which is convenient for the implementation of the manufacturing process.

[0041] Please continue to refer to Figure 3, in this embodiment, the semiconductor test structure 30 further includes a third test module 33 and a fourth test module 34. The third test module 33 is disposed diagonally to the first test module 31 and adjacent to the second test module 32. Among them, the setting of the third test module 33 is the same as that of the first test module 31. The fourth test module 34 is disposed diagonally to the second test module 32 and adjacent to the first test module 31 and the third test module 33. Among them, the setting of the fourth test module 34 is the same as that of the second test module 32. There may be a gap between each test module. By diagonally arranging two test modules in the same direction, different process windows of semiconductor devices in this direction can be tested more comprehensively; by diagonally arranging two identical test modules, the test results of the two identical test modules can be verified with each other to optimize the test results more.

[0042] As a specific implementation manner, the semiconductor test structure can be used to test the process windows of semiconductor devices such as SRAM and DRAM, and then optimize the process windows of semiconductor devices according to the test results.

[0043] Based on the same inventive concept, the present invention also provides a preparation method of a semiconductor test structure for preparing the semiconductor test structure of the present invention for testing different process windows of semiconductor devices in a corresponding direction.

[0044] Please refer to Figure 6 , which is a schematic diagram of the steps of a preparation method of a semiconductor test structure provided by an embodiment of the present invention. As Figure 6 shown, in this embodiment, the method includes the following steps: S1. Provide a semiconductor substrate; S2. Form a plurality of first test units arranged at intervals along the first direction on the semiconductor substrate, thereby forming a first test module including at least one first sub-test module extending along the first direction. The critical dimensions of the plurality of first test units gradually change along the first direction for testing different process windows of semiconductor devices in the first direction.

[0045] In some embodiments, the critical dimension CD gradually increases in an arithmetic or geometric progression along the first direction X. For example, the critical dimension CD gradually increases at a ratio of 5% along the first direction X, CD1 < CD2 <... < CDn, as Figure 4 shown. By gradually changing the critical dimension CD, it is possible to effectively test the change in the loss amount of the target film layer and / or the change in the morphology of the target structure caused by different critical dimensions CD.

[0046] In some embodiments, the step of forming, on the semiconductor substrate, a plurality of first test units arranged at intervals along the first direction in step S2 further includes: 1) forming a plurality of first grooves arranged at intervals along the first direction in the active region of the semiconductor substrate; 2) forming a first film layer to be tested in each of the first grooves; 3) forming a plurality of first gate structures arranged at intervals along the first direction on the semiconductor substrate, wherein each gate structure is disposed adjacent to a corresponding first film layer to be tested; 4) forming a second film layer to be tested on the surface of each first gate structure away from the semiconductor substrate; 5) etching corresponding regions of the first film layer to be tested and the second film layer to be tested with a critical dimension that gradually changes along the first direction to form a plurality of first hole structures arranged at intervals along the first direction. A cross-sectional view of the formed first sub-test module is shown in Figure 5 as shown.

[0047] In some embodiments, the first hole structure 55 is selected from any one of a shared contact hole, a contact hole, or a via hole; the materials of the first film layer 52 to be tested and the second film layer 54 to be tested are both metal silicide. By performing failure analysis to detect the loss amount of the first film layer 52 to be tested corresponding to the first hole structure 55 with a corresponding critical dimension in the active region, the loss amount of the second film layer 54 to be tested in the region corresponding to the first gate structure 53, and the morphology of the first gate structure 53, the process window test result of the semiconductor device in the first direction X can be obtained.

[0048] In some embodiments, the step of forming the first test module including at least one first sub-test module extending along the first direction in step S2 further includes: forming a plurality of first sub-test modules 311 extending along the first direction X and arranged at intervals along the second direction Y on the semiconductor substrate; the plurality of first sub-test modules 311 are arranged in the same manner. By statistically analyzing the test results of the plurality of identical first sub-test modules 311, the distribution of the process window test results of the semiconductor device in the first direction X can be obtained, the accuracy of the test results can be improved, and thus a more optimized process window can be provided. The intervals of the plurality of first sub-test modules 311 along the second direction Y can be the same to facilitate the implementation of the manufacturing process.

[0049] In some embodiments, the method further includes: S3. Forming a plurality of second test units spaced along the second direction on the semiconductor substrate, thereby forming a second test module including at least one second sub-test module extending along the second direction. The critical dimensions of the plurality of second test units gradually change along the second direction for testing different process windows of the semiconductor device in the second direction; wherein the second test module is adjacent to the first test module, and the second direction is perpendicular to the first direction. The intervals of the plurality of second test units 3211 along the second direction Y may be the same to facilitate the implementation of the manufacturing process.

[0050] In some embodiments, the setting of the second sub-test module 321 is the same as that of the first sub-test module 311 (specific reference Figures 4 to 5 as shown); by providing the first test module 31 and the second test module 32, different process windows of the semiconductor device can be tested simultaneously in the first direction X and the second direction Y, so as to select a suitable critical dimension applicable to the target film layer and / or target structure to optimize the process window, and then apply the optimized process window to the corresponding semiconductor device manufacturing process to effectively improve the manufacturing yield of the semiconductor device.

[0051] In some embodiments, the step of forming the second test module including at least one second sub-test module extending along the second direction in step S3 further includes: forming a plurality of second sub-test modules 321 extending along the second direction Y and spaced along the first direction X on the semiconductor substrate. The settings of the plurality of second sub-test modules 321 are the same and are all the same as the setting of the first sub-test module 311. That is, in this embodiment, a plurality of identical second sub-test modules 321 can be provided in the first direction X of the second test module 32. By statistically analyzing the test results of the plurality of identical second sub-test modules 321, the distribution of the process window test results of the semiconductor device in the second direction Y can be obtained, the accuracy of the test results can be improved, and then a more optimized process window can be provided. The intervals of the plurality of second sub-test modules 321 along the first direction X may be the same to facilitate the implementation of the manufacturing process.

[0052] In some embodiments, the method further includes: S4. Forming a third test module 33 and a fourth test module 34, where the third test module 33 is disposed diagonally with respect to the first test module 31 and adjacent to the second test module 32, and the fourth test module 34 is disposed diagonally with respect to the second test module 32 and adjacent to the first test module 31 and the third test module 33. Among them, the setting of the third test module 33 is the same as that of the first test module 31; the setting of the fourth test module 34 is the same as that of the second test module 32. The formed semiconductor test structure is as Figure 3 shown. By diagonally arranging two test modules in the same direction, different process windows of semiconductor devices in this direction can be tested more comprehensively; by diagonally arranging two identical test modules, the test results of the two identical test modules can be verified with each other to optimize the test results more.

[0053] It can be seen from the above that for the semiconductor test structure and its manufacturing method provided in this embodiment, by improving the semiconductor test structure and setting test units with key dimensions gradually changing along a certain direction, different process windows of semiconductor devices are tested in this direction to effectively detect the over-etching amount of metal silicide in the hole structure etching and the influence of shared contact holes with different key dimensions on the gate sidewall topography, so as to select a suitable key dimension applicable to the target film layer and / or target structure to optimize the process window, and then apply the optimized process window to the corresponding semiconductor device manufacturing process to effectively improve the manufacturing yield of semiconductor devices. Further, by respectively setting test units with key dimensions gradually changing in different directions, different process windows of semiconductor devices are tested in different directions.

[0054] It should be noted that the terms "including" and "having" and their variants involved in the documents of the present invention are intended to cover non-exclusive inclusion. The terms "first", "second", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context and can be used to describe a feature, structure or property in a singular sense or can be used to describe a combination of features, structures or features in a plural sense. The term "based on" can be understood as not necessarily aiming to express a set of exclusive factors, but instead, again at least in part depending on the context, allowing for the existence of other factors that are not necessarily explicitly described. Additionally, in the case of no conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. Furthermore, in the above description, the description of well-known components and technologies is omitted to avoid unnecessarily confusing the concepts of the present invention. In each of the above embodiments, the focus of each embodiment is on the differences from other embodiments, and the same / similar parts among the embodiments can be referred to each other.

[0055] The above is only the preferred embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A semiconductor test structure, characterized in that, Comprising: A first test module, the first test module including at least one first sub-test module extending in a first direction, the first sub-test module including a plurality of first test units formed on a semiconductor substrate; the plurality of first test units are arranged at intervals along the first direction, and the critical dimensions of the plurality of first test units gradually change along the first direction, so as to test different process windows of a semiconductor device in the first direction; Each of the first test units includes: a plurality of first grooves, formed in the active region of the semiconductor substrate and arranged at intervals along the first direction; a first film layer to be tested, formed in the first grooves; a plurality of first gate structures, formed on the semiconductor substrate and arranged at intervals along the first direction, wherein each of the first gate structures is adjacent to a first film layer to be tested; a second film layer to be tested, formed on the surface of the first gate structure away from the semiconductor substrate; a plurality of first hole structures, formed by etching corresponding regions of the first film layer to be tested and the second film layer to be tested by using critical dimensions that gradually change along the first direction, and arranged at intervals along the first direction, and each of the first hole structures is adjacent to a first gate structure; the materials of the first film layer to be tested and the second film layer to be tested are both metal silicides.

2. The semiconductor test structure according to claim 1, wherein The critical dimension gradually increases in an arithmetic or geometric sequence along the first direction.

3. The semiconductor test structure according to claim 1, wherein The first hole structure is selected from any one of a shared contact hole, a contact hole or a via hole.

4. The semiconductor test structure according to claim 1, wherein By performing failure analysis to detect the loss amount of the first film layer to be tested corresponding to the first hole structure with the corresponding critical dimension in the active region, the loss amount of the second film layer to be tested in the region corresponding to the first gate structure, and the morphology of the first gate structure, the process window test result of the semiconductor device in the first direction is obtained.

5. The semiconductor test structure according to claim 1, wherein, The first test module includes a plurality of first sub-test modules extending along the first direction and arranged at intervals along a second direction, and the settings of the plurality of first sub-test modules are the same; wherein, the second direction is perpendicular to the first direction.

6. The semiconductor test structure according to claim 1, wherein The semiconductor test structure further includes a second test module, the second test module including at least one second sub-test module extending in the second direction, the second sub-test module including a plurality of second test units formed on the semiconductor substrate; the plurality of second test units are arranged at intervals along the second direction, and the critical dimensions of the plurality of second test units gradually change along the second direction, so as to test different process windows of a semiconductor device in the second direction; wherein, the second test module is adjacent to the first test module, and the second direction is perpendicular to the first direction.

7. The semiconductor test structure according to claim 6, wherein The second test module includes a plurality of second sub-test modules extending along the second direction and arranged at intervals along the first direction, and the settings of the plurality of second sub-test modules are the same and are both the same as the settings of the first sub-test modules.

8. The semiconductor test structure according to claim 6, wherein The semiconductor test structure further includes a third test module and a fourth test module; the third test module is disposed diagonally to the first test module and adjacent to the second test module, wherein the arrangement of the third test module is the same as that of the first test module; the fourth test module is disposed diagonally to the second test module and adjacent to the first test module and the third test module, wherein the arrangement of the fourth test module is the same as that of the second test module.

9. A method for preparing a semiconductor test structure, characterized in that, Comprising: providing a semiconductor substrate; forming a plurality of first test units arranged at intervals in a first direction on the semiconductor substrate, thereby forming a first test module including at least one first sub-test module extending in the first direction, and the critical dimensions of the plurality of first test units gradually change in the first direction for testing different process windows of semiconductor devices in the first direction; The step of forming a plurality of first test units arranged at intervals in the first direction on the semiconductor substrate further includes: forming a plurality of first grooves arranged at intervals in the first direction in the active region of the semiconductor substrate; forming a first film layer to be tested in each of the first grooves; forming a plurality of first gate structures arranged at intervals in the first direction on the semiconductor substrate, wherein each of the first gate structures is adjacent to a first film layer to be tested; forming a second film layer to be tested on the surface of each of the first gate structures away from the semiconductor substrate; etching corresponding regions of the first film layer to be tested and the second film layer to be tested with critical dimensions gradually changing in the first direction to form a plurality of first hole structures arranged at intervals in the first direction, wherein each of the first hole structures is adjacent to a first gate structure, and the materials of the first film layer to be tested and the second film layer to be tested are both metal silicide.

10. The method according to claim 9, characterized in that, The method further includes: forming a plurality of second test units arranged at intervals in a second direction on the semiconductor substrate, thereby forming a second test module including at least one second sub-test module extending in the second direction, and the critical dimensions of the plurality of second test units gradually change in the second direction for testing different process windows of semiconductor devices in the second direction; wherein the second test module is adjacent to the first test module, and the second direction is perpendicular to the first direction.

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