Semiconductor structure, three-dimensional memory and method of fabrication

Abstract

The application provides a semiconductor structure, a three-dimensional memory and respective preparation methods, the preparation method of the semiconductor structure comprises the following steps: providing a semiconductor substrate, forming a stack structure on the semiconductor substrate, the stack structure comprises a storage area and a connection area divided along an X direction, the connection area at least comprises a first connection sub-area and a second connection sub-area, performing preset etching on the stack structure of the first connection sub-area by a preset level number, then performing synchronous etching on the remaining stack structure of the first connection sub-area, and performing synchronous etching on the stack structure of the second connection sub-area to obtain a to-be-formed step. The method adopts a process combining preset etching (chop) and synchronous etching (trim and etch), reduces the process difficulty of device preparation, reduces the number of mask plates, realizes the preparation of the required step by combining X direction and Y direction etching, cuts off the continuity of the step in the Y direction, improves the stress and expansion of the material, and improves the stability of the device.

Description

[0001] This application is a divisional application of Chinese patent application filed on January 2, 2020, with application number 202010000511.9 and entitled "Semiconductor Structure, Three-Dimensional Memory and Preparation Method". Technical Field

[0002] This invention belongs to the field of integrated circuit manufacturing, and specifically relates to a semiconductor structure, a three-dimensional memory, and a method for its fabrication. Background Technology

[0003] Flash memory (FRAM) is a type of non-volatile memory (NVM), meaning that the data stored in it is retained even when the power is turned off. In contrast, dynamic random access memory (DRAM) and static random access memory (SRAM) are volatile memory (VM), meaning that the data stored in them is lost when the power is turned off.

[0004] Flash memory cells are classified into two types based on their structure: NOR Flash and NAND Flash. NOR Flash has a faster read speed, but slower write and erase speeds, and its capacity is much smaller than NAND Flash. However, NOR Flash can access any selected byte. Embedded flash memory within ICs is generally NOR Flash, primarily used to store boot files, applications, operating systems, and eXecute-in-Place (XIP) code in mobile devices and computers. NOR Flash memory cells are much larger than NAND Flash cells, and due to their structure, NOR Flash is inherently more reliable than NAND Flash. NAND Flash has a slightly slower read speed, but its write and erase speeds are much faster than NOR Flash. IC capacities can reach 128GB or more, but it cannot access specific bytes; instead, it processes data in small blocks (pages). NAND Flash is commonly used as a large-scale data storage device. Currently, GB (Gigabyte) level USB flash drives and SSDs (Solid State Drives / Disks) on the market both use NAND Flash.

[0005] However, existing steps are distributed on one side of the array region and are mostly long staircases, increasing or decreasing sequentially. Steps are often divided into different zones (two, three, or four zones). For example, there might be three zones increasing in one direction (e.g., X-axis) and continuous steps in another direction (e.g., Y-axis), with the X and Y directions perpendicular. Generally, after step formation, oxide filling and chemical mechanical polishing are performed. For example, since the steps are continuous in the Y-axis, the filler is also continuous. The filler oxide and the steps are different materials, and under the same heat treatment, their deformation is inconsistent, leading to differences in stress and expansion. This deteriorates the structural performance of the core and stair-step (SS) regions of the device, and may even cause failure.

[0006] Therefore, it is essential to provide a semiconductor structure, a three-dimensional memory, and a fabrication method to solve the aforementioned problems in the prior art. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor structure, a three-dimensional memory, and a method for fabricating each, in order to solve the problems of difficult step fabrication process and device structural performance deterioration or even failure due to stress and expansion in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor structure, the method comprising the following steps:

[0009] A semiconductor substrate is provided, and mutually perpendicular X and Y directions are defined in the plane where the semiconductor substrate is located, and a Z direction is defined in the direction perpendicular to the plane where the semiconductor substrate is located;

[0010] A stacked structure is formed on the semiconductor substrate. The stacked structure includes a plurality of stacked material units stacked along the Z direction. The stacked structure includes a memory region and a connection region divided along the X direction. The connection region includes at least a first connection partition and a second connection partition.

[0011] The portion of the stacked structure located in the first connecting partition is etched with a preset number of layers. After etching, the remaining stacked structure in the first connecting partition includes a first etched area and a second etched area sequentially divided along the X direction. The portion of the stacked structure located in the first etched area is etched such that the bottom surface of the first etched area is at least one layer lower than the bottom surface of the second etched area. Each layer includes one stacked material unit. The portions of the stacked structure located in the first etched area and the second etched area are etched simultaneously to form a first stepped structure in the first etched area and a second stepped structure in the second etched area. The first stepped structure gradually rises from the center outwards, and the second stepped structure gradually rises from the center outwards, so that each step surface constitutes several consecutive first leading steps of different levels, and the difference between adjacent levels of the first leading steps is S levels, where S is greater than or equal to 1.

[0012] The second connecting partition includes a third etching region and a fourth etching region sequentially divided along the X direction. The portion of the stacked structure located in the third etching region is etched, such that the bottom surface of the third etching region is at least one level lower than the bottom surface of the fourth etching region. The portions of the stacked structure located in the third etching region and the fourth etching region are etched simultaneously to form a third step structure located in the third etching region and a fourth step structure located in the fourth etching region. The third step structure gradually rises from the center outwards, and the fourth step structure gradually rises from the center outwards, so that each step surface constitutes a number of consecutive second lead-out steps of different levels, and the difference between adjacent levels of the second lead-out steps is S levels. The sum of the levels of the second lead-out steps and the levels of the first lead-out steps is equal to the level of the step to be formed.

[0013] Optionally, the connection area further includes a third connection partition to an Nth connection partition, where N is an integer greater than three. The portion of the stacked structure located between the third and Nth connection partitions is etched with a preset number of layers to obtain several consecutive third lead-out steps to several consecutive Nth lead-out steps of different layers. The preset number of layers for each connection partition is different from the preset number of layers for the first connection partition. The sum of the layers from the first lead-out step to the Nth lead-out step is equal to the layer number of the step to be formed. For each group of lead-out steps, in other groups of lead-out steps, there exists a group where the lowest-level step differs from the highest-level step by the S layers, and another group where the highest-level step differs from the lowest-level step by the S layers.

[0014] Optionally, the sum of the number of steps in each group of leading steps and the preset number of layers of the preset etching of the corresponding connecting partition is equal to the number of steps to be formed, and the number of steps from the first leading step to the Nth leading step are all equal.

[0015] Optionally, the steps of forming the first step structure and the second step structure include:

[0016] a) A mask layer with an opening is formed on the first connection partition, the opening dividing the mask layer into a first mask located on the first etched area and a second mask located on the second etched area, and the opening exposing a predetermined distance between the edge of the first etched area and the edge of the second etched area.

[0017] b) The first connection partition is etched based on the mask layer to form a first step in the first etched area, wherein the etching depth is M levels, and M is an integer greater than or equal to 1;

[0018] c) Trim the second mask so that the second mask retracts from the side close to the first mask to the direction away from the first mask by the preset distance, and etch the first connection partition based on the trimmed mask layer, with an etching depth of the M levels, so as to form a second step in the second etched area, and the first step descends by the M levels.

[0019] d) Trim the first mask so that the first mask is retracted by the preset distance from the side close to the second mask to the direction away from the second mask, and etch the first connection partition based on the trimmed mask layer, with an etching depth of M levels, so as to form a third step in the first etched area, and both the first step and the second step are reduced by the M levels.

[0020] e) Repeat steps c) through d) at least once to increase the number of steps.

[0021] Optionally, the storage area includes a first storage partition and a second storage partition, and the first storage partition, the connection area, and the second storage partition are arranged sequentially.

[0022] Optionally, the connection area includes a first part and a second part, and the first part, the storage area and the second part are arranged sequentially, wherein the first part includes at least the first connection partition and the second part includes at least the second connection partition.

[0023] Optionally, the connection region is divided into at least a first part and a second part along the X direction, and into a symmetrical first auxiliary region and a second auxiliary region along the Y direction. The portion of the first part overlapping with the first auxiliary region or the second auxiliary region constitutes the first connection partition, and the portion of the second part overlapping with the first auxiliary region or the second auxiliary region constitutes the second connection partition. A portion symmetrical to the first connection partition along the Y direction constitutes the first connection auxiliary region, and a portion symmetrical to the second connection partition along the Y direction constitutes the second connection auxiliary region. After the preset etching of the first connection partition and before etching the first connection partition and the second connection partition in the X direction, the method further includes the following steps:

[0024] At least the portions of the stacked structure that overlap with the first and second auxiliary regions and the first and second portions along the Y direction are simultaneously etched to form a first auxiliary step structure located in the first auxiliary region and a second auxiliary step structure located in the second auxiliary region. The first auxiliary step structure gradually decreases from the center outwards, and the second auxiliary step structure gradually decreases from the center outwards.

[0025] Optionally, the first auxiliary step structure and the second auxiliary step structure have the same number of steps, and the number of steps that the bottom surface of the first etched region is lower than the bottom surface of the second etched region, and the number of steps that the bottom surface of the third etched region is lower than the bottom surface of the fourth etched region, are all equal; the stacked material unit includes a stacked dielectric layer and a sacrificial layer.

[0026] Optionally, the steps of forming the first auxiliary step structure and the second auxiliary step structure include:

[0027] f) A photoresist layer is formed at least on the portion where the first auxiliary area and the second auxiliary area overlap with the first portion and the second portion, and a preset auxiliary spacing is exposed at the edges of the first auxiliary area and the second auxiliary area;

[0028] g) The stacked structure is etched with K layers based on the photoresist layer to form a first auxiliary step in the first auxiliary region and a second auxiliary step in the second auxiliary region, where K is an integer greater than or equal to 1;

[0029] h) Trim the photoresist layer to shrink the preset auxiliary spacing from both sides to the center along the Y direction, and etch the stacked structure based on the trimmed photoresist layer to form a third auxiliary step in the first auxiliary area and a fourth auxiliary step in the second auxiliary area. Both the first auxiliary step and the second auxiliary step are lowered by the K level.

[0030] i) Repeat step h) at least once to increase the number of auxiliary steps.

[0031] Optionally, the connection area includes at least a first auxiliary area and a second auxiliary area along the Y direction. The first and second connection areas are arranged parallel to each other along the X direction and have the same width along the Y direction. The first and second auxiliary areas are respectively arranged on both sides of the connection area along the Y direction, and the height of the first and second auxiliary areas is equal to the height of the highest lead-out step in the first and second connection areas.

[0032] The present invention also provides a method for fabricating a three-dimensional memory, the method comprising the step of fabricating the semiconductor structure using the semiconductor structure fabrication method described in any one of the above embodiments.

[0033] The present invention also provides a semiconductor structure, wherein the semiconductor structure is preferably prepared using the semiconductor structure preparation method provided by the present invention, but can also be prepared using other methods, the semiconductor structure comprising:

[0034] A semiconductor substrate, wherein an X-direction and a Y-direction are defined perpendicularly in the plane in which the semiconductor substrate is located, and a Z-direction is defined perpendicular to the plane in which the semiconductor substrate is located;

[0035] A stacked structure includes a plurality of stacked material units stacked along the Z direction, the stacked structure includes a storage area and a connection area divided along the X direction, and the connection area includes at least a first connection partition and a second connection partition.

[0036] The first connecting partition's stacked structure forms a first stepped structure and a second stepped structure arranged along the Z direction. The first stepped structure gradually rises from the center outwards, and the second stepped structure gradually rises from the center outwards, so that each step surface constitutes a number of consecutive first leading steps of different levels. The bottom surface of the first stepped structure has at least one fewer level than the bottom surface of the second stepped structure. Each level includes one of the stacked material units. The difference between adjacent levels of the first leading steps is S levels, where S is an integer greater than or equal to 1.

[0037] The stacked structure of the second connecting partition forms a third step structure and a fourth step structure arranged along the Z direction. The third step structure gradually rises from the center outwards, and the fourth step structure gradually rises from the center outwards, so that each step surface constitutes a number of consecutive second leading steps of different levels, and the second leading steps of adjacent levels differ by the number of S levels. The sum of the number of levels of the second leading steps and the number of levels of the first leading steps is equal to the number of levels of the step to be formed.

[0038] Optionally, the connection area further includes a third connection partition to an Nth connection partition, where N is an integer greater than three. Each connection partition corresponds to several consecutive third leading-out steps of different levels to several consecutive Nth leading-out steps of different levels. The sum of the levels of the first leading-out steps to the Nth leading-out steps is equal to the level of the steps to be formed. For each group of leading-out steps, in other groups of leading-out steps, there exists a group where the lowest level step differs from the highest level step in that group by the S levels, and there exists another group where the highest level step differs from the lowest level step in that group by the S levels.

[0039] Optionally, the number of steps from the first lead-out step to the Nth lead-out step are all equal; the stacked material unit includes a stacked dielectric layer and a gate conductive layer.

[0040] Optionally, the storage area includes a first storage partition and a second storage partition, and the first storage partition, the connection area, and the second storage partition are arranged sequentially.

[0041] Optionally, the connection area includes a first part and a second part, and the first part, the storage area and the second part are arranged sequentially, wherein the first part includes at least the first connection partition and the second part includes at least the second connection partition.

[0042] Optionally, the connection area is divided into at least a first part and a second part along the X direction, and into a symmetrical first auxiliary area and a second auxiliary area along the Y direction. The portion of the first part that overlaps with the first auxiliary area or the second auxiliary area constitutes the first connection partition, and the portion of the second part that overlaps with the first auxiliary area or the second auxiliary area constitutes the second connection partition. Furthermore, the portion symmetrical to the first connection partition along the Y direction constitutes the first connection auxiliary area, and the portion symmetrical to the second connection partition along the Y direction constitutes the second connection auxiliary area. Wherein:

[0043] The stacked structure of the first auxiliary area forms a first auxiliary step structure arranged along the Z direction, and the stacked structure of the second auxiliary area forms a plurality of second auxiliary step structures arranged along the Z direction. The first auxiliary step structure gradually decreases from the center outwards, and the second auxiliary step structure gradually decreases from the center outwards.

[0044] Optionally, the first auxiliary step structure and the second auxiliary step structure have the same number of steps, and the number of steps that the bottom surface of the first step structure is lower than the bottom surface of the second step structure, and the number of steps that the bottom surface of the third step structure is lower than the bottom surface of the fourth step structure, are all equal; the step surfaces of adjacent steps in the steps to be formed differ by one step.

[0045] Optionally, the connection area includes at least a first auxiliary area and a second auxiliary area along the Y direction. The first and second connection areas are arranged parallel to each other along the X direction and have the same width along the Y direction. The first and second auxiliary areas are respectively arranged on both sides of the connection area along the Y direction, and the height of the first and second auxiliary areas is equal to the height of the highest lead-out step in the first and second connection areas.

[0046] The present invention also provides a three-dimensional memory structure, the three-dimensional memory structure comprising a semiconductor structure as described in any of the above embodiments.

[0047] As described above, the semiconductor structure and its fabrication method, as well as the three-dimensional memory structure and its fabrication method of the present invention, employ a combination of pre-defined etching (chop) and simultaneous etching (trim and etch, a process of alternating trimming and etching of the mask layer). This reduces the difficulty of device fabrication and the number of masks required. By combining etching in the X and Y directions, the necessary steps are fabricated. By severing the continuity of the steps in the Y direction, the continuity of subsequent filling of oxides and other materials on the steps is also severed, improving the stress and expansion of the materials and enhancing the stability of the device. Dividing the steps to be formed into at least two parts for separate formation and placing the connection area in the middle or on both sides of the memory area allows for flexible arrangement of the steps, reducing the difficulty of fabrication, shortening the word line length, enhancing the control capability of the word line, and reducing latency. Attached Figure Description

[0048] Figure 1 The diagram shows the process flow for fabricating the semiconductor structure of this invention.

[0049] Figure 2 The diagram shown is a schematic diagram of the second connection partition division in Embodiment 1 of the present invention.

[0050] Figure 3 This is a schematic diagram showing the formation of the first step in Embodiment 1 of the present invention.

[0051] Figure 4 The diagram shown illustrates the formation of the second step in Embodiment 1 of the present invention.

[0052] Figure 5The diagram shown illustrates the formation of the third step in Embodiment 1 of the present invention.

[0053] Figure 6 The diagram shown illustrates the formation of the fourth step in Embodiment 1 of the present invention.

[0054] Figure 7 The diagram shows the first connecting partition and the surrounding stacked structure in Embodiment 1 of the present invention.

[0055] Figure 8 The diagram shows the structure after the first connection partition has been pre-etched in Embodiment 1 of the present invention.

[0056] Figure 9 The illustration shows the process of etching the first connecting partition in the Y direction to form the first step in Embodiment 1 of the present invention.

[0057] Figure 10 The illustration shows the process of etching the first connecting partition in the Y direction to form a second step in Embodiment 1 of the present invention.

[0058] Figure 11 The illustration shows the process of etching the first connecting partition in the Y direction to form the third step in Embodiment 1 of the present invention.

[0059] Figure 12 The illustration shows a stepped structure formed by etching the second connecting partition in the Y direction in Embodiment 1 of the present invention.

[0060] Figure 13 The diagram shown is an example of a 144-step staircase layout in Embodiment 1 of the present invention.

[0061] Figure 14 Displayed as Figure 13 The example shows a cross-sectional structural diagram of a step.

[0062] Figure 15 The diagram shown is an example of a 144-step staircase layout in Embodiment 2 of the present invention.

[0063] Figure 16 This is a schematic diagram illustrating an example of the arrangement of the connection area and storage area in Embodiment 1 of the present invention.

[0064] Figure 17 This is a schematic diagram showing another example of the arrangement of the connection area and storage area in Embodiment 1 of the present invention.

[0065] Component designation explanation

[0066] Detailed Implementation

[0067] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0068] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0069] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0070] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0071] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0072] Example 1:

[0073] like Figure 1 As shown, this embodiment provides a method for fabricating a semiconductor structure, the method comprising the following steps:

[0074] A semiconductor substrate is provided, and mutually perpendicular X and Y directions are defined in the plane where the semiconductor substrate is located, and a Z direction is defined in the direction perpendicular to the plane where the semiconductor substrate is located;

[0075] A stacked structure is formed on the semiconductor substrate. The stacked structure includes a plurality of stacked material units stacked along the Z direction. The stacked structure includes a memory region and a connection region divided along the X direction. The connection region includes at least a first connection partition and a second connection partition.

[0076] The portion of the stacked structure located in the first connecting partition is etched with a preset number of layers. After etching, the remaining stacked structure in the first connecting partition includes a first etched area and a second etched area sequentially divided along the X direction. The portion of the stacked structure located in the first etched area is etched so that the bottom surface of the first etched area is at least one layer lower than the bottom surface of the second etched area. Each layer includes one stacked material unit. The portions of the stacked structure located in the first etched area and the second etched area are etched simultaneously to form a first stepped structure located in the first etched area and a second stepped structure located in the second etched area. The first stepped structure gradually rises from the center outwards, and the second stepped structure gradually rises from the center outwards, so that each step surface constitutes several consecutive first leading steps of different levels, and the first leading steps of adjacent levels differ by S levels, where S is greater than or equal to 1.

[0077] The second connecting partition includes a third etching region and a fourth etching region sequentially divided along the X direction. The portion of the stacked structure located in the third etching region is etched, such that the bottom surface of the third etching region is at least one level lower than the bottom surface of the fourth etching region. The portions of the stacked structure located in the third etching region and the fourth etching region are etched simultaneously to form a third step structure located in the third etching region and a fourth step structure located in the fourth etching region. The third step structure gradually rises from the center outwards, and the fourth step structure gradually rises from the center outwards, so that each step surface constitutes a plurality of consecutive second leading steps of different levels, and the difference between adjacent levels of the second leading steps is S levels. The sum of the level of the second leading steps and the level of the first leading steps is equal to the level of the steps to be formed, and the difference between the highest level step in the first leading steps and the lowest level step in the second leading steps is S levels.

[0078] The method for preparing the semiconductor structure of the present invention will now be described in detail with reference to the accompanying drawings.

[0079] like Figure 1 S1 and Figure 2 As shown, a semiconductor substrate 100 is provided, and mutually perpendicular X and Y directions are defined in the plane containing the semiconductor substrate 100, and a Z direction is defined in the direction perpendicular to the plane containing the semiconductor substrate 100. Figure 2Only the X and Z directions are shown, but the X, Y, and Z directions can form a three-dimensional coordinate system. Furthermore, the semiconductor substrate 100 includes, but is not limited to, semiconductor substrates such as Si, Ge, SiGe, SiC, III-V compound semiconductors, and silicon-on-insulator (SOI).

[0080] like Figure 1 S1 and Figure 2 As shown, a stacked structure 200 is formed on the semiconductor substrate 100. The stacked structure 200 includes a plurality of stacked material units stacked along the Z direction. The stacked structure 200 includes a memory region and a connection region divided along the X direction, and the connection region includes at least a first connection partition and a second connection partition. Figure 2 This is merely an example; other layer structures may also be provided between the semiconductor substrate 100 and the stacked structure 200, and the scope of protection of this invention should not be excessively limited here.

[0081] In one example, the stacked material unit may be a dielectric layer and a sacrificial layer that are stacked alternately in the Z direction. For example, the dielectric layer and the sacrificial layer are deposited alternately on the semiconductor substrate using methods such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition, for example, 8-layer, 16-layer, 32-layer, 64-layer, 96-layer, 128-layer, 136-layer, 144-layer, etc., wherein one layer includes one stacked material unit, that is, one layer includes a pair of stacked dielectric layers and sacrificial layers. In this embodiment, eight tiers are alternately stacked, including, from bottom to top, dielectric layer 201a, sacrificial layer 201b, dielectric layer 202a, sacrificial layer 202b, dielectric layer 203a, sacrificial layer 203b, dielectric layer 204a, sacrificial layer 204b, dielectric layer 205a, sacrificial layer 205b, dielectric layer 206a, sacrificial layer 206b, dielectric layer 207a, sacrificial layer 207b, dielectric layer 208a, and sacrificial layer 208b.

[0082] Furthermore, in the division of the stacked structure 200 along the X direction, the connection region includes at least two connection partitions, namely a first connection partition and a second connection partition. It should be noted that etching the first and second connection partitions using different methods can be considered as representing two types of connection partitions. Of course, the connection region may also include three or more connection partitions, which can be named a third connection partition and an Nth connection partition, where N is an integer greater than or equal to 3. In one example, steps are formed in each connection partition, and each step is connected to the memory region of the device structure. Further, it can be electrically connected to the gate in the memory region, thereby achieving electrical lead-out of the gate based on the subsequently formed steps.

[0083] The following description uses two connected partitions as an example to further illustrate the semiconductor structure fabrication method based on steps S3 and S4 of the present invention. Regarding the description of this embodiment, it should be noted that... Figure 1 The process flow of the semiconductor structure fabrication method of the present invention is shown. Figure 2-6 The diagram shows a schematic of the etching process for etching a connected partition in the X direction. Figure 7-8 This is a schematic diagram of the structure after the preset etching is performed on another type of connection partition; Figure 9-11 Displayed as a pair Figure 7-8 A schematic diagram of the etching process structure for Y-direction etching of the type of connection partition shown. Figure 12 Displayed as a pair Figure 2-6 A schematic diagram of the etching process structure for Y-direction etching of the type of connection partition shown. Figure 13-15 The diagram shows a step obtained by simultaneously etching the X and Y directions of connection regions with different distributions according to the present invention. Figure 14 Displayed as Figure 13 A schematic diagram of a cross-section of the structure that forms a step; Figure 16-17 This diagram illustrates the different divisions and distributions of the storage and connection areas.

[0084] like Figure 2-8 The diagram shows an X-direction etching of the stacked structure 200 located in the first and second connection partitions. The difference in the etching process between the first and second connection partitions is that the first connection partition is first subjected to a preset etching (chop), that is, the portion of the stacked structure located in the first connection partition is first etched away with a preset number of layers. Each layer includes one stacked material unit. In one example, a layer includes a pair of stacked dielectric layers and a sacrificial layer. After this, the etching process for the first and second connection partitions is similar.

[0085] For ease of illustration, the following description uses the second connection partition without the preset etching as an example:

[0086] First, such as Figure 2 As shown, the second connection partition is divided along the X direction. The second connection partition includes a third etched region 200a and a fourth etched region 200b sequentially divided along the X direction. This division can be along the X-axis of a three-dimensional coordinate system. Preferably, the third etched region 200a and the fourth etched region 200b are adjacent. More preferably, the lengths of the third etched region 200a and the fourth etched region 200b along the X direction are equal.

[0087] Next, refer to Figure 3 The third etched area 200a is etched such that its bottom surface is at least one level lower than the bottom surface of the fourth etched area 200b. This means that, based on this etching, the bottommost surface of the stepped structure formed by the third etched area 200a (the surface of the lowest step) is at least one level lower than the bottommost surface of the stepped structure formed by the fourth etched area 200b. Here, the number of etched levels in this etching process is the number of levels by which the bottom surface of the third etched area 200a is lower than that of the bottom surface of the fourth etched area 200b. Furthermore, since a stepped structure needs to be formed subsequently, this etching is not a complete etching of the third etched area 200a.

[0088] Continue, see reference Figure 4-6 The stacked structure 200 is simultaneously etched in portions located in the third etched region 200a and the fourth etched region 200b, forming a third stepped structure in the third etched region 200a and a fourth stepped structure in the fourth etched region 200b. The third stepped structure gradually rises from the center outwards, and the fourth stepped structure also gradually rises from the center outwards. Here, the center can be considered as the interface between the third and fourth etched regions, so that each step surface constitutes several consecutive second leading steps of different levels, and the difference between adjacent levels of second leading steps is S levels, where S is an integer greater than or equal to 1. After this etching step, the third step structure and the fourth step structure are formed to obtain the required number of steps.

[0089] In a specific example of the etching process, such as Figure 3 As shown, the bottom surface of the third etched region 200a is two levels lower than the bottom surface of the fourth etched region 200b. The etching process includes: forming a mask layer 300 with an opening on the second connecting partition. The opening divides the mask layer into a first mask 301 on the third etched region 200a and a second mask 302 on the fourth etched region 200b. The opening exposes a predetermined distance d between the edge of the third etched region 200a and the edge of the fourth etched region 200b. The opening defines the step surface of the bottommost step of the stepped structure formed in the third etched region 200a, i.e., the bottom surface. The second connecting partition is etched based on the mask layer 300 to form a first step A1 (the bottommost step) in the third etched region 200a. The etching depth is M levels, where M is an integer greater than or equal to 1; here, M is chosen as 2.

[0090] Next, in this specific example, such as Figure 4 As shown, the second mask 302 is trimmed so that it retracts a predetermined distance d from the side closest to the first mask 301 towards the side furthest from the first mask 301. Based on the trimmed mask layer 300, the second connection partition is etched to a depth of M levels, where M is chosen as two levels, consistent with the depth of the first etching, to form a second step A2 in the fourth etched area. The first step A1 decreases by the M levels. It should be noted that... Figure 3 In the etching process shown, a first step A1 is formed. During this etching, the first step A1 is simultaneously etched down by the M layers, and the actual exposed material layer changes. However, because synchronous etching is performed, the relative layers do not change. For ease of description, the subsequent etching will still be described using the first step A1 as the material. Other steps are described similarly. Next, as... Figure 5 As shown, the first mask 301 is trimmed so that it retracts by a predetermined distance from the side closest to the second mask 302 towards the side furthest from the second mask 302. Based on the trimmed mask layer 300, the second connection partition is etched to a depth of M levels to form a third step A3 in the third etched area. Both the first step A1 and the second step A2 decrease by the M levels. Then, as... Figure 6 As shown, repeat the above steps at least once to increase the number of steps, where, Figure 6 The second mask 302 is repeatedly adjusted once to form the fourth step A4. Of course, more steps can be formed later to obtain the third and fourth step structures.

[0091] It can be seen that the bottom surface of the third-step structure is M levels lower than the bottom surface of the fourth-step structure, which is the etching depth of the first etching. In the above example, the etching depth after trimming the first mask 301 and the second mask 302 is also M levels. Of course, in other examples, the number of subsequent etching levels can be selected according to the actual situation. Figure 6 The result shows that four levels of the second lead-out steps were obtained. The difference between the second lead-out steps of each adjacent level is two levels, which depends on the etching depth and can be selected according to actual needs. In one example, the stacked structure of the second connecting partition is etched only in the X direction. The etching depth is selected consistently for each etching, which is M levels. The height difference S levels between the M levels and the steps of the adjacent levels is also selected consistently.

[0092] Furthermore, referring to the above description of the etching process for the second connection partition and... Figure 7-8As shown, the etching of the first connection partition will be described below. First, as... Figure 7 As shown, the first connection partition 400b and the adjacent stacked structure therewith (i.e., the stacked structure 400a surrounding the first connection partition) are displayed. Then, as... Figure 8 As shown, the first connection partition 400b is subjected to the preset etching (chop), wherein the preset number of preset layers for the preset etching is selected according to the actual situation. Next, analogous to the division of the etched area of ​​the second connecting partition, the remaining part of the first connecting partition after the preset etching is divided, which includes a first etched area and a second etched area divided sequentially along the X direction. Here, since the first connecting partition has been etched, for ease of description, its remaining stacked structure can be directly referred to as the first connecting partition. The part of the stacked structure located in the first etched area is etched, so that the bottom surface of the first etched area is at least one level lower than the bottom surface of the second etched area. Here, one level includes one stacked material unit. The parts of the stacked structure located in the first etched area and the second etched area are etched simultaneously to form a first stepped structure located in the first etched area and a second stepped structure located in the second etched area. The first stepped structure gradually rises from the center outwards, and the second stepped structure gradually rises from the center outwards, so that each step surface constitutes several consecutive first lead-out steps of different levels, and the difference between adjacent levels of the first lead-out steps is S levels, where S is greater than or equal to 1. The etching of the first connection partition can be referred to the etching of the second connection partition. As an example, the steps for forming the first step structure and the second step structure include:

[0093] a) A mask layer with an opening is formed on the first connection partition, the opening dividing the mask layer into a first mask located on the first etched area and a second mask located on the second etched area, and the opening exposing a predetermined distance between the edge of the first etched area and the edge of the second etched area.

[0094] b) The first connection partition is etched based on the mask layer to form a first step in the first etched area, wherein the etching depth is M levels, and M is an integer greater than or equal to 1;

[0095] c) Trim the second mask so that the second mask retracts from the side close to the first mask to the direction away from the first mask by the preset distance, and etch the first connection partition based on the trimmed mask layer, with an etching depth of the M levels, so as to form a second step in the second etched area, and the first step descends by the M levels.

[0096] d) Trim the first mask so that the first mask is retracted by the preset distance from the side close to the second mask to the direction away from the second mask, and etch the first connection partition based on the trimmed mask layer, with an etching depth of M levels, so as to form a third step in the first etched area, and both the first step and the second step are reduced by the M levels.

[0097] e) Repeat steps c) through d) at least once to increase the number of steps.

[0098] Based on the etching of the aforementioned stacked structure, the sum of the number of levels of the second lead-out step and the number of levels of the first lead-out step equals the number of levels of the step to be formed. That is, if 36 steps are to be formed, 18 steps can be formed based on the first connecting partition, and 18 steps can be formed based on the second connecting partition. Specifically, the first connecting partition can form steps 1 to 18, and the second connecting partition can form steps 19 to 36. The corresponding partitions for the preset etching form a lower number of steps. Alternatively, 32 steps can be formed based on the first connecting partition, and 4 steps can be formed based on the second connecting partition. The specific method can be determined based on actual conditions. Through this scheme, the steps to be formed can be divided into at least two parts for separate formation, thereby achieving flexible step arrangement, reducing the difficulty of the fabrication process, reducing the use of mask plates, cutting off continuous step structures, and improving stress and material expansion. In one example, the highest level step in the first leading-out step differs from the lowest level step in the second leading-out step by the S levels. That is, in the steps to be formed, the difference between any adjacent levels of steps is equal, thereby obtaining steps that are evenly distributed in height and a continuous and uniform overall step.

[0099] As an example, the connection area further includes a third connection partition to an Nth connection partition, where N is an integer greater than three. The portion of the stacked structure located between the third and Nth connection partitions is etched with a preset number of layers to obtain several consecutive third lead-out steps of different levels to several consecutive Nth lead-out steps of different levels. The preset number of layers for the preset etching of each connection partition is different and also different from the preset number of layers for the preset etching of the first connection partition. The sum of the levels of the first lead-out step to the Nth lead-out step is equal to the level of the step to be formed. In other words, when dividing the connection area, it includes three or more partitions, namely the N partitions. One partition is not subject to the preset etching (chop), while the other partitions are each subject to the preset etching. The number of layers for the preset etching of each partition is different. Then, the stacked structure below the preset etching is etched according to the etching method of the second connection partition. Through the above scheme, the connection area is formed into at least three sets of stepped structures by forming at least three connection partitions, and finally the required steps are obtained.

[0100] As an example, the sum of the number of steps in each group of leading steps and the preset number of layers in the preset etching of the corresponding connecting partition is equal to the number of steps to be formed. Furthermore, the number of steps from the first leading step to the Nth leading step is equal. For each group of leading steps, in other groups of leading steps, there exists a group where the lowest-level step differs from the highest-level step by the specified S layers, and another group where the highest-level step differs from the lowest-level step by the specified S layers. In this example, the sum of the number of steps in each group of leading steps and the preset number of layers in the preset etching of the corresponding connecting partition is equal to the number of steps to be formed. That is, the number of layers chopped off in this group is the number of steps formed in the other groups. Based on the steps to be formed in this example, each group forms steps with equal height differences, meaning the difference in layers between adjacent steps is the same; in this example, one layer is chosen.

[0101] like Figure 9-12 As shown, the stacked structure 200 is further etched in the Y direction, thereby forming the required steps based on the etching in the Y direction and the etching in the X direction. In one example, the connection partitions that need to be pre-etched are first etched in the X direction (chop), then the stacked structure 200 in the Y direction is etched, and then the stacked structure of each connection partition is etched in the X direction in a synchronous manner similar to the second connection partition, forming a stepped structure and resulting in the lead-out steps. The etching in the Y direction is described in detail below with reference to the accompanying drawings:

[0102] First, the connection region is divided into at least a first part and a second part along the X direction, and symmetrically divided into a first auxiliary region 501 and a second auxiliary region 502 along the Y direction. The portion of the first part that overlaps with the first auxiliary region or the second auxiliary region constitutes the first connection partition, and the portion of the second part that overlaps with the first auxiliary region or the second auxiliary region constitutes the second connection partition. A portion symmetrical to the first connection partition along the Y direction constitutes the first connection auxiliary region, and a portion symmetrical to the second connection partition along the Y direction constitutes the second connection auxiliary region. After the first connection partition is etched (chop), and before the first connection partition and the second connection partition are etched in the X direction, the following steps are also included:

[0103] At least the portions of the stacked structure that overlap with the first part and the second part in the first auxiliary region 501 and the second auxiliary region 502 along the Y direction are simultaneously etched to form a first auxiliary step structure in the first auxiliary region and a second auxiliary step structure in the second auxiliary region. The first auxiliary step structure gradually decreases from the center outwards, and the second auxiliary step structure gradually decreases from the center outwards. Here, the center can refer to the interface where the first auxiliary region 501 and the second auxiliary region 502 are in contact. This step breaks the continuity of the steps in the Y direction.

[0104] In one example of etching, the steps of forming the first auxiliary step structure and the second auxiliary step structure include:

[0105] First, such as Figure 9 As shown, a photoresist layer 500 is formed at least on the overlapping portions of the first auxiliary region 501 and the second auxiliary region 502 with the first portion and the second portion, and a preset auxiliary spacing is exposed at the edges of the first auxiliary region 501 and the second auxiliary region 502; then, the stacked structure 200 is etched at K levels based on the photoresist layer 500 to form a first auxiliary step C1 in the first auxiliary region 501 and a second auxiliary step B1 in the second auxiliary region 502, where K is an integer greater than or equal to 1;

[0106] like Figure 10 As shown, the photoresist layer 500 is trimmed so that the photoresist layer 500 shrinks back from both sides to the center along the Y direction by the preset auxiliary spacing. Based on the trimmed photoresist layer 500, the stacked structure 200 is etched to form a third auxiliary step C2 in the first auxiliary region 501 and a fourth auxiliary step B2 in the second auxiliary region 502. Both the first auxiliary step C1 and the second auxiliary step B2 are lowered by the K-level.

[0107] Alternatively, step h) can be repeated at least once to increase the number of auxiliary steps.

[0108] See Figure 11 As shown, after removing the photoresist layer 500, a fifth auxiliary step C3 is formed in the first auxiliary region 501, and a sixth auxiliary step B3 is formed in the second auxiliary region 502, resulting in a structure with six steps along the Y direction. Figures 9-11 This shows an example of etching the first connected partition in the Y direction to perform a preset etch (chop). Figure 10 This example shows an instance of etching the second connection partition in the Y direction without performing a preset etch (chop), forming steps D1, D2, D3, E1, E2, E3.

[0109] This invention employs a combination of pre-defined etching (chop) and simultaneous etching (trim and etch, a process of alternatingly trimming and etching the mask layer), which reduces the difficulty of device fabrication and the number of masks required. Forming the necessary steps using only a process similar to simultaneous etching is difficult, and forming the necessary steps using only a process similar to pre-defined etching requires a large number of masks. Furthermore, this invention combines etching in both the X and Y directions to create the necessary steps, breaking the continuity of the steps in the Y direction, thus breaking the continuity of subsequent filling of oxides and other materials on the steps. This improves material stress and expansion, and enhances device stability.

[0110] As an example, the number of levels of the first auxiliary step structure and the second auxiliary step structure are equal, and the number of levels that the bottom surface of the first etched area is lower than the bottom surface of the second etched area, and the number of levels that the bottom surface of the third etched area is lower than the bottom surface of the fourth etched area, are also equal.

[0111] Specifically, in this example, the stacked structure is etched in the X and Y directions, wherein, see [reference needed]. Figure 13As shown, taking the first stepped structure formed by the first connecting partition 601 as an example, the first auxiliary stepped structure is symmetrically formed in the Y direction. It can be seen that the number of levels of the first auxiliary stepped structure in the Y direction is 3. In this example, during the etching process of the first connecting partition 601 in the X direction, the first etching makes the first etched area 3 levels lower than the second etched area. Then, when the first etched area and the second etched area are etched simultaneously to form the first stepped structure and the second stepped structure, the depth of each etching is 3 levels, thereby obtaining several independent steps, and the difference between each adjacent step is one level. That is, the number of levels that the bottom surface of the first etched area is lower than the bottom surface of the second etched area during the first etching depends on the number of steps to be formed in the Y direction.

[0112] like Figure 13-14 As shown, an example is provided where 144 steps need to be formed. The process involves etching in three partitions: a first connecting partition 601, a second connecting partition 602, and a third connecting partition 603. During etching, the stacked structures above the first connecting partition 601 and the third connecting partition 603 are pre-etched. Specifically, 96 layers (chop 96 pairs) are etched away at the location corresponding to the first connecting partition 601, ultimately forming 48 steps in the first connecting partition 601, creating steps 1 to 48. Similarly, 48 layers (chop48) are etched away at the location corresponding to the third connecting partition 603. (pairs), ultimately forming 48 steps in the third connection region 603, forming steps 49 to 96. Additionally, the second connection partition 602 is not pre-etched; in subsequent processes, 48 ​​steps are formed there, forming steps 97 to 144. Next, the first, third, and second connection partitions formed after etching are etched using the aforementioned embodiment of the invention. First, etching is performed in the Y direction, forming three symmetrical steps on each auxiliary partition, decreasing sequentially from the center outwards to form a mountain-shaped structure. That is, the 48 steps of each connection partition are divided into three rows. Then, each connection partition is etched in the X-square, wherein... Figure 14 The image shows a cross-sectional view of the innermost layer after etching the first connective partition in the X direction. The left side of the image also shows a cross-sectional view of the first connective partition at a symmetrical position along the Y direction, ultimately forming the required number of steps in each region. See also... Figure 13 As shown, steps are also formed at the symmetrical positions and around each connecting partition, which actually forms the uppermost three-level steps, enabling WL continuity and isolation of the filled oxide.

[0113] In one example, when two or more connected partitions are formed, the connectable partitions can be alternately set to left and right in the Y direction, such as... Figure 13 The way it's set up in the configuration facilitates the layout of the device structure. For example... Figure 13 As shown, the stepped structure in the connecting partition has a first wall structure Q1 extending along the X direction on at least one side along the Y direction, and a second wall structure Q2 is provided between two adjacent connecting partitions along the X direction. The first wall structure Q1 is a connecting auxiliary area, and the second wall structure Q2 is an isolation auxiliary area. The height of the first wall structure Q1 and the second wall structure Q2 along the Z direction is equal to the height of the highest leading-out step among the plurality of connecting partitions along the Z direction.

[0114] See Figure 16 As shown, in one example, the storage area includes a first storage partition 804 and a second storage partition 805, and the first storage partition 804, the connection area 800, and the second storage partition 805 are arranged sequentially. In this example, the connection area is placed between the two storage areas, thereby shortening the word line length, enhancing word line control, and reducing latency. In this example, a first connection partition 801, a second connection partition 802, and a third connection partition 803 are set in the connection area to form the required steps in each connection partition. In this example, the storage area is divided into two parts, respectively placed on both sides of the connection area, which can shorten the word line length, enhance word line control, and reduce latency.

[0115] See Figure 17 As shown, the connection area includes a first connection portion 901 and a second connection portion 902, and the first connection portion 901, the storage area 900, and the second connection portion 902 are arranged sequentially. The first connection portion 901 includes at least a first connection partition 903, and the second connection portion 902 includes at least a second connection partition 904. In this example, dividing the connection partition into two parts and placing them on both sides of the storage area 900 can shorten the word line length, enhance word line control, and reduce latency. Furthermore, each part of the connection area only needs to have at least one connection partition; the specific arrangement depends on the actual situation. The second connection partition, which is not chopped, can be placed on the left or right side of the storage area.

[0116] The above scheme divides the steps to be formed into at least two parts and forms them separately. The connecting area is set in the middle or on both sides of the storage area, which can realize the flexible arrangement of the steps, reduce the difficulty of the manufacturing process, shorten the word line length, enhance the control capability of the word line, and reduce the latency. Compared with single-end power-on, which is transmitted to the other side of the storage area through WL, if the steps are placed in the middle of the storage area or divided into two parts and set on both sides of the storage area, the word line will be shortened, the control capability will be enhanced, and the latency will be reduced.

[0117] Example 2:

[0118] like Figure 15 As shown, another embodiment is provided, wherein the connection area includes at least a first auxiliary area (first wall structure Q1) and a second auxiliary area (first wall structure Q1) along the Y direction, and a second wall structure Q2 extending along the Y direction is provided between the connection area and the storage area and between two adjacent connection partitions along the X direction, and the height of the second wall structure Q2 along the Z direction is equal to the height of the highest lead-out step among the plurality of connection partitions along the Z direction. The first connecting partition and the second connecting partition are arranged parallel to each other along the X direction and have equal widths along the Y direction. The first auxiliary area and the second auxiliary area are respectively arranged on both sides of the connecting area along the Y direction, and the height of the first auxiliary area and the second auxiliary area is equal to the height of the highest leading step in the first connecting partition and the second connecting partition. In an optional example, it includes a first connecting partition 701, a second connecting partition 702, and a third connecting partition 703. In this example, each connecting partition is arranged parallel to each other along the X direction. The position for the preset etching (chop) is different from that in Embodiment 1. Other fabrication processes are the same as in Embodiment 1. In this example, the first auxiliary area and the second auxiliary area do not need to be etched to directly form the last step. When performing preset etching on the area within the frame in the Y direction, the width of each step can be selected according to actual needs. In this example, the width of the first step in the Y direction is wider and can be twice that of other steps, but it is not limited to this. Figure 5 Showing the results Figure 13 The distribution of the 144 steps in this embodiment is shown.

[0119] Example 3:

[0120] like Figure 13-17 As shown, and see Figure 1-12This embodiment provides a semiconductor structure, wherein the semiconductor structure is preferably prepared using any one of the preparation methods in Embodiment 1 and Embodiment 2. Of course, it can also be prepared using other methods well known to those skilled in the art. The description of the relevant structures of the semiconductor structure in this embodiment can be referred to the descriptions in Embodiment 1 and Embodiment 2, and will not be repeated here. The semiconductor structure includes:

[0121] A semiconductor substrate 100, wherein an X-direction and a Y-direction are defined perpendicularly in the plane in which the semiconductor substrate 100 is located, and a Z-direction is defined perpendicular to the plane in which the semiconductor substrate 100 is located.

[0122] The stacked structure 200 includes a plurality of stacked material units stacked along the Z direction. The stacked structure includes a storage area and a connection area divided along the X direction, and the connection area includes at least a first connection partition and a second connection partition.

[0123] The first connecting partition's stacked structure forms a first stepped structure and a second stepped structure arranged along the Z direction. The first stepped structure gradually rises from the center outwards, and the second stepped structure gradually rises from the center outwards, so that each step surface constitutes a number of consecutive first leading steps of different levels. The bottom surface of the first stepped structure has at least one fewer level than the bottom surface of the second stepped structure. Each level includes one of the stacked material units. The difference between adjacent levels of the first leading steps is S levels, where S is an integer greater than or equal to 1.

[0124] The stacked structure of the second connecting partition forms a third step structure and a fourth step structure arranged along the Z direction. The third step structure gradually rises from the center outwards, and the fourth step structure gradually rises from the center outwards, so that each step surface constitutes a number of consecutive second leading steps of different levels, and the difference between adjacent levels of the second leading steps is S levels. The sum of the number of levels of the second leading steps and the number of levels of the first leading steps is equal to the number of levels of the steps to be formed, and the difference between the highest level step in the first leading steps and the lowest level step in the second leading steps is S levels.

[0125] As an example, the connection area further includes a third connection partition to an Nth connection partition, where N is an integer greater than three. Each connection partition corresponds to several consecutive third leading-out steps of different levels to several consecutive Nth leading-out steps of different levels. The sum of the levels of the first leading-out steps to the Nth leading-out steps is equal to the level of the steps to be formed. For each group of leading-out steps, in other groups of leading-out steps, there exists a group where the lowest level step differs from the highest level step in that group by the S levels, and there exists another group where the highest level step differs from the lowest level step in that group by the S levels.

[0126] As an example, the number of stages from the first lead-out step to the Nth lead-out step are all equal; the stacked material unit includes a stacked dielectric layer and a gate conductive layer. The description of the gate conductive layer can be found in the description of the sacrificial layer in Embodiments 1 and 2, i.e., the gate conductive layer is formed at the location of the sacrificial layer during the fabrication process.

[0127] like Figure 13-14 As shown, an example is provided where 144 steps need to be formed. The process involves etching in three partitions: a first connecting partition 601, a second connecting partition 602, and a third connecting partition 603. During etching, the stacked structures above the first connecting partition 601 and the third connecting partition 603 are pre-etched. Specifically, 96 layers (chop 96 pairs) are etched away at the location corresponding to the first connecting partition 601, ultimately forming 48 steps in the first connecting partition 601, creating steps 1 to 48. Similarly, 48 layers (chop48) are etched away at the location corresponding to the third connecting partition 603. (pairs), ultimately forming 48 steps in the third connection region 603, forming steps 49 to 96. Additionally, the second connection partition 602 is not pre-etched; in subsequent processes, 48 ​​steps are formed there, forming steps 97 to 144. Next, the first, third, and second connection partitions formed after etching are etched using the aforementioned embodiment of the invention. First, etching is performed in the Y direction, forming three symmetrical steps on each auxiliary partition, decreasing sequentially from the center outwards to form a mountain-shaped structure. That is, the 48 steps of each connection partition are divided into three rows. Then, each connection partition is etched in the X-square, wherein... Figure 14 The image shows a cross-sectional view of the innermost layer after etching the first connective partition in the X direction. The left side of the image also shows a cross-sectional view of the first connective partition at a symmetrical position along the Y direction, ultimately forming the required number of steps in each region. See also... Figure 13As shown, steps are also formed at the symmetrical positions and around each connecting partition, which actually forms the uppermost three-level steps, enabling WL continuity and isolation of the filled oxide.

[0128] In one example, when two or more connected partitions are formed, the connectable partitions can be alternately set to left and right in the Y direction, such as... Figure 13 The configuration method in the middle is conducive to the layout of the device structure.

[0129] like Figure 15 As shown, in one example, the connection area includes at least a first auxiliary area and a second auxiliary area along the Y direction. The first and second connection areas are arranged parallel to each other along the X direction and have the same width along the Y direction. The first and second auxiliary areas are respectively arranged on both sides of the connection area along the Y direction, and the height of the first and second auxiliary areas is equal to the height of the highest step leading out of the first and second connection areas.

[0130] In an optional example, the system includes a first connecting partition 701, a second connecting partition 702, and a third connecting partition 703. In this example, each connecting partition is arranged parallel to the X-direction. The location for the preset etching (chop) differs from that in Example 1. Other fabrication processes are the same as in Example 1. In this example, the first and second auxiliary regions do not require etching and directly form the final step. When performing preset etching in the Y-direction on the area within the frame, the width of each step can be selected according to actual needs. In this example, the width of the first step in the Y-direction is wider and can be twice that of the other steps, but this is not a limitation. Figure 5 Showing the results Figure 13 The distribution of the 144 steps in this embodiment is shown.

[0131] like Figure 16 As shown, the storage area includes a first storage partition 804 and a second storage partition 805, and the first storage partition 804, the connection area 800, and the second storage partition 805 are arranged sequentially. In this example, the connection area is placed between the two storage areas, thereby shortening the word line length, enhancing word line control capabilities, and reducing latency. In this example, a first connection partition 801, a second connection partition 802, and a third connection partition 803 are set in the connection area to form the required steps in each connection partition. In this example, the storage area is divided into two parts, respectively placed on both sides of the connection area, which can shorten the word line length, enhance word line control capabilities, and reduce latency.

[0132] like Figure 17As shown, the connection area includes a first connection portion 901 and a second connection portion 902, and the first connection portion 901, the storage area 900, and the second connection portion 902 are arranged sequentially. The first connection portion 901 includes at least a first connection partition 903, and the second connection portion 902 includes at least a second connection partition 904. In this example, dividing the connection partition into two parts and placing them on both sides of the storage area 900 can shorten the word line length, enhance word line control, and reduce latency. Furthermore, each part of the connection area only needs to have at least one connection partition; the specific arrangement depends on the actual situation. The second connection partition, which is not chopped, can be placed on the left or right side of the storage area.

[0133] As an example, the connection area is at least divided into a first part and a second part along the X direction, and symmetrically divided into a first auxiliary area and a second auxiliary area along the Y direction. The portion of the first part that overlaps with the first auxiliary area or the second auxiliary area constitutes the first connection partition, and the portion of the second part that overlaps with the first auxiliary area or the second auxiliary area constitutes the second connection partition. Furthermore, the portion symmetrical to the first connection partition along the Y direction constitutes the first connection auxiliary area, and the portion symmetrical to the second connection partition along the Y direction constitutes the second connection auxiliary area, wherein:

[0134] The stacked structure of the first auxiliary area forms a first auxiliary step structure arranged along the Z direction, and the stacked structure of the second auxiliary area forms a plurality of second auxiliary step structures arranged along the Z direction. The first auxiliary step structure gradually decreases from the center outwards, and the second auxiliary step structure gradually decreases from the center outwards.

[0135] In addition, this invention combines etching in the X and Y directions to achieve the fabrication of steps, which cuts off the continuity of the steps in the Y direction, and also cuts off the continuity of subsequent filling of oxides and other materials on the steps, thereby improving the stress and expansion of the material and improving the stability of the device.

[0136] As an example, the first auxiliary step structure and the second auxiliary step structure have the same number of steps, and the number of steps that the bottom surface of the first step structure is lower than the bottom surface of the second step structure and the number of steps that the bottom surface of the third step structure is lower than the bottom surface of the fourth step structure are also equal; the step surfaces of adjacent steps in the steps to be formed differ by one of the aforementioned steps.

[0137] Example 4:

[0138] This embodiment provides a method for fabricating a three-dimensional memory. The method includes the step of fabricating the semiconductor structure using the semiconductor structure fabrication method described in any one of Embodiments 1 and 2. In the three-dimensional memory, a gate structure is formed in the storage region. In the fabrication process of the three-dimensional memory, the position of the sacrificial layer in the stacked structure corresponds to the formation of a gate wire layer, thereby forming a required number of steps based on the gate wire layer to electrically lead out the gate junction structure in the storage region.

[0139] In addition, the present invention also provides a three-dimensional memory structure, which includes a semiconductor structure as described in any one of the embodiments in Example 1. Preferably, it is prepared by the three-dimensional memory preparation method provided in this embodiment. Of course, it can also be prepared by other methods well known in the art.

[0140] In summary, the semiconductor structure and its fabrication method, as well as the three-dimensional memory structure and its fabrication method of the present invention, employ a combination of pre-defined etching (chop) and simultaneous etching (trim and etch, a process of alternating trimming and etching of the mask layer). This reduces the difficulty of device fabrication and the number of masks required. The combination of etching in the X and Y directions enables the fabrication of necessary steps, breaking the continuity of the steps in the Y direction, thus breaking the continuity of subsequent filling of oxides and other materials on the steps. This improves material stress and expansion, enhancing device stability. Dividing the required steps into at least two parts for separate formation and placing the connection area in the middle or on both sides of the memory area allows for flexible step arrangement, reducing fabrication difficulty, shortening word line length, enhancing word line control, and reducing latency. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0141] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: The stack structure comprises a plurality of stack material units stacked along a Z direction, the stack structure comprises a storage area and a connection area arranged along an X direction, and the connection area comprises a plurality of connection sub-areas arranged along the X direction; the X direction is perpendicular to the Z direction; The stack structure of the connection sub-area comprises a first stepped structure and a second stepped structure which are both stepped along the X direction and the Y direction, the first stepped structure and the second stepped structure are arranged adjacently and the lowest step surface of each of the first stepped structure and the second stepped structure is at the adjacent position, so that each step surface constitutes a plurality of continuous different order lead-out steps, wherein the lowest step surface of the first stepped structure is at least one level lower than the lowest step surface of the second stepped structure, one level comprises one stack material unit, the lead-out steps of adjacent orders are different by S levels, S is an integer greater than or equal to 1; the Y direction is perpendicular to the X direction and the Z direction; The projections of the stepped structures in different connection sub-areas on the plane where the X direction and the Y direction are located do not overlap; the sum of the orders of the lead-out steps in each connection sub-area in the plurality of connection sub-areas is equal to the total number of stack material units; the stepped structure in the connection sub-area is provided with a connection auxiliary area extending along the X direction on at least one side along the Y direction, the connection auxiliary area comprises a number of stack material units equal to the total number of stack material units, and the connection auxiliary area comprises an auxiliary stepped structure which cuts off the continuity of the stepped structure in the connection sub-area in the Y direction.

2. The semiconductor structure of claim 1, wherein, The stack material unit comprises a dielectric layer and a gate conductive layer which are stacked.

3. The semiconductor structure of claim 1, wherein, The storage area comprises a first storage sub-area and a second storage sub-area, and the first storage sub-area, the connection area and the second storage sub-area are arranged in sequence.

4. The semiconductor structure of claim 1, wherein, The connection area comprises a plurality of parts, and the plurality of parts are arranged in sequence along the X direction, each part comprises a corresponding connection sub-area and the connection auxiliary area located on at least one side of the corresponding connection sub-area along the Y direction.

5. The semiconductor structure of claim 4, wherein, The connection auxiliary areas in two adjacent parts along the X direction are located on the same side of the connection sub-area.

6. The semiconductor structure of claim 4, wherein, The connection auxiliary areas in two adjacent parts along the X direction are located on both sides of the connection sub-area.

7. The semiconductor structure of claim 4, wherein, The connection auxiliary areas in two adjacent parts along the X direction are located on different sides of the connection sub-area; an isolation auxiliary area is arranged between two adjacent connection sub-areas along the X direction, and the isolation auxiliary area comprises a number of stack material units equal to the total number of stack material units.

8. The semiconductor structure of any of claims 1-7, wherein, The orders of the lead-out steps corresponding to the first stepped structure and the second stepped structure are cross-changed.

9. The semiconductor structure of any of claims 1-7, wherein, Each step surface in the first stepped structure and the second stepped structure comprises a plurality of sub-step surfaces along the Y direction; two adjacent sub-step surfaces along the Y direction are different by a certain number of levels.

10. A semiconductor structure, characterized by The semiconductor structure comprises: A stack structure includes a plurality of stack material units stacked along a Z direction, the stack structure includes a storage region and a connection region arranged along an X direction, and the connection region includes a plurality of connection sub-regions arranged along the X direction; the X direction is perpendicular to the Z direction; The stack structure of the connection sub-region includes a first ladder structure and a second ladder structure which are both stepped along the X direction and the Y direction, the first ladder structure and the second ladder structure are arranged adjacently and each of the adjacent positions is a lowest step surface of the corresponding ladder structure, so that each step surface constitutes a plurality of continuous different order lead-out steps, wherein the lowest step surface of the first ladder structure is at least one level less than the lowest step surface of the second ladder structure, one level includes one stack material unit, the lead-out steps of adjacent orders are different by S levels, S is an integer greater than or equal to 1; The projections of the ladder structures in different connection sub-regions on the plane where the X direction and the Y direction are located do not overlap; the sum of the orders of the lead-out steps in each connection sub-region of the plurality of connection sub-regions is equal to the total number of stack material units; the ladder structure in the connection sub-region is provided with a connection auxiliary region extending along the X direction on both sides along the Y direction, a plurality of connection auxiliary regions on each side are arranged continuously along the X direction, the connection auxiliary region includes a number of stack material units equal to the total number of stack material units, the connection auxiliary region includes an auxiliary ladder structure, and the auxiliary ladder structure cuts off the continuity of the ladder structure in the connection sub-region in the Y direction.

11. The semiconductor structure of claim 10, wherein, The connection region and the storage region, and the connection sub-regions adjacent along the X direction are all provided with an isolation auxiliary region extending along the Y direction, and the isolation auxiliary region includes a number of stack material units equal to the total number of stack material units.

12. The semiconductor structure of claim 10, wherein, The orders of the lead-out steps corresponding to the first ladder structure and the second ladder structure are cross-changed.

13. The semiconductor structure of claim 10, wherein, The number of lead-out steps corresponding to each connection sub-region of the plurality of connection sub-regions is the same.

14. The semiconductor structure of claim 10, wherein, The plurality of connection sub-regions are arranged in parallel along the X direction, and the widths along the Y direction are equal.

15. The semiconductor structure of claim 10, wherein, Each step surface in the first ladder structure and the second ladder structure includes a plurality of sub-step surfaces along the Y direction; two adjacent sub-step surfaces along the Y direction are different by a certain number of levels.

16. The semiconductor structure of claim 15, wherein, Each step surface in the first ladder structure and the second ladder structure includes a first sub-step surface, a second sub-step surface, a third sub-step surface and a fourth sub-step surface along the Y direction; wherein the first sub-step surface is one level more than the second sub-step surface, the second sub-step surface is one level more than the third sub-step surface, and the number of levels of the stack material units included in the third sub-step surface is the same as the number of levels of the stack material units included in the fourth sub-step surface.

17. A three-dimensional memory structure comprising: The three-dimensional memory structure includes the semiconductor structure as claimed in any one of claims 1-9 or the semiconductor structure as claimed in any one of claims 10-16.

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