Method of making three-dimensional memory

Abstract

The application provides a three-dimensional memory manufacturing method. In the process of forming a sacrificial layer, a top sacrificial layer has a first etching selectivity A to a bottom sacrificial layer, and the top sacrificial layer has a second etching selectivity B to a middle sacrificial layer, wherein A<=B<=1 and A<>1. The etching rate of the sacrificial layer is changed in the process of removing the sacrificial layer by wet etching by changing the material composition in the deposition stage of the sacrificial layer. The etching rate of the lower sacrificial layer is greater than that of the upper sacrificial layer. The difference in the etching rate can balance the difference in the etching rate of the lower sacrificial layer and the upper sacrificial layer caused by the etching load effect in the process, reduce the damage of the part of the charge blocking layer in contact with the upper sacrificial layer, effectively solve the uneven damage of the charge blocking layer in the upper and lower positions, and improve the step coverage of the charge blocking layer in the upper and lower positions.

Description

[0001] Divisional Statement

[0002] This application is a divisional application of the Chinese Patent Application No. 202010438263.6, with the title of “Manufacturing Method of Three-dimensional Memory”, filed on May 21, 2020. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor technology, in particular to a manufacturing method of three-dimensional memory. BACKGROUND

[0004] In the prior art, the main function of flash memory is to keep the stored information for a long time without power supply, and it has the advantages of high integration, fast access speed, easy erasing and rewriting, etc., so it has been widely used in electronic products. In order to further improve the bit density of flash memory and reduce the bit cost, three-dimensional NAND flash memory is further proposed.

[0005] The storage structure is a key structure of three-dimensional memory, and the commonly used storage structure includes a charge blocking layer, a charge trapping layer, a tunneling layer and a channel layer, which plays a role in controlling the charge storage of the memory. At present, the manufacturing process of the storage structure in the three-dimensional NAND flash memory is to form a channel via in the stacked structure, and then sequentially deposit along the sidewall of the channel via.

[0006] The charge blocking layer in the above storage structure is generally high-bandgap silicon dioxide, which mainly plays a role in blocking the charge on the gate side, and has the following functions:

[0007] 1. Preventing charge tunneling between the storage structure and the gate during programming or erasing operation, resulting in programming failure or erasing failure;

[0008] 2. Preventing electrons from tunneling through the charge blocking layer into the gate layer due to thermal motion or radiation in the storage structure at static time, causing threshold voltage drift.

[0009] However, since the above-mentioned charge blocking layer is formed before the gate layer, when the sacrificial layer is removed after the channel via process is completed, damage will be caused to the formed charge blocking layer. Due to the etching loading effect, the upper sacrificial layer is etched first, and the part of the charge blocking layer in contact with the upper sacrificial layer will be damaged first, and relatively speaking, the part of the charge blocking layer in contact with the lower sacrificial layer will be damaged less. As a result, the thickness of the charge blocking layer in contact with the upper and lower sacrificial layers will be uneven, thereby increasing the risk of leakage of the back gate of the upper word line (WL).

[0010] And, since the part of the charge blocking layer in contact with the upper layer of the sacrificial layer is damaged more, the gate is deepened to the channel direction, thereby causing the upper layer of the word line programming coupling effect to be enhanced, and for TLC (3bit / cell) or QLC (4bit / cell) programming, the distance between the multiple programming states of the upper layer of the word line is insufficient, which easily causes data read failure. SUMMARY

[0011] The main purpose of the present application is to provide a three-dimensional memory manufacturing method to solve the problem that the manufacturing process of the three-dimensional memory in the prior art is prone to cause a large leakage risk of the upper layer of the word line (WL) back gate.

[0012] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a three-dimensional memory manufacturing method is provided, comprising the following steps: S1, forming a stack structure on a substrate, the stack structure comprising sacrificial layers and isolation layers which are alternately stacked in a direction away from the substrate, the sacrificial layers comprising a top layer of sacrificial layer, a bottom layer of sacrificial layer and an intermediate layer of sacrificial layer between the top layer of sacrificial layer and the bottom layer of sacrificial layer, the top layer of sacrificial layer having a first etching selectivity A to the bottom layer of sacrificial layer, and the top layer of sacrificial layer having a second etching selectivity B to the intermediate layer of sacrificial layer, wherein A≤B≤1, and A≠1; S2, forming a channel through hole in the stack structure to the substrate, and forming a storage structure on the sidewall of the channel through hole, the storage structure having a charge blocking layer covering the sidewall; S3, forming a common source trench in the stack structure to the substrate, and performing wet etching on the sacrificial layers to remove each sacrificial layer; S4, forming a control gate structure at the position corresponding to the sacrificial layer, so that the control gate structure is in contact with the charge blocking layer, and forming a conductive channel in the common source trench.

[0013] Further, the intermediate layer of sacrificial layer is multi-layered, and the second etching selectivity B of the top layer of sacrificial layer to each intermediate layer of sacrificial layer decreases in turn from top to bottom.

[0014] Further, the intermediate layer of sacrificial layer is multi-layered, and the intermediate layer of sacrificial layer comprises at least one upper layer of intermediate layer of sacrificial layer and at least one lower layer of intermediate layer of sacrificial layer, the etching selectivity of the top layer of sacrificial layer to each upper layer of intermediate layer of sacrificial layer is equal to 1, and the etching selectivity of the top layer of sacrificial layer to each lower layer of intermediate layer of sacrificial layer is less than 1.

[0015] Further, SiN is deposited to form the sacrificial layer, and O element is doped in the deposition process of the top layer of sacrificial layer and / or the upper layer of intermediate layer of sacrificial layer.

[0016] Further, SiN is deposited to form the sacrificial layer, and the Si content in SiN is increased in the deposition process of the top layer of sacrificial layer and / or the upper layer of intermediate layer of sacrificial layer.

[0017] Further, the SiN deposition is used to form the sacrificial layer, and Ge element is doped in the deposition process of the bottom sacrificial layer and / or the middle sacrificial layer.

[0018] Further, in step S3, the wet etching of the sacrificial layer is performed by using an etching solution, and the etching solution comprises phosphoric acid aqueous solution, and preferably, the etching solution further comprises a regulator, and the regulator is ammonium salt and / or sulfuric acid.

[0019] Further, the step of forming the storage structure comprises sequentially forming a stacked charge blocking layer, a charge trapping layer, a tunneling layer and a channel layer on the sidewall of the channel via.

[0020] Further, after the step of forming the common source trench, step S3 further comprises the step of forming a doped region in the region of the substrate communicating with the common source trench, and the doped region is opposite to the doped type of the substrate.

[0021] Further, after the step of removing the sacrificial layer, step S3 further comprises the step of forming a select gate dielectric layer on the doped region.

[0022] The technical scheme of the present application provides a manufacturing method of a three-dimensional memory, which makes the sacrificial layer comprise a top sacrificial layer, a bottom sacrificial layer and a middle sacrificial layer between the top sacrificial layer and the bottom sacrificial layer in the process of forming the sacrificial layer, the top sacrificial layer has a first etching selectivity A to the bottom sacrificial layer, and the top sacrificial layer has a second etching selectivity B to the middle sacrificial layer, wherein A≤B≤1, and A≠1. Since the etching rate of the sacrificial layer is changed by changing the material composition in the deposition stage of the sacrificial layer, the etching rate of the sacrificial layer in the lower layer is greater than that of the sacrificial layer in the upper layer, thereby obtaining the first etching selectivity A and the second etching selectivity B. In the process of removing the sacrificial layer by wet etching, the difference in the etching rate can balance the difference in the etching rate of the lower sacrificial layer and the upper sacrificial layer caused by the etching load effect in the process, reduce the damage of the part of the charge blocking layer in contact with the upper sacrificial layer, effectively solve the problem of uneven damage of the charge blocking layer in the upper and lower positions, improve the step coverage capability of the charge blocking layer in the upper and lower positions, and reduce the risk of leakage of the upper word line back gate. Since the upper charge blocking layer has less loss, the charges in the trapping layer are more difficult to tunnel into the gate layer, thereby not only improving the data retention characteristics of the upper storage unit, reducing the inter-sub-line coupling effect, and improving the distance between the programming states, but also reducing the programming or erasing failure caused by the tunneling of charges between the blocking layer and the gate. BRIEF DESCRIPTION OF DRAWINGS

[0023] The drawings constituting a part of the specification of the present application are used to provide a further understanding of the present application, and the illustrative embodiments of the present application and the description thereof are used to explain the present application, and do not constitute an improper limitation on the present application.

[0024] In the drawings:

[0025] Figure 1 Fig. 1 shows a schematic diagram of a cross-sectional structure of a substrate after forming a stack structure on a surface of the substrate in a method of fabricating a three-dimensional memory according to embodiments of the present application;

[0026] Figure 2 Fig. 2 shows a schematic diagram of a cross-sectional structure of a substrate after forming a storage structure in the stack structure shown in Fig. 1; Figure 1

[0027] Figure 3 Fig. 3 shows a schematic diagram of a cross-sectional structure of a substrate after forming a common-source trench in the stack structure shown in Fig. 2; Figure 2

[0028] Figure 4 Fig. 4 shows a schematic diagram of a cross-sectional structure of a substrate after removing the sacrificial layer shown in Fig. 3; Figure 3

[0029] Figure 5 Fig. 5 shows a schematic diagram of a cross-sectional structure of a substrate after forming a lower select gate dielectric layer on the surface of the substrate in the common-source trench shown in Fig. 4; Figure 4

[0030] Figure 6 Fig. 6 shows a schematic diagram of a cross-sectional structure of a substrate after forming a gate layer at the positions where the sacrificial layer is removed in the stack structure shown in Fig. 5; Figure 5

[0031] Figure 7 Fig. 7 shows a schematic diagram of a cross-sectional structure of a substrate after forming a conductive channel in the common-source trench shown in Fig. 6; Figure 6

[0032] Figure 8 Fig. 8 shows a schematic diagram of a cross-sectional structure of a part of a control gate structure and a region adjacent to the control gate structure shown in Fig. 7. Figure 7

[0033] In the drawings, the following reference numerals are used:

[0034] 10, substrate; 20, sacrificial layer; 210, top sacrificial layer; 220, bottom sacrificial layer; 230, middle sacrificial layer; 30, isolation layer; 40, storage structure; 410, charge blocking layer; 420, charge trapping layer; 430, tunneling layer; 440, channel layer; 450, filled oxide layer; 50, common-source trench; 60, doped region; 70, select gate dielectric layer; 80, control gate structure; 810, gate layer; 820, high-K dielectric layer; 90, sidewall insulating layer; 100, conductive channel. DETAILED DESCRIPTION

[0035] ​​​​​​​It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other in the case of no conflict. The technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0036] In order for those skilled in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the protection scope of the present application.

[0037] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0038] As introduced in the background, due to the etching loading effect in the prior art, the upper sacrificial layer 20 is etched first, and the part of the charge blocking layer 410 in contact with the upper sacrificial layer 20 is damaged first, and the part of the charge blocking layer 410 in contact with the lower sacrificial layer 20 is relatively less damaged, which results in that the thickness of the charge blocking layer 410 in contact with the upper and lower sacrificial layers 20 is not uniform, thereby increasing the risk of leakage of the upper word line (WL) back gate; and since the part of the charge blocking layer 410 in contact with the upper sacrificial layer 20 is damaged more, the gate extends deeply to the channel direction, thereby causing the programming coupling effect of the upper WL to be enhanced, and the margin of the programming state of the upper WL to be reduced.

[0039] The present inventors have conducted research on the above problems, and proposed a manufacturing method of a three-dimensional memory, as shown in Figures 1 to 8As shown, the method comprises the following steps: S1, forming a stack structure on a substrate 10, the stack structure comprising sacrificial layers 20 and isolation layers 30 alternately stacked in a direction away from the substrate 10, the sacrificial layers 20 comprising a top sacrificial layer 210, a bottom sacrificial layer 220, and an intermediate sacrificial layer 230 between the top sacrificial layer 210 and the bottom sacrificial layer 220, the top sacrificial layer 210 having a first etching selectivity A to the bottom sacrificial layer 220, and the top sacrificial layer 210 having a second etching selectivity B to the intermediate sacrificial layer 230, wherein A≤B≤1, and A≠1; S2, forming a channel via in the stack structure, and forming a storage structure 40 on the sidewall of the channel via, the storage structure 40 having a charge blocking layer 410 covering the sidewall; S3, forming a common source trench 40 in the stack structure to the substrate 10, and performing wet etching on the sacrificial layers 20 to remove each sacrificial layer 20; S4, forming a control gate structure 80 gate layer 810 at a position corresponding to the sacrificial layer 20, so that the control gate structure 80 gate layer 810 is in contact with the charge blocking layer 410, and forming a conductive channel 100 in the common source trench 40.

[0040] The top sacrificial layer 210 has a first etching selectivity A to the bottom sacrificial layer 220, which can be understood as that under the same wet etching condition, the same etching liquid etches the top sacrificial layer 210 and the bottom sacrificial layer 220 respectively, so that the top sacrificial layer 210 has a first etching rate, and the bottom sacrificial layer 220 has a second etching rate, and the first etching selectivity A is the ratio of the first etching rate to the second etching rate. Similarly, the top sacrificial layer 210 has a second etching selectivity B to the intermediate sacrificial layer 230, which can be understood as that under the same wet etching condition, the same etching liquid etches the intermediate sacrificial layer 230, so that the intermediate sacrificial layer 230 has a third etching rate, and the second etching selectivity B is the ratio of the first etching rate to the third etching rate.

[0041] The first etching selectivity A and the second etching selectivity B are obtained by changing the etching rate of the lower sacrificial layer 20 and the upper sacrificial layer 20 by changing the material composition during the deposition of the sacrificial layer 20, so that the etching rate of the lower sacrificial layer 20 is greater than that of the upper sacrificial layer 20. In the process of removing the sacrificial layer 20 by wet etching, the difference in etching rate balances the difference in etching rate of the lower sacrificial layer 20 and the upper sacrificial layer 20 caused by the etching load effect, reduces the damage to the part of the charge blocking layer 410 in contact with the upper sacrificial layer 20, effectively solves the problem of uneven damage of the charge blocking layer 410 at the upper and lower positions, and improves the step coverage of the charge blocking layer 410 at the upper and lower positions. Moreover, since the upper charge blocking layer 410 has less loss, the charges in the trapping layer are more difficult to tunnel into the gate layer 810, thereby not only improving the data retention characteristics of the upper storage unit, reducing the sub-line interlayer coupling effect, and improving the distance between programming states, but also reducing the programming or erasing failure caused by the tunneling of charges between the blocking layer and the gate.

[0042] Exemplary embodiments of a method for manufacturing a three-dimensional memory provided by the present application will be described in more detail below. However, these exemplary embodiments can be implemented in various different forms, and should not be interpreted as being limited only to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of the present application is complete and complete, and the concepts of these exemplary embodiments are fully conveyed to those skilled in the art.

[0043] First, step S1 is performed: forming a stack structure on the substrate 10, the stack structure including sacrificial layers 20 and isolation layers 30 alternately stacked in a direction away from the substrate 10, the sacrificial layers 20 including a top sacrificial layer 210, a bottom sacrificial layer 220, and one or more intermediate sacrificial layers 230 between the top sacrificial layer 210 and the bottom sacrificial layer 220, as shown in Figure 1 The top sacrificial layer 210 has a first etching selectivity A to the bottom sacrificial layer 220, and a second etching selectivity B to the intermediate sacrificial layer 230, where A≤B≤1, and A≠1.

[0044] The material of the substrate 10 can be monocrystalline silicon (Si), monocrystalline germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can also be other materials, such as gallium arsenide and other Group III-V compounds. In this embodiment, the semiconductor substrate 10 is a P-type Si substrate 10.

[0045] In step S1, the isolation layer 30 and the sacrificial layer 20 can be formed by using conventional deposition processes in the prior art, such as chemical vapor deposition. The number of layers of the sacrificial layer 20 and the isolation layer 30 can be set according to actual needs by those skilled in the art. The isolation layer 30 can be SiO2, and the sacrificial layer 20 can be SiN, but is not limited to the above-mentioned types. Those skilled in the art can also reasonably select the types of the isolation layer 30 and the sacrificial layer 20 according to the prior art.

[0046] The intermediate sacrificial layer 230 can be one layer or multiple layers. For the multiple-layer intermediate sacrificial layer 230, the etching rates of the layers can be partially the same. In a preferred embodiment, the intermediate sacrificial layer 230 includes at least one upper intermediate sacrificial layer and at least one lower intermediate sacrificial layer. The etching selectivity ratio of the top sacrificial layer 210 to each upper intermediate sacrificial layer is equal to 1, and the etching selectivity ratio of the top sacrificial layer 210 to each lower intermediate sacrificial layer is less than 1. As the name implies, the lower intermediate sacrificial layer refers to the intermediate sacrificial layer 230 located below in the multiple-layer intermediate sacrificial layer 230, and the upper intermediate sacrificial layer refers to the intermediate sacrificial layer 230 located above in the multiple-layer intermediate sacrificial layer 230, i.e., any upper intermediate sacrificial layer is located on the side of the lower intermediate sacrificial layer away from the substrate 10.

[0047] For n upper intermediate sacrificial layers and m lower intermediate sacrificial layers (a total of n+m layers of sacrificial layers 20), in the above embodiment, the etching rates of the top sacrificial layer 210 and the n upper intermediate sacrificial layers are both S1 under the same wet etching condition. At this time, the etching selectivity ratio of the top sacrificial layer 210 to the upper intermediate sacrificial layer is equal to 1 (i.e., the second etching selectivity ratio B = 1). The etching rates of the m lower intermediate sacrificial layers and the bottom sacrificial layer 220 are both S2, and S1 is less than S2. At this time, the etching selectivity ratio of the top sacrificial layer 210 to the lower intermediate sacrificial layer is less than 1 (i.e., the second etching selectivity ratio B < 1). At the same time, since the etching selectivity ratio of the top sacrificial layer 210 to the bottom sacrificial layer 220 is also less than 1 (i.e., the first etching selectivity ratio A < 1), and the etching rates of the lower intermediate sacrificial layer and the bottom sacrificial layer 220 are the same, A = B.

[0048] For the multiple-layer intermediate sacrificial layer 230, the etching rates of the layers can also all be different. In a preferred embodiment, the intermediate sacrificial layer 230 is multiple layers. In order from top to bottom, the second etching selectivity ratio B decreases in turn.

[0049] The m intermediate sacrificial layers 230 are taken as an example. In the above embodiment, the etching rate of the top sacrificial layer 210 is S1, the etching rate of the bottom sacrificial layer 220 is S2, and the etching rate of each intermediate sacrificial layer 230 gradually increases from S3 to S4 in the direction from top to bottom, and S1 < S3 < S4 < S2 under the same wet etching condition.

[0050] It should be noted that the top sacrificial layer 210, the bottom sacrificial layer 220 and the intermediate sacrificial layer 230 are not limited to the above preferred embodiment in the above step S1. The n upper intermediate sacrificial layers and the m lower intermediate sacrificial layers (a total of n+m sacrificial layers 20) are taken as an example. In other alternative embodiments, the etching rate of the top sacrificial layer 210 and the n upper intermediate sacrificial layers is S1, the etching rate of the bottom sacrificial layer 220 is S2, and the etching rate of the m lower intermediate sacrificial layers gradually increases from S3 to S4 in the direction from top to bottom, and S1 < S3 < S4 < S2 under the same wet etching condition; or the etching rate of the top sacrificial layer 210 is S1, the etching rate of the n upper intermediate sacrificial layers decreases from S5 to S6 in the direction away from the substrate 10, the etching rate of the m lower intermediate sacrificial layers and the bottom sacrificial layer 220 is S2, and S1 < S5 < S6 < S2.

[0051] In the above step S1, the etching rate of the upper sacrificial layer 20 can be reduced while keeping the etching rate of the lower sacrificial layer 20 unchanged by adjusting the deposition process of the top sacrificial layer 210 and / or the upper intermediate sacrificial layer, so that the first etching selection ratio is less than 1. When SiN is used to deposit the sacrificial layer 20, O element can be doped in the deposition process of the upper sacrificial layer 20, or Ge element can be doped in the deposition process of the lower sacrificial layer 20 to reduce the etching rate of the upper sacrificial layer 20 in the etching liquid such as phosphoric acid.

[0052] In the above step S1, the etching rate of the lower sacrificial layer 20 can be increased while keeping the etching rate of the upper sacrificial layer 20 unchanged by adjusting the deposition process of the bottom sacrificial layer 220 and / or the lower intermediate sacrificial layer, so that the first etching selection ratio is less than 1. When SiN is used to deposit the sacrificial layer 20, Ge element can be doped in the deposition process of the lower sacrificial layer 20 to increase the etching rate of the lower sacrificial layer 20 in the etching liquid such as phosphoric acid. In order to increase the etching rate of the sacrificial layer 20, in addition to doping Ge element, N content can also be increased.

[0053] In addition to the above-mentioned method of doping elements, the etching rate can also be adjusted by changing the deposition process of the sacrificial layer 20. For example, the SiN deposited by HCD (high plasma enhanced CVD) has a higher density than that deposited by LPCVD, and the SiN deposited by ALD (Atom level deposition) has a higher density than that deposited by HCD. Therefore, the etching rate of the sacrificial layer 20 can be adjusted by reasonably selecting the deposition process to adjust the density of the sacrificial layer 20. In addition, the etching rate can also be adjusted by adjusting the deposition temperature in the deposition process, because the etching rate of SiN deposited at a high temperature is generally lower than that of SiN deposited at a low temperature.

[0054] After the above-mentioned step S1 is completed, step S2 is performed: forming a channel via in the stack structure, and forming a storage structure 40 on the sidewall of the channel via, the storage structure 40 having a charge blocking layer 410 covering the sidewall, as shown in Figure 2 .

[0055] In the above-mentioned step S2, before the storage structure 40 is formed, an epitaxial layer covering the substrate 10 can be formed at the bottom of the channel via, and the upper surface of the epitaxial layer exceeds the upper surface of the bottommost sacrificial layer 220. The above-mentioned storage structure 40 can be a charge trap type storage structure 40, and the step of forming the storage structure 40 includes sequentially forming a laminated charge blocking layer 410, a charge trapping layer 420, a tunneling layer 430 and a channel layer 440 on the sidewall of the channel via, and the charge blocking layer 410 covers the sidewall of the channel via, as shown in Figure 2 . The above-mentioned storage structure 40 can further include a filling oxide layer 450 covering the inner surface of the channel layer 440, as shown in Figure 2 . The above-mentioned filling oxide layer 450 is generally SiO2, and can be deposited by ALC or CVD process, which aims to cover the channel layer 440.

[0056] Those skilled in the art can reasonably select the materials of the above-mentioned functional layers in the storage structure 40 according to the prior art. For example, the material of the charge blocking layer 410 can be SiO2, the material of the charge trapping layer 420 can be SiN, the material of the tunneling layer 430 can be SiO2, and the material of the channel layer 440 can be polysilicon. In addition, those skilled in the art can form the above-mentioned storage structure 40 by using conventional deposition processes in the prior art, which will not be described here.

[0057] After the above-mentioned step S2 is completed, step S3 is performed: forming a common source trench 40 in the stack structure, which penetrates to the substrate 10, and wet etching the sacrificial layer 20 to remove the sacrificial layer 20, as shown in Figure 3 and Figure 4 .

[0058] In step S3 above, the purpose of forming the common source trench 40 is to form an array common source (ACS). Those skilled in the art can use conventional etching processes in the prior art to form the common source trench 40. After forming the common source trench 40 that communicates with the substrate 10, as... Figure 5 As shown, step S3 may further include forming a doped region 60 in the region of the substrate 10 that is connected to the common source trench 40, wherein the doping type of the doped region 60 is opposite to that of the substrate 10; after forming the doped region 60, step S3 may further include forming a select gate dielectric layer 70 on the doped region 60, such as... Figure 5 As shown.

[0059] In step S3 above, by forming the common source trench 40, the sacrificial layer 20 is made to have an exposed end face. Then, starting from the exposed end face, the sacrificial layer 20 is wet-etched using an etchant to remove it. Since there is a first etching selectivity between the upper sacrificial layer 20 and the lower sacrificial layer 20 formed by the deposition process in step S1, and this first etching selectivity is less than 1, in step S2 above, by using the etchant to wet-etch the sacrificial layer 20, the difference in etching rate between the lower sacrificial layer 20 and the upper sacrificial layer 20 caused by the etching load effect in the process can be balanced by utilizing the difference in etching rate, thereby effectively solving the problem of uneven damage to the charge barrier layer 410 at the upper and lower positions. The etchant may include an aqueous solution of phosphoric acid. The etchant may also include modifiers such as ammonium salts and sulfuric acid to adjust the etching effect of the etchant.

[0060] After completing step S3 above, step S4 is performed: a control gate structure 80 is formed at the location where the sacrificial layer 20 is removed, so that the control gate structure 80 contacts the charge blocking layer 410, and a conductive channel 100 is formed in the common source trench 40, such as... Figure 6 and Figure 7 As shown.

[0061] After step S3 above, by removing the sacrificial layer 20, a laterally extending channel can be formed at the location where the sacrificial layer 20 is removed. In step S4 above, the gate material is deposited using the channel as a deposition channel to obtain the gate layer 810. The deposition process can be atomic layer deposition (ALD). The gate material is usually a metal and can be selected from one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni.

[0062] Furthermore, after the aforementioned deposition process, step S4 may also include an etch-back step to remove excess gate material from the common-source trench 40, such as... Figure 6 As shown.

[0063] The control gate structure 80 includes a gate layer 810, and before forming the gate layer 810, a high-K dielectric layer 820 can be deposited on the channel surface, as shown. Figure 8 The K dielectric layer and the gate layer 810 together form the control gate structure 80. The material forming the high-K dielectric layer 820 can be selected from one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, and BaSrTiO.

[0064] In step S4, by forming the gate layer 810, the replacement of the sacrificial layer 20 and the gate layer 810 is completed, thereby forming a stacked structure of the gate layer 810 and the isolation layer 30 alternately, and the bottommost gate layer 810 is used as the source-end selection gate, and the epitaxial layer formed in step S2 is used as the channel layer 440 of the source-end selection gate.

[0065] After the step of forming the gate layer 810, in step S4, as shown in Figure 7 The conductive channel 100 is separated from the gate layer 810 by the sidewall insulation layer 90, the storage structure 40 forms a common source connection through the substrate 10, and the conductive channel 100 provides a conductive path for the common source connection to the source line.

[0066] From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

[0067] The above-mentioned manufacturing method of the present application can balance the difference in etching rate between the lower sacrificial layer and the upper sacrificial layer caused by the etching load effect, reduce the damage to the part of the charge blocking layer in contact with the upper sacrificial layer, effectively solve the problem of uneven damage of the charge blocking layer at the upper and lower positions, improve the step coverage capability of the charge blocking layer at the upper and lower positions, and reduce the risk of leakage of the upper word line back gate;

[0068] Because the upper charge blocking layer is less damaged, the charges in the trapping layer are more difficult to tunnel into the gate layer, thereby not only improving the data retention characteristics of the upper storage unit, reducing the inter-sub-line coupling effect, and improving the distance between the programming states, but also reducing the programming or erasing failure caused by the tunneling of charges between the blocking layer and the gate.

[0069] The above merely provides the preferred embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the principles and technical scope of the present application shall fall into the scope of the present application.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: A first stacked structure includes alternating stacked first dielectric layers and second dielectric layers. The first dielectric layer includes an upper first dielectric layer and a lower first dielectric layer. The upper first dielectric layer has a first etch selectivity A over the lower first dielectric layer, where A < 1. The second dielectric layer includes an isolation layer, and the first dielectric layer is located between adjacent isolation layers. A first channel structure extends through the first stacked structure in a direction from the upper first dielectric layer to the lower first dielectric layer. The first channel structure includes a storage structure, in which a charge blocking layer is in contact with the first dielectric layer and the second dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, The storage structure includes the charge blocking layer, charge trapping layer, tunneling layer and channel layer in the radially inward direction along the first channel structure.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: The second stacked structure includes an alternately stacked conductive layer and a second dielectric layer.

4. The semiconductor structure according to claim 3, characterized in that, The first stacked structure and the second stacked structure are arranged adjacent to each other, wherein the first dielectric layer and the conductive layer are in contact.

5. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure also includes: A second channel structure extends through the second stacked structure in a direction from the upper first dielectric layer to the lower first dielectric layer. The second channel structure includes a storage structure, in which a charge blocking layer and the conductive layer and the second dielectric layer are in contact.

6. The semiconductor structure according to claim 5, characterized in that, The storage structure includes the charge blocking layer, charge trapping layer, tunneling layer and channel layer in the radially inward direction along the second channel structure.

7. The semiconductor structure according to claim 1, characterized in that, The material of the upper first dielectric layer is doped with O; and / or, the material of the lower first dielectric layer is doped with Ge.

8. The semiconductor structure according to claim 1, characterized in that, When the material of the first dielectric layer is SiN, the Si content of the upper first dielectric layer is higher than the Si content of the lower first dielectric layer.

9. The semiconductor structure according to claim 1, characterized in that, The density of the upper first dielectric layer is greater than that of the lower first dielectric layer.

10. The semiconductor structure according to claim 1, characterized in that, The deposition temperature for forming the upper first dielectric layer is higher than the deposition temperature for forming the lower first dielectric layer.

11. The semiconductor structure according to claim 1, characterized in that, The first dielectric layer further includes an intermediate first dielectric layer located between the upper first dielectric layer and the lower first dielectric layer; wherein the upper first dielectric layer has a second etch selectivity B to the intermediate first dielectric layer, where A < B ≤ 1.

12. The semiconductor structure according to claim 11, characterized in that, The intermediate first dielectric layer is multi-layered, and along the direction from the upper first dielectric layer to the lower first dielectric layer, the second etch selectivity B of the upper first dielectric layer for each intermediate first dielectric layer decreases sequentially.

13. The semiconductor structure according to claim 11, characterized in that, The intermediate first dielectric layer is multilayered, and the multilayer intermediate first dielectric layer includes at least one upper intermediate first dielectric layer and at least one lower intermediate first dielectric layer. The etching selectivity ratio of the upper first dielectric layer to each of the upper intermediate first dielectric layers is equal to 1, and the etching selectivity ratio of the upper first dielectric layer to each of the lower intermediate first dielectric layers is less than 1.

14. The semiconductor structure according to claim 11, characterized in that, The intermediate first dielectric layer is multilayered, and the multilayer intermediate first dielectric layer includes at least one upper intermediate first dielectric layer and at least one lower intermediate first dielectric layer. The etching selectivity ratio of each upper intermediate first dielectric layer to the lower first dielectric layer is less than 1, and the etching selectivity ratio of each lower intermediate first dielectric layer to the lower first dielectric layer is equal to 1.

15. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A semiconductor layer is located below the first stacked structure; wherein the distance between the lower first dielectric layer and the semiconductor layer along the stacking direction is smaller than the distance between the upper first dielectric layer and the semiconductor layer along the stacking direction.

16. The semiconductor structure according to claim 15, characterized in that, The semiconductor structure also includes: A common source structure that penetrates the first stacked structure and extends to the semiconductor layer; A doped region located within the semiconductor layer and connected to the common source structure.

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