Ferroelectric memory based on oxide semiconductor

Abstract

A ferroelectric memory based on an oxide semiconductor includes a substrate, a write electrode disposed on the substrate, a ferroelectric dielectric layer disposed on the write electrode, an oxide semiconductor layer disposed on the ferroelectric dielectric layer, a source and a drain disposed on the oxide semiconductor layer at a predetermined distance apart from each other, wherein the source and the drain are also connected to a metal plate line and a bit line, respectively, a gate insulating layer disposed on the source, the drain and the oxide semiconductor layer, and a word line disposed on the gate insulating layer, wherein the word line, the oxide semiconductor layer, the ferroelectric dielectric layer and the write electrode overlap each other in a direction perpendicular to the substrate.

Description

Technical Field

[0001] This invention relates to a ferroelectric memory, and more specifically, to a ferroelectric memory based on oxide semiconductors. Background Technology

[0002] In current memory storage technologies, traditional flash memory (FRAM) is unsuitable for frequent write applications due to its limited number of write cycles, while static random access memory (SRAM) requires too large a layout area, hindering the improvement of storage capacity and miniaturization. Ferroelectric random access memory (FRAM), as a type of random access memory, combines the advantages of the aforementioned memory types, such as small layout area and high read / write tolerance. Theoretically, FRAM can combine the non-volatile data storage characteristics of read-only memory (ROM) with the unlimited read / write cycles, high-speed read / write, and low power consumption advantages of random access memory (RAM), making it a promising next-generation memory type.

[0003] Currently, most ferroelectric memory designs are FeFET and FeRAM. FeFET has a structure similar to NAND Flash, replacing the floating gate in NAND Flash with a ferroelectric material integrated into the gate dielectric layer. Because its structure is also a field-effect transistor, it can be used as either permanent memory or a transistor. Furthermore, due to its similar structure to NAND Flash, it can also be made into a 3D structure, achieving very high storage density. FeRAM, on the other hand, has a structure similar to DRAM, using a transistor connected in series with a capacitor (1T1C architecture) to form a memory bit, except that the dielectric material in the capacitor is replaced with a ferroelectric material.

[0004] Because the existing ferroelectric memory designs integrate the ferroelectric capacitors into the gate dielectric layer or connect them in series with the source terminal of the transistor, the write operation of the memory relies on applying a voltage far exceeding the supply voltage V to the bit line at the drain terminal or the character line at the gate terminal. CC Using high voltage to achieve the write operation can easily damage transistor components. Therefore, those skilled in the art still need to improve the existing ferroelectric memory architecture to overcome the above-mentioned drawbacks. Summary of the Invention

[0005] In view of the shortcomings of the prior art, this invention proposes a novel ferroelectric RAM (FRAM) structure based on oxide semiconductor, characterized by fabricating the capacitor of the ferroelectric memory directly below the channel region of the oxide semiconductor field-effect transistor (OSFET), thereby reducing the overall layout area required for the memory. Furthermore, a write electrode is added directly below the capacitor to control the write operation of the ferroelectric memory, thus solving the problems in the prior art where the write voltage is provided only through bit lines or character lines, resulting in excessively high required write voltage and damage to transistor components.

[0006] One aspect of the present invention is to provide a ferroelectric memory based on oxide semiconductor, comprising a substrate, a write electrode disposed on the substrate, a ferroelectric dielectric layer disposed on the write electrode, an oxide semiconductor layer disposed on the ferroelectric dielectric layer, a source electrode and a drain electrode respectively disposed on the oxide semiconductor layer and separated by a predetermined distance, wherein the source electrode and the drain electrode are respectively connected to a metal plate line and a bit line, a gate insulating layer disposed on the source electrode, the drain electrode and the oxide semiconductor layer, and a character line disposed on the gate insulating layer, wherein the character line, the oxide semiconductor layer, the ferroelectric dielectric layer and the write electrode overlap each other in a direction perpendicular to the substrate.

[0007] Another aspect of the present invention is to provide a ferroelectric memory based on an oxide semiconductor, comprising a substrate, a character line disposed on the substrate, a gate insulating layer disposed on the character line, an oxide semiconductor layer disposed on the gate insulating layer, a source and a drain respectively disposed on the oxide semiconductor layer and separated by a predetermined distance, wherein the source and the drain are also respectively connected to a metal plate line and a bit line, a ferroelectric dielectric layer disposed on the source, the drain and the oxide semiconductor layer, and a write electrode disposed on the ferroelectric dielectric layer, wherein the write electrode, the ferroelectric dielectric layer, the oxide semiconductor layer, the gate insulating layer and the character line overlap each other in a direction perpendicular to the substrate.

[0008] These and other objects of the invention should become more apparent to the reader after reading the detailed description of the preferred embodiments described below with reference to various accompanying drawings and illustrations. Attached Figure Description

[0009] This specification includes accompanying drawings, which form part of this specification, to provide the reader with a further understanding of embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description herein, illustrate its principles. In these drawings:

[0010] Figure 1 This is a circuit diagram of a ferroelectric memory based on oxide semiconductor in an embodiment of the present invention;

[0011] Figure 2 This is a schematic diagram showing the voltage list of each node in a ferroelectric memory based on oxide semiconductor during read and write operations according to an embodiment of the present invention.

[0012] Figure 3 This is a cross-sectional schematic diagram of a ferroelectric memory based on oxide semiconductor according to an embodiment of the present invention; and

[0013] Figure 4 This is a cross-sectional schematic diagram of a ferroelectric memory based on oxide semiconductor in another embodiment of the present invention.

[0014] It should be noted that all illustrations in this specification are for illustrative purposes. For clarity and ease of illustration, the size and scale of the components in the figures may be exaggerated or reduced. Generally, the same reference symbols in the figures are used to indicate corresponding or similar component features in modified or different embodiments.

[0015] Symbol Explanation

[0016] 10 Ferroelectric memory

[0017] 20 Ferroelectric memory

[0018] 100 base

[0019] 101 Ferroelectric Dielectric Layer

[0020] 104 First oxide semiconductor layer

[0021] 106 Second oxide semiconductor layer

[0022] 108 gate insulation layer

[0023] 110 Protective Layer

[0024] 200 base

[0025] 201 Ferroelectric Dielectric Layer

[0026] 204 First oxide semiconductor layer

[0027] 206 Second oxide semiconductor layer

[0028] 208 gate insulation layer

[0029] 210 Protective Layer

[0030] C channel

[0031] D drain

[0032] G gate

[0033] PL metal plate wire

[0034] S source pole

[0035] WE writing electrode

[0036] WL character line

[0037] V CC Power supply voltage

[0038] V R Read voltage

[0039] V B bias Detailed Implementation

[0040] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the features described so that the reader can understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various features in the embodiments that do not conflict with each other can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0041] Readers should readily understand that the meanings of "on," "above," and "above" in this context should be interpreted broadly. "On" implies not only being "directly" on something but also includes being "on" something with an intervening feature or layer. Similarly, "above" or "above" implies not only being "above" or "above" something but also being "above" or "above" something without an intervening feature or layer (i.e., directly on something). Furthermore, spatially related terms such as "below," "under," "lower part," "above," and "upper part" are used herein for descriptive convenience to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0042] As used herein, the term "substrate" refers to the material on which subsequent material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0043] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0044] Readers can generally understand terms at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in multiple senses. Similarly, depending at least partially on the context, terms such as "a," "an," "the," or "the" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partially on the context.

[0045] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0046] First, please refer to... Figure 1 This is a circuit diagram of a ferroelectric random access memory (FRAM) 10 based on oxide semiconductor (OS) according to an embodiment of the present invention. The ferroelectric memory 10 structure of the present invention includes two main components (1T1C architecture) namely an oxide semiconductor field-effect transistor (OSFET) and a capacitor C. Figure 1As shown, an oxide semiconductor field-effect transistor (OSFET) consists of a gate (G), a source (S), and a drain (D). In a preferred embodiment of the invention, the gate (G) itself is a word line (WL), or can be connected to a word line (WL). The source (S) and drain (D) are located on opposite sides of the gate (G) and are respectively connected to a plate line (PL) and a bit line (BL). Furthermore, a ferroelectric capacitor (C) is disposed below the OSFET, with one end connected to the channel of the OSFET and the other end connected to a write electrode (WE).

[0047] Now please refer to the following: Figure 2 This is a list of voltages for each node in a ferroelectric memory based on oxide semiconductor according to an embodiment of the present invention during read and write operations. According to the foregoing... Figure 1 The circuit diagram shown indicates that during read operation, a read voltage V is applied to the bit line BL. R The signal passes through the channel of the oxide semiconductor field-effect transistor (OSFET) to the drain (D), thus achieving the function of reading the stored state of the capacitor C. At this time, a supply voltage V is applied to the character line WL (i.e., the gate G). CC To enable gate G, so that the read voltage V R It can pass through the channel connected to capacitor C, and the write electrode WE is also supplied with the supply voltage V. CC This is done to adjust the critical voltage of the channel. Thus, the reading voltage V flowing through the channel is determined. R The numerical value can determine the current logical storage state of capacitor C, such as "0" or "1".

[0048] On the other hand, memory write operations are basically divided into two types: writing to a "0" memory state and writing to a "1" memory state. In the operation of writing to a "1" memory state, no voltage is applied to the bit line BL and the character line WL, the transistor element is in the off state, and a write voltage is applied to the write electrode WE to perform the write operation on the ferroelectric capacitor C. The feature of this invention is that the write operation can be performed by voltage division using the metal plate line PL. For example, if the memory element requires a write voltage of 10V, then with the voltage on the metal plate line PL at 0V, a voltage of 10V must be applied to the write electrode WE to achieve the write operation. Considering that excessive voltage can easily damage the element, it can be changed to applying -5V and +5V bias voltages to the metal plate line PL and the write electrode WE respectively, thus achieving a 10V voltage difference at the capacitor C to achieve the write operation. The voltage division design of the write electrode WE and the metal plate line PL described above in this invention can divide the required write voltage into +V... B / 2 and -V BA / 2 bias voltage is applied from different nodes to reduce the required bias voltage. Similarly, in writing a "0" operation, the opposite of writing a "1" is achieved by applying +V to the PL terminal of the metal plate line and the WE terminal of the write electrode, respectively. B / 2 and -V B A bias voltage of / 2 is used to achieve the action of writing to the opposite storage state.

[0049] As can be seen from the above operation, the component design of this invention allows the read and write operations of the memory to have different paths. Conventional existing technologies typically employ a design that connects ferroelectric capacitors in series with the source terminal of the transistor or integrates them into the gate dielectric layer. While such designs do not require additional write electrodes as in this invention, they must rely on bit lines or character lines to apply voltages far exceeding the supply voltage V. CC Using a high voltage to perform a write operation can easily damage transistor components. This invention proposes a method of connecting the two ends of a ferroelectric capacitor to the transistor channel and an additional write electrode without increasing the cell layout area. This separates the memory read and write paths, and the memory write operation does not pass through the bit line or character line. In addition, the voltage can be divided between the write electrode WE and the metal plate line PL, thus reducing the risk of damage to the oxide semiconductor field-effect transistor (OSFET).

[0050] Please refer to now. Figure 3 This is a cross-sectional schematic diagram of a ferroelectric memory based on an oxide semiconductor according to an embodiment of the present invention. This cross-sectional diagram illustrates the structural composition of the ferroelectric memory structure of the present invention in the direction perpendicular to the substrate. Figure 3As shown, the ferroelectric memory 10 of the present invention includes a substrate 100, which serves as the basis for the entire ferroelectric memory element. The substrate 100 can be any component with a load-bearing function, such as a semiconductor substrate, including silicon-containing substrates, silicon-on-insulator (SOI) substrates, sapphire substrates, etc., but is not limited thereto. The surface of the substrate 100 includes an insulating layer (not shown), which can be a nitrogen-containing silicon layer, such as silicon nitride, silicon oxynitride, etc. A write electrode WE is formed on the surface of the substrate 100, for example, disposed on the aforementioned insulating layer. The write electrode WE can be a conductive layer, such as a metal layer of copper (Cu), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), etc. Alternatively, its material can be a nitride of the aforementioned metal elements, such as titanium nitride, molybdenum nitride, tungsten nitride, etc. Alternatively, the material can be a conductive metal oxide, such as indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), indium oxide-tin oxide (In₂O₃-SnO₂), or indium oxide-zinc oxide (In₂O₃-ZnO). In other embodiments, the write electrode WE may also be part of a metal interconnect structure, integrated in the back-end semiconductor fabrication (BEOL) process. A ferroelectric dielectric layer 101 is formed on the write electrode WE, covering and directly contacting the surface of the write electrode WE. In this embodiment of the invention, the ferroelectric dielectric layer 101 is the storage site of the ferroelectric memory 10, which can change its storage state, such as "0" or "1", by applying a voltage to achieve storage functionality. The material of the ferroelectric dielectric layer 101 can be a ferroelectric material, such as lead zirconate titanate (PZT), hafnium zirconium oxide (HZO), barium titanate (BaTiO3), lead titanate (PbTiO3), and hafnium dioxide (HfO2) doped with elements such as nitrogen, silicon, aluminum, yttrium, and strontium.

[0051] Rereference Figure 3 A first oxide semiconductor layer 104 and a second oxide semiconductor layer 106 are sequentially formed on the surface of the ferroelectric dielectric layer 101. In this embodiment of the invention, the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 serve as the channel of an oxide semiconductor field-effect transistor (OSFET), and are made of an oxide semiconductor material, such as gallium oxide (GaO). X Gallium zinc oxide (Ga2Zn) x O yThe first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 may contain the same or similar elements, but have different compositions. For example, both the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 may be composed of indium gallium zinc oxide, but the atomic ratio of indium / gallium / zinc in the second oxide semiconductor layer 106 may be 1:1:1 or 3:1:2, while the atomic ratio of indium / gallium / zinc in the first oxide semiconductor layer 104 is 1:3:1, meaning that the first oxide semiconductor layer 104 will have a higher gallium content and a lower indium content. Since the bandgap of the oxide semiconductor layer can be controlled by adjusting the ratio between indium and gallium, the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106, which have the same elements but different proportions, can stabilize the interface and reduce charge trapping at the interface, thereby avoiding transistor degradation and increasing reliability. In some embodiments, the crystallinity of the first oxide semiconductor layer 104 is lower than that of the second oxide semiconductor layer 106. In some embodiments, the first oxide semiconductor layer 104 and the second oxide semiconductor layer 106 can be considered as the same oxide semiconductor layer, having the same elemental composition, proportion, and crystallinity.

[0052] In a preferred embodiment of the present invention, the aforementioned write electrode WE, ferroelectric dielectric layer 101, first oxide semiconductor layer 104, and second oxide semiconductor layer 106 are sequentially aligned, stacked, and in direct contact with each other, and can be patterned into an island shape by an etching process. The first and second oxide semiconductor layers 104, 106, the ferroelectric dielectric layer 101, and the write electrode WE constitute a ferroelectric capacitor similar to a metal-insulator-metal (MIM) capacitor structure. This ferroelectric capacitor serves as the storage location of the ferroelectric memory 10, achieving read functionality through an oxide semiconductor field-effect transistor directly above it, and achieving write functionality using the voltage difference between its upper electrode (i.e., the first and second oxide semiconductor layers 104, 106) and lower electrode (i.e., the write electrode WE). In other embodiments, electrode plates may be additionally formed on both sides of the ferroelectric dielectric layer 101 to connect with the write electrode WE and the first and second oxide semiconductor layers 104, 106 respectively, without limitation. In this invention, since the ferroelectric capacitor is designed to be placed directly below the oxide semiconductor field-effect transistor, the structural design of this invention can reduce the overall layout area required for the memory compared to the prior art, and can be applied to three-dimensional single-crystal integration (M3D) technology.

[0053] Rereference Figure 3In the ferroelectric memory 10, a source electrode S and a drain electrode D are formed on the second oxide semiconductor layer 106, respectively, and are separated from each other by a predetermined distance. They are in direct contact with the first and second oxide semiconductor layers 104 and 106 and extend to the substrates 100 on both sides. In an embodiment, the source electrode S and the drain electrode D overlap with portions of the first oxide semiconductor layer 104, the second oxide semiconductor layer 106, and the ferroelectric dielectric layer 101, but do not overlap with the write electrode WE. Symmetrically about the write electrode WE, a portion of the second oxide semiconductor layer 106 is exposed from the trench between the source electrode S and the drain electrode D. The materials of the source electrode S and the drain electrode D can be the same as those of the write electrode WE, such as copper (Cu), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), etc. Alternatively, their materials can be nitrides of the above-mentioned metal elements, such as titanium nitride, molybdenum nitride, tungsten nitride, etc. Alternatively, the material can be a conductive metal oxide, such as indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide-tin oxide (In2O3-SnO2), indium oxide-zinc oxide, etc. In an embodiment, the source S and drain D can be connected upwards to a metal plate line PL and a bit line BL (not shown) respectively via contacts (not shown) to receive / transmit signals or voltages from these components to achieve read or write operations of the memory.

[0054] Rereference Figure 3A gate insulating layer 108 is formed on the source electrode S and drain electrode D, conformally covering the source electrode S, drain electrode D, and the exposed second oxide semiconductor layer 106. The gate insulating layer 108 can be made of silicon oxide, silicon nitride, silicon oxynitride, or a high-k material such as hafnium oxide. In some embodiments, the gate insulating layer 108 preferably contains some of the metal elements contained in the second oxide semiconductor layer 106, such as aluminum, gallium, zinc, etc., to reduce charge trapping at the interface and the generation of parasitic channels. In addition, in embodiments, a thicker protective layer 110 may be formed above the gate insulating layer 108, the material of which may be the same as that of the gate insulating layer 108, including silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, gallium oxide, zinc gallium oxide, etc. A gate electrode G is formed on the protective layer 110 at a position relative to the lower write electrode WE. The gate G, protective layer 110, gate insulating layer 108, source S and drain D, and first and second oxide semiconductor layers 104 and 106 constitute an oxide semiconductor field-effect transistor. In a preferred embodiment of the present invention, the gate G is the character line WL of the ferroelectric memory 10, which can receive the supply voltage to control the switching of the oxide semiconductor field-effect transistor. The material of the gate G can be the same as that of the write electrode WE, such as copper (Cu), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), etc. Alternatively, its material can be a nitride of the above-mentioned metal elements, such as titanium nitride, molybdenum nitride, tungsten nitride, etc. Or, its material can be a conductive metal oxide, such as indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide-tin oxide (In2O3-SnO2), indium oxide-zinc oxide, etc. In other embodiments, the gate G may also be connected upward to a character line.

[0055] Please refer to now. Figure 4 This is a cross-sectional schematic diagram of a ferroelectric memory 20 based on an oxide semiconductor according to another embodiment of the present invention. This embodiment is similar to the one described above. Figure 3 The components in the embodiments are largely the same, differing only in their arrangement. In this embodiment, the write electrode WE is positioned above the oxide semiconductor field-effect transistor, while the gate G is positioned below it.

[0056] like Figure 4As shown, the ferroelectric memory 20 of the present invention includes a substrate 200, which serves as the basis for the entire ferroelectric memory element. A gate G is formed on the substrate 200. In this embodiment, the gate G is the character line WL of the ferroelectric memory 20, which can receive a supply voltage to control the switching of the oxide semiconductor field-effect transistor. A gate insulating layer 208 conformally covers the gate G. A first oxide semiconductor layer 204 and a second oxide semiconductor layer 206 are sequentially formed on the surface of the gate insulating layer 208. In this embodiment, the first oxide semiconductor layer 204 and the second oxide semiconductor layer 206 serve as the channel of the oxide semiconductor field-effect transistor. The aforementioned gate G, gate insulating layer 208, first oxide semiconductor layer 204, and second oxide semiconductor layer 206 are sequentially aligned, stacked, and in direct contact with each other, and can be patterned into an island shape by an etching process. In the ferroelectric memory 20, a source S and a drain D are formed on the second oxide semiconductor layer 106, respectively, and are separated from each other by a predetermined distance. They are in direct contact with the first and second oxide semiconductor layers 204 and 206 and extend to the substrates 200 on both sides. In an embodiment, the source S and drain D overlap with portions of the first oxide semiconductor layer 204, the second oxide semiconductor layer 206, and the gate insulating layer 208, but do not overlap with the gate G. Symmetrical about the gate G, a portion of the second oxide semiconductor layer 206 is exposed from the trench between the source S and the drain D. The gate G, the gate insulating layer 208, the source S and drain D, and the first and second oxide semiconductor layers 204 and 206 constitute an oxide semiconductor field-effect transistor.

[0057] Rereference Figure 4A ferroelectric dielectric layer 201 and a protective layer 210 are sequentially formed on the source S and drain D, conformally covering the source S, drain D, and the exposed second oxide semiconductor layer 206. The ferroelectric dielectric layer 201 is the storage site of the ferroelectric memory 20, and its storage state, such as "0" or "1", can be changed by applying a voltage to achieve storage. A write electrode WE is formed on the protective layer 210 at a position relative to the lower gate G, with the protective layer 210 situated between the ferroelectric dielectric layer 201 and the write electrode WE. In this embodiment, a portion of the write electrode WE passes through the protective layer 210 and contacts the lower ferroelectric dielectric layer 201. The first and second oxide semiconductor layers 204, 206, the ferroelectric dielectric layer 201, and the write electrode WE constitute a ferroelectric capacitor with a structure similar to a metal-insulator-metal (MIM) capacitor. The ferroelectric capacitor serves as the storage location of the ferroelectric memory 20, and its read function is achieved through the oxide semiconductor field-effect transistor directly beneath it. Its write function is achieved using the voltage difference between its upper electrode (i.e., the write electrode WE) and its lower electrode (i.e., the first and second oxide semiconductor layers 204, 206). The materials and operating principles of the components in the above embodiments are similar to those described above. Figure 3 The implementation methods are the same, so they will not be described in detail here.

[0058] Based on the above embodiments, it can be understood that the ferroelectric memory of the present invention includes an oxide semiconductor field-effect transistor (OSP) and a ferroelectric capacitor disposed below or above the OSP. Its key feature is that data stored in the ferroelectric capacitor is read through the OSP, and the ferroelectric memory is written to through the write electrode of the ferroelectric capacitor. Compared to the prior art, its advantages include a significant reduction in component layout area, making it suitable for three-dimensional single-crystal integration technology. Furthermore, the write electrode reduces the voltage load on the transistor component, lowering the risk of component degradation or damage.

[0059] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A ferroelectric memory based on oxide semiconductor, comprising: Base; Write electrodes are disposed on this substrate; A ferroelectric dielectric layer is disposed on the write electrode; An oxide semiconductor layer is disposed on the ferroelectric dielectric layer; The source and drain are respectively disposed on the oxide semiconductor layer and separated by a predetermined distance. The source and drain are also respectively connected to the metal plate line and the bit line. During the write operation, the write electrode is biased and the metal plate line is reverse biased to write data to the ferroelectric dielectric layer. A gate insulating layer is disposed on the source, the drain, and the oxide semiconductor layer; as well as A character line is disposed on the gate insulating layer, wherein the character line, the oxide semiconductor layer, the ferroelectric dielectric layer, and the write electrode overlap each other in a direction perpendicular to the substrate.

2. The ferroelectric memory based on oxide semiconductor as described in claim 1 further includes a protective layer disposed on the gate insulating layer and between the character line and the gate insulating layer.

3. The ferroelectric memory based on oxide semiconductor as claimed in claim 1, wherein the source and the drain do not overlap with the write electrode in a direction perpendicular to the substrate.

4. The ferroelectric memory based on oxide semiconductor as claimed in claim 1, wherein the substrate surface includes an insulating layer, and the write electrode is disposed on the insulating layer.

5. The ferroelectric memory based on oxide semiconductor as claimed in claim 1, wherein during read operation, a read voltage is applied to the bit line to read data stored in the ferroelectric dielectric layer.

6. The ferroelectric memory based on oxide semiconductor as claimed in claim 1, wherein during a read operation, a supply voltage is applied to the character line to open a channel in the oxide semiconductor layer, and the supply voltage is applied to the write electrode to adjust a threshold voltage of the channel.

7. A ferroelectric memory based on oxide semiconductor, comprising: Base; Character lines are set on this base; A grid insulating layer is disposed on the character line; An oxide semiconductor layer is disposed on the gate insulating layer; The source and drain are respectively disposed on the oxide semiconductor layer and separated by a predetermined distance, wherein the source and drain are also respectively connected to the metal plate line and the bit line; A ferroelectric dielectric layer is disposed on the source, the drain, and the oxide semiconductor layer; and A write electrode is disposed on the ferroelectric dielectric layer, wherein the write electrode, the ferroelectric dielectric layer, the oxide semiconductor layer, the gate insulating layer, and the character line overlap each other in a direction perpendicular to the substrate, wherein during write operation, the write electrode is biased and the metal plate line is reverse biased to write data to the ferroelectric dielectric layer.

8. The ferroelectric memory based on oxide semiconductor as claimed in claim 7, further comprising a protective layer between the ferroelectric dielectric layer and the write electrode, wherein a portion of the write electrode passes through the protective layer and contacts the ferroelectric dielectric layer.

9. The ferroelectric memory based on oxide semiconductor as claimed in claim 7, wherein the source and the drain do not overlap with the character line in a direction perpendicular to the substrate.

10. The ferroelectric memory based on oxide semiconductor as claimed in claim 7, wherein the substrate surface includes an insulating layer, and the character line is disposed on the insulating layer.

11. The ferroelectric memory based on oxide semiconductor as claimed in claim 7, wherein during a read operation, a read voltage is applied to the bit line to read data stored in the ferroelectric dielectric layer.

12. The ferroelectric memory based on oxide semiconductor as claimed in claim 11, wherein during a read operation, a supply voltage is applied to the character line to open a channel in the oxide semiconductor layer, and the supply voltage is applied to the write electrode to adjust a threshold voltage of the channel.

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