An interpreter of reconfigurable cryptographic algorithms based on custom high-level c language

Abstract

The application provides an interpreter of a reconfigurable cryptographic algorithm based on a customized high-level C language, and belongs to the technical field of information security. The interpreter comprises an input program of a cryptographic algorithm customization language, a compiling optimization module, a generation module of an intermediate file and a data flow graph, a mapping module and an array generation configuration code module. The application provides an automatic mapping tool for a reconfigurable processor, which can take the customized high-level C language as input. The interpreter arranges and connects computing units such as operators according to the program setting mode, so as to complete the mapping of the whole computing function. This mode can not only shorten the development cycle of the reconfigurable system, but also reduce the need for the user's hardware mastering degree, so that the computing function units of each part are mapped to the reconfigurable processor in a more optimized mode, and the performance of the reconfigurable processor is further effectively improved.

Description

TECHNICAL FIELD

[0001] The application relates to the design of a reconfigurable system chip compiler for information security applications, in particular to an interpreter for reconfigurable cryptographic algorithms based on a customized high-level C language, and belongs to the technical field of information security. BACKGROUND

[0002] Reconfigurable processors have obvious energy efficiency advantages, combining the high performance of application specific integrated circuits (ASIC) and the flexibility of general purpose processors (GPP), and thus have attracted widespread attention. For reconfigurable processors, flexibility is reflected in the fact that users can configure the computing functions of hardware, and high performance is achieved by using hardware parallel computing. However, the configuration scheme often becomes the key to computing performance when implementing a certain computing function. Because the computing units and storage resources of reconfigurable processors need to be combined with the characteristics of application programs in terms of time and space, the difficulty of algorithm mapping is increased. In this context, the mapping process of algorithms on reconfigurable processors is often completed manually. However, manual configuration has the disadvantages of long time, unstable effect, high error rate, etc. Traditional compilation techniques mainly target instruction set-based serial general-purpose processors and cannot meet the mapping problem of parallel reconfigurable processors based on data flow graphs (DFG). Therefore, how to effectively and efficiently map computing functions to reconfigurable processors by combining the structural characteristics and resource characteristics of reconfigurable processors has become a research hotspot and difficulty in the field of reconfigurable systems. An automatic mapping tool for reconfigurable processors can not only shorten the development cycle of reconfigurable systems, but also map the computing functions required by users to reconfigurable processors in a more optimized way, thereby effectively improving performance. Therefore, the automatic mapping tool has become an indispensable part of reconfigurable systems.

[0003] The implementation of cryptographic algorithms is one of the important goals of high-performance processor design and application. Cryptographic algorithm reconfigurable processors are typical representatives of special domain reconfigurable processor structures. Unlike other computing functions, cryptographic algorithms have the characteristics of "confusion" and "diffusion", and the data computation is complex and staggered. Therefore, the research on automatic mapping technology for cryptographic algorithm reconfigurable processors is more challenging and valuable.

[0004] Reconfigurable processors share similar computational capabilities with ASICs, performing parallel computation and data transfer directly through circuitry, thus possessing high computational performance. However, unlike ASICs, the computational functions of a reconfigurable processor can be altered through internal reconfiguration operations. This variability in computational function gives reconfigurable processors the same flexibility as Geometric Producers (GPPs). However, compared to the serial, one-dimensional functional configuration of GPPs, the parallel, two-dimensional functional configuration in reconfigurable processors presents greater challenges. In reconfigurable processors, computation is typically handled by a two-dimensional array, such as... Figure 1 As shown, this is called a Reconfigurable Computing Array (RCA). The RCA contains many configurable processing elements (PEs) and configurable routing interfaces (IRs). The former performs data computation, while the latter facilitates data flow. The operation of configuring computational functions onto the RCA is called mapping. The purpose of mapping is to correctly and efficiently configure and implement computational functions within the RCA. Therefore, the quality of the mapping is crucial for the reconfigurable processor to achieve its high-performance characteristics.

[0005] In the absence of automatic mapping tools, manual mapping is the only option for users when using reconfigurable processors. Currently, automatic mapping technology is not mature, which has led to manual mapping becoming the current choice for some smaller organizations. However, manual mapping has the following significant drawbacks:

[0006] (1) High requirements are placed on the mapping personnel, who need to be very familiar with the computing functions and array structure.

[0007] (2) The mapping time cost is high, requiring a lot of time for functional analysis, array analysis, layout and routing and adjustment.

[0008] (3) The mapping effect is not good or uneven, and different mapping personnel will get different configuration results.

[0009] (4) Lacks tolerance for hardware changes; manual remapping is required when the array structure changes.

[0010] In comparison, automatic mapping is fast and effective, avoiding the drawbacks of manual mapping. Therefore, it has become an indispensable part of reconfigurable systems. Furthermore, traditional mature compilation techniques cannot be directly applied to reconfigurable mapping problems, making automatic mapping technology a research hotspot in the field of reconfigurability.

[0011] At present, the research of reconfigurable processor structure for special field is a hot direction, and the wide application scene of the cryptographic algorithm makes the reconfigurable processor for the cryptographic algorithm become one of the typical representatives. In order to realize the general function, the calculation form of the general calculation is simple and clear, and in order to improve the security level of the ciphertext, the cryptographic algorithm as the algorithm in the security field must decouple the ciphertext and plaintext as much as possible, so a large amount of complex data calculation is usually carried out, and compared with the general calculation, the manual mapping of the cryptographic algorithm has more shortcomings in the requirements of the mapping personnel, the mapping time and the mapping effect. At present, the research of the reconfigurable technology for the cryptographic algorithm is more inclined to the research of the array structure, and other manual mapping schemes for specific cryptographic algorithms are also researched, and the research of the automatic mapping technology is not much, so the manual mapping becomes the only choice of some institutions at present, which seriously delays the system development cycle, so the research of the automatic mapping technology of the reconfigurable processor for the cryptographic algorithm is still very urgent, and its importance is self-evident.

[0012] Based on the above background, the design of the compiler of the reconfigurable cryptographic chip for information security has become a hot research problem. The existing compiler tool design of the reconfigurable chip based on the cryptographic algorithm has been optimized to a certain extent, but in the actual application, due to the different structures of the hardware and the different input languages, the design scheme of the compiler also has certain differences. SUMMARY

[0013] In order to solve the above problems, the application provides a reconfigurable cryptographic algorithm interpreter based on a customized high-level C language, which solves the problems of high requirements for mapping personnel, long time period, poor mapping effect and poor hardware change tolerance in the case that the existing mapping technology is not mature enough.

[0014] In order to achieve the above purpose, the application provides the following technical scheme:

[0015] A reconfigurable cryptographic algorithm interpreter based on a customized high-level C language, comprising a cryptographic algorithm customized language input program, a compilation optimization module, an intermediate file and / or a data flow graph generation module, a mapping module and an array generation configuration code module.

[0016] The input program of the cryptographic algorithm customization language is an input program written in a customized high-level C language; the compiling optimization module comprises a software and hardware division unit, a hardware code optimization unit, a hardware code compiling unit and a software compiling and linking unit, the software and hardware division unit is configured to add annotations to a loop body to mark hardware code; the hardware code optimization unit is configured to rewrite the marked hardware code according to code specifications of hardware function implementation; the hardware code compiling unit comprises a source file and a plurality of functional units for compiling code; the software compiling and linking unit is configured to link symbols generated in different compiling units to form an executable program; the intermediate file generation module is configured to convert a data packet generated by the input program through the front-end compiling optimization module into an intermediate file in a fixed format; the mapping module is configured to map the input intermediate file into a flowchart of a corresponding algorithm according to a fixed mapping mode; and the array generation configuration code module is configured to extract configuration information from the mapped flowchart and convert the configuration information into configuration code for configuring a corresponding hardware architecture through compression.

[0017] Further, the hardware code optimization unit adopts BFU, SBOX and BENES operators for code optimization.

[0018] Further, the process of optimizing by using the BFU operator comprises:

[0019] 1. According to the algorithm, determine the operation number and the mode of the modular operation that need to be processed, and assign values to the three inputs A, B and T of the function and the mode of the modular operation that need to be processed;

[0020] 2. According to the BFU operator function implementation scheme, determine the BFU function that needs to be implemented, and pass the parameters to the operator function func, which will select the specific calculation operator according to the parameters in the function;

[0021] 3. In the bottom layer of the function, specify the relevant input and output parameters of the specific operator that needs to be implemented, set according to the BFU operator function implementation scheme, and complete the final packaging;

[0022] 4. Pass the parameters to be output to the result output X and the bypass output Y.

[0023] Further, the process of optimizing by using the SBOX operator comprises:

[0024] 1. Use lookup table resources as much as possible, each lookup table is divided into two 256x32 sub-lookup tables, select different sub-lookup tables according to 1-bit group configuration or select which bits in 32 bits as valid data output according to 2-bit byte_sel configuration;

[0025] 2: Each SBOX has four tables inside, each table is divided into eight small tables according to the group configuration and byte_sel configuration;

[0026] 3: The function bottom layer is encapsulated according to the SBOX function implementation scheme table.

[0027] Further, the process of optimizing by using the BENES operator includes:

[0028] 1: Determine the input and output function parameters;

[0029] 2: The function bottom layer uses an NxN BENES permutation unit to realize all selection transformations of N inputs and N outputs, that is, any one of the N outputs of the NxN permutation unit can select any one of the N inputs, and the number of configuration bits required by the BENES128 is determined by the formula BENES(N).length=(n / 2)*(2*log2(n)-1);

[0030] 3: Save the data unit after permutation and wait for subsequent use.

[0031] Further, the code rewritten by the hardware code optimization unit supports at most two levels of For loop nesting.

[0032] Further, when there is only a one-level loop Loop, a single-layer for loop is used to realize it, and the For loop is marked with a tag according to the software and hardware division specification; when there is a two-level loop Loop, a two-layer For loop is used to realize it, the outer layer corresponds to the two-level loop, and the inner layer corresponds to the one-level loop, the outer For loop does not need to be marked with a tag, and the inner For loop is marked with a tag according to the software and hardware division specification.

[0033] Further, the tag is used to extract the innermost loop body, and the innermost loop body is mapped to an array for processing, and the outside of the loop body is run by software.

[0034] Further, the BENES operator is used to realize the permutation function of nonlinear operation bits

[0035] Further, the mapping module maps the corresponding operator function to a fixed operator icon.

[0036] Compared with the prior art, the present application has the following advantages and beneficial effects:

[0037] 1. The application provides an automatic mapping tool for reconfigurable processor, which can take customized high-level C language as input, and an interpreter arranges and connects computing units such as operators according to the input high-level C program, so as to complete the mapping of the entire computing function, which can not only shorten the development cycle of the reconfigurable system, but also reduce the need for users to master hardware, so that the computing function units of each part are mapped to the reconfigurable processor in an optimized manner, and the performance of the reconfigurable processor is further improved effectively.

[0038] 2. The application provides an interpreter for reconfigurable cryptographic algorithm based on customized high-level C language, which has the characteristics of fast speed and good effect, and overcomes the defects that the personnel requirement for the mapping algorithm is high and the computing function and array must be very familiar.

[0039] 3. The design input based on customized language is adopted, only the corresponding software code needs to be written, and a large amount of time is not needed to spend on function analysis, array analysis, layout and wiring and adjustment of operators and other steps, so that the mapping cost is greatly reduced.

[0040] 4. The problem that the performance structures of algorithms configured by different mapping personnel are inconsistent is avoided, and the uneven mapping effect is avoided.

[0041] 5. The application scheme has good hardware inclusiveness, when the array structure changes, a manual mapping change scheme does not need to be reconfigured. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 It is a reconfigurable computing unit RCA structure schematic diagram.

[0043] Figure 2 It is a simplified compilation framework of the overall compilation framework and reconfigurable mapping of the application, wherein (a) is the overall compilation framework, and (b) is the simplified compilation framework of the reconfigurable mapping.

[0044] Figure 3 It is a mark cycle example of software and hardware division of the application.

[0045] Figure 4 It is a structure schematic diagram of the BFU computing module of the application.

[0046] Figure 5 It is a SBOX lookup schematic diagram.

[0047] Figure 6 It is a BENES 128 bit schematic diagram. DETAILED DESCRIPTION

[0048] The technical solutions provided by the present application will be described in detail below in combination with specific embodiments. It should be understood that the following specific embodiments are only used to illustrate the present application and not to limit the scope of the present application.

[0049] The overall compilation framework for implementing the present application is shown in (a) of FIG. 1, and the interpreter for reconfigurable cryptographic algorithm based on customized high-level C language provided by the present application is improved based on the dashed oval frame part in (a), and specifically includes the input program of cryptographic algorithm customization language, the front-end compilation optimization module, the intermediate file generation module, the back-end mapping module and the array generation configuration code module. Figure 2

[0050] The input program of cryptographic algorithm customization language contains an extended special field language based on standard C language, and the input program contains the writing of built-in functions such as BFU, SBOX and BENES. In order to improve the performance of the mapped hardware circuit, an extended language of standard C language is designed as the input language. The following points should be noted in the design of the extended C language:

[0051] (1) No logical judgment statement is needed, because there is no inevitable logical judgment statement in the cryptographic algorithm, and there is also no corresponding function in the calculation array;

[0052] (2) No loop statement containing complex logical judgment is needed, and the loop statement containing loop number information is needed, and the following two points should be noted for the second loop:

[0053] ◆ Only the Loop of the first loop is implemented by using a single-layer for loop. The for loop is marked with a tag according to the soft and hardware code division specification.

[0054] ◆ The Loop of the second loop is implemented by using two-layer for loop. The outer layer corresponds to the second loop, and the inner layer corresponds to the first loop.

[0055] The outer for loop does not need to be marked with a tag, and the inner for loop is marked with a tag according to the soft and hardware code division specification. Refer to the programming example.

[0056] (3) Special built-in functions are needed to represent some special calculations. Among them, the functions of LU, SU, AU and MU operators are all combinations of simple operations, which can be represented by ordinary expressions, while nonlinear operations such as table lookup and permutation cannot be represented by ordinary expressions, and therefore special built-in functions need to be designed for them.

[0057] The front-end compilation optimization module includes a soft and hardware division unit, a hardware code optimization unit, a hardware code compilation unit and a software compilation and linking unit.

[0058] ​The hardware and software division unit is configured to add a comment ( / / DFG loop) to the loop body to mark the hardware code, and the RCA only extracts the innermost loop body to map to an array for processing. Figure 3 The code example of the marked loop for the software division is shown in the source code. The loop is marked according to the requirements. The innermost loop body is extracted by using the mark, and the loop body is mapped to an array for processing. The outer part of the loop body is run by software.

[0059] The hardware code optimization unit is configured to rewrite the marked hardware code according to the code specification of the hardware function implementation.

[0060] The hardware code compilation unit contains a single source file with all necessary information, and contains necessary units for compiling all contents (contents contained in the source file, such as header files, etc.) and its own contents (its own program).

[0061] The software compilation and linking unit is configured to associate the symbols generated in different compilation units to form an executable program.

[0062] Based on the above-mentioned extended C language design, the code specification is: at most only two layers of For loop nesting are supported, and while and other irregular loops are not supported; the coding inside the loop body does not support pointers, and recursive calls are not supported; BFU, SBOX, and BENES operators are used for programming.

[0063] As shown in Figure 4 , the BFU operator can implement addition operation (AU), logical operation (LU), shift operation (SU), and multiplication operation (MU). Each BFU unit has 3 inputs of 32 bits, and has 2 outputs of 32 bits. The three inputs of the BFU are named A, B, and T, and the outputs are named X and Y, wherein X is the result output and Y is the bypass output. The REG register unit in the operator can temporarily store the calculation structure of the BFU calculation, and can output X\Y when receiving the output or calling the CMD. The definition of the function is int*BFU(int a,int b,int t,char*func,char*exp,int bypass,char*bypassExp,int mode); wherein a, b, and t are input parameters of the BFU operator; func is the function of the BFU operator: lu, au, su, and mu; exp is the expression implemented by the BFU: such as A^B; bypass is an input, and takes a value of 0-3, 0: A, 1: B, 2: T, and 3: B; bypassExp is the bypass expression; mode is the modulus operation to be processed, and takes a value of 0-3, 0: 2 32 , 1: 2 16 , 2: 2 8 , and 3: 231 -1; return value is int pointer points to two outputs of BFU, directly used after BFU function call. The specific implementation process of BFU operator is as follows:

[0064] 1: According to the algorithm, determine the operation number and the processing mode of the modular operation, and assign A, B, T and mode to the function respectively;

[0065] 2: According to the BFU operator function implementation scheme, determine the BFU function to be implemented, and pass the parameters to func. The function will select the specific calculation operator according to the parameters;

[0066] 3: In the function bottom, the specific operator to be implemented is specified, the related input and output parameters are specified, and the BFU operator function implementation scheme in table 1 is set. The specific implementation scheme of AU and MU operators is shown in table 2 and table 3, and the implementation of LU and SU according to the related logical function requirements can be completed, and finally encapsulated;

[0067] 4: Pass the parameters to be output to X and Y;

[0068]

[0069]

[0070] Table 1

[0071]

[0072]

[0073] Table 2

[0074]

[0075] Table 3

[0076] As Figure 5As shown, SBOX is a nonlinear lookup unit, and there are four SBOXs in a reconfigurable configuration line, and each SBOX has four lookup tables. In order to make the best use of the lookup table resources, each lookup table is divided into two sub-lookup tables, and different sub-lookup tables are selected according to 1-bit group configuration. Meanwhile, SBOX has different modes to realize different lookup functions. The function definition is int * SBOX (int a, int mode, char * src, int id0, int id1, int id2, int id3); wherein a is the input parameter of SBOX operator; mode is the splicing mode of SBOX, and the value is 0-7, 0: 4->4 splicing, 1: 6->4 splicing, 2: 8->8 splicing, 3: 8->8 XOR, 4: 8->32, 5: 9->9 one way, 6: 10->8 one way, and 7: 12->8 one way; src is the SBOX data source file name; id0-id3 correspond to the values of the four groups of SBOX, and the value range is 0-3; and the return value int pointer points to the four outputs of SBOX, which is directly used after SBOX function call. The specific implementation process of SBOX includes the following steps:

[0077] 1: In order to make the best use of the lookup table resources, each lookup table is divided into two sub-lookup tables, and different sub-lookup tables are selected according to 1-bit group configuration. In some lookup table modes, 32 bits can be selected as valid data output according to 2-bit byte_sel configuration;

[0078] 2: Each SBOX has four tables, and each table can be divided into eight small tables according to group configuration and byte_sel configuration;

[0079] 3: The implementation function of each table is shown in Table 4, and the function is encapsulated according to the table.

[0080]

[0081]

[0082] Table 4

[0083] As Figure 6The BENES operator shown is used to realize the permutation function of nonlinear operation bits, the input of the BENES is four 32-bit operators, and the output is four 32-bit data, which realizes the permutation of any bit of 128-bit data, the RCU contains a 128-bit BENES used for bit permutation. The definition of the function is int*BENES(int a, int b, int c, int d, char*src), wherein a, b, c, d are four input parameters of the BENES operator; src is the file name of the BENES data source; the return value int pointer points to the four outputs of the BENES, which is directly used after the BENES function is called. The specific implementation scheme of the BENES is as follows:

[0084] 1: Determine the input and output function parameters, that is, input four 32-bit operators a, b, c, d;

[0085] 2: The bottom layer of the function uses a NxN BENES permutation unit to realize all selection transformations of N inputs and N outputs, that is, any one of the N outputs of the NxN permutation unit can select any one of the N inputs. The configuration bit number required by the BENES128 is calculated by the formula BENES(N).length=(n / 2)*(2*log2(n)-1)=832bit, wherein n is the number of bits of the input of the BENES unit, that is, 128.

[0086] 3: Save the data unit after permutation and wait for subsequent use.

[0087] The intermediate file generation module is used to convert the data packet generated by the front-end compilation optimization module to an intermediate file in a fixed format, wherein the intermediate file includes a data flow graph.

[0088] The mapping module is used to map the input intermediate file into a flowchart of a corresponding algorithm according to a fixed mapping mode. In this part, the application will one-to-one convert the customized C language to map the corresponding operator function into a fixed operator icon, for example, mapping the BFU operator function into the corresponding BFU operator icon in the array.

[0089] The array generation configuration code module: extracts configuration information from the data flowchart after program mapping, and compresses and converts the configuration information into a configuration code in a certain way. The configuration code can be used to configure the corresponding hardware architecture, that is, the array configuration code available for the RCA.

[0090] The application can take customized advanced C language as input, and the compiler arranges and connects the calculation units such as operators according to the input advanced C program in a manner set by the program, so as to complete the mapping of the whole calculation function. The application scheme is integrated in an open source CGRA-ME evaluation framework, and the target architecture file of the data flow representation required by the target hardware architecture is generated by compilation.

[0091] The technical means disclosed by the application scheme is not limited to the technical means disclosed by the above-mentioned embodiments, and also includes the technical scheme composed of any combination of the above technical features. It should be pointed out that, for ordinary skilled persons in the art, some improvements and refinements can be made without departing from the principles of the application, and these improvements and refinements are also considered within the protection scope of the application.

Claims

1. An interpreter for a reconfigurable cryptographic algorithm based on a custom high-level C language, characterized in that, It includes an input program for a custom language of cryptographic algorithms, a compilation and optimization module, a module for generating intermediate files and data flow graphs, a mapping module, and a module for generating configuration codes from arrays; The input program for the custom language of the cryptographic algorithm is an input program written in a custom high-level C language; the compilation optimization module includes a hardware / software partitioning unit, a hardware code optimization unit, a hardware code compilation unit, and a software compilation and linking unit. The hardware / software partitioning unit is used to add comments to the loop body to mark the hardware code. The hardware code optimization unit is used to rewrite the marked hardware code according to the code specifications for hardware function implementation. The hardware code optimization unit uses BFU, SBOX, and BENES operators for code optimization. The code rewritten by the hardware code optimization unit supports up to two levels of nested For loops: when there is only a single-level loop, a single-level For loop is used, and the For loop is tagged according to the hardware / software partitioning specifications; when there is a second-level loop, two levels of For loops are used, with the outer loop corresponding to the second-level loop and the inner loop corresponding to the first-level loop. The outer For loop does not need to be tagged, while the inner For loop is tagged according to the hardware / software partitioning specifications. The tags are used to extract the innermost loop. The innermost loop body is mapped onto the array for processing, while the outer loop body is run by software. The hardware code compilation unit contains source files and several functional units for compiling code. The software compilation and linking unit links the symbols generated in different compilation units to form an executable program. The intermediate file generation module converts the data packets generated by the front-end compilation and optimization module into intermediate files of a fixed format. The mapping module maps the input intermediate files into flowcharts of the corresponding algorithms according to a fixed mapping method. The array configuration code generation module extracts configuration information from the mapped flowcharts and compresses the configuration information into configuration codes for configuring the corresponding hardware architecture.

2. The interpreter for the reconfigurable cryptographic algorithm based on a custom high-level C language according to claim 1, characterized in that, The optimization process using the BFU operator includes: (1): According to the algorithm requirements, determine the operands to be operated on and the modulo operation mode to be processed, and assign the three inputs A, B, and T of the function and the modulo operation mode to be processed respectively; (2): Select the BFU function to be implemented according to the BFU operator function implementation scheme, and pass the parameter to the operator function func. The function will select the specific calculation operator according to the parameter. (3): At the function level, specify the relevant input and output parameters for the specific operators to be implemented, set them according to the BFU operator function implementation scheme, and complete the final encapsulation; (4): Pass the parameters to be output to the result output X and bypass the output Y.

3. The interpreter for the reconfigurable cryptographic algorithm based on a custom high-level C language according to claim 1, characterized in that, The optimization process using the SBOX operator includes: (1): Make full use of lookup table resources. Each lookup table is divided into two 256x32 sub-lookup tables. Select different sub-lookup tables to search according to the 1-bit group configuration or select which bits in the 32 bits to use as valid data output according to the 2-bit byte_sel configuration. (2): Each SBOX has four tables, and each table is divided into eight smaller tables according to the group configuration and byte_sel configuration; (3): The underlying function is encapsulated based on the SBOX function implementation scheme table.

4. The interpreter for the reconfigurable cryptographic algorithm based on a custom high-level C language according to claim 1, characterized in that, The optimization process using the BENES operator includes: (1): Determine the input and output function parameters; (2): The function uses an NxN BENES permutation unit to implement all selection transformations of N inputs and N outputs. That is, any one of the N outputs of the NxN permutation unit can select any one of the N inputs. The number of bits required for BENES128 is determined by the formula BENES (N).length = (n / 2)*(2*log2 (n)-1). (3): Save the replaced data units for later use.

5. The interpreter for the reconfigurable cryptographic algorithm based on a custom high-level C language according to claim 1, characterized in that, The BENES operator is used to implement the bit permutation function for nonlinear operations.

6. The interpreter for the reconfigurable cryptographic algorithm based on a custom high-level C language according to claim 1, characterized in that, The mapping module maps the corresponding operator functions to fixed operator icons.

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