A data processing method for implementing one instruction to process multiple sets of data in parallel

Abstract

The application provides a data processing method for realizing one instruction to multiple groups of parallel processing, and the method comprises a segmented SIMD vector instruction, which comprises: segmenting a vector register according to the number of data needing parallel processing and the size of the data in a calculation requirement, and processing one group of data needing parallel processing in each segment; and for the data groups needing combined processing, the method comprises: copying each group of data of one data set to each segment of the same vector register one by one, so as to realize the processing of data loading and operation. In view of the defect of low hardware resource utilization rate in the calculation process of the current SIMD extension dot product operation instruction, the application provides an innovative segmented processing instruction type, which can simultaneously complete the vector operation on multiple groups of operation data by segmenting the data and the vector register of the instruction operation, improves the utilization rate of hardware resources, and improves the calculation efficiency of the instruction.

Description

Technical Field

[0001] This invention relates to the field of multimedia computing technology, and in particular to a data processing method that enables a single instruction to perform parallel processing on multiple groups of data. Background Technology

[0002] With the widespread adoption of the internet, multimedia applications such as images, audio, and video have rapidly emerged. To meet the intensive computing demands of the multimedia field, the requirements for processor hardware computing power are increasing. However, traditional methods of improving computing power by increasing clock speed and adding more hardware pipeline stages are gradually reaching their limits. Hardware designers have begun to consider improving computing power through parallelism, leading to the development of multi-machine architectures, multi-core architectures, and SIMD architectures. Among these, SIMD is an extended instruction set that efficiently implements parallel processing, using a single instruction to perform the same operation on a set of data simultaneously, thereby achieving parallel data processing.

[0003] Multimedia applications typically involve a large number of homogeneous and independent memory access and computation operations, and the data types used are generally very narrow (e.g., color data bit width is 8 bits in graphics systems; audio sampling bit width is usually 8 bits or 16 bits). The SIMD extension instruction set features independent long-width vector registers (64 / 128 / 256 / 512 / 1024...), allowing contiguous memory address data that would otherwise require multiple loads to be loaded into a single vector register. Using a split mode, the long vector register is treated as multiple independent narrow-width elements (typically supporting signed or unsigned 8-bit, 16-bit, 32-bit, and 64-bit integers or 32-bit single-precision floating-point data). A single SIMD extension instruction enables parallel processing of all data elements in the SIMD vector register. The number of data elements that each instruction can process in parallel is determined by the length of the vector register and the data type. For example, a 128-bit vector register can process four 32-bit data elements, eight 16-bit data elements, or sixteen 8-bit data elements simultaneously. Furthermore, as the length of the SIMD vector register increases, the amount of data that an instruction can process simultaneously also increases, resulting in higher performance acceleration. This execution method is well-suited for processing computationally intensive multimedia programs such as audio and video decoding with low data correlation.

[0004] SIMD extensions only require copying the same processing units a few times on top of the original scalar units, without adding much extra hardware, to bring significant performance improvements to specific applications such as multimedia. Therefore, SIMD has become an essential extension for modern processors, such as the MMX / SSE / AVX / FMA extension instructions successively launched by Intel and the NEON extension instructions of ARM.

[0005] SIMD extension instructions are not significantly different from ordinary scalar instructions in their implementation mechanism. All operations supported by the scalar instruction set can be implemented on the SIMD extension instruction set, such as access operations, arithmetic operations, logical operations, bit operations, and commonly used functions like saturation processing, rounding, and conditional execution. Meanwhile, with the development of computer technology, various new computing needs are constantly emerging, and the computing functions supported by the SIMD extension instruction set are constantly being enriched. Many processors today support hundreds of SIMD extension instructions. The design intent of many instructions has long since transcended the scope of multimedia application processing, extending to fields requiring high-performance computing capabilities such as signal processing and scientific computing.

[0006] For example, with the rapid development of artificial intelligence technologies such as machine learning in recent years, applications involving dot product operations such as convolution and matrix multiplication are becoming increasingly common. As a result, the SIMD extensions of various mainstream processors have added relevant instructions for dot product operations to achieve efficient processing of related applications in the field of artificial intelligence.

[0007] As mentioned above, the dot product instructions in the SIMD extended instruction set can efficiently accelerate the operation of such applications, addressing the computational needs related to convolution and matrix multiplication in the field of artificial intelligence that have emerged in recent years. The following will illustrate the specific operation and implementation of the SIMD dot product instructions with examples. Considering that convolution operations are ultimately transformed into matrix multiplication operations, this article uses matrix multiplication examples to analyze and introduce the operation of the dot product instructions.

[0008] Suppose the two matrices involved in the multiplication operation are matrix A (size 16*16) and matrix B (size 16*16), where each data element is 8 bits. According to the rules of matrix multiplication, the calculation process involves multiplying each row (16 elements) of matrix A with each column (16 elements) of matrix B, then summing the products, and using the sum as an element of the resulting matrix. After calculating all possible combinations of all rows of matrix A and all columns of matrix B, a 16*16 matrix is ​​obtained. The process of multiplying each row of matrix A with each column of matrix B and summing the results corresponds to the dot product operation of two vectors, and therefore can be implemented using the dot product instruction.

[0009] To achieve parallel processing of the 16 8-bit multiplication and accumulation operations in the matrix multiplication operation described above, the vector register used to load and store the data only needs to be 128 bits in size. Considering that current SIMD extended instructions use vector registers of 512 bits or even 1024 bits to achieve higher parallelism, this paper uses the currently mainstream 512-bit vector register size as an example to illustrate the implementation process of the dot product operation. For 8-bit data, a 512-bit vector register can simultaneously support the parallel processing of 64 data points; therefore, the extended hardware components corresponding to the SIMD instructions contain 64 parallel computing units.

[0010] Taking the dot product operation between the 16 elements a(1,1)~a(1,16) in the first row of matrix A and the 16 elements b(1,2)~b(16,2) in the second column of matrix B as an example, the elements of matrix A and matrix B are loaded into the vector registers vrp and vrs respectively, and the dot product calculation result is stored in the destination register vrd. This completes the dot product calculation between a row of data in matrix A and a column of data in matrix B. Because this operation only needs to process the multiplication and accumulation calculation of two sets of 16 8-bit data, it only occupies one-quarter of the space of the 512-bit vector registers vrp and vrs respectively. The remaining register space is zero-padded, and the corresponding hardware computing unit processes zero operations.

[0011] By sequentially loading each row of data from matrix A and each column of data from matrix B into the vector register according to the above process, the calculation of all possible combinations of all rows in matrix A and all columns in matrix B is completed, and the final result matrix can be obtained.

[0012] As described above, the dot product instruction in the current SIMD extended instructions, through special parallel processing of parameters, enables efficient operation of convolution and matrix multiplication operations in artificial intelligence applications. Furthermore, with the increasing width of the SIMD vector register, the amount of data that SIMD instructions can support for parallel processing is also increasing, leading to even higher acceleration performance.

[0013] However, as the width of the SIMD vector register gradually increases, meaning that the parallelism supported by the SIMD extension instructions becomes higher and higher, when the number of elements that need to be processed in parallel is less than the number of data that a single SIMD extension instruction can support in parallel operations, problems such as low hardware resource utilization and reduced computing performance will occur.

[0014] As in the example above, the vector register is 512 bits wide. For 8-bit data elements, 64 data elements can be processed in parallel simultaneously, meaning the extended hardware corresponding to the SIMD vector instruction contains 64 computation units. However, the operation to be processed is the multiplication of a 16*16 matrix A with a 16*16 matrix B. This matrix multiplication operation is ultimately broken down into multiple dot product operations of one-dimensional vectors containing 16 elements each. That is, each SIMD dot product instruction only needs to process 16 data elements (two groups), using only a quarter of the register storage space and computation units. The remaining vector register space is zero-padded as described in the example above, and the corresponding computation units process zero operations. This results in a waste of hardware resources, with a hardware resource utilization rate of only a quarter, leading to a decrease in computational performance.

[0015] In addition, commonly used terms in the prior art include:

[0016] SIMD: Single Instruction Multiple Data, is an extended instruction set that enables efficient parallel processing.

[0017] vrp: Source operand number one in a SIMD instruction;

[0018] vrs: The second source operand in the SIMD instruction;

[0019] vrd: The destination operand in a SIMD instruction. Summary of the Invention

[0020] This application is based on an analysis of the specific operation of the dot product operation instruction in the current SIMD extended instructions. For the problem of wasted hardware resources caused by the number of data that need to be processed in parallel being less than the number of data that a single SIMD extended instruction can support in parallel operations, this application innovatively proposes a segmented vector instruction type. By segmenting the vector register and the operands that the instruction can support, a single instruction can perform parallel processing on multiple sets of data that need to be processed in parallel. This not only improves the utilization of hardware resources, but also enhances the computational efficiency of the instruction.

[0021] Specifically, the present invention provides a data processing method for implementing a single instruction to process multiple sets of data in parallel. The method includes a segmented SIMD vector instruction defined as an SMAC instruction, which is a segmented instruction designed based on the SIMD instruction set. The method includes: segmenting the vector register according to the number and size of the data to be processed in parallel in the computational requirements, with each segment processing one set of data that needs to be processed in parallel; for data sets that need to be processed in pairs, copying each set of data from one dataset to each segment of the same vector register one by one to realize the data loading and operation processing.

[0022] Since convolution operations are ultimately transformed into matrix multiplication operations, the method analyzes the operation of dot product operation instructions using matrix multiplication. It segments the high-bit-width SIMD vector register, and the number of segments is determined by the data type that the SMAC instruction needs to process and the number of data that need to be processed in parallel. Each segment has an independent vector register fragment and a corresponding computation unit, and an independent set of data is computed in parallel within the segment. There is no computational relationship between the segments.

[0023] Through this segmented processing, when the number of data to be processed is much smaller than the number of data that the vector register can support for parallel computation, the SMAC instruction can process a maximum of 512 bits, or 16 words of data, per instruction. The basic format of the instruction name is SR. <lseg>MAC <fmt>Where lseg represents the number of words in each segment, fmt represents the data format in each segment, and the operand format of this instruction is vrd[m], vrs, vrp[n], where vrd represents the destination register of the instruction, vrs and vrp represent the source registers of the instruction, n represents which segment of data in vrp is used, and m represents which word of data in each segment of vrd is used for accumulation and the final result is saved; specifically including SR1MAC2BI, SR2MAC2BI, SR4MAC2BI, SR8MAC2BI, SR16MAC2BI, SR1MAC4BI, SR2MAC4BI, SR4MAC4BI, SR8MAC4BI, SR16MAC4BI, SR1MACUUB, SR2MACUUB, SR4MACUUB, SR8MACUUB, SR16MACUUB, SR1MACSUB, SR2MACSUB, SR4MAC SUB, SR8MACSUB, SR16MACSUB, SR1MACSSB, SR2MACSSB, SR4MACSSB, SR8MACSSB, SR16MACSSB, SR1MACSSH, SR2MACSSH, SR4MACSSH, SR8MACSSH, SR16MACSSH. Each of these segments has a length of 1 / 2 / 4 / 8 / 16 words. When the total length is 16 words, it is divided into 16 / 8 / 4 / 2 / 1 segments. FMT is divided into 2BI / 4BI / UUB / SUB / SSB / SSH, representing respectively: vrs and vrp are both unsigned 2-bit data; vrs and vrp are both unsigned 4-bit data; vrs and vrp are both unsigned byte data; vrs are signed byte data and vrp are unsigned byte data; vrs and vrp are both signed byte data; vrs and vrp are both signed half-byte data. Word data; the SMAC instruction in the processor goes through instruction fetch, decoding, operand reading, and execution, and finally writes the corresponding result back to the destination register, so as to realize the operation of a single instruction processing a set of data that needs to be processed in parallel within each segment, and multiple segments processing multiple sets of data that need to be processed in parallel at the same time.

[0024] The design of the dot product operation instruction combines multiple fused multiplication and addition operations into a single step. A single instruction can multiply each pair of data elements in two sets of data and sum the product results. Then, the summation results are stored in the corresponding registers. In other words, it simultaneously realizes the operation between two SIMD vector registers and the operation between elements in each register.

[0025] Let matrix A and matrix B be the two matrices involved in the multiplication operation. The data elements in both matrices are unsigned bytes. Matrix A has a size of m*p, where m = 16 and p = 16. The size of matrix B is p*n, where p = 16 and n = 16. Matrix B = The product of matrices A and B is denoted as matrix C = A * B, where C has a size of m * n. The element in the i-th row and j-th column of matrix C can be represented as: For the above operation, the basic data type is unsigned byte. According to p=16, each segment contains 16 elements, so the length of each segment is 4 words. Therefore, the SR8MACUUB instruction is selected for operation. Since the maximum length that the SMAC instruction can operate on at one time is 512 bits, or 16 words, the SR8MACUUB instruction will be divided into 4 segments. Since n=16, each row in matrix C requires 4 SR8MACUUB instructions for operation. Since m=16, there are 16 rows in C, so a total of 64 SMAC instructions are needed. Therefore, the multiplication operation of matrix A and matrix B is finally transformed into the operation of multiple SR8MACUUB instructions.

[0026] Suppose that it occupies three source vector registers vrp, vrs, new vrp and one destination vector register vrd, and the bit width of each register is 512 bits;

[0027] Based on the design of the segmented SMAC instruction, the 512-bit vector register is divided into 4 segments according to the actual data to be processed, and each segment can perform the dot product operation on a set of vector data.

[0028] The method further includes the following steps:

[0029] S1, simultaneously load the four rows of data from matrix A into the vector source register vrp, and similarly load the four columns of data from matrix B into the vector source register vrs. Each row of data in matrix A and each column of data in matrix B occupies one segment in the vector register.

[0030] S2: Select data from a segment in the vector source register vrp and copy it to the four segments in a new vector register newvrp;

[0031] S3 performs a dot product operation on the data elements in the corresponding segments of the vector registers new vrp and vrs, and stores the result in the segment corresponding to the vector register vrd.

[0032] S4. Following steps S1-S3 above, copy the data in each segment of the vector source register vrp to the four segments of the vector register new vrp, and perform dot product operations with the data elements of the corresponding segments in the vector register vrs. Finally, the operation of all possible combinations of the four rows of data in the initially loaded matrix A and the four columns of data in matrix B can be completed.

[0033] Therefore, the advantage of this application is:

[0034] To address the low hardware resource utilization in current SIMD extended dot product operation instructions, this application proposes an innovative segmented processing instruction type. This type segments the data and vector registers to be operated on, enabling simultaneous vector operations on multiple sets of data, thereby improving hardware resource utilization and increasing instruction computation efficiency. Attached Figure Description

[0035] The accompanying drawings, which are provided to further illustrate the invention and form part of this application, are not intended to limit the scope of the invention.

[0036] Figure 1 This is a flowchart of the method of the present invention.

[0037] Figure 2 This is a schematic diagram illustrating how the vector register is divided into four segments to perform operations in an embodiment of the present invention. Detailed Implementation

[0038] To better understand the technical content and advantages of the present invention, the present invention will now be described in further detail with reference to the accompanying drawings.

[0039] This invention relates to a data processing method for performing parallel processing on multiple sets of data with a single instruction. Addressing the problem of wasted hardware resources caused by the number of data items requiring parallel processing being less than the number of data items that a single SIMD extended instruction can support in parallel operations, this application innovatively proposes a segmented vector instruction type. By segmenting the vector register and the operands supported by the instruction, parallel processing on multiple sets of data requiring parallel processing with a single instruction can be achieved. This not only improves the utilization rate of hardware resources but also enhances the computational efficiency of the instruction.

[0040] In the method described, the two matrices involved in the multiplication operation are denoted as matrix A and matrix B, respectively. The data elements in both matrices are of unsigned byte type, and matrix A has a size of m*p, where m = 16 and p = 16. Matrix B has a size of p*n, where p = 16 and n = 16. The product of matrices A and B is denoted as matrix C = A * B, where C has a size of m * n. The element in the i-th row and j-th column of matrix C can be represented as: For the above operation, the basic data type is unsigned byte. Since p=16, each segment contains 16 elements, and the length of each segment is 4 words. Therefore, the SR8MACUUB instruction is selected for operation. Since the maximum length that the SMAC instruction can operate on at one time is 512 bits, or 16 words, the SR8MACUUB instruction will be divided into 4 segments. Since n=16, each row in matrix C requires 4 SR8MACUUB instructions for operation. Since m=16, there are 16 rows in C, so a total of 64 SMAC instructions are needed. The data elements in the matrix are all 8 bits in size. The multiplication operation between matrix A and matrix B is ultimately transformed into a dot product operation of multiple vectors containing 16 8-bit data elements. Assume that it occupies three source vector registers vrp, vrs, new vrp and one destination vector register vrd, and the bit width of each register is 512 bits. According to the design of the segmented SMAC instruction, the 512-bit vector register is divided into four segments (determined by the actual matrix size and data type size) to meet the calculation requirements. Each segment can perform a dot product operation on a set of vector data.

[0041] like Figure 1 As shown, the method further includes the following steps:

[0042] S1, simultaneously load the four rows of data from matrix A into the vector source register vrp, and similarly load the four columns of data from matrix B into the vector source register vrs. Each row of data in matrix A and each column of data in matrix B occupies one segment in the vector register.

[0043] S2: Select data from a segment in the vector source register vrp and copy it to the four segments in a new vector register newvrp;

[0044] S3 performs a dot product operation on the data elements in the corresponding segments of the vector registers new vrp and vrs, and stores the result in the segment corresponding to the vector register vrd.

[0045] S4. Following steps S1-S3 above, copy the data in each segment of the vector source register vrp to the four segments of the vector register new vrp, and perform dot product operations with the data elements of the corresponding segments in the vector register vrs. Finally, the operation of all possible combinations of the four rows of data in the initially loaded matrix A and the four columns of data in matrix B can be completed.

[0046] The design principle of the dot product instruction is to combine multiple fused multiplication and addition operations into a single step. For example, executing the dot product of four 32-bit elements a0×b0+a1×b1+a2×b2+a3×b3 on two 128-bit SIMD vector registers achieves a single-cycle throughput. The dot product instruction differs from the vector multiplication and accumulation instruction in that a single instruction can multiply each pair of data elements in two sets of data pairwise, sum the products, and then store the sum in the corresponding register. This simultaneously achieves operations between the two SIMD vector registers and operations between elements within each register.

[0047] The innovative segmented SIMD instruction proposed in this application is named SMAC (Segment Multiply-Add). The specific operation and implementation method of this instruction are described below:

[0048] The main design concept of SMAC instructions is to segment the high-width SIMD vector register. The number of segments is determined by the data type and the number of data points that need to be processed in parallel. Each segment has an independent vector register fragment and a corresponding computation unit, and each segment performs parallel computation on an independent set of data; there is no computational relationship between segments. Through this segmented processing, in situations where the number of data points to be processed is much smaller than the number of data points that the vector register can support in parallel computation, SMAC instructions can achieve the operation of a single instruction processing one set of data points requiring parallel processing within each segment, or multiple segments processing multiple sets of data points requiring parallel processing simultaneously. This can efficiently improve the utilization of hardware resources and enhance single-instruction computation performance.

[0049] The following illustrations demonstrate the specific implementation process of the SMAC command:

[0050] like Figure 2 As shown, to contrast with the current technical solution, matrix multiplication is used as an example. Similar to the previous example, the two matrices involved in the multiplication are matrix A (16*16) and matrix B (16*16). The data elements in both matrices are 8 bits in size. The multiplication of matrix A and matrix B is ultimately transformed into a dot product operation of multiple vectors containing 16 8-bit data elements. The three source vector registers (vrp, vrs, new vrp) and the destination vector register (vrd) are all 512 bits wide.

[0051] Based on the design principles of the SMAC instruction, and to meet the aforementioned computational requirements, the 512-bit vector register can be divided into four segments, each capable of performing a dot product operation on a set of vector data. The specific implementation can be divided into the following steps:

[0052] S1: Simultaneously load the four rows of data from matrix A into the vector source register vrp, and similarly load the four columns of data from matrix B into the vector source register vrs. Each row of data from matrix A and each column of data from matrix B occupies one segment in the vector register.

[0053] S2: Select data from a segment in the vector source register vrp and copy it to the four segments in a new vector register newvrp.

[0054] S3: Perform a dot product operation on the data elements in the corresponding segments of vector registers new vrp and vrs, and store the result in the segment corresponding to vector register vrd.

[0055] S4: Following steps S1-S3 above, copy the data in each segment of the vector source register vrp to the four segments of the vector register new vrp, and perform dot product operations with the data elements of the corresponding segments in the vector register vrs. Finally, the operation of all possible combinations of the four rows of data in the initially loaded matrix A and the four columns of data in matrix B can be completed.

[0056] This invention innovatively proposes a segmented processing method, which can perform dot product operations between multiple rows of data in matrix A and multiple columns of data in matrix B in parallel, effectively improving the utilization of hardware computing resources and enhancing computing performance. In this example, the hardware computing resource utilization reaches 100%, and four sets of data can be processed in a single cycle, significantly increasing the single-cycle throughput of instructions.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.< / fmt> < / lseg>

Claims

1. A data processing method for implementing one instruction for multiple sets of parallel processing, characterized by, The method includes: The operation of dot product operation instruction is analyzed using matrix multiplication. The high-bit-width SIMD vector register is segmented. The number of segments is determined by the data type that the SMAC instruction needs to process and the number of data that need to be processed in parallel. Each segment has an independent vector register fragment and a corresponding calculation unit, and an independent set of data is calculated in parallel within the segment. There is no calculation relationship between the segments. The SMAC commands specifically include SR1MAC2BI, SR2MAC2BI, SR4MAC2BI, SR8MAC2BI, SR16MAC2BI, SR1MAC4BI, SR2MAC4BI, SR4MAC4BI, SR8MAC4BI, SR16MAC4BI, SR1MACUUB, SR2MACUUB, SR4MACUUB, SR8MACUUB, SR16MACUUB, SR1MACSUB, SR2MACSUB, SR4MACSUB, SR8MACSUB, SR16MACSUB, SR1MACSSB, SR2MACSSB, SR4MACSSB, SR8MACSSB, and SR16MACS. SB, SR1MACSSH, SR2MACSSH, SR4MACSSH, SR8MACSSH, SR16MACSSH, the length of each segment of the above instructions is 1 / 2 / 4 / 8 / 16 words. When the total length is 16 words, it is divided into 16 / 8 / 4 / 2 / 1 segments. fmt is divided into 2BI / 4BI / UUB / SUB / SSB / SSH, which respectively represent vrs and vrp are both unsigned 2-bit data, vrs and vrp are both unsigned 4-bit data, vrs and vrp are both unsigned byte data, vrs are signed byte data and vrp are unsigned byte data, vrs and vrp are both signed byte data, and vrs and vrp are both signed half-word data. The SMAC instruction, in the processor, undergoes instruction fetching, decoding, operand reading, and execution, ultimately writing the result back to the destination register. This allows a single instruction to process one set of data requiring parallel processing within each segment, or multiple segments to process multiple sets of data requiring parallel processing simultaneously. Through this segmented processing, for cases where the number of data to be processed is much smaller than the number of data points supported by the vector registers for parallel computation, each SMAC instruction can process a maximum of 512 bits (16 words) of data at a time. The basic format of the instruction name is SR. <lseg>MAC <fmt> lseg represents the number of words in each segment, fmt represents the data format in each segment, and the operand format of this instruction is vrd[m], vrs, vrp[n], where vrd represents the destination register of the instruction, vrs and vrp represent the source registers of the instruction, n represents the use of the nth segment of data in vrp, and m represents the accumulation and storage of the data of the mth word in each segment of vrd.< / fmt> < / lseg> 2. The data processing method of claim 1, wherein, The design of the dot product operation instruction combines multiple fused multiplication and addition operations into a single step. A single instruction can multiply each pair of data elements in two sets of data and sum the product results. Then, the summation results are stored in the corresponding registers. In other words, it simultaneously realizes the operation between two SIMD vector registers and the operation between elements in each register.

3. The data processing method of implementing one instruction for processing multiple sets of data in parallel according to claim 2, wherein, The two matrices involved in the multiplication operation are denoted as matrix A and matrix B. The data elements in both matrices are of size unsigned byte type, and matrix A has a size of 1. Where m=16, p=16, matrix The size of matrix B is Where p=16, n=16, matrix The product of matrix A and matrix B is denoted as matrix A. The size of C is The element in the i-th row and j-th column of matrix C is represented as: For the above operation, the basic data type is unsigned byte. According to p=16, each segment contains 16 elements, so the length of each segment is 4 words. Therefore, the SR8MACUUB instruction is selected for operation. Since the maximum length that the SMAC instruction can operate on at one time is 512 bits, or 16 words, the SR8MACUUB instruction will be divided into 4 segments. Since n=16, each row in matrix C needs 4 SR8MACUUB instructions for operation. Since m=16, there are 16 rows in C, so a total of 64 SMAC instructions are needed. Therefore, the multiplication operation of matrix A and matrix B is finally transformed into the operation of multiple SR8MACUUB instructions. Suppose that it occupies three source vector registers vrp, vrs, new vrp and one destination vector register vrd, and the bit width of each register is 512 bits; Based on the design of the segmented SMAC instruction, the 512-bit vector register is divided into 4 segments according to the actual data to be processed, and each segment can perform the dot product operation on a set of vector data.

4. The data processing method of implementing one instruction for processing multiple sets of data in parallel according to claim 3, wherein, The method further Includes the following steps: S1, simultaneously load the four rows of data from matrix A into the vector source register vrp, and similarly load the four columns of data from matrix B into the vector source register vrs. Each row of data in matrix A and each column of data in matrix B occupies one segment in the vector register. S2: Select data from a segment in the vector source register vrp and copy it to the four segments in a new vector register new vrp; S3 performs a dot product operation on the data elements in the corresponding segments of the vector registers new vrp and vrs, and stores the result in the segment corresponding to the vector register vrd. S4. Following steps S1-S3 above, copy the data in each segment of the vector source register vrp to the four segments of the vector register new vrp, and perform dot product operations with the data elements of the corresponding segments in the vector register vrs. Finally, the operation of all possible combinations of the four rows of data in the initially loaded matrix A and the four columns of data in the matrix B is completed.

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