Sensitive amplifier and memory chip

Abstract

The application discloses a sensitive amplifier and a storage chip. The sensitive amplifier comprises a first clamping unit, a second clamping unit, a first current unit and a feedback unit. The control end of the first clamping unit is coupled with a total bit line through the feedback unit, so that the potential change of the total bit line forms a closed-loop control. That is, when the potential of the total bit line rises, the current flowing through the first current unit and the feedback unit is reduced, and the current flowing through the second clamping unit is increased. The potential of the control end of the first clamping unit is reduced, the current flowing through the first clamping unit is also reduced, and the potential of the total bit line is reduced to a preset potential and is kept stable. Conversely, the potential of the total bit line is increased to a preset potential and is kept stable.

Description

Technical Field

[0001] This application relates to the field of storage technology, specifically to a sensitive amplifier and a storage chip. Background Technology

[0002] In memory chips or memory, sensitive amplifiers are used to read stored data from memory cells. However, in actual operation, the sensitive amplifier can be affected by factors such as unstable total bit line or bit line voltage, or insufficient or overcharged pre-charge of the bit lines, all of which can severely impact the resolution of the sensitive amplifier. Summary of the Invention

[0003] This application provides a sensitive amplifier and a memory chip to alleviate the technical problem of low stability of total bit line voltage.

[0004] In a first aspect, this application provides a sensitive amplifier, which includes a first clamping unit, a second clamping unit, a first current unit, and a feedback unit. A first terminal of the first clamping unit is electrically connected to a power supply terminal, and a second terminal of the first clamping unit is electrically connected to a bus line. A first terminal of the second clamping unit is electrically connected to a control terminal of the first clamping unit, and a second terminal of the second clamping unit is electrically connected to a ground terminal. The control terminal of the second clamping unit is also electrically connected to the second terminal of the first clamping unit. A first terminal of the first current unit is electrically connected to a power supply terminal, and a second terminal of the first current unit is electrically connected to the first terminal of the second clamping unit. The control terminal of the first current unit is also electrically connected to a first bias voltage terminal. A first terminal of the feedback unit is electrically connected to a power supply terminal, and a second terminal of the feedback unit is electrically connected to the second terminal of the first current unit. The control terminal of the feedback unit is also electrically connected to the second terminal of the first clamping unit.

[0005] In some embodiments, the feedback unit includes a feedback transistor, the first terminal of which is electrically connected to a power supply terminal, the second terminal of which is electrically connected to the second terminal of a first current unit, and the control terminal of which is electrically connected to the second terminal of a first clamping unit.

[0006] In some embodiments, the first current unit includes a first current transistor, the first terminal of the first current transistor is electrically connected to a power supply terminal, the second terminal of the first current transistor is electrically connected to the second terminal of a feedback transistor, and the control terminal of the first current transistor is electrically connected to a first bias voltage terminal.

[0007] In some embodiments, the second clamping unit includes a second clamping transistor, the first terminal of which is electrically connected to the second terminal of the feedback transistor and the second terminal of the first current transistor, the second terminal of which is electrically connected to a ground terminal, and the gate of which is electrically connected to the second terminal of the first clamping unit.

[0008] In some embodiments, the first clamping unit includes a first clamping transistor, the first terminal of which is electrically connected to a power supply terminal, the second terminal of which is electrically connected to a total bit line, and the control terminal of which is electrically connected to the first terminal of a second clamping transistor, the second terminal of a feedback transistor, and the second terminal of a first current transistor.

[0009] In some embodiments, the first clamping transistor and the second clamping transistor are both N-channel transistors; the first current transistor and the feedback transistor are both P-channel transistors.

[0010] In some embodiments, the sensitive amplifier further includes a second current transistor and a precharge transistor. The first terminal of the second current transistor is electrically connected to a power supply terminal, the second terminal of the second current transistor is electrically connected to the first terminal of a first clamping transistor, and the control terminal of the second current transistor is electrically connected to a second bias voltage terminal. The first terminal of the precharge transistor is electrically connected to a power supply terminal, the second terminal of the precharge transistor is electrically connected to the first terminal of the first clamping transistor and the second terminal of the second current transistor, and the control terminal of the precharge transistor is electrically connected to a precharge control terminal.

[0011] In some embodiments, the sensitive amplifier further includes a first transistor, a second transistor, and a buffer. The first terminal of the first transistor is electrically connected to a power supply terminal, and the control terminal of the first transistor is electrically connected to the first terminal of a first clamping transistor, the second terminal of a precharge transistor, and the second terminal of a second current transistor. The first transistor is a P-channel transistor. The first terminal of the second transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the second transistor is electrically connected to a ground terminal. The control terminal of the second transistor is electrically connected to a third bias voltage terminal. The second transistor is an N-channel transistor. The input terminal of the buffer is electrically connected to the second terminal of the first transistor and the first terminal of the second transistor. The output terminal of the buffer is used to output the corresponding readout data.

[0012] In some implementations, the ratio of the current flowing through the feedback unit to the current flowing through the first current unit is 1:M, where M is a positive number.

[0013] Secondly, this application provides a memory chip that includes the sensitive amplifier described in at least one of the above embodiments.

[0014] In some embodiments, the memory chip further includes a decoding transistor, the first terminal of which is electrically connected to the total bit line, the second terminal of which is electrically connected to the bit line, and the control terminal of which is electrically connected to the decoding selection terminal. The decoding transistor is an N-channel transistor.

[0015] In some embodiments, the memory chip further includes a memory transistor, a first terminal of which is electrically connected to the second terminal of a decoding transistor, the second terminal of which is electrically connected to a ground terminal, and a control gate of which is electrically connected to a word line.

[0016] The sensitive amplifier and memory chip provided in this application, through a feedback unit coupled to the control terminals of the total bit line and the first clamping unit, can achieve closed-loop control of the potential change of the total bit line. Specifically, the first constant current unit and the second clamping unit constitute a unipolar common-source cascode amplifier. The addition of the feedback unit increases the gain and speed of the common-source cascode amplifier. When the potential of the total bit line increases, i.e., the control electrode potential of the second clamping unit increases, the potential at the output terminal of the common-source cascode amplifier, i.e., the control terminal of the first clamping unit, drops significantly. The first clamping unit, acting as a source follower, pulls the potential of the total bit line down to a preset potential for stabilization. Conversely, when the potential of the total bit line decreases, through the combined action of the second clamping unit, the first constant current unit, and the feedback unit, the potential of the total bit line is raised back to the preset potential for stability. This combination of the feedback unit and the first constant current unit makes the clamping circuit react faster, thereby making the clamping voltage of the total bit line more stable. On the other hand, when this sensitive amplifier is in the bit line pre-charge start stage, the total bit line potential is very low, the current of the feedback unit will be very large, which will cause the control electrode voltage of the first clamping unit to rise rapidly. As a result, the current of the first clamping unit, i.e. the charging current of the total bit line, will increase rapidly and thus accelerate the charging speed of the total bit line, so that the total bit line potential reaches the expected clamping voltage earlier.

[0017] Furthermore, compared to the limited types of clamping circuits available in existing sensitive amplifiers, this application can construct clamping circuits that differ from existing technologies through the first current unit, feedback unit, and second clamping unit, thus enriching the types of clamping circuits and expanding their application scenarios. Attached Figure Description

[0018] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0019] Figure 1 A circuit diagram of a sensitive amplifier provided in an embodiment of this application.

[0020] Figure 2 A circuit diagram of a memory chip provided in an embodiment of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0022] In view of the aforementioned technical problem of low stability of the total bit line DBL voltage, this embodiment provides a sensitive amplifier, such as... Figure 1 As shown, the sensitive amplifier includes a first clamping unit 10, a second clamping unit 20, a first current unit 30, and a feedback unit 40. The first end of the first clamping unit 10 is electrically connected to the power supply terminal VCC, and the second end of the first clamping unit 10 is electrically connected to the total bit line DBL. The first end of the second clamping unit 20 is electrically connected to the control terminal of the first clamping unit 10, and the second end of the second clamping unit 20 is electrically connected to the ground terminal GND. The control terminal of the second clamping unit 20 is also electrically connected to the second end of the first clamping unit 10. The first end of the first current unit 30 is electrically connected to the power supply terminal VCC, and the second end of the first current unit 30 is electrically connected to the first end of the second clamping unit 20. The control terminal of the first current unit 30 is also electrically connected to the first bias voltage terminal BIASP. The first end of the feedback unit 40 is electrically connected to the power supply terminal VCC, and the second end of the feedback unit 40 is electrically connected to the second end of the first current unit 30. The control terminal of the feedback unit 40 is also electrically connected to the second end of the first clamping unit 10.

[0023] It is understood that the sensitive amplifier provided in this embodiment, through the feedback unit 40 coupled to the control terminal of the total bit line DBL and the first clamping unit 10, can make the potential change of the total bit line DBL form a closed loop control, that is, the first constant current unit 30 and the second clamping unit 20 constitute a unipolar common source cascode amplifier. The access of the feedback unit 40 makes the gain of the common source cascode amplifier greater and the response faster. When the potential of the total bit line DBL increases, i.e., the control electrode potential of the second clamping unit 20 increases, the potential of the output terminal of this common-source common-gate amplifier, i.e., the control terminal of the first clamping unit 10, drops significantly. The first clamping unit 10, acting as a source follower, pulls the potential of the total bit line DBL down to the preset potential and stabilizes it. Conversely, when the potential of the total bit line DBL decreases, through the combined action of the second clamping unit 20, the first constant current unit 30, and the feedback unit 40, the potential of the total bit line DBL is raised back to the preset potential and remains stable. This combination of the feedback unit 40 and the first constant current unit 30 makes the clamping circuit react faster, thereby making the clamping voltage of the total bit line DBL more stable. On the other hand, when this sensitive amplifier is in the pre-charge start stage of the total bit line DBL, the potential of the total bit line DBL is very low, and the current of the feedback unit 40 will be very large, which will cause the control electrode voltage of the first clamping unit 10 to rise rapidly. As a result, the current of the first clamping unit 10, i.e. the charging current of the total bit line DBL, will increase rapidly and significantly, thereby accelerating the charging speed of the total bit line DBL and enabling the potential of the total bit line DBL to reach the expected clamping voltage earlier.

[0024] Furthermore, compared to the limited types of clamping circuits available in existing sensitive amplifiers, this application can construct clamping circuits that differ from existing technologies through the first current unit 30, feedback unit 40, and second clamping unit 20, thus enriching the types of clamping circuits and expanding their application scenarios.

[0025] In one embodiment, the feedback unit 40 includes a feedback transistor M4, the first terminal of which is electrically connected to the power supply terminal VCC, the second terminal of which is electrically connected to the second terminal of the first current unit 30, and the control terminal of which is electrically connected to the second terminal of the first clamping unit 10.

[0026] It should be noted that the first terminal of the feedback transistor M4 can be the first terminal of the feedback unit 40, the second terminal of the feedback transistor M4 can be the second terminal of the feedback unit 40, and the control terminal of the feedback transistor M4 can be the control terminal of the feedback unit 40. The feedback transistor M4 can be, but is not limited to, a P-channel transistor. In other embodiments, it can also be a first controlled current source, the output current of which changes in opposite direction to the potential of the total bit line DBL. That is, when the potential of the total bit line DBL increases, the output current of the first controlled current source decreases; or, when the potential of the total bit line DBL decreases, the output current of the first controlled current source increases.

[0027] In one embodiment, the first constant current unit 30 includes a first current transistor M3, the first terminal of the first current transistor M3 is electrically connected to the power supply terminal VCC, the second terminal of the first current transistor M3 is electrically connected to the second terminal of the feedback transistor M4, and the control terminal of the first current transistor M3 is electrically connected to the first bias voltage terminal BIASP.

[0028] It should be noted that the first terminal of the first current transistor M3 can be the first terminal of the first current unit 30, the second terminal of the first current transistor M3 can be the second terminal of the first current unit 30, and the control terminal of the first current transistor M3 can be the control terminal of the first current unit 30. The first current transistor M3 can be, but is not limited to, a P-channel transistor. In other embodiments, it can also be a second controlled current source, whose output current changes in the same direction as the output current of the first controlled current source. That is, if the output current of the first controlled current source increases, the output current of the second controlled current source also increases; or, if the output current of the first controlled current source decreases, the output current of the second controlled current source also decreases. Preferably, the ratio of the output current of the first controlled current source to the output current of the second controlled current source is 1:M, where M is a positive number. More preferably, M is a positive number greater than 1, to provide the required voltage and / or current to the control terminal of the first clamping unit 10 or the control terminal of the first clamping transistor M1.

[0029] In one embodiment, the second clamping unit 20 includes a second clamping transistor M2, the first terminal of the second clamping transistor M2 is electrically connected to the second terminal of the feedback transistor M4 and the second terminal of the first current transistor M3, the second terminal of the second clamping transistor M2 is electrically connected to the ground terminal GND, and the gate of the second clamping transistor M2 is electrically connected to the second terminal of the first clamping unit 10.

[0030] It should be noted that the first terminal of the second clamping transistor M2 can be the first terminal of the second clamping unit 20, the second terminal of the second clamping transistor M2 can be the second terminal of the second clamping unit 20, and the control terminal of the second clamping transistor M2 can be the control terminal of the second clamping unit 20. The second clamping transistor M2 can be, but is not limited to, an N-channel transistor. In other embodiments, it can also be a third controlled current source, the output current of which changes positively with the potential of the total bit line DBL. That is, as the potential of the total bit line DBL increases, the output current of the third controlled current source also increases; or, as the potential of the total bit line DBL decreases, the output current of the third controlled current source also decreases.

[0031] In one embodiment, the first clamping unit 10 includes a first clamping transistor M1, the first terminal of the first clamping transistor M1 is electrically connected to the power supply terminal VCC (the first terminal of the first clamping transistor M1 is connected to the first terminal of the second reference current transistor M5, the first terminal of the precharge transistor M6 and the control terminal of the first transistor M7), the second terminal of the first clamping transistor M1 is electrically connected to the total bit line DBL, and the control terminal of the first clamping transistor M1 is electrically connected to the first terminal of the second clamping transistor M2, the second terminal of the feedback transistor M4 and the second terminal of the first current transistor M3.

[0032] It should be noted that the first terminal of the first clamping transistor M1 can be the first terminal of the first clamping unit 10, the second terminal of the first clamping transistor M1 can be the second terminal of the first clamping unit 10, and the control terminal of the first clamping transistor M1 can be the control terminal of the first clamping unit 10. The first clamping transistor M1 can be, but is not limited to, an N-channel transistor. In other embodiments, it can also be a fourth controlled current source, the output current of which changes in a positive direction with the potential of its controlled terminal. That is, if the potential of the controlled terminal of the fourth controlled current source increases, the output current of the fourth controlled current source also increases; or, if the potential of the controlled terminal of the fourth controlled current source decreases, the output current of the fourth controlled current source also decreases.

[0033] It should be noted that the working principles of the first clamping transistor M1, the second clamping transistor M2, the first current transistor M3, and the feedback transistor M4 are as follows:

[0034] The first constant current transistor 30 and the second clamping transistor 20 constitute a unipolar cascode amplifier. The connection of the feedback transistor 40 makes the gain of this cascode amplifier greater and the response faster. In order to maintain the voltage of the total bit line DBL at a preset potential, i.e., the clamping voltage, when the potential of the total bit line DBL is higher than the preset potential, that is, the control electrode potential of the second clamping transistor 20 is raised to a level higher than the preset potential, the potential of the output terminal of this cascode amplifier, i.e., the control terminal (point B) of the first clamping transistor 10, drops significantly. The first clamping transistor 10, acting as a source follower, causes the potential of the total bit line DBL to decrease accordingly and thus be maintained at the preset potential. Similarly, when the potential of the total bit line DBL is lower than the preset potential, through the combined action of the second clamping transistor 20, the first constant current transistor 30, and the feedback transistor 40, the potential of the total bit line DBL also rises accordingly and is maintained at the preset potential. The combination of the feedback transistor 40, the first constant current transistor 30, and the second clamping transistor 20 in this clamping circuit makes the clamping circuit react faster, thereby making the clamping voltage of the total bit line DBL more stable.

[0035] On the other hand, when this sensitive amplifier is in the pre-charge start stage of the total bit line DBL, the potential of the total bit line DBL is very low, and the current of the feedback transistor 40 will be very large, which will cause the control electrode voltage of the first clamping transistor 10 to rise rapidly. As a result, the current of the first clamping transistor 10, i.e. the charging current of the total bit line DBL, will increase rapidly and greatly, thereby accelerating the charging speed of the total bit line DBL and making the potential of the total bit line DBL reach the expected clamping voltage earlier.

[0036] In one embodiment, the sensitive amplifier further includes a second reference current transistor M5 and a precharge transistor M6. The first terminal of the second current transistor M5 is electrically connected to the power supply terminal VCC, the second terminal of the second current transistor M5 is electrically connected to the first terminal of the first clamping transistor M1, and the control terminal of the second current transistor M5 is electrically connected to the second bias voltage terminal BIAS_REF. The first terminal of the precharge transistor M6 is electrically connected to the power supply terminal VCC, the second terminal of the precharge transistor M6 is electrically connected to the first terminal of the first clamping transistor M1 and the second terminal of the second current transistor M5, and the control terminal of the precharge transistor M6 is electrically connected to the precharge control terminal PREb.

[0037] It should be noted that in this embodiment, the second current transistor M5 is used to provide the reference current Iref of the sensitive amplifier; the precharge transistor M6 is used to provide the bit line charging current Ipre of the sensitive amplifier. As the potential of the second bias voltage terminal BIAS_REF increases, the current Iref flowing through the second current transistor M5 decreases; or, as the potential of the second bias voltage terminal BIAS_REF decreases, the current Iref flowing through the second current transistor M5 increases. As the potential of the precharge control terminal PREb increases, the current Ipre flowing through the precharge transistor M6 decreases; or, as the potential of the precharge control terminal PREb decreases, the current Ipre flowing through the precharge transistor M6 increases. That is to say, the second current transistor M5 and the precharge transistor M6 can be, but are not limited to, P-channel transistors, or other components capable of achieving the above functions, such as a controlled current source, etc.

[0038] In one embodiment, the sensitive amplifier further includes a first transistor M7, a second transistor M8, and a buffer 50. The first terminal of the first transistor M7 is electrically connected to the power supply terminal VCC, and the control terminal of the first transistor M7 is electrically connected to the first terminal of the first clamping transistor M1, the second terminal of the precharge transistor M6, and the second terminal of the second current transistor M5. The first transistor M7 is a P-channel transistor. The first terminal of the second transistor M8 is electrically connected to the second terminal of the first transistor M7, and the second terminal of the second transistor M8 is electrically connected to the ground terminal GND. The control terminal of the second transistor M8 is electrically connected to the third bias voltage terminal BIASN. The second transistor M8 is an N-channel transistor. The input terminal of the buffer 50 is electrically connected to the second terminal of the first transistor M7 and the first terminal of the second transistor M8. The output terminal of the buffer 50 is used to output the corresponding readout data DOUT.

[0039] It should be noted that the first transistor M7 and the second transistor M8 in this embodiment can be used to construct a single-phase amplifier. The buffer 50 is used to further amplify and shape the output readout data DOUT as needed, thereby facilitating the logic output and control of subsequent circuits.

[0040] In one embodiment, the ratio of the current flowing through the feedback unit 40 to the current flowing through the first current unit 30 is 1:M, where M is a positive number.

[0041] In one embodiment, this embodiment provides a memory chip, such as... Figure 2 As shown, the memory chip includes the sensitive amplifier described in at least one of the above embodiments.

[0042] It is understood that the memory chip provided in this embodiment, through the feedback unit 40 coupled to the control terminal of the total bit line DBL and the first clamping unit 10, can make the potential change of the total bit line DBL form a closed loop control, that is, the first constant current unit 30 and the second clamping unit 20 constitute a single-pole common-source common-gate amplifier. The access of the feedback unit 40 makes the gain of the common-source common-gate amplifier greater and the response faster. When the potential of the total bit line DBL increases, i.e., the control electrode potential of the second clamping unit 20 increases, the potential of the output terminal of this common-source common-gate amplifier, i.e., the control terminal of the first clamping unit 10, drops significantly. The first clamping unit 10, acting as a source follower, pulls the potential of the total bit line DBL down to the preset potential and stabilizes it. Conversely, when the potential of the total bit line DBL decreases, through the combined action of the second clamping unit 20, the first constant current unit 30, and the feedback unit 40, the potential of the total bit line DBL is raised back to the preset potential and remains stable. This combination of the feedback unit 40 and the first constant current unit 30 makes the clamping circuit react faster, thereby making the clamping voltage of the total bit line DBL more stable.

[0043] On the other hand, when this sensitive amplifier is in the pre-charge start stage of the total bit line DBL, the potential of the total bit line DBL is very low, and the current of the feedback unit 40 will be very large, which will cause the control electrode voltage of the first clamping unit 10 to rise rapidly. As a result, the current of the first clamping unit 10, i.e. the charging current of the total bit line DBL, will increase rapidly and significantly, thereby accelerating the charging speed of the total bit line DBL and enabling the potential of the total bit line DBL to reach the expected clamping voltage earlier.

[0044] Furthermore, compared to the limited types of clamping circuits available in existing sensitive amplifiers, this application can construct clamping circuits that differ from existing technologies through the first current unit 30, feedback unit 40, and second clamping unit 20, thus enriching the types of clamping circuits and expanding their application scenarios.

[0045] It should be noted that the aforementioned memory chips may be, but are not limited to, NOR flash memory.

[0046] In one embodiment, the memory chip further includes a decoding transistor M9, the first terminal of which is electrically connected to the total bit line DBL, the second terminal of which is electrically connected to the bit line BL, and the control terminal of which is electrically connected to the decoding selection terminal Y_MUX. The decoding transistor M9 is an N-channel transistor.

[0047] In one embodiment, the memory chip further includes a memory transistor Mst, the first terminal of which is electrically connected to the second terminal of the decoding transistor M9, the second terminal of which is electrically connected to the ground terminal GND, and the control gate of which is electrically connected to the word line WL.

[0048] It should be noted that the current flowing through the storage transistor Mst is Icell. During the process of reading the data stored in the storage transistor Mst, the precharge transistor M6 is first turned on, precharging the potential of its second terminal (point A) to the potential of the power supply terminal VCC. At the same time, the total bit line DBL and the corresponding bit line BL are also precharged to the clamping voltage of the pointer. After the precharge is completed, the precharge transistor M6 is turned off. During the sensitive amplification process, when the current of the second current transistor M5, i.e. the reference current Iref of the sensitive amplifier, is greater than the current Icell of the storage transistor Mst, the control voltage of the first transistor M7 will remain at a high potential. This high potential is insufficient to turn on the first transistor M7. At this time, the second transistor M8 is turned on, and the read data DOUT output through the buffer 50 is "0". When the reference current Iref is less than the storage cell Icell, the control voltage of the first transistor M7 will decrease over time. When the voltage drops to a level that allows the first transistor M7 to conduct, as the current of the first transistor M7 increases to a level greater than the current of the second transistor M8, the read data DOUT output by the buffer 50 will be "1".

[0049] In one embodiment, at least one of the transistors described above may be, but is not limited to, a P-channel transistor or an N-channel thin-film transistor.

[0050] It should be noted that in the above embodiments, the first electrode can be either the source or the drain, the second electrode can be either the source or the drain, and the control electrode can be the gate; or, the first electrode can be either the collector or the emitter, the second electrode can be either the collector or the emitter, and the control electrode can be the base.

[0051] In the above embodiments, each transistor may also be a bipolar junction transistor or a field-effect transistor.

[0052] In summary, the potential of the total bit line DBL in related technologies is easily affected by different voltages and process corners, making it impossible to maintain consistency. For example, the potential of the total bit line DBL will be lower at FF corner (Fast nmos and Fast pmos, where the threshold voltages of nmos and pmos are relatively low) or at high voltage and low temperature. Conversely, the potential of the total bit line DBL will be higher at SS corner (Slow nmos and Slow pmos, where the threshold voltages of nmos and pmos are relatively high) or at low voltage and high temperature, making it more difficult for the total bit line DBL or bit line BL to charge to the expected potential. Furthermore, the potential of DBL is easily affected by power supply voltage fluctuations and cannot be sufficiently stable. This application adds a feedback unit 40 and controls the current Ifb flowing through the feedback unit 40 by controlling the potential of the total bit line DBL. By adjusting the ratio of the two currents Ifb and Ibias, the potential of the total bit line DBL can be kept more consistent under different voltages and process corners. At the same time, the potential of the total bit line DBL is less susceptible to interference from the power supply voltage, and the bit line BL is easier to charge to the expected potential, thereby improving the overall resolution of the sensitive amplifier.

[0053] Taking the 1.8V (potential of total bit line DBL) / 64M (capacity of memory chip) project as an example, before adding feedback unit 40, the potential difference of total bit line DBL under different voltages and process corners is about 250mV; after adding feedback unit 40, the potential difference of total bit line DBL is about 100mV, and at the same time, under the low voltage condition of SS corner, the precharge time of bit line BL is shortened by about 3ns.

[0054] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0055] The above provides a detailed description of the sensitive amplifier and memory chip provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A sensitive amplifier, characterized in that, The sensitive amplifier includes: The first clamping unit has a first end electrically connected to the power supply terminal and a second end electrically connected to the main bit line. The second clamping unit has a first end electrically connected to the control terminal of the first clamping unit, a second end electrically connected to the ground terminal, and a control terminal electrically connected to the second end of the first clamping unit. A first current unit, wherein a first terminal of the first current unit is electrically connected to the power supply terminal, a second terminal of the first current unit is electrically connected to the control terminal of the first clamping unit and the first terminal of the second clamping unit, and the control terminal of the first current unit is electrically connected to a first bias voltage terminal; and The feedback unit has a first end electrically connected to the power supply terminal, a second end electrically connected to the control terminal of the first clamping unit, the first end of the second clamping unit, and the second end of the first current unit, and a control terminal electrically connected to the second end of the first clamping unit, the control terminal of the second clamping unit, and the main bit line.

2. The sensitive amplifier according to claim 1, characterized in that, The feedback unit includes a feedback transistor, the first terminal of which is electrically connected to the power supply terminal, the second terminal of which is electrically connected to the second terminal of the first current unit, and the control terminal of which is electrically connected to the second terminal of the first clamping unit.

3. The sensitive amplifier according to claim 2, characterized in that, The first current unit includes a first current transistor, the first terminal of the first current transistor is electrically connected to the power supply terminal, the second terminal of the first current transistor is electrically connected to the second terminal of the feedback transistor, and the control terminal of the first current transistor is electrically connected to the first bias voltage terminal.

4. The sensitive amplifier according to claim 3, characterized in that, The second clamping unit includes a second clamping transistor. The first terminal of the second clamping transistor is electrically connected to the second terminal of the feedback transistor and the second terminal of the first current transistor. The second terminal of the second clamping transistor is electrically connected to the ground terminal. The gate of the second clamping transistor is electrically connected to the second terminal of the first clamping unit.

5. The sensitive amplifier according to claim 4, characterized in that, The first clamping unit includes a first clamping transistor, the first terminal of the first clamping transistor is electrically connected to the power supply terminal, the second terminal of the first clamping transistor is electrically connected to the total bit line, and the control terminal of the first clamping transistor is electrically connected to the first terminal of the second clamping transistor, the second terminal of the feedback transistor, and the second terminal of the first current transistor.

6. The sensitive amplifier according to claim 5, characterized in that, The first clamping transistor and the second clamping transistor are both N-channel transistors; the first current transistor and the feedback transistor are both P-channel transistors.

7. The sensitive amplifier according to claim 6, characterized in that, The sensitive amplifier also includes: A second current transistor, wherein the first terminal of the second current transistor is electrically connected to the power supply terminal, the second terminal of the second current transistor is electrically connected to the first terminal of the first clamping transistor, and the control terminal of the second current transistor is electrically connected to the second bias voltage terminal; and A precharge transistor, wherein the first terminal of the precharge transistor is electrically connected to the power supply terminal, the second terminal of the precharge transistor is electrically connected to the first terminal of the first clamping transistor and the second terminal of the second current transistor, and the control terminal of the precharge transistor is electrically connected to the precharge control terminal.

8. The sensitive amplifier according to claim 7, characterized in that, The sensitive amplifier also includes: The first transistor has its first terminal electrically connected to the power supply terminal, and its control terminal is electrically connected to the first terminal of the first clamping transistor, the second terminal of the precharge transistor, and the second terminal of the second current transistor. The first transistor is a P-channel transistor. A second transistor, wherein the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, the second terminal of the second transistor is electrically connected to ground, and the control terminal of the second transistor is electrically connected to a third bias voltage terminal; the second transistor is an N-channel transistor. The buffer has its input terminal electrically connected to the second terminal of the first transistor and the first terminal of the second transistor, and its output terminal is used to output the corresponding read data.

9. The sensitive amplifier according to any one of claims 1 to 8, characterized in that, The ratio of the current flowing through the feedback unit to the current flowing through the first current unit is 1:M, where M is a positive number.

10. A memory chip, characterized in that, Including the sensitive amplifier as described in any one of claims 1 to 9.

11. The memory chip according to claim 10, characterized in that, The memory chip also includes a decoding transistor, the first terminal of which is electrically connected to the total bit line, the second terminal of which is electrically connected to the bit line, and the control terminal of which is electrically connected to the decoding selection terminal. The decoding transistor is an N-channel transistor.

12. The memory chip according to claim 11, characterized in that, The memory chip also includes a memory transistor, the first terminal of which is electrically connected to the second terminal of the decoding transistor, the second terminal of which is electrically connected to a ground terminal, and the control gate of which is electrically connected to a word line.

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